TLV1171xxDCY
VOUT
VIN
2
3
1
GND
GND
TLV1171
www.ti.com
SBVS177 –APRIL 2012
1-A, Positive Fixed-Voltage, Low-Dropout Regulator
1FEATURES DESCRIPTION
The TLV1171 low-dropout (LDO) linear regulator is a
2• Accuracy: 1.5% (typ) low input voltage version of the popular 1117 voltage
• Low IQ: 100 μA (max) regulator.
– 500x Lower Than Standard 1117 Devices The TLV1171 is an extremely low-power device that
• VIN: 2.0 V to 5.5 V consumes 500x lower quiescent current than the
– Absolute Maximum VIN: 6.0 V traditional 1117 voltage regulator, making the
TLV1171 suitable for applications that mandate very
• Stable with 0-mA Output Current low standby current. The TLV1171 LDO is also stable
• Low Dropout: 455 mV at 1 A for VOUT = 3.3 V with 0 mA of load current; there is no minimum load
• High PSRR: 65 dB at 1 kHz requirement, making the device an ideal choice for
applications where the regulator is required to power
• Minimum Ensured Current Limit: 1.1 A very small loads during standby in addition to large
• Stable with Cost-Effective Ceramic Capacitors: currents on the order of 1 A during normal operation.
– With 0-ΩESR The TLV1171 offers excellent line and load transient
performance, resulting in very small magnitude output
• Temperature Range: –40°C to +125°C voltage undershoots and overshoots when the load
• Thermal Shutdown and Overcurrent Protection current requirement changes from less than 1 mA to
• Available Package: SOT223 more than 500 mA.
– See the Package Option Addendum at the A precision band gap and error amplifier provides
end of this document for a complete list of 1.5% accuracy. A very high power-supply rejection
available voltage options. ratio enables the device to be used for post-
regulation after a switching regulator. Other valuable
APPLICATIONS features include low output noise and low-dropout
voltage.
• Set Top Boxes The device is internally compensated to be stable
• TVs and Monitors with 0-Ωequivalent series resistance (ESR)
• PC Peripherals, Notebooks, and Motherboards capacitors. These key advantages enable the use of
• Modems and Other Communication Products cost-effective, small-size ceramic capacitors. Cost-
effective capacitors that have higher bias voltages
• Switching Power-Supply Post-Regulation and temperature derating can also be used if desired.
The TLV1171 is available in a SOT223 package. For
alternate pin outs of the device, refer to the
TLV1117LV.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TLV1171
SBVS177 –APRIL 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT VOUT
TLV1171vvyyyz VV is the nominal output voltage (for example, 33 = 3.3 V).
YYY is the package designator.
Zis the package quantity. Use Rfor reel (2500 pieces), and Tfor tape (250 pieces).
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
At TJ= +25°C, unless otherwise noted. All voltages are with respect to GND. VALUE
MIN MAX UNIT
Input voltage range, VIN –0.3 +6.0 V
Voltage Output voltage range, VOUT –0.3 +6.0 V
Current Maximum output current, IOUT Internally limited
Output short-circuit duration Indefinite
Continuous total power dissipation PDISS See Thermal Information Table
Operating junction, TJ–55 +150 °C
Temperature Storage, Tstg –55 +150 °C
Human body model (HBM) 2 kV
QSS 009-105 (JESD22-A114A)
Electrostatic discharge (ESD)
ratings Charged device model (CDM) 500 V
QSS 009-147 (JESD22-C101B.01)
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
THERMAL INFORMATION TLV1171
THERMAL METRIC(1) DCY (SOT223) UNITS
3 PINS
θJA Junction-to-ambient thermal resistance 62.9
θJCtop Junction-to-case (top) thermal resistance 47.2
θJB Junction-to-board thermal resistance 12.0 °C/W
ψJT Junction-to-top characterization parameter 6.1
ψJB Junction-to-board characterization parameter 11.9
θJCbot Junction-to-case (bottom) thermal resistance N/A
space
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
2Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
TLV1171
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SBVS177 –APRIL 2012
ELECTRICAL CHARACTERISTICS
At TA= +25°C, VIN = VOUT(TYP) + 1.5 V, IOUT = 10 mA, and COUT = 1.0 μF, unless otherwise noted. TLV1171
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range 2.0 5.5 V
VOUT > 2 V –1.5 +1.5 %
VOUT DC output accuracy 1.5 V ≤VOUT < 2 V –2 +2 %
1.2 V ≤VOUT < 1.5 V –40 +40 mV
ΔVO/ΔVIN Line regulation VOUT(NOM) + 0.5 V ≤VIN ≤5.5 V, IOUT = 10 mA 1 5 mV
ΔVO/ΔIOUT Load regulation 0 mA ≤IOUT ≤1 A 1 35 mV
IOUT = 200 mA 115 mV
IOUT = 500 mA 285 mV
VOUT < 3.3 V IOUT = 800 mA 455 mV
IOUT = 1 A 570 800 mV
VDO Dropout voltage(1) VIN = 0.98 x VOUT(NOM) IOUT = 200 mA 90 mV
IOUT = 500 mA 230 mV
VOUT ≥3.3 V IOUT = 800 mA 365 mV
IOUT = 1 A 455 700 mV
ICL Output current limit VOUT = 0.9 × VOUT(NOM) 1.1 A
IQQuiescent current IOUT = 0 mA 50 100 µA
PSRR Power-supply rejection ratio VIN = 3.3 V, VOUT = 1.8 V, IOUT = 500 mA, f = 100 Hz 65 dB
VNOutput noise voltage BW = 10 Hz to 100 kHz, VIN = 2.8 V, VOUT = 1.8 V, IOUT = 500 mA 60 µVRMS
tSTR Startup time(2) COUT = 1.0 µF, IOUT = 1 A 100 µs
UVLO Undervoltage lockout VIN rising 1.95 V
Shutdown, temperature increasing +165 °C
Thermal shutdown
TSD temperature Reset, temperature decreasing +145 °C
Operating junction
TJ–40 +125 °C
temperature
(1) VDO is measured for devices with VOUT(NOM) = 2.5 V so that VIN = 2.45 V.
(2) Startup time is the time from when VIN asserts to when output is sustained at a value greater than or equal to 0.98 × VOUT(NOM).
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 3
VOUT
VIN
2
3
1
GND
GND
Current
Limit
Bandgap
Thermal
Shutdown
IN OUT
LOGIC
GND
TLV1171 Series
UVLO
TLV1171
SBVS177 –APRIL 2012
www.ti.com
PIN CONFIGURATION
DCY PACKAGE
SOT223
(TOP VIEW)
PIN DESCRIPTIONS
NAME PIN DESCRIPTION
GND 2, Tab Ground pin
Input pin.
IN 1 See the Input and Output Capacitor Requirements section for more details.
Regulated output voltage pin.
OUT 3 See the Input and Output Capacitor Requirements section for more details.
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Block Diagram
4Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
Input Voltage (V)
1.9
1.85
1.8
1.75
1.7
Output Voltage (V)
+125 C
+85 C
+25 C
40 C-
°
°
°
°
V = 1.8 V
I = 10 mA
OUT
OUT
3.3 3.5 3.7 3.9 4.1 4.3 4.7 5.1 5.5
Input Voltage (V)
1.9
1.85
1.8
1.75
1.7
Output Voltage (V)
+85 C
+25 C
40 C-
°
°
°
V = 1.8 V
I = 1 A
OUT
OUT
4.5 4.9 5.3
0 100 200 300 400 500 600 700 1000
Output Current (mA)
1.9
1.85
1.8
1.75
1.7
Output Voltage (V)
+125 C
+85 C
+25 C
40 C-
°
°
°
°
800 900
V = 1.8 V
OUT
2 2.5 3 3.5 4 4.5
1200
1000
800
600
400
200
0
Dropout Voltage (mV)
Input Voltage (V)
+85 C
+25 C
40 C-
°
°
°
600
500
400
300
200
100
0
Dropout Voltage (mV)
0 100 200 300 400 500 600 700 800 900 1000
Output Current (mA)
+125 C
+85 C
+25 C
40 C-
°
°
°
°
-40 -25 -10 5 20 35 65 95 125
Temperature ( )C°
1.9
1.85
1.8
1.75
1.7
Output Voltage (V)
V = 1.8 V
OUT
50 80 110
10 mA
500 mA
TLV1171
www.ti.com
SBVS177 –APRIL 2012
TYPICAL CHARACTERISTICS
At TA= +25°C, VIN = VOUT(TYP) + 1.5 V; IOUT = 10 mA, and COUT = 1.0 μF, unless otherwise noted.
LINE REGULATION LINE REGULATION
Figure 2. Figure 3.
LOAD REGULATION DROPOUT VOLTAGE vs INPUT VOLTAGE
Figure 4. Figure 5.
DROPOUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs TEMPERATURE
Figure 6. Figure 7.
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 5
600
500
400
300
200
100
0
Quiescent Current ( A)m
0 100 200 300 400 500 600 700 800 900 1000
Output Current (mA)
+125 C
+85 C
+25 C
40 C-
°
°
°
°
3.3 3.5 3.7 3.9 4.1 4.3 4.7 5.1 5.5
Input Voltage (V)
1.8
1.78
1.76
1.74
1.72
1.7
1.68
1.66
1.64
1.62
1.6
Current Limit (mA)
4.5 4.9 5.3
+85 C
+25 C
40 C-
°
°
°
10 100 1 k 100 k 1 M 10 M
Frequency (Hz)
90
80
70
60
50
40
30
20
10
0
Power-Supply Rejection Ratio (dB)
10 k
V V = 3 V-
IN OUT
I = 500 mA
I = 150 mA
I = 30 mA
OUT
OUT
OUT
10 100 1 k 100 k 1 M 10 M
Frequency (Hz)
90
80
70
60
50
40
30
20
10
0
Power-Supply Rejection Ratio (dB)
10 k
V V = 1.5 V-
IN OUT
I = 500 mA
I = 150 mA
I = 30 mA
OUT
OUT
OUT
0 100 200 300 400 500 600 700 800 900 1000
Output Current (mA)
90
80
70
60
50
40
30
20
10
0
Power-Supply Rejection Ratio (dB)
V V = 1.5 V-
IN OUT
f = 120 Hz
f = 50 Hz
f = 10 kHz
f = 10 MHz
f = 1 kHz f = 100 kHz
f = 1 MHz
TLV1171
SBVS177 –APRIL 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, VIN = VOUT(TYP) + 1.5 V; IOUT = 10 mA, and COUT = 1.0 μF, unless otherwise noted.
QUIESCENT CURRENT vs OUTPUT CURRENT CURRENT LIMIT vs INPUT VOLTAGE
Figure 8. Figure 9.
PSRR vs FREQUENCY PSRR vs FREQUENCY
Figure 10. Figure 11.
PSRR vs OUTPUT CURRENT SPECTRAL NOISE DENSITY vs FREQUENCY
Figure 12. Figure 13.
6Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
V = 2.8 V
IN
50 s/divm
50 mV/div 200 mA/div
IOUT
VOUT
200 mA
500 mA
V = 2.8 V
IN
50 s/divm
50 mV/div 200 mA/div
IOUT
VOUT
200 mA
500 mA
V = 2.8 V
IN
50 s/divm
50 mV/div 500 mA/div
IOUT
VOUT
1 mA
500 mA
50 s/divm
50 mV/div 500 mA/div
IOUT
VOUT
1 mA
500 mA
50 s/divm
100 mV/div 500 mA/div
IOUT
VOUT
200 mA
1 A
50 s/divm
100 mV/div 500 mA/div
IOUT
VOUT
200 mA
1 A
TLV1171
www.ti.com
SBVS177 –APRIL 2012
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, VIN = VOUT(TYP) + 1.5 V; IOUT = 10 mA, and COUT = 1.0 μF, unless otherwise noted.
LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
(200 mA to 500 mA, COUT = 1 μF) (200 mA to 500 mA, COUT = 10 μF)
Figure 14. Figure 15.
LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
(1 mA to 500 mA, COUT = 1 μF) (1 mA to 500 mA, COUT = 10 μF)
Figure 16. Figure 17.
LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
(200 mA to 1 A, COUT = 1 μF) (200 mA to 1 A, COUT = 10 μF)
Figure 18. Figure 19.
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 7
50 s/divm
100 mV/div 500 mA/div
IOUT
VOUT
1 mA
1 A
50 s/divm
100 mV/div 500 mA/div
IOUT
VOUT
1 mA
1 A
200 s/divm
5 mV/div 1 V/div
VIN
VOUT
3.3 V
4.3 V
200 s/divm
5 mV/div 1 V/div
VIN
VOUT
3.3 V
4.3 V
200 s/divm
10 mV/div 1 V/div
VIN
VOUT
3.3 V
4.3 V
200 s/divm
10 mV/div 1 V/div
VIN
VOUT
3.3 V
5.5 V
TLV1171
SBVS177 –APRIL 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, VIN = VOUT(TYP) + 1.5 V; IOUT = 10 mA, and COUT = 1.0 μF, unless otherwise noted.
LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
(1 mA to 1 A, COUT = 1 μF) (1 mA to 1 A, COUT = 10 μF)
Figure 20. Figure 21.
LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
(VOUT = 1.8 V, IOUT = 10 mA) (VOUT = 1.8 V, IOUT = 500 mA)
Figure 22. Figure 23.
LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
(VOUT = 1.8 V, IOUT = 1 A) (VOUT = 1.8 V, IOUT = 10 mA)
Figure 24. Figure 25.
8Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
200 s/divm
10 mV/div 1 V/div
VIN
VOUT
3.3 V
5.5 V
200 s/divm
10 mV/div 1 V/div
VIN
VOUT
3.3 V
5.5 V
TLV1171
www.ti.com
SBVS177 –APRIL 2012
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, VIN = VOUT(TYP) + 1.5 V; IOUT = 10 mA, and COUT = 1.0 μF, unless otherwise noted.
LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
(VOUT = 1.8 V, IOUT = 500 mA) (VOUT = 1.8 V, IOUT = 1 A)
Figure 26. Figure 27.
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 9
V = I R
OUT LIMIT LOAD
´
TLV1171
SBVS177 –APRIL 2012
www.ti.com
APPLICATION INFORMATION
The TLV1171 is a low quiescent current linear regulator designed for high-current applications. Unlike typical
high-current linear regulators, the TLV1171 consumes significantly less quiescent current. The device delivers
excellent line and load transient performance. The TLV1171 is low noise, and exhibits a very good power-supply
rejection ratio (PSRR). As a result, the device is ideal for high-current applications that require very sensitive
power-supply rails.
The TLV1171 regulator offers both current limit and thermal protection. The device operating junction
temperature range is –40°C to +125°C.
INPUT AND OUTPUT CAPACITOR REQUIREMENTS
For stability, 1.0-μF ceramic capacitors are required at the output. Higher-valued capacitors improve transient
performance. X5R- and X7R-type ceramic capacitors are recommended because these capacitors have minimal
variation in value and equivalent series resistance (ESR) over temperature. Unlike traditional linear regulators
that need a minimum ESR for stability, the TLV1171 is ensured to be stable with no ESR. Therefore, cost-
effective ceramic capacitors can be used with this device. Effective output capacitance that takes bias,
temperature, and aging effects into consideration must be greater than 0.5 μF to ensure device stability.
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to
1.0-μF, low-ESR capacitor across the IN and GND pins of the regulator. This capacitor counteracts reactive input
sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be
necessary if large, fast, rise-time load transients are anticipated, or if the device is not located physically close to
the power source. If source impedance is greater than 2 Ω, a 0.1-μF input capacitor may also be necessary to
ensure stability.
BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE
Input and output capacitors should be placed as close to the device pins as possible. To improve characteristic
ac performance such as PSRR, output noise, and transient response, it is recommended that the board be
designed with separate ground planes for VIN and VOUT, with the ground plane connected only at the GND pin of
the device. In addition, the output capacitor ground connection should be connected directly to the device GND
pin. Higher-value ESR capacitors may degrade PSRR performance.
INTERNAL CURRENT LIMIT
The TLV1171 internal current limit helps to protect the regulator during fault conditions. During current limit, the
output sources a fixed amount of current that is largely independent of the output voltage. In such a case, the
output voltage is not regulated and can be calculated by Equation 1:
(1)
The PMOS pass transistor dissipates [(VIN – VOUT) × ILIMIT] until thermal shutdown is triggered and the device
turns off. As the device cools down, it is turned on by the internal thermal shutdown circuit. If the fault condition
continues, the device cycles between current limit and thermal shutdown. See the Thermal Information section
for more details.
The PMOS pass element in the TLV1171 has a built-in body diode that conducts current when the voltage at
OUT exceeds the voltage at IN. This current is not limited; if extended reverse voltage operation is anticipated,
external limiting to 5% of the rated output current is recommended.
10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
P =(V V )I-
D IN OUT OUT
TLV1171
www.ti.com
SBVS177 –APRIL 2012
DROPOUT VOLTAGE
The TLV1171 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device
behaves like a resistor in dropout.
As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout.
TRANSIENT RESPONSE
As with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude.
UNDERVOLTAGE LOCKOUT (UVLO)
The TLV1171 uses an undervoltage lockout circuit to keep the output shut off until the internal circuitry operates
properly.
THERMAL INFORMATION
Thermal protection disables the output when the junction temperature rises to approximately +165°C, thus
allowing the device to cool. When the junction temperature cools to approximately +145°C, the output circuitry is
again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal
protection circuit may cycle on and off. This cycling limits dissipation of the regulator, protecting it from damage
as a result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to +125°C (max). To estimate the margin
of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection
is triggered; use worst-case loads and signal conditions.
The TLV1171 internal protection circuitry has been designed to protect against overload conditions. It is not
intended to replace proper heatsinking. Continuously running the TLV1171 into thermal shutdown degrades
device reliability.
POWER DISSIPATION
The ability to remove heat from the die is different for each package type and presents different considerations in
the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves
heat from the device to ambient air. Performance data for JEDEC low and high-K boards are given in the
Thermal Information table. Using heavier copper increases the effectiveness in removing heat from the device.
The addition of plated through-holes to heat-dissipating layers also improves heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of
the output current and voltage drop across the output pass element, as shown in Equation 2:
(2)
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 11
PACKAGE OPTION ADDENDUM
www.ti.com 19-Nov-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLV117112DCYR ACTIVE SOT-223 DCY 4 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 YX
TLV117112DCYT ACTIVE SOT-223 DCY 4 250 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 YX
TLV117115DCYR ACTIVE SOT-223 DCY 4 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 C9
TLV117115DCYT ACTIVE SOT-223 DCY 4 250 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 C9
TLV117118DCYR ACTIVE SOT-223 DCY 4 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 WF
TLV117118DCYT ACTIVE SOT-223 DCY 4 250 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 WF
TLV117125DCYR ACTIVE SOT-223 DCY 4 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 WE
TLV117125DCYT ACTIVE SOT-223 DCY 4 250 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 WE
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 19-Nov-2014
Addendum-Page 2
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV117112DCYR SOT-223 DCY 4 2500 330.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
TLV117112DCYT SOT-223 DCY 4 250 180.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
TLV117118DCYR SOT-223 DCY 4 2500 330.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
TLV117118DCYT SOT-223 DCY 4 250 180.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
TLV117125DCYR SOT-223 DCY 4 2500 330.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
TLV117125DCYT SOT-223 DCY 4 250 180.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Nov-2014
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV117112DCYR SOT-223 DCY 4 2500 340.0 340.0 38.0
TLV117112DCYT SOT-223 DCY 4 250 340.0 340.0 38.0
TLV117118DCYR SOT-223 DCY 4 2500 340.0 340.0 38.0
TLV117118DCYT SOT-223 DCY 4 250 340.0 340.0 38.0
TLV117125DCYR SOT-223 DCY 4 2500 340.0 340.0 38.0
TLV117125DCYT SOT-223 DCY 4 250 340.0 340.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Nov-2014
Pack Materials-Page 2
MECHANICAL DATA
MPDS094A – APRIL 2001 – REVISED JUNE 2002
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DCY (R-PDSO-G4) PLASTIC SMALL-OUTLINE
4202506/B 06/2002
6,30 (0.248)
6,70 (0.264)
2,90 (0.114)
3,10 (0.122)
6,70 (0.264)
7,30 (0.287) 3,70 (0.146)
3,30 (0.130)
0,02 (0.0008)
0,10 (0.0040)
1,50 (0.059)
1,70 (0.067)
0,23 (0.009)
0,35 (0.014)
1 2 3
4
0,66 (0.026)
0,84 (0.033)
1,80 (0.071) MAX
Seating Plane
0°–10°
Gauge Plane
0,75 (0.030) MIN
0,25 (0.010)
0,08 (0.003)
0,10 (0.004) M
2,30 (0.091)
4,60 (0.181) M
0,10 (0.004)
NOTES: A. All linear dimensions are in millimeters (inches).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC TO-261 Variation AA.
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