1
4205B–AUTO–12/04
Features
•Fully Compliant to VAN Specification ISO/11519-3
•Handles All Specified Module Types
•Handles All Specified Message Types
•Handles Retransmission of Frames on Contention and Errors
•3 Separate Line Inputs with Automatic Diagnosis and Selection
•Normal or Pulsed (Optical and Radio Mode) Coding
•VAN Transfer Rate: 1 Mbit/s Maximum
•SPI/SCI Interface
– SPI Transfer Rate: 4 Mbit/s Maximum
– SCI Transfer Rate: 125 Kbit/s Maximum
•Idle and Sleep Modes
•128 Bytes of General-purpose RAM
•14 Identifier Registers with All Bits Individually Maskable
•6-source Maskable Interrupt, Including an Interrupt-on-reset to Detect Glitches on the
Reset Pin
•Integrated Crystal or Resonator Oscillator with Internal Baud Rate Generator and
Buffered Clock Output
•Single +5V Power Supply
•0.8 µm CMOS Technology
•SO16 Package
Description
The TSS463AA is a circuit that allows the transfer of all the status information needed
in a car or truck over a single low-cost wire pair , that minimizes electrical wire usage. It
can be used t o i nterc onn ec t p owerf u l f unctio ns to c ontrol a nd interface c ar b ody elec-
tronics (lights, wipers, power window, etc.).
The TSS 463AA is fully c omplian t with the VAN ISO Standa rd 11 519-3. T his standa rd
supports a wide ran ge of appl ications s uch as low- cost re mote-contr olled switc hes.
Typically it is used for lamp control, complex, highly-autonomous, distributed systems,
which require fast and secure data transfers.
The TSS463AA is a microprocessor-interfaced line controller for mid- to high-com-
plexity bus-maste rs and liste ners like dashboard controllers, car stere o or mobil e
telephone CPUs.
The micr oproces sor inte rfac e consis ts of a 256-by te RAM a nd a re giste r area di vide d
into 11 control registers, 14 channel register sets and 128 bytes of ge neral purpose
RAM, used as a message storage area, and a 6-source maskable interrupt.
The circuit operates in the RAM using DMA techniques, controlled by the channel and
control registers. This allows virtually any microprocessor , including SPI/SCI interface,
to be connected easily to the TSS463AA.
Messages are encoded in enhanced Manchester code, and an optional pulsed code
for use with an o pti cal or radi o li nk, at a ma xi mu m bi t ra te of 1 Mbi t/s. Th e TSS 463 AA
analyzes the messages received or transmitted according to 6 different criteria includ-
ing some higher level checks.
In additi on, the bus i nte rface ha s t hr ee se parate in puts with auto mati c s ourc e di ag no-
sis and selection. The interface allows for multibus listening or the automatic selection
of the most reliable source at any time if severa l line receivers are connected to the
same bus.
VAN Data Link
Controller with
Serial Interface
TSS463-AA
2 TSS463-AA 4205B–AUTO–12/04
Block Diagram
3
TSS463-AA
4205B–AUTO–12/04
Pin Configuration
Pin Description
1 16
215
314
413
512
6 11
710
8 9
MISO
SS
INT RESET
VDD
XTAL1
XTAL2
TEST/VSS
CKOUT
MOSI
SCLK
GND
TXD
RXD0
RXD2
RXD1
TOP VIEW
I/O Type Pin Name Pin No. Pin Funct ion
O 3-state MISO 1 SPI /SCI D a ta Ou tput
I trig g er CM OS SS 2SPI/SCI Slave Select (active low)
Open-drain INT 3Interrupt (active low)
Power VDD 4+ 5V power supply
I CMOS XTAL1 5Crystal oscillator or clock input pin from 1 to 16 MHz
OXTAL2 6Crystal oscillator output pin
Ground TEST/VSS 7Test mod e input
OCKOUT 8Buffered clock output
I CMOS Pull- d o w n RXD1 9VAN bus input 1
I CMOS Pull- d o w n RXD2 10 VAN bus input 2
I CMOS Pull- d o w n RXD0 11 VAN bus input 0
O 3-state TXD 12 VAN bus output
Ground GND 13
I trigger CMOS pull-up RESET 14 Hardware Reset (active low)
I trig g er CM OS SCLK 15 SPI/SCI Clock Input
I trig g er CM OS MOSI 16 SPI/SCI Data Input
4 TSS463-AA 4205B–AUTO–12/04
Application The TSS463AA is a microprocessor controlled line controller for the VAN bus. It can
interface to virtually any microprocessor which includes SPI or SCI interface.
• The TSS463AA provides one full Motorola compatible SPI interface.
• It includes one full compatible Intel UART (mode 0 only).
• And finally, one 9-bits SCI interface is also integrated.
In addi tion, the c ircuit featu res a singl e interru pt pin. This pin can be tr eated as lev el
sensitive. For example, if there is a pending interrupt inside the circuit when another
interrupt is rese t, the INT pin will emit a high pulse with the same pulse width as the
internal write strobe (typically 20 ns).
Figure 1. Typical Application With Motorola SPI Mode
Notes: 1. The TSS463AA RESET pin can either be connected to GND through a 1 µF capaci-
tor, or the µC RESET pin or unconnected (inactive with internal pull-up).
2. Leaving MISO output pin floating in high impedance mode slightly increases standby
consumption. A 100 KΩ pull-up/pull-down resistor is recommended.
TEST/VSS
TxD
mC
CKOUT
IRQ
POR T X.Y
MISO
XTAL1
INT
SS
RESET (1)
MISO(2) 1
2
3
4
5
6
7
89
10
11
12
13
14
15
16 SCLK
MOSI
RxD0
RxD1
RxD2
RESET (1)
VDD GND
XTAL2 VAN Bus
General I/O
Remaining pins
SCLK (if needed)
100K
MOSI
CKOUT
TSS463
Microcontroller
5
TSS463-AA
4205B–AUTO–12/04
Microprocessor
Interface The proce ssor controls the T SS463AA by r eading and writing the internal reg isters of
the circuit. These registers appear to the processor as regular memory locations.
Interface Modes The TSS4 63AA must be co nnected with an SP I or SCI serial in terface. The fol lowing
section provides information on switching from one mode to another.
Motorola SPI Mode The first two bytes to be sent by the mast er (CPU) are called “Initialization Sequence”:
This sequence provides a proper asynchronous RESET in the TSS463AA and it selects
the Motorola SPI, Intel SPI or the SCI serial mode. This initialization sequence is shown
on Figure 4. Two 0x00 will cause an internal RESET and assert the Motorola SPI mode,
Two “0xFF” will provide an internal RESET and assert the Intel® SPI mode and “9 bits to
0 followed by 0xFF or 0xFE ” will generat e an internal RE SET and ass ert the 9-bits S CI
mode.
Figure 2. Mode Configuration Byte
The M otor ola Ser ial Pe riphe ral Inte rface (S PI) is f ully com pat ible wit h th e SP I M oto rola
protocol. The interface is implemented for slave-mode only (the TSS463AA can not gen-
erate SPI frames by itself).
The SPI interface allows the interconnection of several CPUs and peripherals on the
same printed circuit board.
The SPI mode interface consists of 4 pins: separate wires are required for data and
clock, so the clock is not included in the data stream as shown in Figure 5. One pin is
needed for the serial clock (SCLK), two pins for data communication MOSI and MISO
and one pin for Slave Select (SS).
MOSI
or
MOSI
0 . 0000 . 0000
0x00
SCLK
SS
SS
SCLK
SPI 8 Pulses
SCI 9 Pulses
0x00
1 . 1111 . 1111
Internal RESET and SPI Mode (Intel or Motorola)
Internal RESET and SCI Mode
0xFF 0xFF Intel
Motorola
I
nternal RESET
I
nternal RESET
6 TSS463-AA 4205B–AUTO–12/04
Figure 3. SPI Data Stream
SCLK: Serial Clock The maste r device provides the seria l clock for the slav e devices. Data is tra nsferred
synchronously with this clock in both directions. The master and the slave devices
send/receive a data byte during an eight-clock pulse sequence.
MOSI: Master Out Slave In The MOSI pin is the master device data output (CPU) and the slave device data input
(TSS46 3AA). Data is transf erred ser ially fr om the mast er to the slav e on this line; most
significant bit (MSB) first, least significant bit (LSB) last.
MISO: Master In Slave Out The MISO pin is configu re d as the slav e dev ic e data output (TSS 463 AA ) and as mas ter
device data input (CPU). When the slave device is not selected (SS = 1), this pin is in
high impedance state.
SS: Slav e Select The SS pin is the slave chip select. It is low active. A low state on the Slave Select input
allows th e TSS463A A to accep t data on the MOSI pin an d send dat a on the MIS O pin.
The Slave Select signal must not toggle between each transmitted byte and should be
left at a low level during the whole SPI frame. SS must be asserted to inactive high level
at the end of the SPI frame.
As me ntioned b efore , if SS is not asserted, MISO pin is in a high impedance state and
incoming data is not driven to the serial data register.
SPI Protocol The general format of the data communication in the SPI frame between the TSS463AA
and the host is a bit-for-bit exchange on each SCLK clock pulse. Data is arranged in the
TSS46 3AA suc h t hat the si gni ficance of a b it is de ter mi ned by i ts posit ion from the start
for output and from the end for input, most significant bit (MSB) is sent first. Bit
exchanges in multiples of 8 bits are allowed.
The Idle Clock Polarity (CPOL) and the Clock Phase (CPHA) are not programmable: the
CPOL and CPHA values to be programmed in the master (CPU) are CPOL = CPHA = 1.
This is available for all modes. Waveforms with transmit and sample points are shown in
Figure 6.
0x55
S
CLK
M
OSI
S
S
SPI 8 Pulses
0x66
M
ISO
7
TSS463-AA
4205B–AUTO–12/04
Figure 4. CPOL and CPHA in the TSS463AA
At the beg inning of a transmiss ion over the s erial interfa ce, the first by te is the addre ss
of the TSS4 63AA register to be accesse d. The next byte trans mitted is the co ntrol byte
which determines the direction of the communication. The following bytes are data bytes
(conse cutive by tes are writ ten in or read fr om Address , Address + 1, Ad dress + 2,.. .,
Address + n with n = 0 to 28).
To make sure th e TSS463 AA is not out of sync hron ization , the SPI in terface will tran s-
mit data “ 0xAA" a nd "0x55” on the M ISO p in during addre ss and c ontrol by te time . This
way, th e mas ter always ens ures the TSS4 63AA is we ll- synch roni zed. If th e TSS 463AA
is out of synchronization, the master can assert the SS pin inactive to re synchronize the
SPI interface or can assert the RESET pin active or can send an initialization sequence.
When the SS pin is inactive, the SCLK is allowed to toggle. This will have no effect on
the TSS463AA SPI module.
SPI Control Byte The SPI control byte is transmitted by the master (CPU) to the TSS463AA. It specifies
whether it is a TSS463AA Write or Read.
Table 1. SPI Control Byte
DIR: Serial Transfer Direction Zero: Read Operation. The data bytes will be read by the master (CPU) from the
TSS463AA.
One: Write Operation. The data bytes will be written by the master (CPU) to the
TSS463AA.
In both cas es, addres s auto-in crement me chanism will take plac e when more th an one
data byte is read or wri tten. This mechanism is inhibited when address value reaches
0xFF.
The seven following bits are reserved and must be equal to: 1100000.
When th e mast er (CPU ) cond ucts a w rite, it sends a n addr ess byte , a cont rol byte and
data byt es on its MOS I line . The slave de vice (TSS4 63AA) will send, if we ll-sync hro-
nized, “0xAA ” during the address byte and “0x55” dur ing the co ntrol byte on its MISO
line.
0x55
SCLK
MOSI
SS
S
PI 8 Pulses
Data T ransmit Points
Data Sample Points
CPOL = CPHA = 1
MISO 0x66
76543210
DIR 1100000
8 TSS463-AA 4205B–AUTO–12/04
When the master (CPU) conducts a read, it sends an address byte, a control byte and
dummy characters ("0xFF" for instance) on its MOSI line. In the case of a VAN mes-
sages R AM r ead (VA N fram e rece ived) , the first d ata by te sen t bac k by the TSS 463AA
on its MISO pi n is the data length so the m aster k nows how man y dum my char acte rs it
must send to r ead the VAN frame prope rly. When the TSS463AA responds back with
data, it will not take care of the MOSI line.
The master must activate and de-activate SS between each data frame.
Synchronization bytes must be monitored carefully. For instance, if “0xAA” and “0x55”
are not monitored correctly, then the previous transmission may be incorrect too.
A control byte cont aining "0x00" or "0xFF" is forbidden except during an "Initialization
Sequence".
Intel SPI Mode The Intel SPI mode is the second type of interface. As mentioned before, the TSS463AA
enters this m ode if the Ini tiali zation Seque nce c ontain s (f irst two by tes rec eived ) "0xF F,
0xFF".
This mode is fully compatible to the Intel UART serial interface programmed in mode 0
only. It is the same as Motorola SPI mode (same CPOL and CPHA) but with inverte d
communication sense (LSB first and MSB last). The protocol is also the same.
However, fr om the master p oin t of v iew (hos t mi cro co ntrol ler) , th e h ar dware is di fferen t.
Figure 5 shows how to connect the TSS463AA and Intel type microcontroller.
Figure 5. Typical Application With the 8051 UART in Mode 0
Notes: 1. The RESET pin can either be connected to GND through a 1 µF capacitor, or the
microcontroller RESET pin or unconnected (inactive with internal pull-up).
INT
IRQ
PORT X.z SS
PORT X.y
RXD
1
2
3
4
5
6
7
89
10
11
12
13
14
15 SCLK
MISO MOSI
RxD0
RxD1
RxD2
TXD
RESET (1)
VDD GND
CKOUT
XTAL1
XTAL2
TXD
VAN Bus
General I/O
Remaining pins
TEST/VSS
XTAL1
C1
C2
100k
(if needed)
optional
RESET (1)
16
Microcontroller
TSS463
9
TSS463-AA
4205B–AUTO–12/04
The master device provides the serial clock on the TxD pin and is still c onnected to
SCLK pin of the slave device.
Then, the RxD replaces the MOSI and MISO pins and is a bi-directional pin. To achieve
a correct communication, the user should add a few gates to connect the master RxD
pin to the MOSI-MISO slave pins.
Figure 5 proposes two 3-state buffers contr olled by the master through a general pur-
pose I/O pin.
It is obvious that, in this Intel SPI mode, the master cannot monitor the "0xAA and 0x55"
synchron iz ati on by tes while se ndi ng the ad dr es s and c ont rol by tes . It i s the onl y ex c ep -
tion in this mode compared with the Motorola SPI mode.
SCI Mode The SCI mode is the third type of interface. The TSS463AA enters this mode if the Ini-
tialization Sequence contains (first two bytes received) "0x00, 0xFF".
The SCI is compatible with a 9-bits SCI protocol. The interface is implemented for slave-
mode only (the TSS463AA cannot generate SCI frames by itself).
The SCI interface allows an interconnection of several CPUs and peripherals on the
same printed circuit board.
The SCI mode interface consists of 4 pins: separate wires are required for data and
clock, so the clock is not included in the data stream as shown in Figure 6. One pin is
needed fo r the serial cl ock (SCLK), two pin s for data excha nge MOSI and MISO and
one pin for Slave Select SS.
Figure 6. SCI Data Stream
SCLK: Serial Clock The maste r device provides the seria l clock for the slav e devices. Data is tra nsferred
synchronously with this clock in both directions. The master and the slave devices
exchange a data byte during a nine clock pulses sequence. However, the TSS463AA
will only monitor 8 bits on its MOSI line and send 9 bits on its MISO line.
MOSI: Master Out Slave In The MOSI pin is the master device data output (CPU) and the slave device data input
(TSS463 AA). Data i s trans ferred serial ly fro m the m aster to th e sla ve on th is l ine; least
signifi cant bit (LSB) firs t, most significa nt bit (MS B) last. T he TSS463 AA wil l only moni-
tor 8 bits starting from the LSB to MSB-1.
MISO: Master In Slave Out The MISO pin is configu re d as the slav e dev ic e data output (TSS 463 AA ) and as mas ter
device data input (CPU). When the slave device is not selected (SS = 1), this pin is in
high impedance state. The value of the MSB (9th bit) sent on the MISO pin will always be
"1" and should not be used by the master.
SS: Slav e Select The SS pin is the slave chip select. It is low active. A low state on the Slave Select input
allows th e TSS463A A to accep t data on the MOSI pin an d send dat a on the MIS O pin.
M
OSI
MISO
0x55
SS
SCLK
SCI 9 Pulses
0x66
10 TSS463-AA 4205B–AUTO–12/04
The Slave Select signal must not toggle between each transmitted byte and therefore,
should be left at a low level during the whole SCI frame. SS must be asserted to inactive
high level at the end of the SCI frame.
If SS is not asserted, MISO pin is in high impedance state and incoming data is not
driven to the serial data register.
SCI Protocol Same as the SPI protocol described earlier except for data arranging (LSB first and
MSB last) .
Only 8 bits a re monitored by the TSS463AA and master must monitor the 8 first
bits too (9th bit always equal to 1).
SCI Control Byte Same as the SPI control byte.
Clocks and Speed
Considerations
SCLK and XTAL Clocks The SPI/SCI speed rate is given by the CPU producing SCLK. XTAL clock controls the
speed r ate on the V AN bus. The t wo clo cks are asyn chro nous, but a minim um SP I/SCI
interframe spacing must be apply according to XTAL clock.
Intel and Motorola SPI Modes Within an SPI byte, the maximum speed allowed on the MOSI line is 4 Mbits/s.
For example, when using a 1 MHz oscillator (sufficient to provide 62.5 kTS/s on the VAN
bus) the minimum inter-character delay is 12 µs (12 oscillator periods). Speed consider-
ations are detailed in Figure 7.
Figure 7. SPI Speed Considerations
SCI Mode Within an S CI 9-bits data , th e m axi mu m s pe ed all owe d on th e M OS I lin e i s 125 Kb its /s .
When using a 1 MHz oscillator, the data transfer speed and the minimum delay time
between SCI bytes are shown on Figure 8.
S
S
s at 1 MHz)
(4 s at 1 MHz) (15 s at 1 MHz) 12 Xtal Min
8 Xtal Min 15 Xtal Min
4 Xtal Min
M
OSI Address Control
S
CLK
4 Mbits/s Max for SCLK
Data
(12 s at 1 MHz)
(8
11
TSS463-AA
4205B–AUTO–12/04
Figure 8. SCI Speed Considerations
Interrupts If an event occurs in the TSS463AA that needs the attention of the processor, this will
be sig nalled on the ac tive l ow, open -drai n inte rrupt re quest pin. The event that cre ates
this request is controlled by the internal registers.
Every time the microprocessor accesses any of the interrupt registers (addresses 0x08
to 0x0B), the INT pin will be released momentarily. This enables the TSS463AA to work
with processors that have either edge or level sensitive interrupt inputs.
Reset The reset is applied asynchronously or synchronously to the XTAL clock.
Asynchronous Reset It can be done either by the RESET pin (hardware asynchronous reset) or by software
(software asy nchr on ous reset).
The RESET pin is a CMOS trigger input with a pull-up resistor (~ 70 kΩ). An external
1 µF capa citor to GN D provides to RESET pin an efficient behavior.
The as ynchr onous sof tware r eset is ma de by the "Initi alizat ion Sequ ence" descri bed in
“Motorola SPI Mode” on page 5.
Two "0x00" bytes provide an asynchronous software reset and configure the TSS463AA
in the Motorola SPI mode while two "0xFF" bytes provide a reset and configure the com-
ponent in the Intel SPI mode and "0x00 followed by 0xFF " provide a reset and configure
the component in the SCI mode. The SS pin must be asser ted as shown on Figure 9.
The SPI/SCI logic will monitor these two bytes and provide an internal reset pulse
asserting the TSS463AA in the right mode.
Synchronous Reset A synchronous reset (regarding XTAL clock) is available on the TSS463AA during cur-
rent operation. It is made through the GRES command bit of the Command Register
(address 0x03).
The two kinds of reset are ordered and filtered. Then the internal reset, always asserted
asynchro nously, enables the internal osci llator. Then i t waits for 12 clock period s and
the oscilla tor stability.
The different blocks of the TSS463AA need to be turned on synchronously. The release
of the internal reset is synchronous and a loose of clock can let the TSS463AA in per-
manent reset after applying Reset.
It is impor tant to n ote t hat e ve n af ter a r eset on the RESET pi n, th e us er s hou ld wai t for
12 clock periods before sending the "Initialization Sequence" in order to select the SPI
or SCI mo de (because the default mode after a hardware r eset is the M otorola SPI
mode).
DataControlAddress
12 Xtal Min
(8 s at 1 MHz)
(4 s at 1 MHz) 15 Xtal Min
(15 s at 1 MHz)
S
S
S
CLK
M
OSI Start Bit Stop Bit
125 Kbits/s Max for SCLK
8 Xtal Min
4 Xtal Min (12 s at 1 MHz)
12 TSS463-AA 4205B–AUTO–12/04
Figure 9. Asynchronous Software Reset with UART Intel Mode
Oscillator An oscillator is integrated in the TSS463AA, and consists of an inverting amplifier of
which the input is XTAL1 and the output XTAL2.
A par allel re sonan ce quar tz cry stal o r ceram ic reso nator m ust be connect ed to these
pins. As shown in Figure 5, two capacitors have to be connected from the crystal pins to
ground. The values of C2 depend on the frequency chosen and can be selected using
the schematic given in Figure 39.
If the osc illator is not used, then a cl ock sign al must be fed to the ci rcuit vi a the XTAL 1
input.
Note that this pin will behave as a CMOS level compatible Schmitt trigger input.
In this case the XTAL2 output should be left unconnected. The oscillator also features a
buffered clock output pin CKOUT. The signal on this pin is directly buffered from the
XTAL1 input, with out inv er sion .
There is on e more pin u sed for the osc illator. The TE ST/VSS pin i s in fact its g round,
and unless this pin is firmly connected to ground, with decoupling capacitors, the oscilla-
tor will not operate correctly.
The tes t mode itse lf, i.e., when the TEST/V SS pin is he ld high, is only intend ed for fac-
tory use, and the functionality of this mode is not specified in any way.
The TE ST/V SS pin is subj ect to ch ange without noti ce, t he onl y exc eptio n is for incom-
ing inspection tests using the test program.
The cl ock signal i s then fed to the cl ock gener ator that g ene rates al l the n eces sary ti m-
ing signa ls for the ope ration of the circuit. The clock gener ator is control led by a 4-bit
code called the clock divider.
S
CLK
15 XTAL Min
M
OSI 0xFF 0xFF
S
S
R
eset Internal Pulse
Detection of Forbidden Control
End of Chip Sele
ct
4 XTAL Min
fTSCLK()
fXTAL
1
()
n16×
-------------------------
=
13
TSS463-AA
4205B–AUTO–12/04
Table 2. Clock Divider
Clock
Divider Divide by
8 MHz 6 MHz 4 MHz 2 MHz
KTS/s Kbits/s KTS/s Kbits/s KTS/s Kbits/s KTS/s Kbits/s
0000 1500 400 375 300 250 200 125 100
0001 2250 200 187.50 150 125 100 62.50 50
0010 4125 100 93.75 75 62.50 50 31.25 25
0011 862.5 50 46.875+ 37.5 31.25 25 15.625 12.5
0100 16 31.25 25 23.438 18.75 15.625 12.5 7.813 6.25
0101 32 15.625 12.5 11.718 9.375 7.813 6.25 3.906 3.125
0110 64 7.813 6.25 5.859 4.688 3.906 3.125 1.953 1.562
0111 128 3.906 3.125 500 400 1.953 1.562 166.666 133.333
1000 1.5 333.333 266.666 250 200 166.666 133.333 83.333 66.666
1001 3166.666 133.333 125 100 83.333 66.666 41.666 33.333
1010 683.333 66.666 62.50 50 41.666 33.333 20.833 16.666
1011 12 41.666 33.333 31.25 25 20.833 16.666 10.416 8.333
1100 24 20.833 16.666 15.625 12.50 10.416 8.333 5.208 4.166
1101 48 10.416 8.333 7.813 6.25 5.208 4.166 2.604 2.083
1110 96 5.208 4.166 3.906 3.125 2.604 2.083 1.302 1.042
1111 192 2.604 2.083 1.953 1.5625 1.302 1.042 0.651 0.521
14 TSS463-AA 4205B–AUTO–12/04
VAN Protocol
Line Interface There are three line inputs and one line output available on the TSS463AA. Which of the
three inputs to use is either programmable by software or automaticall y selected by a
diagnosis system.
The diagnosis system continuously monitors the data received through the three inputs,
and co mpa res i t with eac h oth er a nd th e se lecte d bi trate . It t hen choo ses t he mo st reli-
able input according to the results.
The data on the line is encoded according to the VAN standard ISO/11519-3. This
means that the TSS463AA is using a two level signal having a recessive (1) and a dom-
inant (0) state. Furthermore, due to the simple medium used, all data transmitted on the
bus is also rece iv ed simul taneousl y.
The VAN protocol is hence a CSMA/CD (Carrier Sense Multiple Access Collision Detec-
tion) pro toc ol, al lowing for c on tin uous bitw is e a rb itrat ion of the bus, a nd non -d estru ct ive
(for the higher priority messa ge) collision detection.
Figure 10. CSMA/CD Arbritration
In addition to the VAN specific ation there is also a pulsed c oding of the dominant and
recessive states. This mode is intended to be used with an optical or radio link. In this
mode, the dominant state for the transmitter is a low pulse, (2x prescaled clocks at the
beginning of the bit) and the recessive state is just a high level. When receiving in this
mode, it is not the state of the signal itself which is decoded, but the edges. Also, recep-
tion is imposed on the RxD0 input, and the diagnosis system does not operate correctly.
In addition, in this mode there is an internal loopback in the c ircuit since optical trans-
ceivers are not able to receive the signal that they transmit.
Node a: TxD Node a loses the arbitration
Node a releases the bus
Node b wins the arbitration
Node c loses the arbitration
Node c releases the bus
R
D
Node b: TxD R
D
N
ode c: TxD R
D
O
n Bus: DATA R
D
Arbitration field
R: Recessive Level D: Dominant Level
1
2
3
15
TSS463-AA
4205B–AUTO–12/04
In Figure 11 the pulsed waveforms are shown. In Figure 14 through Figure 20 the low
"timeslots" (i.e. blocks of 16 prescaled clocks) should be replaced by the dominant
waveform show ed in Figure 11 if the correct representations for pulsed coding are to be
seen.
Figure 11. State Encoding
VAN Frame Figure 12. VAN Bus Frame
The VAN bus supports three different module (unit) types:
1. The Autonomous module, which is a bus master. It can transmit Start Of Frame
(SOF) sequences, it can initiate data transfers and can receive messages.
2. The Synchronous access module. It cannot transmit SOF sequences, but it can
initiate data transfers and can receive messages.
3. The Slave module, which can only transmit using an in-frame mechanism and
can receive messages.
Figure 13. Hierarchical Access Methods
Figure 12 sho ws a norm al VAN bus frame. It is initiate d with a St art of Fr ame (SOF)
sequence shown in Figure 14. The SOF can only be tr ansmitted by an autonomous
module. Durin g the pre amble , the TS S463AA will sy nchroni ze its b it rate clock to the
data received.
SOF Identifier
Field
Command Data
Field
Frame
Check
Sum EOD ACK EOF
EXT RAK R/W RTR
SOF ID COM DATA ACK EOF
EOD
Autonomous
R
ank 0
ID COM DATA FCS ACK EOF
EOD
Synchronous
R
ank 1
DATA FCS ACK EOFEOD
Slave
R
ank 16
RTR
FCS
16 TSS463-AA 4205B–AUTO–12/04
Figure 14. Framing Sequences
When the complete SOF sequence has been transmitted or received, the circuit will
start the transmission or reception of the identifier field.
All data on the VAN bus, including the identifier and Frame Check Sum (FCS), are
transmitted using enhanced Manchester code.
In enhanc ed Manchester c ode, three NRZ bits are tran smitted first foll owed by one
Manchester bit, then three more NRZ bits followed by one Manchester bit and so on.
Since the high state is recessive and the low state is dominant, the bus arbitration can
be done. If a module wants access to the bus, it must first listen to the bus during one
full End of Frame (EOF) and one full Inter Frame Spacing (IFS) period to determine
whether the bus is free or not (i.e. no dominant states received).
Figure 15. Data Encoding
The IFS is defined to be a minimum of 64 prescaled clock periods. The TSS463AA,
accepts an IFS of zero prescaled clocks for the reception only of a SOF sequence.
Once the bus ha s been determined as bein g free, the module must, if it is an autono-
mous module, emit an SOF sequence or, if it is a synchronous access module, wait until
it detects a preamble sequence.
At this point there could be several modules transmitting on the bus, and there is no
poss ibility of knowing if thi s is the ca se or not. T herefor e, the fi rst fiel d in which a rbitra -
VAN BUS
SEQUENCE
VAN BUS
SEQUENCE
NUMBER OF
PRESCALED
CLOCKS
PREAMBLE
START OF FRAME
START
SYNC
END OF
DATA ACK END OF FRAME
0 16 32 48 64 80 96 112 128 144 160 176 192
VAN BUS
SEQUENCE
VAN BUS
SEQUENCE
VAN BUS
SEQUENCE
NUMBER OF
PRESCALED
CLOCKS
NRZ 0 NRZ 1
MANCHESTER 0
MANCHESTER 1
0 8 16 24 32
17
TSS463-AA
4205B–AUTO–12/04
tion can be performed is the identifi er field. Since the logical ze roes on the b us are
domina nt, and all dat a is transmi tted with the most signific ant bit (MSB) fi rst, the first
module t o tran smit a log ical z ero on th e b us will be th e prior itized module , i.e. the me s-
sage that is tagged with the lowest identifier will have priority over the other messages.
It is possible that two messages transmitted on the bus will have the same identifier. The
TSS463AA, therefore, continues the arbitration of the bus throughout the whole frame.
Moreov er, i f the ide nti fie r in tr an sm is sion has bee n pr ogr am med fo r rece pti on as we ll , i t
transmits and receives messages simultaneously, right up until the Frame Check
Sequence (FCS). Only then, if the TSS463AA has transmitted the whole message, it
discard the message recei ved. Arbi tration los s in th e FCS fi eld is considered as a CRC
error during transmission.
This feature is called full data field arbitration, and it enables the user to extend the iden-
tifier. For instance it can be used to trans mit the emi tting modules address i n the first
bytes of the data field, thus enabling the identifier to specify the contents of the fr ame
and the data field to specify the source of the information.
The identifier field of the VAN bus frame is always 12 bits long, and it is always followed
by the 4-bit command field:
• The first bit of the command is the extension bit (EXT). This bit is defined by the
user on transmission and is received and retained by the TSS463AA. To conform
with the standard it should be set to 1 (recessive) by the user, else the frame is
ignored without any IT generation.
• The second bit is the request ACKnowledge bit (RAK). If this bit is a logical one, the
receiving module must acknowledge the transfer with an in-frame
acknowledgement in the ACK field. If it is set to logical zero, then the ACK field must
contain an acknowledge absent sequence.
• The third bit is the Read/Write (R/W). This bit indicates the direction of the data in a
frame.
– If set to zero, it is a "write" message, i.e., data transmitted by one module to
be received by another module.
– If it is set to one, it implies a "read" message, i.e. a request that another
module should transmit data to be received by the one that requested the
data (reply request message).
• Last in the command field is the Remote T ransmission Request bit (RTR). This bit is
a logical zero if the frame contains data and a logical one if the frame does not
contain data. In order to conform with the standard, a received frame includes the
combination R/W. RTR = 01 is ignored without any IT generation.
All the bit s in the command field are autom atically hand led by the TSS 463AA, so the
user ne ed not to be conce rned for encod ing and dec oding of thes e bits. The c ommand
bits transm itted on the VAN bus are calculated from the cur rent status of the ac tive
message.
The data field comes after the command field. This is just a sequence of bytes transmit-
ted MSB first. In the VAN standard the maximum message length is set to 28 bytes, but
the TSS463AA handles messages up to 30 bytes.
The next field is the FCS field. This field is a 15 bit CRC checksum defined by the follow-
ing generator polynomial g(x) of order 15:
g(x)= x15 + x11 + x10 + x9 + x8 + x7 + x4 + x3 + x2 + 1
The division is done with a rest initialized to 0x7FFF, and an inversion of the CRC bits is
performed befo re transmi s sion.
18 TSS463-AA 4205B–AUTO–12/04
However, since the CRC is calculated automatically from the identifier, command and
data fie lds by th e TSS4 63AA, the refor e, the user should not be con cerned with the c ir-
cuit. W hen the frame chec k sequence has be en transm itted, the tra nsmittin g module
must transmi t an End of Data (EOD) sequenc e, followed by the ACKnowledge fiel d
(ACK) and the End of Frame sequence (EOF) to terminate the transfer.
Figure 16. Acknowledge Sequences
Frame Example s The frames transmitted on the VAN bus are generated by several modules, each sup-
plying differ ent parts of the mes sage. Figure 17 through Figure 20 show the four frame
types specified in the VAN standard, and the module that is generating the different
fields.
• The most straightforward frame is the normal data frame in Figure 17. Lik e al l ot h er
frames, it is initiated with a SOF sequence. This sequence is generated by a bus
master (not shown in the figure).
During this frame, there is basically only one module transmitting with the exception of
the acknowledgement, generated by the receiving module if requested in the RAK bit.
• The reply request frame with immediate reply in Figure 18 is the only frame in which
a slave module can transmit data by filling it into the appropriate field.
The onl y d iff erenc e fo r the frame on the bus is tha t th e R/W bi t ha s ch ange d s tate c om-
pared to the normal fram e.
This is a high ly inter active frame whe re a bus ma ster generate s the S OF and the i nitia-
tor generates the identifier, the thr ee first bits of the command , and the acknowledge.
The RTR bit, the data field, the frame check, the EOD and the EOF are all generated by
the replying module.
• The reply request frame with deferred reply in Figure 19 is basically the same frame
as the reply request frame with immediate reply, but since the requested module
does not generate the RTR bit the requesting module will continue with the frame
check, the EOD and the EOF.
During this frame, the requested module will only generate the acknowledge, and only if
this was requested by the initiator through the RAK bit.
• Finally, the deferred reply frame in Figure 20 which is sent when a module has
prepared a reply for a reply request that has been received earlier.
This frame very closely mimics the normal data frame with the exception is the R/W bit
that has changed state.
VAN BUS
SEQUENCE
VAN BUS
SEQUENCE
NUMBER OF
PRESCALED
CLOCKS
POSITIVE ACKNOWLEDGE
ABSENT ACKNOWLEDGE
0 8 16 24 32
19
TSS463-AA
4205B–AUTO–12/04
Figure 17. Normal Data Frame
F
RAME
o
n bus
T
RANSMITTING
F
RAME
o
n bus
T
RANSMITTING
m
odule
CRC
CRC
CRC
CRC
SOF
SOF
SOF
SOF
IDENTIFIER
IDENTIFIER
IDENTIFIER
IDENTIFIER
DATA
DATA
DATA
DATA
EOF
EOF
EOF
EOF
m
odule
R
ECEIVING
m
odule
R
ECEIVING
m
odule
: Positive from Receiver because RAK is Recessive
RAK
EXT
R/W
RTR
ACK
: Recessive for acknowledge from Transmitter
: Recessive from Transmitter
: Dominant from Transmitter
: Dominant from Transmitter- (*) Manchester bit
With acknowledgment
Without acknowledgment
: Absent from Transmitter and from Receiv er because RAK is Dominant
RAK
EXT
R/W
RTR
ACK
: Dominant for no acknowledge from Transmitter
: Recessive from Transmitter
: Dominant from Transmitter
: Dominant from Transmitter- (*) Manchester bit
EXT
RAK
R/W
RTR
(*)
EXT
RAK
R/W
RTR
(*)
EXT
RAK
R/W
RTR
(*)
EXT
RAK
R/W
RTR
(*)
EOD
ACKACK
EOD
ACK
EOD
ACK
EOD
ACK
20 TSS463-AA 4205B–AUTO–12/04
Figure 18. Reply Request Frame with Immediate Reply
Figure 19. Reply Request Frame with Deferred Reply
(*)
SOF IDENTIFIER
RTR
FRAME
module
REQUESTED
module
R
EQUESTING
(*)
CRC
CRC
SOF IDENTIFIER DATA
DATA EOF
EOF
on bus
: Absent from Requestee and Posit ive fr om Requestor because RAK is Recessive
RAK
EXT
R/W
RTR
ACK
: Recessive for acknow ledge from Requestor
: Recessive from Requestor
: Recessive from Requestor
: Recessive from Requestor and Dominant from Requestee
- (*) Manchester bit
EXT
RAK
R/W
RTR
(*)
EOD
ACK ACK
EXT
RAK
R/W
RTR
EOD
ACK
SOF
RTR
IDENTIFIER
FRAME
on Bus
REQUESTING
(*)
CRC
CRC
SOF IDENTIFIER
EOF
EOF
Module
REQUESTED
Module
: Absent from Requestor and Positive from Requestee because RAK is Recessive
RAK
EXT
R/W
RTR
ACK
: Recessive for acknowledge from Requestor
: Recessive from Requestor
: Recessive from Requestor
: Recessive from Requestor - (*) Manchester bit
EXT
RAK
R/W
EOD
ACK
EOD
ACK ACK
RTR
EXT
RAK
R/W
(*)
21
TSS463-AA
4205B–AUTO–12/04
Figure 20. Deferred Reply Frame
F
RAME
o
n bus
m
odule
R
EPLYING
CRC
CRCSOF
SOF
IDENTIFIER
IDENTIFIER DATA
DATA EOF
EOF
R
ECEIVING
m
odule
: Absent from Replyer and Positive from Receiver because RAK is Recessive
RAK
EXT
R/W
RTR
ACK
: Recessive for acknowledge from Replyer
: Recessive from Replyer
: Recessive from Replyer
: Dominant from Replyer - (*) Manchester bit
EXT
RAK
R/W
EOD
ACK
EOD
ACK ACK
EXT
RAK
R/W
(*) (*)
RTRRTR
22 TSS463-AA 4205B–AUTO–12/04
Diagnosis System The purpose of the diagnosis system is to detect any short or open circuits on either the
DATA or DATA line s and to per mit, if it is pos sible, to c arry the c ommuni cations on the
non-defective line.
The diagnosis system is based on the assumption that three separate line receivers are
connected to the VAN bus see Figure 1:
• One of the line receivers is connected in differential mode, sensing both DATA and
DATA signals, and is connected to the RxD0 input.
• The other two line receivers are operating in single wire mode and are sensing only
one of the two VAN bus signals:
– The line receiver sensing DATA is connected to RxD1
– The line receiver sensing DATA is connected to RxD2
The diagnosis system analyzes and compares the data sent over both VAN lines. So,
the diag nos is sy ste m ex ecutes a d igi tal fi lt er ing an d tra nsiti on an aly s es. In or de r to pe r-
form its inv estigation, three internal signa ls are generated, RI (Return to Id le), SDC
(Synchronous Diagnosis Clock) and TIP (Transmission In Progress).
One of four operating modes c an be chosen to manage the results of the diagnosis
system.
Diagnosis States If the diagnosis system finds a fail ure on any of the VAN bus signals , it changes from
nominal to degraded mode, and connects the line receiver not coupled to the failing sig-
nal to the reception logic.
When the diagnosis system finds that the failing signal is working again, it returns to
nominal mode and re-connects the differential line receiver to the reception logic.
A major error occurs when both the VAN bus signals failed.
Figure 21. Diagnosis States
Nominal
Degraded
Data Degraded
Data
Major
Error
- Failure during the frame
- Default of transitions on the valid input between 2 consecutive SDC rising edges.
- Protocol fault
-In specified selection mode, every RI pulse when an EOF is detected or through an active SDC.
-In automatic selection mode and SDC active, no failuresampled by 2 consecutive SDC rising edges
.
-General Reset
23
TSS463-AA
4205B–AUTO–12/04
Status bits give permanent information on the diagnosis performed, whatever the pro-
grammed operating mode. This is encoded over three bits: Sa, Sb and Sc.
• Sa and Sb bits indicate the four possible states of the VAN bus.
Table 3. Status Bits: Sa and Sb
• Sc: As soon as one of the three inputs (RXD2, RXD1, RXD0) differs from the others
in the input comparison analysis performed by the diagnosis system, Sc is set.
The only way to reset this status bit is through the RI signal or a general reset.
Internal Operations
Digital Filtering If several spurious pulses occur during one bit, the diagnosis for defective conductor
may occur. To avoid such errors, digital filters are implemented.
Filtering operation is based on sampling of the comparator output signals. A transition is
taken into account only if it is observed over five samples (1/16th of timeslot).
Transition Analyses These analyses are continuously done on the effective edges on comparators after digi-
tal filtering.
•Asynchronous diagnosis
The asynchronous diagnosis is done by comparing the number of edges on DATA
and DATA.
If four edges are detected on one input and no edges on the other during the same
period, the second input is considered faulty and the diagnosis mode will change to
one of the degraded modes.
•Synchronous diagnosis
The synchronous diagnosis counts the number of edges on the data input
connected to the reception logic during one SDC period.
If there are less than four edges during one SDC period, the diagnosis mode will
change to the major error mode.
Sa Sb Communication
0 0
Mode Nominal
Fault No fault on VAN bus
Status Differential communication on DATA and DATA
0 1
Mode Degraded on DATA
Fault Fault on DATA
Status Communication on DATA
1 0
Mode Degraded on DATA
Fault Fault on DATA
Status Communication on DATA
1 1
Mode Major e rror
Fault Fault on DATA and DATA
Status No com munication on DATA and DATA (attempt to communicate
alternatively on DATA then DATA every SDC period)
24 TSS463-AA 4205B–AUTO–12/04
•Transmission diagnosis
The transmission compares RxD1 and RxD2 inputs (through the input comparators
and the filters) with the data transmi tted on TxD output.
At a time when the transmission logic generates a dominant - recessive transition,
the inputs can give different values. Taking into account the filtering delay, the bus
line seen as dominant is assumed to be correct, the other one, recessive, is
considered faulty. The diagnosis mode is changed to reflect that.
•Protocol fault
The protocol fault is detected by counting the number of consecutive dominant
timeslots.
If eight consecutive timeslots are dominant, the diagnosis mode will change to the
major error mode.
Generation of Internal
Signals
RI Signal (Return to Idle) This signal is used to return to nominal mode in the three specified selection modes (see
“Diagnosis States” on page 22 and “ Progr a mmi ng Mod es” on pag e 25). The RI signal is
disabled in automatic selection mode.
The RI signal is a pulse generated when an EOF is detected. Thus, at the end of each
frame, regarding the diagnosis status bit Sa, Sb and Sc, the user can m ake its own
choice.
SDC Signal (Synchronous
Diagnosis Clock) This time base is used by diagnosis system in automatic selection mode (see
Section “Pr ogra mmi ng Mod es ”, page 25) when no event is recorded on the bus.
The S DC is gene rated eithe r by a spec ial SD C divide r conne cted t o the tim eslot c lock,
or can be performed manually. The SDC clock period must be long compared to the
timeslot duration.
A typical SDC period should be greater than the maximum frame length appearing on
the VAN network.
TIP Signal (Transmission in
Progress) This signal must be enabled to allow the transmission diagnosis (see Section “Transition
Analyses”, page 23).
The TIP turns on synchronously with the beginning of the transmission:
• for asynchronous bus access, the beginning of SOF;
• for synchronous bus access, the beginning of the identifier field; and
• for a request of in frame reply, the RTR bit of the command field.
The TIP turns off synchronously with the end of the transmission:
•after EOF;
• after a losing of arbitration or a code violation detection; and
• for a requestor of in frame reply, when the arbitration is lost on RTR the bit.
This signal is not generated when the transmission logic only sends an ACK.
25
TSS463-AA
4205B–AUTO–12/04
Programming Modes Four program ming mod es determi ne how to use the three different inp uts and the di ag-
nosis system.
• 3 specified selection modes
• 1 automatic selection m ode
Table 4. Programming Modes
Ma Mb Operating Mode
0 0 Diff erential communication
0 1 Degraded communication on RxD2 (DATA)
1 0 Degraded communication on RxD1 (DATA)
1 1 Automatic selection according the diagnosis status
26 TSS463-AA 4205B–AUTO–12/04
Registers
The TSS463AA memory map consists of three different areas, the Control and Status
registers, the Channel registers and the Message data (or Mailbox).
Mapping
Figure 22. Memory Map
Notes: 1. All the non-specified addresses between 0x00 and 0x7F are considered as absent.
2. (r) means read-only register.
(w) means write-only register.
(r/w) means read/write register.
3. Value after RESET is found after register name. If no value is given, the register is not initialized at RESET.
0x70 to 0x77 (r/w)
Reserved
0x7C and 0x7D Reserved
Channel 90x58 to 0x5F (r/w)
Channel 100x60 to 0x67 (r/w)
0x17 (r/w)
Channel 20x20 to 0x27 (r/w) 0x10 (r/w)
0x28 to 0x2F (r/w)
Channel 5
0x78 (r/w)
0x79 (r/w)
0x7A (r/w)
0x7B (r/w)
Channel 13
0x78 to 0x7F (r/w)
0x38 to 0x3F (r/w)
ID_Mask [11..4]
ID_TAG [11..4]
ID_Mask [3..0]
0x11 (r/w)
0x12 (r/w)
0x13 (r/w)
0x14 and 0x15
0x16 (r/w)
Line Control (0x00)
0x01 (r/w) Transmit Control (0x02) 0x81 Data Byte 1
Diagnosis Control (0x00)
Command (0x00)
Line Status (0bx01xxx00)
Transmit Status (0x00)
Last Message Status (0x00)
Last Error Status (0x00)
Reserved
Interrupt Status (0x80)
Interrupt Enable (0x80)
0x00 (r/w)
0x02 (r/w)
0x03 (w)
0x04 (r)
0x05 (r)
0x06 (r)
0x07 (r)
0x08
0x09 (r)
0x0B (w) Interrupt Reset
0x0A (r/w)
0xFF Data Byte 127
0x80
0x82
0x83
0x84
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
Data Byte 0
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
Data Byte 8
Data Byte 9
Data Byte 10
Data Byte 11
Data Byte 12
Channel 4
Channel 8
Channel 6
Channel 12
Channel 1
Channel 11
Channel 7
Reserved
0x10 to 0x17 (r/w)
0x30 to 0x37 (r/w)
0x50 to 0x57 (r/w)
0x40 to 0x47 (r/w)
0x18 to 0x1F (r/w)
0x68 to 0x6F (r/w)
0x48 to 0x4F (r/w)
0x0C to 0x0F
Register Message
ID_TAG [3..0] + COM
DRAK + Message Address
Message Length + Status
Reserved
Channel 0 Registers
Channel 0
ID_TAG (lsb) + COM
ID_TAG (msb)
DRAK + Message Address
Message Length + Status
0x7E (r/w)
Channel 13 Registers
ID_Mask [11..4]
0x7F (r/w) ID_Mask [3..0]
ID_Mask [11..4]
Channel 3
Channel 13
Channel 2
0x17 (r/w)
27
TSS463-AA
4205B–AUTO–12/04
Control and Status Registers
Line Control Register (0x00)
• Read/write register.
• Default value after reset: 0×00
• Reserved: Bit 2, this bit must not be set by the user; a 0 must always be written to
this bit.
CD[3:0]:Clock Divider They contr o l th e VA N B us ra te th rough a B aud Rate gene ra tor ac c ordin g to the fo r mul a
below:
PC: Pulsed Code One: The TSS463AA will transmit and receive data using the pulsed coding mode (i.e
optical or radio link mode). The use of this mode implies communication via the RxD0
input and the non-functionality of the diagnosis system.
Zero: (Default at reset). The TSS463AA will transmit and receive data using the
Enhanced Manchester code. (RxD0, RxD1, RxD2 used).
IVTX: Invert TxD output
IVRX: Invert RxD inputs The user can invert the logical levels used on either the TxD output or the RxD inputs in
order to adapt to different line drivers and receivers.
One: A one on either of these bits will invert the respective signals.
Zero: (Default at reset ). The TSS463 AA will set TxD to recessive sta t e in Idle mode and
consider the bus free (recessive states on RxD inputs).
Transmit Control Register
(0x01)
Read/Write re gist e r.
Default value after reset: 0x02
MR[3:0]: Maximum Retries These bits allow the user to c ontrol the amount of retries the circuit wil l perform if any
errors occurred during transmission.
76543210
CD3 CD2 CD1 CD0 PC 0IVTX IVRX
fTSCLK()
fXTAL
1
()
n16×
-------------------------
=
76543210
MR3 MR2 MR1 MR0 VER2 VER1 VER0 MT
28 TSS463-AA 4205B–AUTO–12/04
Table 5. Retries
Note: Bus contention is not regarded as an error and an infinite number of transmission
attempts will be performed if bus contention occurs continuously.
VER[2:0] = 001 DLC Version after reset.
These bits must not be set by user. 001 must always be written to these bits.
MT: Module type
The three differ ent mod ule types are suppor te d (see “VAN Frame” on page 15):
One: The TSS463AA is at once an autonom ous module (Rank 0 ), a synchronous
access module (Rank 1) or a slave module (Rank 16).
Zero: The TSS463AA is at once an synchronous access module (Rank 1) or a slave
module (Rank 16).
MR [3: 0] Max. # of retries Max. # of transmissions
0000 0 1
0001 1 2
0010 2 3
0011 3 4
0100 4 5
0101 5 6
0110 6 7
0111 7 8
1000 8 9
1001 910
1010 10 11
1011 11 12
1100 12 13
1101 13 14
1110 14 15
1111 15 16
29
TSS463-AA
4205B–AUTO–12/04
Diagnosis Control Register (0x02)
• Read/Write register
• Default value after reset: 0×00.
The diagnosis is discussed in greater detail in the section “Diagnos is Syste m” o n page
22.
• In its four high order bits, the user can program the SDC rate SDC [3:0]
• In its two medium order bits, the diagnosis system mode is controlled: M1, M0.
• In the two low order bits, the user controls if the SDC and TIP are to be generated
automati c all y ETIP, ESD C.
SDC [3:0]: SDC divider
The input clock is the timeslot clock.
Table 6. System Diagnosis Clock Divider
76543210
SDC3 SDC2 SDC1 SDC0 Ma Mb ETIP ESDC
SDC DIVIDER SDC [3:0] Divide by
0000 64
0001 128
0010 256
0011 512
0100 1024
0101 2048
0110 4096
0111 8192
1000 16384
1001 32768
1010 65536
1011 131072
1100 262144
1101 524288
1110 1048576
1111 2097152
SDC calculation: (see “SDC Signal (Synchronous Diagnosis Clock)” on page 24).
Notes: 1. For each module, determine the largest interframe spacing, LIFS (*).
2. For the whole network, get the maximum LIFS, MAX-LIFS.
3. SDC period > MAX-LIFS.
(*) IFS min. = 4 TS
Example: For VAN frame speed rate = 62,5 KTS/s (1 TS = 16 µs), SDC >100 ms
=> 100 ms / 16 µs = 6250, divider chosen: 8192, SDC [3:0] = 0111.
30 TSS463-AA 4205B–AUTO–12/04
Ma, Mb: Operating Mode
Command Bits Table 7. Diagnosis System Command Bits
ETIP: Enable Transmission In
Progress The Transmission In Pr ogress (TIP) tells the diagnosis system to enable transmission
diagnosis.
One: Enable TIP generation
Zero: Disable TIP generation.
ESDC: Enable System
Diagno si s C lo ck The S ynchronou s Diagno sis Clock ( SDC) cont rols the cy cle time of t he synchr onous
diagnosis.
One: Enable SDC divider.
Zero: Disable SDC divider.
Command Register (0x03)
• Write only register.
• Reserved: Bit 1, 2 these bits must not be set by the user; a zero must always be
written to these bit.
• If the circuit is operating at low bitrates there might be a considerable delay between
the writing of this register and the performing of the actual command (worst case 6
timeslots). The user is therefore recommended to verify, by reading the Line Status
Register (0x04), that the commands have been performed.
GRES: General Reset The Reset circuit command bit performs, if set, exactly as if the external reset pin was
asserted. This command bit has its own auto-reset circuitry.
One: Reset active
Zero: Reset inactive
SLEEP: Sleep Command (See Section “S leep Command”, page 52).If the user sets the Sleep bit, the circuit will
enter sl eep mod e. When the circ uit is in s leep m ode, all non-u ser reg isters are setup to
minimize power consum ption. Read/write accesses to the TSS463AA via the S PI/SCI
interface are impossible, the oscillator is stopped.
To exit from this mode the us er must apply either an hardware reset (external RESET
pin) or an asynchronous software reset (via the SPI/SCI interface).
One: Sleep active
Zero: Sleep ina cti ve
Ma Mb
0 0 Forces the Communication on RxD0 (differential)
0 1 Forces the Communication on RxD2 (DATA)
1 0 Forces the Communication on RxD1 (DATA )
1 1 Automatic select ion
76543210
GRES SLEEP IDLE ACTI REAR 0 0 MSDC
31
TSS463-AA
4205B–AUTO–12/04
IDLE: Idle Command (See Section “Idle and Activate Commands”, page 52). If the user sets the Idle bit, the
circuit wil l enter idle mode. In idl e mode the oscillator will opera te, but the TSS463AA
will not transmit or receive anything on the bus, and the TxD output will be in three state.
One: Idle active
Zero: Idle inactive
ACTI: Activate Command (See Section “Idle and Activate Commands”, page 52). The Activate command will put
the ci rcuit in the a ctive mo de, i. e it will tra nsmit and rece ive nor mally on th e bu s. W hen
the circuit is in activate mode the TxD three-state output is enabled.
One: Activate active
Zero: Activate inactive
REAR: Re-Arbitrate Command This com man d wi ll , aft er the cu rrent attemp t, r eset th e r etr y c ount er and re- arbit ra te th e
messages to be transmitted in order to find the highest priority message to transmit.
One: Re-arbitrate active
Zero: Re-arbitrate inactive
MSDC: Manual System
Diagno si s C lo ck Rather than using the SDC divider described in Section “Mes sage Da ta (str ing poi nted
by: Message Pointer Register + 1)”, page 44, the user can use the manual SDC com-
mand to generate a SDC pulse for the diagnosis system.
This MSDC pulse should be high at least 2 timeslot clocks.
Line Status Register (0x04)
• Read only register
• Default value after reset: 0bx01xxx00.
• This register reports the operation mode of the TSS463AA in the Sleep an Idle bits
(Command Register located at address 0×03) as well as the diagnosis system
status bits Sa to Sc discussed in the section “Diagnosis System” on page 22.
SPG: Sleeping
IDG: Idling Default mode at reset
Sa, Sb and Sc: Diagnosis
System Status Bits • Sa and Sb
Diagnosis System Status Bits
76543210
XSPG IDG Sc Sb Sa TXG RXG
Sb Sa Communication Indication
0 0 Nom inal mod e, differential communication
0 1 Degraded over DATA, fault on DATA
1 0 Degraded over DATA, fault on DATA
1 1 Major error, fault on DATA and DATA
32 TSS463-AA 4205B–AUTO–12/04
•Sc: As soon as one of the three inputs (RxD2, RxD1, RxD0) differs from the others
in the input comparison analysis performed by the diagnosis system, Sc is set.
The only ways to reset this status bits through the RI signal or a general reset.
TXG: Transmitting If this status bit is active, it indicates that the TSS463AA has chosen an identifier to
transm it, and it will continue to ma ke transmis sion atte mpt for this mes sage until it suc-
ceeds or the retry count is exceeded.
RXG: Receiving The receiving indicates that there is activity on the bus.
Note: For safe modification of active channel registers both bits should be inactive
(except “abort ” command).
Transmission Status Register
(0x05)
• Read only register.
• Default value after reset: 0x00.
• The transmission Status register contains the number of retries made up-to-date,
according tothe table above, and the channel currently in transmission.
NRT [3:0]: Number of retries done in transmission.
IDT [3:0]: Channel number currently in transmission.
Last Message Status Register
(0x06)
• Read only register.
• Default value after reset: 0x00.
• This register is basically the same as the transmission status register . It contains the
last identifier number that was successfully transmitted, received or exceeded its
retry count.
If it was a successful transmission, the number of retries performed can be seen in
this register as well.
NRTR [3:0]: Number of retries done successfully in transmission. In case of reception NRTR[3:0] is
undefined.
IDTR [3:0]: Channel number that was successfully transmitted, received or exceeded its retry count.
76543210
NRT3 NRT2 NRT1 NRT0 IDT3 IDT2 IDT1 IDT0
76543210
NRTR3 NRTR2 NRTR1 NRTR0 IDTR3 IDTR2 IDTR1 IDTR0
33
TSS463-AA
4205B–AUTO–12/04
Last Error Status Register (0x07)
• Read only register.
• Default value after reset: 0×00.
• The Last Error Status Register contains the error code for the last transmission or
reception attempt. It is updated after each attempt, i.e., several error codes can be
reported during one single transmission (with several retries).
BOC: Buf fer Occ up ie d • when one channel configured in “Reply request” mode has its “received” bit set
when it attempts to transmit its request.
• BOC with the link capability between two channels sharing the same received
buffer, is set when one channel has already set its “received” bit in its “Message
length and status Channel register” and a receive is attempt on the other one.
One: BOC active
Zero: BOC inactive
BOV: Buffer Overflow BOV indicates that the buffer length setup in the Channel Status Register was shorter
than the number of bytes received plus 1, and thus, some data was lost.
One: BOV active
Zero: BOV inactive
FCSE: Framing Check
Sequence Error FCSE indicates a mismatch between the FCS received and the FCS calculated
One: FCSE active
Zero: FCSE inactive
ACKE: Acknowledge Error ACKE indic ates a phy sical violation or collision o n ACK field of the frame when the
TSS463AA is a producer.
One: ACKE active
Zero: ACKE inactive
76543210
XBOC BOV XFCSE ACKE CV FV
34 TSS463-AA 4205B–AUTO–12/04
Figure 23. ACKE Status bit
CV: Code Violation CV indicates:
• either a Manchester code violation (2 identical TS on Manchester bit), or a physical
violation (transmitted bit “dominant”, received bit “recessive”), on fields ID, COM,
DATA and CRC.
• or a physical violation or collision on field “preamble” and the “recessive” bit of the
“Star Sync” field.
One: CV active
Zero: CV inactive
FV: Frame Violation FV indicates a physical violation or collision on ACK field of the frame when the
TSS463AA is a consumer.
One: FV active
Zero: FV inactive
RAK* = 1
*RAK: Bit of the Frame COMMAND Field
ACKE = 0
ACKE = 1
ACKE = 1
ACKE = 1
ACKE = 0
ACKE = 1
ACKE = 1
ACKE = 1
EOD fi e l d ACK field
EOD field ACK field
Expected
Received
Received
Received
Expected
Received
Received
Received
DLC: ProducerRAK = 0
35
TSS463-AA
4205B–AUTO–12/04
Figure 24. FV Status Bit
Interrupt Status Register (0x09)
• Read only register.
• Default value after reset: 1xx0 0000
RST: Reset Inter rupt RE indicates that the circuit has detected a valid reset command via the RESET pin or
the reset command bit GRES. This interrupt cannot be disabled, since its enable bit is
set when a reset is detected.
One: Status flag activated
Zero: No status flag.
TE: Transmit Error Status Flag
(or Exceeded Retry) This flag is set only when the Max number of transmission (1 + MR [3:0]) is reached with
error o f transmission.
One: Status flag activated
Zero: No status flag.
Figure 25. Exceeded Retry with MR[3..0] = 3
FV = 0
FV = 1
FV = 1
FV = 1
FV = 0
FV = 1
FV = 1
FV = 1
EOD field ACK field
EOD field ACK field
Expected
Received
Received
Received
Expected
Received
Received
Received
DLC: Consumer
76543210
RST X X TE TOK RE ROK RNOK
1st TX 2nd TX 3rd TX set TE
set CHER
set CHTx
36 TSS463-AA 4205B–AUTO–12/04
TOK: Transmit OK Status Flag One: Status flag activated
Zero: No status flag.
RE: Receive Error Status Flag One: Status flag activated
Zero: No status flag.
ROK: Receive “with RAK
(RAK=1)” OK Status Flag One: Status flag activated
Zero: No status flag.
RNOK: Receive “with no RAK
(RAK=0)” OK Status Flag One: Status flag activated
Zero: No status flag.
Interrupt Enable Register (0x0A)
• Read/write register.
• Default value reset: 1xx0 0000
Note: On reset the Reset Interrupt Enable bit is set to 1 instead of 0, as is the general rule.
TEE: Transmit Error Enable One: IT enabled.
Zero: IT disabled.
TOKE: Transmission OK Enable One: IT enabled.
Zero: IT disabled.
REE: Reception Error Enable One: IT enabled.
Zero: IT disabled.
ROKE: Reception “with RAK”
OK Enable One: IT enabled.
Zero: IT disabled.
RNOKE: Reception “with no
RAK” OK Enable One: IT enabled.
Zero: IT disabled.
Interrupt Reset Register (0x0B):
• Write only register.
• Reserved bit: 5 and 6. This bit must not be set by user; a zero must always be
written to this bit.
76543210
1 X X TEE TOKE REE ROKE RNOKE
76543210
RSTR 0 0 TER TOKR RER ROKR RNOKR
37
TSS463-AA
4205B–AUTO–12/04
RSTR: Reset Interrupt Reset One: Status flag reset.
Zero: Status flag unchanged.
TER: Transmit Error S t atus Flag
Reset One: Status flag reset.
Zero: Status flag unchanged.
TOKR: Transmit OK Status Flag
Reset One: Status flag reset.
Zero: Status flag unchanged.
RER: Receive Error St atus Flag
Reset One: Status flag reset.
Zero: Status flag unchanged.
ROKR: Receive “with RAK” OK
Status Flag Reset One: Status flag reset.
Zero: Status flag unchanged.
RNOKR: Receive “with no RAK”
OK Status Flag Reset One: Status flag reset.
Zero: Status flag unchanged.
Figure 26. Update of the Status Register
RST TE TOK RE ROK RNOK
Flag
Write Flag
Write Flag
Write Flag
Write Flag
Write
IN
T
RSTR TOKR RER ROKR RNOKRTER
TOKE REE ROKE RNOKETEE
Interrupt Statu
s
Register
Interrupt Enab
le
Register
Interrupt Rese
t
Register
Pin 3
I
nternal
R
ESET
Reset RXG, TXG
Line Status Register (0x04
)
4 TS
Set RXG
Set TXG
4 TS 1 to 2 TS 6 TS
SOF ID+COM+DATA+CRC
EOD
ACK
BUS
INT
Write “IT Status Register”
Write “Last error Register”
Write “Last message Register”
Write “Message Length and Status Register”Write “Message Status”
38 TSS463-AA 4205B–AUTO–12/04
Channel Registers Ther e is a tota l of 14 chann el regis ter sets , each o ccupyi ng 8 byt es for address ing sim -
plicity, integrated into the circuit. Each set contains two 2 x 8-bit registers for the
identifier tag, id entifier mask and c ommand fields plus two 1 x 8-bit register s for DMA
pointers and message status.
The base_address of each set is:
(0x10 + [0x08 * channel_number]).
When the TSS463AA is reset either via the external RESET pin or the general reset
command , the channel regis ters are not affected. T hat is, on power-up of the cir cuit, all
the channel registers start with random values.
Due to this fact, the us er should take care to initialize al l the chan nel register s before
exiting from idle mode. The easiest way to disable a channel register is to set the
received and transmitted bits to 1 in the Message Length and Status Register.
Table 8. Chann el Regi st er Sets Map
Table 9. Channel Register Set Structure
Channel Number from to Channel Number from to
60x40 0x47 13 0x78 0x7F
50x38 0x3F 12 0x70 0x77
40x30 0x37 11 0x68 0x6F
30x28 0x2F 10 0x60 0x67
20x20 0x27 90x58 0x5F
10x18 0x1F 80x50 0x57
00x10 0x17 70x48 0x4F
Reg. Name Offset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 bit 0
ID_MASK 0x07 ID_ M [3: 0 ] x x x x
ID_MASK 0x06 ID_M [11:4]
(No register) 0x05 x x x x x x x x
(No register) 0x04 x x x x x x x x
MESS_L/
STA 0x03 M_L [4:0] CHER CHTx CHRx
MESS_PTR 0x02 DRACK M_P [6:0]
ID_TAG/
CMD 0x01 ID _ T [3 : 0 ] EXT RAK RNW RTR
ID_TAG 0x00 ID_T [11:4]
39
TSS463-AA
4205B–AUTO–12/04
Identifier Tag and Command
Registers The identifier tag and command registers are located at the base_address and
base_address + 1. It allows the user to specify the full 12-bit identifie r field of the ISO
standard and the 4-bit command.
• Read/Write registers.
ID_T [11:0]: Identifier Tag Upon a reception hit (i.e, a good comparison between the identifier received and an
identifi er specifi ed, taki ng the c omparison mask i nto acco unt, as w ell as a s tatus an d
command indicating a message to be received), the identifier tag bits value will be
rewritten with the identifier bits actually received.
EXT, RAK, RNW and RTR (See Section “Message Types”, page 45). No comparison will be done on the command
bits, except on EXT bit. The RAK, RNW and RTR bits will be written into the first byte of
the Message upon a reception hit.
The RNW and RTR bits, as well as the status bits in the length and status register, must
be in a valid position for reception or transmission. If not, the message corresponding to
this identifier is considered as inactive or invalid.
The way of knowing if an acknowledge sequence was requested or not is to check the
first byte of the Message.
Message Pointer Register The message pointer register at address (base_address + 0x02) is 8 bits wide. It indi-
cates where in the Message DATA RAM area the message buffer is located.
• Read/Write register.
DRAK: Disable RAK (Used in
‘Spy Mode’) In reception: whatever is the RAK bit of the incoming valid frame, no ACK answer will be
set. If the message was successfully received, an IT is set (ROK or RNOK).
In transmission: no action.
One: disable active, “spy mode”.
Zero: disable inactive, normal operation.
M_P [6:0]: Message Pointer Since the Message DATA RAM area base address is 0x80, the value in this register is
the offs et fr om t hat ad dress . If t he me ssag e buf fer length val ue i s illega l (i.e. z ero), this
register is redefined as being a link pointer, thus containing the channel number of the
channel tha t c onta in s t he a ct ual me ss ag e po in ter , m ess ag e l eng th a nd re ce iv ed sta tus .
However, the ide ntifier, m ask, error and t rans mitted s tatus us ed will be that of the orig i-
nally ma tch ed c ha nnel . In a ny case, if a l ink is in tend ed, the three high bi ts of M_ P [6: 0]
should be set to 0.
7 6 5 4 3 2 1 0
ID_T 3 ID_ T 2 ID_T 1 ID_T 0 EXT RAK RNW RTR base_address
+ 0x01
7 6 5 4 3 2 1 0
ID_T 11 ID_T 10 ID_T 9 ID_T 8 ID_T 7 ID_T 6 ID_T 5 ID_T 4 base_address
+ 0x00
7 6 5 4 3 2 1 0
DRAK M_P 6 M_P 5 M_P 4 M_P 3 M_P 2 M_P 1 M_P 0 base_address
+ 0x02
40 TSS463-AA 4205B–AUTO–12/04
This allo ws s ev eral cha nne ls to us e the sam e ac tual re ce ption buffer in M essag e DA TA
RAM, thus diminishing the memory usage.
Note: Only 1 level of link is supported.
Message Length And Status
Register The message length and status register at address (base_address + 0x03) is also 8 bits
wide. It ind icates the leng th of reserved for the mess age in the Mess age DATA RAM
area.
• Read/Write register.
M_L [4:0]: Message Length The 5 high bits of this register allows the user to specify either the length of the message
to be transmitted, or the maximum length of a message receivable in the pointed recep-
tion buffer.
Note: T he fir st b yte in thi s regis te r does not con tain da ta, b ut t he l eng th o f the mess ag e
received . Thi s implie s that t he leng th val ue has to b e eq ual to or g reate r than the m axi-
mum length of a message to be received in this buffer (or the length of a message to be
transm itted) plu s 1, thus allowi ng a maximum len gth of 30 bytes an d a minimum le ngth
of 0 byte.
If the value of this field is “illegal” (i.e 0x00) then this message pointer is defined as
being a link (see Message pointer and register and “Linked Channels” on page 53).
Note: Different of a reply request frame with no in-frame reply (deferred reply).
CHER: Channel Error Status
and Abort Command As stat us, this bit is set by the TSS463AA when erro r occurs i n transmi ssion or on a
received frame. The user must reset it.
To abort the transmission defined in the channel, this bit can be set to 1 by the user (see
Section “Activate, Idle and Sleep Modes”, page 52 and “Abort” on page 50).
CHTx: Channel Transmitted and
Transmit Enable Command
CHRx: Channel Received and
Receive Enable Command The 2 low order bits of this register contain the message status. Together with the RNW
and RTR bits of the command register (base_address + 0x01), they define the message
type of this channel (see section “Message Types” on page 45). As a general rule, the
status bits are only set by the TSS463AA, so the user must reset them to perform a
76543210
M_L 4 M_L 3 M_L 2 M_L 1 M_L 0 CHER CHTx CHRx base_address
+ 0x03
M_L [4:0] = 0x00 Linked channel
M_L [4:0] = 0x01 Frame with no DATA field (*)
M_L [4:0] = 0x02 Frame with 1 DATA byte
- - - - - - - - - - - - - - - - - - - - - - - - - - - - -
M_L [4:0] = 0x1D Frame with 28 DATA bytes
M_L [4:0] = 0x1E Frame with 29 DATA bytes
M_L [4:0] = 0x1F Frame with 30 DATA bytes
41
TSS463-AA
4205B–AUTO–12/04
transmission (CHTx) or/and a reception (CHRx). The received and transmitted bits are
only set if the corresponding frame is without errors or if the retry count has been
exceeded.
Identifier Mask Registers The Ident ifier Mas k register s (base_a ddress + 0x06 and b ase_add ress + 0x07) allow
bitwise masking of the comparison between the identifier received and the identifier
specified.
• Read/Write registers.
ID_M [11:0]: Identifier Mask A value of 1 indicates comparison enabled.
A value of 0 indicates comparison disabled.
Example:
– ID_M[11:0] = 0x0FF8
– Acceptance: ID’s from 0x0FF8 up to 0x0FFF
76543210
ID_M 3 ID_M 2 ID_M 1 ID_M 0 xxxxbase_address
+ 0x07
76543210
ID_M 11 ID_M 10 ID_M 9 ID_M 8 ID_M 7 ID_M 6 ID_M 5 ID_M 4 base_address
+ 0x06
42 TSS463-AA 4205B–AUTO–12/04
Mailbox The mailbox contains all the messages received or to be transmitted. Each messages is
link to a ch annel. The Ma ilbox RAM area has 12 8 bytes and is map ped from 0x80 to
0xFF (see Section “Mapping”, page 26 ).
The message (o r mess age buff er) is compo se d of:
• 1 byte of message status (only used in receiving),
• n bytes of data. These data are the bytes of the DATA field of the frame with the
same organization.
The message is pointed by the Message Pointer Register of the channel, the length of
the mes sage i s given by th e Mess age Leng th and St atus Reg ister o f the chan nel. Thi s
area is a pure RAM, it contains a random value after reset.
Figure 27. Message Buffer Structure for Reception
CHER CHTx CHRx Message Pointer Register
DRAK M_P [6..0]
Message Length and Status Register
M_L [4..0]
RTRRNWRAK M_L [4..0] = n+1
receivedreceivedreceived received
DATA 0
Message
RTR
RNW
ID [11..0]
EXT
SOF DATA 0 DATA n FCS
EOD
ACK
EOF
Received DATA Frame, immediate or deffered reply
Received
DATA nReceived M_P + 0x80 + n + 2
( M_L >= n + 2 )
M_P + 0x80
RAK
43
TSS463-AA
4205B–AUTO–12/04
Figure 28. Message Buffer Structure for Transmission
Message Status (Pointed
by: Message Pointer
Register)
• (no significant value in case of message to be transmitted)
RRAK: Received RAK Bit This bit is the RAK bit coming from the COM field of the received frame.
RRNW: Received RNW Bit This bit is the RNW bit coming from the COM field of the received frame.
RRTR: Received RTR Bit This bit is the RTR bit coming from the COM field of the received frame.
RM_L[4:0]: Message Length of
the Received Fra me If the DATA fie ld of th e rece ived fram e included DATA0 to DATAn, R M_L[4:0] = n+1,
even if the reserved length (Message Length and Status Register) is larger.
CHER CHTx CHRx Message Pointer Register
DRAK M_P [6..0]
M
essage Length & Status Register
M_L [4..0]
DA TA 0
Message
RTR
RNW
RAK
ID [11..0]
EXT
SOF DATA 0 DATA n FCS
EOD
ACK
EOF
Transmitted DATA Frame
Transmitted
DATA n
Transmitted M_P + 0x80 + n + 2
( M_L >= n + 2 )
M_P + 0x80
(Nothing)
76543210
RRAK RRNW RRTR RM_L4 RM_L3 RM_L2 RM_L1 RM_L0
44 TSS463-AA 4205B–AUTO–12/04
Figure 29. Message Status Updating
Message Data (string
pointed by: Message
Pointer Register + 1)
DATA0 is the first received (or transmitted) byte, DATAn is the last one.
Note: 1. If the length reserved (in the message length and status register) for an incoming
frame is 2 bytes greater or more, the TSS463AA will write the 2 bytes of the CRC
field in the message string just after DATAn.
Because the VAN frame does not content a message length, the only way for the
component to know the length of the DATA field is either the message length register
value, either the EOD field detection. When the reserved length is too large, at the
moment when it detects the EOD, the TSS463AA has already written the 2 bytes of
the CRC field, considering these bytes as normal DATA.
2. The Mailbox RAM area is a circular buffer. The next location after 0xFF is 0x80.
Data Frame
Immediate
Reply
I, P C
Fram e Type
Node x Message Status on Node A after IT(*)
Commu- Node A
RAK RNW RTR length
previous
value
I, C P
RAK
RNW RTR
Deferred
Reply previous
value
I, C P
RAK RNW RTR
Data Frame
I, PC
Immediate
Reply
I, CP
RAK RNW RTR length
Deferred
Reply
I, CP
RAK RNW RTR length
previous values
P: Producer I: Initiator C: Consumer
(*) After IT ROK or RNOK. In case of IT RE, the values can be erroneous.
nication
76543210
DATAn
- - - - - - - - - - - - - - - - - - -- - - - - -
DATA0
45
TSS463-AA
4205B–AUTO–12/04
Message Ty pes There are 5 b asic message ty pes define d in th e TSS463AA . Two of them (transm it and
receive message types) correspond to the normal frame, and the rest correspond to the
different versions of reply frames.
To transmit a normal data frame on the VAN bus, the user must program an identifier as
a Transmi t Message . The TSS463 AA will then tra nsmit this message on the bu s until it
has succeeded or the retry count is exceeded.
The opposite of the transmit message type is the Receive Message type. This message
type will not generate any frames on the bus. Instead it will listen to the bus until a frame
passes that matches its i dentifier, with the mas k taken into a ccount, and then receiv e
the data in that frame.
The data received will be stored in the message buffer and the length of the message
received is stored in the first byte of the message buffer.
The act ual identif ier rece ived is sto red in the ide ntifier r egister its elf. This i dentifier may
differ from the identifier specified in the register due to the effect of the mask register.
Normally this should not interfere with the next identifier comparison since the bits that
may differ are masked via the mask register.
The Reply Request Message type is a demand to transmit on the VAN bus a reply
request. When this message type is programmed, three things can happen.
In the first case no other modules on the bus responded with an in-frame reply, and in
this case the TSS463AA will set the message type to the after transmission state. When
this message type is programmed, the TSS463AA will lis ten on the bus for a deferred
reply frame matching this identifier, without transmitting the reply request.
Transmit Messa ge
RNW RTR CHTx CHRx
Initial setup 0 0 0 Don’t care
After transmission 0 0 1 Unchanged
Receive Message
RNW RTR CHTx CHRx
Initial setup 0 1 Don’t care 0
After transmission 0 1 Unchanged 1
Reply Request Message
RNW RTR CHTx CHRx
Initial setup 1 1 0 0
After transmission
(Waiting for reply) 1 1 1 0
After reception
(of reply) 1 1 1 1
46 TSS463-AA 4205B–AUTO–12/04
The second case is that another module on the bus replies with an in-frame reply. In this
case the message type will pass immediately into the after reception state, without pass-
ing the after transmission state.
In the third case th e TSS4 63AA ha s not yet st arted to transm it the repl y reques t, when
another mo dul e ei ther r equ es ts a repl y , and ge ts i t, or tra ns mit s a de fer red r epl y. Warn-
ing! This should be avoided as it may result in an ill egal message type (I llegal reply
Request).
The imme diate Re ply Mes s age will atte mpt to tra ns mit an in -f ra me repl y , usi ng the da ta
in the message buffer.
Above a Deferred Reply Message is shown. This message type will immediately trans-
mit a deferred reply frame.
Finally ther e is the Reply Request Detector Message type . Its purpos e is to recei ve a
reply request frame and notify the processor, without transmitting an in-frame reply.
The table above shows all inactive messages types. The last combination will transmit a
reply request, but will not receive the reply since its buffer is tagged as occupied.
Reply Request Message without transmission
RNW RTR CHTx CHRx
Initial setup 1 1 Don’t care 0
After reception 1 1 Unchanged 1
Immediate Reply Message
RNW RTR CHTx CHRx
Initial setup 1 0 0 0
After transmission 1 0 1 1
Deferred Reply Message
RNW RTR CHTx CHRx
Initial setup 1 0 0 1
After reception
(of reply request) 1 0 1 1
Reply Request Detection Message
RNW RTR CHTx CHRx
Initial setup 1 0 1 0
After reception 1 0 1 1
Inactive Message
RNW RTR CHTx CHRx
Recommended Don’t care Don’t care 1 1
After transmission 0 0 1 Don’t care
After reception 0 1 Don’t care 1
Illegal reply request 1 1 0 1
47
TSS463-AA
4205B–AUTO–12/04
Priority Among the
Different Channels The priority handling on the VAN bus itself is already explained in the Line interface sec-
tion. The priorities for the messages in the TSS463AA is however slightly different.
For instance, it’s possible that an identifier matches two or more of the identifiers pro-
grammed into the registers. In this case, it is the lowest identifier number that has
priority. i.e., if both identifier 5 and 10 match the identifier received, it is the identifier 5
that will receive the message.
However, since the identifier 5 will become an inac tive message when it has received
the frame, the next time the same identifier is seen on the bus, the corresponding data
will be received by identifier 10.
The same is valid for messages to be transmitted, i.e. if two or more mes sages are
ready to be transmitted, it is the one with the lowest identifier number that will get
priority.
Retries, Rearbitrate and
Abort Retries and rearbitrate commands are located, respectively, in the Transmit Control
Register and in the Command Register. An abort command is located in each channel
regist er s et, in the Mess age Le ngt h a nd Sta t us Reg is ter (b ase_addr ess + 0x 03) . Thes e
three commands are available only when the TSS463AA is a producer.
Figure 30. Transmit Function
Activate
Ch. Enabled in
Xmit Mode ? No
Select the Lowest
Ch. Number and
Load ”Max - Retries”
Yes
Abor t Activated
on Current Ch. ?
Yes
Disable of
Current Ch.
No
Wait for Bus Free
(EOF+IFS= 12 Timeslots)
Retry Needed ?
Abort
No
no
Abort Required
Rearbitrate?
on Current Ch. Rearbitrate
Yes
Transmit Frame
and Wait for the End
Decrement
Retry Counter
48 TSS463-AA 4205B–AUTO–12/04
Retries The purpose of the retries feature is to provide, for the user, the capability of retrying a
transmit request in case of failure, when a node tries to reach another node, either on
normal DATA frame or on REPLY REQUEST frame.
The maximum number of retries is programmable through MR[3:0] of the Transmit Con-
trol Register (0x01). When a channel is enable – bit CHTx = 0 of Message Length and
Status Register, a 4-bit counter is loaded with MR[3:0]. At each attempt, this counter will
count-down to 0, an IT TE is set in the Interrupt Status Register (0x09), and the trans-
mission is stopped.
MR[3:0] = 1 indicates 1 retry, hence 2 transmission attempts will be performed (see
Table 5, “Retries,” on page 28). The num ber o f re trie s p er for me d, a s we ll as the curre nt
channel number associated, can be read in the Transmission Status Register (0x05).
The Last Error Status Register (0x07) informs about the trouble uncounted:
• Failure cases:
– Code viol (CV error bit)
– Acknowledge error (ACKE error bit)
– CRC error (FCSE error bit)
• It should be noticed that contenti on is considered as normal CSMA/CD protocol
and, therefore, is not taken into account in failure cases. So, an 'infinite' number of
attempts can be performed if bus contention occurs continuously.
There is only one retr y counte r for al l channe ls. Whe n the us er writ es the Max _Retri es
value, all channels start their transmission with this parameter.
Rearbitrate The purpose of rearbitrate feature is to postpone a channel already in transmission in
order to autho rize an higher p riority ( see Se ction "P riority Among the Differ ent Chan-
nels", page 47) message to be transmit.
Typical Example • Max_retries = 1 (2 transmissions attempts).
• If Ch8 is in a the retry loop and the user wants to transmit the Ch5 without waiting
the end of the loop, the user can use the rearbitrate command.
• The TSS463AA will then wait until the end of the current transmission, reload the
retries counter and enable the Ch5 to transmit.
• At the end of this transmission Ch5, either when the attempt is successful or the
exceeded retry count is reached, the retries counter is reloaded and the
transmission is activated for the Ch8 again.
49
TSS463-AA
4205B–AUTO–12/04
Figure 31. Rearbritrate Example
Figure 32. Idle and Rearbitrate Example
If the user se ts the id le bit a nyw here ( after rear bit ra te), the idl e mo de i s e nter ed only at the end o f al l the tr ans mit atte mp ts
(for more information about idle command, see “Activate, Idle and Sleep Modes” on page 52.).
First attempt
Xmit Ch5
Ex: FCS Error
Rearbitrate
EOF+IFS
(Activate Ch5)
Delay
Set CHTx/Ch5 & IT ROK
Xmit Ch8 (Load Max-retries)
(Load Max-retries)
* (not seen by application)
(Load Max-retries)
Ex: FCS Error
(not seen by application)
stand-by
First attempt
Xmit Ch8
S
econd attempt
Xmit Ch8
(Retries - 1)
Delay
Set CHER & CHTx /Ch
8,
Ex: set FSCE status b
it
and set IT TE
Delay Viol Viol
EOF+IFS: 8 + 4 Timeslots
Delay Viol: 12 Timeslots
* (not seen by application means no IT generation)
Viol
First attempt
Xmit Ch5
Ex: FCS Error
Rearbitrate
EOF+IFS
(Activate Ch5)
Set CHTx/Ch5 & IT ROK
Xmit Ch8 (Load Max-retries)
(Load Max-retries)
(Load Max-retries)
Ex: FCS Error
(not seen by application)
First attempt
Xmit Ch8
S
econd attempt
Xmit Ch8
(Retries - 1)
Idle command
Idle
Set CHER & CHTx /Ch
8,
Ex: set FSCE status b
it
and set IT TE
Delay Delay
Delay
Viol Viol Viol
EOF+IFS: 8 + 4 Timeslot
s
Delay Viol: 12 Timeslots
* (not seen by application)
* (not seen by application means no IT generation)
50 TSS463-AA 4205B–AUTO–12/04
Figure 33. Disable Channel After Rearbitrate
In this case, the TSS463AA completes the current attempt (Ch8) and let the transmission go on the new channel (Ch5 if
validated), otherwise it stops all attempts on the current channel.
Abort An abor t command is dedic ated to ch annels a lready enabled i n transm ission or in in-
frame response. For example, this command can be used to break the retry procedure
on one chann el.
Abort channel is done by setting the Error bit (CHER) in the Message Length and Status
Register (base_address + 0x02). This command is taken into account if the channel
aborted i s not trans mitted. Wh en this abort comm and is rea lly done, the TSS46 3AA s et
to 1 the Transmitted bit (CHTx) of the Message Length and Status Register.
The abo rt mecha nis m is in tegr a ted into the tr ans mit fu nc tio n. T h is ma inl y mea ns , ab or t,
priority and retries live together in the transmit function.
First attempt
Ex: FCS Error
Rearbitrate
(Activate Ch5)
Set CHTx/Ch5 & IT TO K
Set CHER & CHTx /Ch5,
Xmit Ch8 (Load Max-retrie
s)
(Load Max-retrie
s)
(not seen by application)
Ex: set ACKE status bit
stand-by
First attempt
Xmit Ch5
Second attempt Xmit Ch5
Ex: ACK Error
(not seen by application)
(Retries - 1)
EOF+IFS stand-by
Disable Ch8(1
)
(1) The disable is applied setting the CHTx/Ch8 bit to 1.
and set IT TE
KO
OK
Delay Delay
Delay
Viol
Viol Viol
EOF+IFS: 8 + 4 Timeslots
Delay Viol: 12 Timeslots
51
TSS463-AA
4205B–AUTO–12/04
Figure 34. Abort Example
Reset
Chs Initialization
Activate
Abort Ch0 (before Xmit)
Set CHTx/Ch0
Abort Ch13 (before Xmit)
Abort Ch4 (during Xmit)
Set CHTx/Ch4 &IT ROK
Set CHTx/Ch6 & IT ROK
if Successful
Set CHTx/Ch6 & IT ROK
if Successful
/Ch6 &
Set CHTx/Ch13
Xmit Ch6
Xmit Ch6
Xmit Ch4
12 Timeslots
i
f Previously Failed
Xmit Ch6
i
f Previously Failed
IT ROK
or IT R
E
Set CHTx
or CHER
52 TSS463-AA 4205B–AUTO–12/04
Activate, Idle and
Sleep Modes Sleep, idle and activate commands are located in the Command Register (0x03). These
three commands are general commands for the TSS463AA.
Idle and Activate
Commands After reset, the TSS46 3AA starts in idl e mode. In this mode , the oscillator operates
(CKOUT pin active) but the c ircui t ca nnot t ransmi t or receive any thing on th e VA N bus .
The TxD output (pin 12) is in tri-state mode, a pull-up resistor must be provided exter-
nally or by the line driver to avoid floating state on the VAN bus. To activate the
TSS463AA, the user must set the activate bit (ACTI) and reset the idle bit (IDLE).
Figure 35. Idle and Activate Timings
In both cases, the idle state can be verified reading the Line Status register (0x04).
Sleep Command If the us er sets the sle ep bit (SL EEP), t he T SS463 AA enter s in sleep m ode , regar dless
of the value s of activate and idle bits. It means that, all non-us er registers are set-up to
reduce the po wer co ns ump tio n and the i nter na l os cil lat or is imm edi ate ly sto ppe d. Th e n,
accesses to all registers (and to the messages) via the SPI/SCI interface are impossible
and CKOUT is not provided.
To exit from this mod e the us er mus t ap ply eit her an ha rdwar e r ese t (exte r nal reset pi n)
either an asynchronous software reset (via the SPI/SCI interface).
In a typical application (see Figure 5), using the CKOUT feature (pin 8), if the
TSS463AA is put in sleep mode , the clock provid ed to the mi crocontroller is stoppe d.
So, the system does not run and the only way to awake this application is an external
reset.
(max)
RxD
TxD
A
fter Reset
Idle Mode Activate Mode
Activate command
3 TS 8 TS
12 TS TS: Timeslot Period
SOF
SOF
Idle Command
FCS
EOD
ACK
5 TS4 TS
RxD
INT
Idle ModeActivate Mode
53
TSS463-AA
4205B–AUTO–12/04
Linked Channels The linkage feature allows two channels to share the same Message area, the message
pointer and the message length assumes this property:
• Zero value as message length (M_L [4:0] - base_address + 0x03) declares the
channel linked to another channel.
• The number of this other channel is defined in the message pointer field (M_P [6:0]
- base_address + 0x02).
• The pointer and the length values for the Message area are defined only once, in
the register set of this other Channel.
Only o ne level of link age c an be c reated. T his mea ns, (see F igure 36 ) a Cha nnel k ca n
be linked to the Channel i but not to Channel j, already defined as linked to Channel i.
All the others can be different between the two channels, for example the ID_Tag.
Figure 36. Linkage Mechanism
This Mes sage area sh aring pe rmits either to optimize the allocation of the 128 bytes of DATA, or to pe rform some specia l
communications between the different nodes of the network.
ID_Tag j (msb)
ID_Tag j (lsb) EXT RAK RNW RTR
DRAK
i
0x00
CHRx
Message Status
DATA 0
--- Channel i ---
ID_Tag i (msb)
ID_Tag i (lsb) EXT RAK RNW
DRAK Mess_Ptr
Mess_Len = n+2 CHERCHTx CHRx
ID_Mask i (lsb)
--- Channel j ---
DATA n
The Channel j linked
to the Channel i
. . . .
Length = n+2
--- Message for Channels i & j ---
Channel i and j
share the same
Message area
ID_Mask i (msb)
RTR
CHERCHTx
ID_Mask j (msb)
ID_Mask j (lsb)
54 TSS463-AA 4205B–AUTO–12/04
Electrical Characteristics
DC Characteristic s
Table 10. TA = -40°C to 125°C; VCC = 5V + 10%; VSS = 0V
Absolute Maximum Ratings
Ambient temperature under bias:
Automotive........................................................-40°C to 125°C
Storage Temp eratu re............. ..... ...... ..... ...........-65°C to 150°C
Volta ge on VCC to VSS..........................................-0.5 to +7.0V
Voltage on any pin to VSS ..........................-0.5V to VCC +0.5V
*NOTICE: S tres ses at or above tho se liste d under Absolute
Maximum Ratings may cause permanent dam-
age to the devi ce. T his i s a st ress ra tin g only a nd
functio nal ope ration of the de vice at th ese or any
other conditio ns exce eding thos e indic ated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Symbol Parameter Min. Max Unit Test Conditions
VIL Input Low Voltage -0.5 0.3·VCC·min V
VIH Input High Voltage 0.7·VCC max VCC+0.5 V
VHY Hyteresis voltage of
trigger CMOS inputs 0.4 - V see Table
VOL Output Low V oltage 0.4 V IOL = 3.2 mA, Vcc min
VOH Output High V oltage 2.4 V IOH = -3.2 mA, Vcc min
IL Input Leakage Current
(SCLK, MOSI, SS) 5µA0 < VIN < VCC
IOZ
Output Tristate
Leakage Current
(MISO) 5µA0 < VIN < VCC
RPU, RPD Input pull-up and pull-
down resistors 70 kΩNote 4
CIO I/O Buffer Capacitance 10 pF Not tested
ICCSB Power Supply Current
Sleep mode 50 µA(Note 1)
ICCOP Power Supply Current
Idle or Active mode 9mA (Notes 2, 3)
Notes : 1. Sleep Mo de I CCSB is measured according to a VSS Cloc k Signal.
2. A ctive mode ICCOP is measured at: XTAL = 8 MHz clock, VAN speed rate = 125 KTS/s.
3. ICC is a function of the Clock Frequency. Figure 38 displays a graph showing ICC versus Clock frequency.
4. RESET, RxD0, RxD1, RxD2 inputs.
55
TSS463-AA
4205B–AUTO–12/04
Figure 37. ICC
Figure 38. ICCOP versus Clock Frequency at 125 KTimeslot/s
mA
9
24
MH
z
8.5
8
7.5
68
56 TSS463-AA 4205B–AUTO–12/04
AC Characteristic s TA = -40°C to 125°C; VCC = 5 V + 10%; VSS = 0V
Table 11. Microprocessor Interface
CLOAD = 200pF on SPI/SCI Lines
Note: 1. Simulated Data
Symbol Characteristic Min Max Unit
fOP Operating Frequency SPI
SCI dc
dc 4
125 MHz
kHZ
tCYC Cycle Time SPI
SCI 250
8-
-ns
ms
tLEAD Enable Lead Time 4 - XTAL Period
tLAG Enable Lead Time 12 -XTAL Period
tW(SCKH) Clock (SCLK) High Tim e 100 -ns
tW(SCKL) Clock (SCLK) Low Time 100 -ns
tSU Data Setup Time (Inputs) 40 -ns
tHData Hold Time (Inputs) 40 -ns
tASlave Access Time (Time to Data Active from
High-Impedance State) 0100 ns
tDIS Slave Disable Ti me (Hold Time to High-
Impedance State) -200 ns
tVData Valid (after Enable Edge) -60 ns
tHO Data Hold Time (Outputs after Enable Edge) 0 - ns
tIZIL(1) INT Float Pulse Width 20 ns
A
SS
(INPUT)
MISO
(
OUTPUT)
MOSI
(INPUT)
SCLK
(INPUT)
INT
float pulse only when address is 0x08 to 0x0B
IZIL
t
CYC
t
LEAD
t
W(SCKL)
t
W(SCKH)
t
FLAG
DIS
t
HO
tV
tH
SU
t
t IZ
IL
t
t
57
TSS463-AA
4205B–AUTO–12/04
Interface
Oscillator Characteristics Figure 39. C2 versus Frequency
Note: C1 (no capacitance needed) see Figure 5 .
External Clock Drive
Characteristics (XTAL1)
200
100
33
12 48
MHz
pF
Symbol Parameter Min Max Unit
tCHCH Oscillator period 120 ns
tCHCX High Time 20 ns
tCLCX Low Time 20 ns
tCLCH Rise Time 20 ns
tCHCL Fall Time 20 ns
t
CHCX
t
CLCX
t
CHCH
X
TAL1
V
IH
V
IL
t
CLCH
t
CHCL
V
IH
V
IH
V
IL
58 TSS463-AA 4205B–AUTO–12/04
Packaging Information
SO16
SO MM Inch
A2.35 2.65 0.093 0.104
A1 0.10 0.30 0.004 0.012
B0.35 0.49 0.014 0.019
C0.23 0.32 0.009 0.013
D10.10 10.50 0.398 0.413
E7.40 7.60 0.291 0.299
e1.27 BSC 0.050 BSC
H10.00 10.65 0.394 0.419
h0.25 0.75 0.010 0.029
L0.40 1.27 0.016 0.050
N16 16
a 0° 8°0° 8°
59
TSS463-AA
4205B–AUTO–12/04
Ordering Information
Note: 1. These products are available in ROHS version.
Part Number Supply Vo l tage Temperature
Range Package Packing
TSS463-AA 5V +10% -40°C to +125°C SO16 Stick
TSS463-AA: R 5V +10% -40°C to +125°C SO16 Tape and Reel
TSS463A-TERZ(1) 5V +10% -40°C - +125°C SO16 Tape and Reel
Printed on recycled paper.
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmel’s Ter ms and Conditions locate d on the Company’s web site. The Company assumes no responsibility for any
errors which may appear in this document, reserves the right to change devices or specifica tions detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are
granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use
as critical components in life support devices or systems.
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