5
DEMO MANUAL DC293
NO-DESIGN SWITCHER
The peak inductor current at which C triggers the one-shot
is controlled by the voltage on Pin 2 (I
TH
), the output of the
error amplifier, EA. An external resistive divider connected
between V
OUT
and ground allows EA to receive an output
feedback voltage, V
FB
. When the load current increases, it
causes a slight decrease in V
FB
relative to the 1.23V
reference, which, in turn, causes the I
TH
voltage to increase
until the average inductor current matches the new load
current.
The main control loop is shut down by pulling Pin 1 (RUN/
SS) low. Releasing RUN/SS allows an internal 1µA current
source to charge the soft-start capacitor, C
SS
. When C
SS
reaches 1V, the main control loop is enabled with the I
TH
voltage clamped at approximately 40% of its maximum
value. As C
SS
continues to charge, I
TH
is gradually re-
leased, allowing normal operation to resume. C
SS
can also
be used for power supply sequencing by setting a turn-on
delay equal to approximately C
SS
/I
RUN/SS
seconds.
Burst Mode OPERATION
The LTC1771 provides outstanding low current efficiency
and ultralow no-load supply current by using Burst Mode
operation when Pin 8 (MODE) is pulled above 2V. Burst
Mode operation commences when the load, detected by a
comparator monitoring the I
TH
voltage, falls below about
20% to 30% of the maximum load. During Burst Mode
operation, short burst cycles of normal switching to charge
the output capacitor are followed by a longer sleep period
with the switch off and the load current supplied by the
output capacitor. During this sleep period, only the mini-
mum required circuitry—the reference voltage and the error
amplifier—are left on. Supply current is further reduced
with innovative new circuitry that allows the error amplifier
to run on 10% of its normal operating current during sleep
mode with no degradation in the transient response,
reducing the total supply current to only 9µA. At light loads,
the regulator spends most of the time in this low quiescent
current sleep mode, thus minimizing the losses that would
normally dominate (DC supply current losses and switch-
ing losses due to the MOSFET switch gate charge).
Burst Mode operation can be disabled by pulling the MODE
pin to ground. Disabling Burst Mode operation allows the
loads to decrease by another decade, to about 1% to 2%
OPERATIO
U
of the maximum load, before the regulator must skip cycles
to maintain regulation. Although less efficient, disabling
Burst Mode operation is useful for reducing both audio
and RF interference by reducing voltage and current ripple
and keeping frequency constant to lower output currents.
SHORT-CIRCUIT PROTECTION
When the output is shorted to ground, the off-time is
increased in inverse proportion to V
OUT
, to a maximum of
70µs at V
OUT
= 0V. This increased off-time allows the
inductor current to discharge, preventing runaway. Fold-
back current limiting can be implemented by adding two
diodes in series between the output and the I
TH
pin, as
shown in Figure 3, to minimize heat dissipation in the catch
diode during the short-circuit condition.
OUTPUT VOLTAGE SETUP
In this demonstration circuit, output voltages of 1.8V
(version A only), 2.5V, 3.3V and 5V (version B only) can be
obtained by moving the jumper JP3 to the appropriate
position, as indicated on the demo board. If an output
voltage other than those provided is desired, one of the
feedback resistors R4, R5, R6, R7 or R8 can be removed
and replaced with a new value to set the desired voltage
according to the following equation:
V
OUT
= 1.23(R4 + R5RX)/R4
where RX is the resistor R6, R7 or R8 associated with the
position of jumper JP3.
Note also that the output capacitor is rated at 6.3V; if the
output voltage approaches this limit, the capacitor must
be replaced with a capacitor with the proper rating (pref-
erably twice the output voltage).
CHECKING TRANSIENT RESPONSE
Switching regulators take several cycles to respond to a
step in DC (resistive) load current. When a load step
occurs, V
OUT
shifts by an amount equal to (∆I
LOAD
)(ESR),
where ESR is the effective series resistance of C
OUT
.
∆I
LOAD
also begins to charge or discharge C
OUT
until the
regulator loop adapts to the current change and returns
V
OUT
to its steady-state value. During this recovery time,
V
OUT
can be monitored for overshoot or ringing, which