ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 14-BIT, 190 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS FEATURES APPLICATIONS * * * * * * * * * * * * * * * * * * * * * * * * * Maximum Sample Rate: 190 MSPS 14-Bit Resolution No Missing Codes Total Power Dissipation 1.1 W Internal Sample and Hold 73.2-dBFS SNR at 70-MHz IF 87-dBc SFDR at 70-MHz IF, 0 dB gain Double Data Rate (DDR) LVDS and Parallel CMOS Output Options Programmable Gain up to 6 dB for SNR/SFDR Trade-Off at High IF Reduced Power Modes at Lower Sample Rates Supports input clock amplitude down to 400 mVPP Clock Duty Cycle Stabilizer No External Reference Decoupling Required Internal and External Reference Support Programmable Output Clock position to ease data capture 3.3-V Analog and Digital Supply 48-QFN Package (7 mm x 7 mm) Wireless Communications Infrastructure Software Defined Radio Power Amplifier Linearization 802.16d/e Test and Measurement Instrumentation High Definition Video Medical Imaging Radar Systems DESCRIPTION ADS5546 is a high performance 14-bit, 190-MSPS A/D converter. It offers state-of-the art functionality and performance using advanced techniques to minimize board space. Using an internal sample and hold and low jitter clock buffer, the ADC supports both high SNR and high SFDR at high input frequencies. It features programmable gain options that can be used to improve SFDR performance at lower full-scale analog input ranges. In a compact 48-pin QFN, the device offers fully differential LVDS DDR (Double Data Rate) interface while parallel CMOS outputs can also be selected. Flexible output clock position programmability is available to ease capture and trade-off setup for hold times. At lower sampling rates, the ADC can be operated at scaled down power with no loss in performance. ADS5546 includes an internal reference, while eliminating the traditional reference pins and associated external decoupling. The device also supports an external reference mode. The device is specified over temperature range (-40C to 85C). the industrial Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2005-2007, Texas Instruments Incorporated ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. CLKP DRGND DRVDD AGND AVDD ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. CLKOUTP CLOCKGEN CLKM CLKOUTM D0_D1_P D0_D1_M D2_D3_P D2_D3_M D4_D5_P D4_D5_M Digital Encoder and Serializer INP 14-Bit ADC SHA INM D6_D7_P D6_D7_M D8_D9_P D8_D9_M D10_D11_P D10_D11_M VCM Control Interface Reference D12_D13_P D12_D13_M OVR MODE OE DFS RESET SEN SDATA SCLK IREF ADS5546 LVDS MODE B0095-01 PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGELEAD ADS5546 QFN-48 (2) (1) (2) 2 PACKAGE DESIGNATOR RGZ SPECIFIED TEMPERATURE RANGE -40C to 85C PACKAGE MARKING AZ5546 ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS5546IRGZT Tape and Reel, 250 ADS5546IRGZR Tape and Reel, 2500 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. JA = 25.41C/W (0 LFM air flow), JC = 16.5C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in x 3 in (7.62 cm x 7.62 cm) PCB. Submit Documentation Feedback ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE UNIT Supply voltage range, AVDD -0.3 V to 3.9 V Supply voltage range, DRVDD -0.3 V to 3.9 V Voltage between AGND and DRGND -0.3 to 0.3 V Voltage between AVDD to DRVDD -0.3 to 3.3 V Voltage applied to VCM pin (in external reference mode) -0.3 to 1.8 V -0.3 V to minimum (3.6, AVDD + 0.3 V) V Voltage applied to analog input pins, INP and INM Voltage applied to input clock pins, CLKP and CLKM TA Operating free-air temperature range TJ Operating junction temperature range Tstg Storage temperature range (1) -0.3 V to AVDD + 0.3 V V -40 to 85 C 125 C -65 to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT Analog supply voltage, AVDD 3 3.3 3.6 V Digital supply voltage, DRVDD 3 3.3 3.6 V SUPPLIES ANALOG INPUTS Differential input voltage range 2 VPP 1.5 0.1 Input common-mode voltage Voltage applied on VCM in external reference mode 1.45 1.5 V 1.55 V 50 190 MSPS 1 60 CLOCK INPUT Input clock sample rate DEFAULT SPEED mode LOW SPEED mode Input clock amplitude differential (V(CLKP) - V(CLKM)) Sine wave, ac-coupled 1.5 VPP LVPECL, ac-coupled 1.6 VPP LVDS, ac-coupled 0.7 VPP LVCMOS, single-ended, ac-coupled 3.3 V Input clock duty cycle (See Figure 33) 0.4 35% 50% 65% DIGITAL OUTPUTS CL Maximum external load capacitance from each output pin to DRGND (LVDS and CMOS modes) RL Differential load resistance between the LVDS output pairs (LVDS mode) Operating free-air temperature 5 100 -40 Submit Documentation Feedback pF 85 C 3 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 ELECTRICAL CHARACTERISTICS Typical values are at 25C, min and max values are across the full temperature range TMIN = -40C to TMAX = 85C, AVDD = DRVDD = 3.3 V, sampling rate = 190 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, -1 dBFS differential analog input, internal reference mode, 0dB gain, DDR LVDS data output (unless otherwise noted) PARAMETER TEST CONDITIONS MIN RESOLUTION TYP MAX UNIT 14 bits Differential input voltage range 2 VPP Differential input capacitance 7 pF ANALOG INPUT -3 dB, source impedance 50 Analog input bandwidth Analog input common mode current (per input pin) 500 MHz 310 A V REFERENCE VOLTAGES V(REFB) Internal reference bottom voltage Internal reference mode 0.5 V(REFT) Internal reference top voltage Internal reference mode 2.5 V(REF) Internal reference error, V(REFT) - V(REFB) VCM Common mode output voltage Internal reference mode 1.5 V VCM output current capability Internal reference mode 4 mA -60 25 V 60 mV DC ACCURACY No Missing Codes DNL Differential non-linearity INL Integral non-linearity Specified Offset error -0.9 0.5 2.5 LSB -5 3 5 LSB -10 5 10 mV Offset error temperature coefficient 0.002 Gain error due to internal reference error alone ( V(REF) / 2.0V) % Gain error excluding internal reference error (1) Gain error temperature coefficient PSRR DC Power supply rejection ratio ppm/C -3 1 3 %FS -2 1 2 %FS 0.01 %/C 0.6 mV/V POWER SUPPLY I(AVDD) I(DRVDD) ICC (1) 4 Analog supply current Digital supply current 291 mA LVDS mode, IO = 3.5 mA, RL = 100 , CL = 5 pF 51 mA CMOS mode, FIN = 2.5 MHz, CL = 5 pF 43 mA Total supply current LVDS mode 342 Total power dissipation LVDS mode 1.13 1.29 W Standby power In STANDBY mode with clock running 100 150 mW Clock stop power With input clock stopped 100 150 mW Gain error is specified from design and characterization; it is not tested in production. Submit Documentation Feedback mA ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 ELECTRICAL CHARACTERISTICS Typical values are at 25C, min and max values are across the full temperature range TMIN = -40C to TMAX = 85C, AVDD = DRVDD = 3.3 V, sampling rate = 190 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, -1 dBFS differential analog input, internal reference mode, 0dB gain, DDR LVDS data output (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC CHARACTERISTICS FIN = 10 MHz 73.8 FIN = 40 MHz 73.6 FIN = 70 MHz SNR Signal to noise ratio 73 FIN = 150 MHz 72.2 FIN = 300 MHz 0 dB gain, 2 VPP FS (1) 71 3 dB gain, 1.4 VPP FS 69.8 0 dB gain, 2 VPP FS 69 Inputs tied to common-mode 1.1 FIN = 10 MHz 90 77 FIN = 100 MHz FIN = 300 MHz 84 0 dB gain, 2 VPP FS 75 3 dB gain, 1.4 VPP FS 78 0 dB gain, 2 VPP FS 72 3 dB gain, 1.4 VPP FS 73.5 FIN = 40 MHz 73.1 FIN = 70 MHz 71 FIN = 100 MHz Signal to noise and distortion ratio FIN = 300 MHz 71.8 0 dB gain, 2 VPP FS Second harmonic 68.5 0 dB gain, 2 VPP FS 67.8 3 dB gain, 1.4 VPP FS 67.5 FIN = 10 MHz 92 FIN = 40 MHz 91 90 89 FIN = 150 MHz 87 FIN = 300 MHz (1) 77 FIN = 100 MHz FIN = 225 MHz dBFS 69 3 dB gain, 1.4 VPP FS FIN = 70 MHz HD2 72.8 72.1 FIN = 150 MHz FIN = 225 MHz dBc 75 FIN = 10 MHz SINAD 87 84 FIN = 150 MHz FIN = 225 MHz LSB 89 FIN = 70 MHz Spurious free dynamic range dBFS 70 3 dB gain, 1.4 VPP FS FIN = 40 MHz SFDR 73.5 FIN = 100 MHz FIN = 225 MHz RMS output noise 71.5 0 dB gain, 2 VPP FS 76 3 dB gain, 1.4 VPP FS 79 0 dB gain, 2 VPP FS 73 3 dB gain, 1.4 VPP FS 75 dBc FS = Full scale range Submit Documentation Feedback 5 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25C, min and max values are across the full temperature range TMIN = -40C to TMAX = 85C, AVDD = DRVDD = 3.3 V, sampling rate = 190 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, -1 dBFS differential analog input, internal reference mode, 0dB gain, DDR LVDS data output (unless otherwise noted) PARAMETER TEST CONDITIONS MIN FIN = 10 MHz 84 84 0 dB gain, 2 VPP FS 75 3 dB gain, 1.4 VPP FS 78 0 dB gain, 2 VPP FS 72 3 dB gain, 1.4 VPP FS 74 FIN = 10 MHz 93 FIN = 40 MHz 92 FIN = 70 MHz 91 FIN = 100 MHz 90 FIN = 150 MHz 89 FIN = 225 MHz 87 FIN = 300 MHz 87 FIN = 10 MHz 85 FIN = 40 MHz 85 FIN = 70 MHz THD Total harmonic distortion IMD PSRR 6 Effective number of bits Two-tone intermodulation distortion 75 81 FIN = 150 MHz 80 FIN = 225 MHz 72 FIN = 10 MHz FIN1 = 50.09 MHz, FIN2 = 46.09 MHz, -7 dBFS each tone dBc dBc 83 FIN = 100 MHz FIN = 300 MHz ENOB 87 FIN = 150 MHz FIN = 300 MHz Worst harmonic (other than HD2, HD3) 77 FIN = 100 MHz FIN = 225 MHz UNIT 89 FIN = 70 MHz Third harmonic MAX 90 FIN = 40 MHz HD3 TYP dBc 68 11.8 bits 95 dBFS FIN1 = 135.08 MHz, FIN2 = 130.08 MHz, -7 dBFS each tone 89 AC power supply rejection ratio 30 MHz, 200 mVPP signal on 3.3-V supply 35 dBc Voltage overload recovery time Recovery to 1% (of final value) for 6-dB overload with sine-wave input at Nyquist frequency 1 Clock cycles Submit Documentation Feedback ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 DIGITAL CHARACTERISTICS (1) The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1 AVDD = DRVDD = 3.3 V, IO = 3.5 mA, RL = 100 (2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS High-level input voltage 2.4 V Low-level input voltage 0.8 V High-level input current 33 A Low-level input current -33 A 4 pF High-level output voltage 3.3 V Low-level output voltage 0 V 2 pF 1375 mV 1025 mV 350 mV 1200 mV 2 pF Input capacitance DIGITAL OUTPUTS - CMOS MODE Output capacitance Output capacitance inside the device, from each output to ground DIGITAL OUTPUTS - LVDS MODE High-level output voltage Low-level output voltage Output differential voltage, |VOD| 225 VOS Output offset voltage, single-ended Common-mode voltage of OUTP and OUTM Output capacitance Output capacitance inside the device, from either output to ground (1) (2) All LVDS and CMOS specifications are characterized, but not tested at production. IO refers to the LVDS buffer current setting, RL is the differential load resistance between the LVDS output pair. TIMING CHARACTERISTICS - LVDS AND CMOS MODES (1) Typical values are at 25C, min and max values are across the full temperature range TMIN = -40C to TMAX = 85C, AVDD = DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA, RL = 100 (3), no internal termination, unless otherwise noted. For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this data sheet. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ta Aperture delay 1.2 ns tj Aperture jitter 150 fs rms Wake-up time Time to valid data after coming out of STANDBY mode 100 Time to valid data after stopping and restarting the input clock 100 s Latency 14 clock cycles DDR LVDS MODE (4) Data setup time (5) Data valid 1.2 1.7 ns th Data hold time (5) Zero-cross of CLKOUTP to data becoming invalid (6) 0.4 0.9 ns tPDI Clock propagation delay Input clock rising edge zero-cross to output clock rising edge zero-cross 4 4.7 tsu (1) (2) (3) (4) (5) (6) (6) to zero-cross of CLKOUTP 5.4 ns Timing parameters are specified by design and characterization and not tested in production. CL is the effective external single-ended load capacitance between each output pin and ground. IO refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair. Measurements are done with a transmission line of 100 characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as reduced timing margin. Data valid refers to logic high of +50 mV and logic low of -50 mV. Submit Documentation Feedback 7 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 TIMING CHARACTERISTICS - LVDS AND CMOS MODES (continued) For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this data sheet. PARAMETER TEST CONDITIONS MIN TYP MAX 45% 50% 55% UNIT LVDS bit clock duty cycle Duty cycle of differential clock, (CLKOUTP-CLKOUTM) 80 Fs 190 MSPS tr , tf Data rise time, Data fall time Rise time measured from -50 mV to 50 mV Fall time measured from 50 mV to -50 mV 1 Fs 190 MSPS 50 100 200 ps tCLKRISE, tCLKFALL Output clock rise time, Output clock fall time Rise time measured from -50 mV to 50 mV Fall time measured from 50 mV to -50 mV 1 Fs 190 MSPS 50 100 200 ps tOE Output enable (OE) to valid data delay Time to valid data after OE becomes active 1 s PARALLEL CMOS MODE tsu (5) (5) Data valid (7) to 50% of CLKOUT rising edge 2.2 3 ns 50% of CLKOUT rising edge to data becoming invalid (7) 0.5 0.9 ns 2.4 3.2 th Data hold time tPDI Clock propagation delay Input clock rising edge zero-cross to 50% of CLKOUT rising edge Output clock duty cycle Duty cycle of output clock (CLKOUT) 80 Fs 190 MSPS tr, tf Data rise time, Data fall time Rise time measured from 20% to 80% of DRVDD Fall time measured from 80% to 20% of DRVDD 1 Fs 190 MSPS 0.8 tCLKRISE, tCLKFALL Output clock rise time, Output clock fall time Rise time measured from 20% to 80% of DRVDD Fall time measured from 80% to 20% of DRVDD 1 Fs 190 MSPS 0.4 tOE Output enable (OE) to valid data delay Time to valid data after OE becomes active (7) 8 Data setup time Data valid refers to logic high of 2 V and logic low of 0.8 V Submit Documentation Feedback 4 ns 1.5 2 ns 0.8 1.2 ns 50 ns 45% ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 N+4 N+3 N+2 N+1 Sample N N+17 N+16 N+15 N+14 Input Signal ta Input Clock CLKP CLKM CLKOUTM CLKOUTP tsu Output Data DXP, DXM E E O E - Even Bits D0,D2,D4,D6,D8,D10,D12 O - Odd Bits D1,D3,D5,D7,D9,D11,D13 O N-14 E O N-13 E E O N-12 tPDI th 14 Clock Cycles DDR LVDS E O N-11 E O N-10 O E O N N-1 E E O O N+2 N+1 tPDI CLKOUT tsu Parallel CMOS 14 Clock Cycles Output Data D0-D13 N-13 N-14 N-12 th N-11 N-10 N N-1 N+1 N+2 Figure 1. Latency Input Clock CLKM CLKP tPDI Output Clock CLKOUTP CLKOUTM tsu th tsu Output Data Pair (1) (2) Dn Dn_Dn+1_P, Dn_Dn+1_M th Dn (1) Dn+1 (2) - Bits D0, D2, D4, D6, D8, D10, D12 Dn+1 - Bits D1, D3, D5, D7, D9, D11, D13 T0106-01 Figure 2. LVDS Mode Timing Submit Documentation Feedback 9 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 CLKM Input Clock CLKP tPDI Output Clock CLKOUT th tsu Output Data Dn Dn (1) (1) Dn - Bits D0-D13 T0107-01 Figure 3. CMOS Mode Timing 10 Submit Documentation Feedback ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 DEVICE PROGRAMMING MODES ADS5546 offers flexibility with several programmable features that are easily configured. The device can be configured independently using either a parallel interface control or a serial interface programming. In addition, the device supports a third mode, where both the parallel interface and the serial control registers are used. In this mode, the priority between the parallel and serial interfaces is determined by a priority table (Table 2). If this additional level of flexibility is not required, the user can select either the serial interface programming or the parallel interface control. USING PARALLEL INTERFACE CONTROL ONLY To control the device using the parallel interface, keep RESET tied to high (DRVDD). Pins DFS, MODE, SEN, SCLK, and SDATA are used to directly control certain modes of the ADC. The device is configured by connecting the parallel pins to the correct voltage levels (as described in Table 4 to Table 7). There is no need to apply reset. In this mode, SEN, SCLK, and SDATA function as parallel interface control pins. Frequently used functions are controlled in this mode--standby, selection between LVDS/CMOS output format, internal/external reference, two's complement/straight binary output format, and position of the output clock edge. Table 1 has a description of the modes controlled by the four parallel pins. Table 1. Parallel Pin Definition PIN DFS MODE CONTROL MODES DATA FORMAT and the LVDS/CMOS output interface Internal or external reference SEN CLKOUT edge programmability SCLK LOW SPEED mode control for low sampling frequencies (< 50 MSPS) SDATA STANDBY mode - Global (ADC, internal references and output buffers are powered down) USING SERIAL INTERFACE PROGRAMMING ONLY To program using the serial interface, the internal registers must first be reset to their default values, and the RESET pin must be kept low. In this mode, SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC. The registers are reset either by applying a pulse on the RESET pin, or by a high setting on the <RST> bit (D1 in register 0x6C). The serial interface section describes the register programming and register reset in more detail. Since the parallel pins DFS and MODE are not used in this mode, they must be tied to ground. USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS For increased flexibility, a combination of serial interface registers and parallel pin controls (DFS, MODE) can also be used to configure the device. The serial registers must first be reset to their default values, and the RESET pin must be kept low. In this mode SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC. The registers are reset either by applying a pulse on RESET pin or by a high setting on the <RST> bit (D1 in register 0x6C). The serial interface section describes the register programming and register reset in more detail. The parallel interface control pins DFS and MODE are used, and their function is determined by the appropriate voltage levels as described in Table 6 and Table 7. The voltage levels are derived by using a resistor string as illustrated in Figure 4. Since some functions are controlled using both the parallel pins and serial registers, the priority between the two is determined by a priority table (Table 2). Submit Documentation Feedback 11 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 Table 2. Priority Between Parallel Pins and Serial Registers PIN MODE FUNCTIONS SUPPORTED PRIORITY Internal/External reference When using the serial interface, bit <REF> (register 0x6D, bit D4) controls this mode, ONLY if the MODE pin is tied low. DATA FORMAT When using the serial interface, bit <DF> (register 0x63, bit D3) controls this mode, ONLY if the DFS pin is tied low. LVDS/CMOS When using the serial interface, bit <ODI> (register 0x6C, bits D3-D4) controls LVDS/CMOS selection independent of the state of DFS pin DFS AVDD (2/3) AVDD R (2/3) AVDD GND R AVDD (1/3) AVDD (1/3) AVDD R To Parallel Pin Figure 4. Simple Scheme to Configure Parallel Pins 12 Submit Documentation Feedback ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 DESCRIPTION OF PARALLEL PINS Table 3. SCLK Control Pin SCLK (Pin 29) 0 DRVDD DESCRIPTION DEFAULT SPEED - Must be used for sampling frequency > 50 MSPS LOW SPEED - Must be used for sampling frequency <= 50 MSPS Table 4. SDATA Control Pin SDATA (Pin 28) 0 DRVDD DESCRIPTION Normal operation (Default) STANDBY. This is a global power down, where ADC, internal references and the output buffers are powered down. Table 5. SEN Control Pin SEN (Pin 27) CMOS mode: CLKOUT edge later by (3/12)Ts (1); LVDS mode: CLKOUT edge aligned with data transition (1/3)DRVDD CMOS mode: CLKOUT edge later by (2/12)Ts (1); LVDS mode: CLKOUT edge aligned with data transition (2/3)DRVDD CMOS mode: CLKOUT edge later by (1/12)Ts (1); LVDS mode: CLKOUT edge earlier by (1/12)Ts DRVDD (1) DESCRIPTION 0 (1) Default CLKOUT position Ts = 1/Sampling Frequency Table 6. DFS Control Pin DFS (Pin 6) 0 DESCRIPTION 2's complement data and DDR LVDS output (Default) (1/3)DRVDD 2's complement data and parallel CMOS output (2/3)DRVDD Offset binary data and parallel CMOS output DRVDD Offset binary data and DDR LVDS output Table 7. MODE Control Pin MODE (Pin 23) DESCRIPTION 0 Internal reference (1/3)AVDD External reference (2/3)AVDD External reference AVDD Internal reference SERIAL INTERFACE The ADC has a set of internal registers, which can be accessed through the serial interface formed by pins SEN (Serial interface Enable), SCLK (Serial Interface Clock), SDATA (Serial Interface Data) and RESET. After device power-up, the internal registers must be reset to their default values by applying a high-going pulse on RESET (of width greater than 10 ns). Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data is loaded in multiples of 16-bit words within a single active SEN pulse. The first 8 bits form the register address and the remaining 8 bits form the register data. The interface can work with SCLK frequency from 20 MHz down to very low speeds (few Hertz) and even with non-50% SCLK duty cycle. Submit Documentation Feedback 13 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 REGISTER INITIALIZATION After power-up, the internal registers must be reset to their default values. This is done in one of two ways: 1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10 ns) as shown in Figure 5. OR 2. By applying software reset. Using the serial interface, set the <RST> bit (D1 in register 0x6C) to high. This initializes the internal registers to their default values and then self-resets the <RST> bit to low. In this case the RESET pin is kept low. Register Address SDATA A7 A6 A5 A4 A3 A2 Register Data A1 A0 D7 t(SCLK) D6 D5 D4 D3 D2 D1 D0 t(DH) t(DSU) SCLK t(SLOADH) t(SLOADS) SEN RESET T0109-01 Figure 5. Serial Interface Timing Diagram SERIAL INTERFACE TIMING CHARACTERISTICS Typical values at 25C, min and max values across the full temperature range TMIN = -40C to TMAX = 85C, AVDD = DRVDD = 3.3 V (unless otherwise noted) MIN TYP UNIT 20 MHz fSCLK SCLK frequency tSLOADS SEN to SCLK setup time 25 ns tSLOADH SCLK to SEN hold time 25 ns tDSU SDATA setup time 25 ns tDH SDATA hold time 25 ns 14 > DC MAX Submit Documentation Feedback ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 RESET TIMING Typical values at 25C, min and max values across the full temperature range TMIN = -40C to TMAX = 85C, AVDD = DRVDD = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS t1 Power-on delay Delay from power-up of AVDD and DRVDD to RESET pulse active MIN t2 Reset pulse width t3 tPO TYP MAX UNIT 5 ms Pulse width of active RESET signal 10 ns Register write delay Delay from RESET disable to SEN active 25 ns Power-up time Delay from power-up of AVDD and DRVDD to output stable 6.5 ms Power Supply AVDD, DRVDD t1 RESET t2 t3 SEN T0108-01 NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset. For parallel interface operation, RESET has to be tied permanently HIGH. Figure 6. Reset Timing Diagram Submit Documentation Feedback 15 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 SERIAL REGISTER MAP Table 8 gives a summary of all the modes that can be programmed through the serial interface. Table 8. Summary of Functions Supported by Serial Interface (1) (2) REGISTER ADDRESS IN HEX A7 - A0 REGISTER FUNCTIONS D7 65 D5 D4 <DATA POSN> OUTPUT DATA POSITION PROGRAMMABILITY 62 63 D6 D3 <LOW SPEED> ENABLE LOW SAMPLING FREQUENCY OPERATION <STBY> GLOBAL POWER DOWN <DF> DATA FORMAT 2's COMP or STRAIGHT BINARY <GAIN> GAIN PROGRAMMING <GAIN> - 1 dB to 6 dB <CUSTOM A> CUSTOM PATTERN (D7 TO D0) 6A <CUSTOM B> CUSTOM PATTERN (D13 TO D8) 6B <CLKIN GAIN> INPUT CLOCK BUFFER GAIN PROGRAMMABILITY <ODI> OUTPUT DATA INTERFACE - DDR LVDS or PARALLEL CMOS 6C 6D <SCALING> POWER SCALING 7E <DATA TERM> INTERNAL TERMINATION - DATA OUTPUTS 7F D0 <TEST PATTERN> - ALL 0S, ALL 1s, TOGGLE, RAMP, CUSTOM PATTERN 69 16 D1 <CLKOUT POSN> OUTPUT CLOCK POSITION PROGRAMMABILITY 68 (1) (2) D2 <RST> SOFTWARE RESET <REF> INTERNAL or EXTERNAL REFERENCE <CLKOUT TERM> INTERNAL TERMINATION - OUTPUT CLOCK <CURR DOUBLE> LVDS CURRENT DOUBLE The unused bits in each register (shown by blank cells in above table) must be programmed as `0'. Multiple functions in a register can be programmed in a single write operation. Submit Documentation Feedback <LVDS CURR> LVDS CURRENT PROGRAMMABILITY ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 DESCRIPTION OF SERIAL REGISTERS Each register function is explained in detail below. Table 9. Serial Register A A7 - A0 (hex) 62 D7 D6 D5 <DATA POSN> OUTPUT DATA POSITION PROGRAMMABILITY D4 D3 D2 D1 D0 <CLKOUT POSN> OUTPUT CLOCK POSITION PROGRAMMABILITY D4 - D0 <CLKOUT POSN> Output Clock Position Programmability 00001 Default CLKOUT position after reset. Setup/hold timings with this clock position are specified in the timing characteristics table. XX011 CMOS - Rising edge later by (1/12) Ts LVDS - Rising edge earlier by (1/12) Ts XX101 CMOS - Rising edge later by (3/12) Ts LVDS - Rising edge aligned with data transition XX111 CMOS - Rising edge later by (2/12) Ts LVDS - Rising edge aligned with data transition 01XX1 CMOS - Rising edge later by (1/12) Ts LVDS - Rising edge earlier by (1/12) Ts 10XX1 CMOS - Rising edge later by (3/12) Ts LVDS - Rising edge aligned with data transition 11XX1 CMOS - Rising edge later by (2/12) Ts LVDS - Rising edge aligned with data transition D6 - D5 <DATA POSN> Output Data Position Programmability (Only in CMOS mode) 00 Data Position 1 - Default output data position after reset. Setup/hold timings with this data position are specified in the timing characteristics table. 01 Data Position 2 - Setup time increases by (2/36) Ts 10 Data Position 3 - Setup time increases by (5/36) Ts 11 Data Position 4 - Setup time decreases by (6/36) Ts Submit Documentation Feedback 17 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 Table 10. Serial Register B A7 - A0 (hex) 63 D7 D6 D5 <STBY> GLOBAL POWER DOWN D4 D3 <LOW SPEED> ENABLE LOW SAMPLING FREQUENCY OPERATION <DF> DATA FORMAT 2's COMP or STRAIGHT BINARY D2 D3 <DF> Output Data Format 0 2's complement 1 Straight binary D4 <LOW SPEED> Low Sampling Frequency Operation 0 Default SPEED mode for 50 < Fs 190 MSPS 1 Low SPEED mode 1 Fs 50 MSPS D7 <STBY> Global power down 0 Normal operation 1 Global power down (includes ADC, internal references and output buffers) D1 D0 Table 11. Serial Register C A7 - A0 (hex) 65 D7 D6 D5 D4 D3 D2 <TEST PATTERNS>-- ALL 0S, ALL 1s, TOGGLE, RAMP, CUSTOM PATTERN D7 - D5 <TEST PATTERN> Outputs selected test pattern on data lines 000 Normal operation 001 All 0s 010 All 1s 011 Toggle pattern - alternate 1s and 0s on each data output and across data outputs 100 Ramp pattern - Output data ramps from 0x0000 to 0x3FFF by one code every clock cycle 101 Custom pattern - Outputs the custom pattern in CUSTOM PATTERN registers A and B 111 Unused 18 Submit Documentation Feedback D1 D0 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 Table 12. Serial Register D A7 - A0 (hex) D7 D6 D5 D4 D3 68 D2 D1 D0 <GAIN> GAIN PROGRAMMING <GAIN> - 1 dB to 6 dB D3 - D0 <GAIN> Gain programmability 1000 0 dB gain, default after reset 1001 1 dB 1010 2 dB 1011 3 dB 1100 4 dB 1101 5 dB 1110 6 dB Table 13. Serial Register E A7 - A0 (hex) D7 D6 D5 69 D4 D3 D2 D1 D0 <CUSTOM A> CUSTOM PATTERN (D7 TO D0) 6A <CUSTOM B> CUSTOM PATTERN (D13 TO D8) Reg 69 D7 - D0 Program bits D7 to D0 of custom pattern Reg 6A D5 - D0 Program bits D13 to D8 of custom pattern Table 14. Serial Register F A7 - A0 (hex) D7 D6 D5 6B D4 D3 D2 D1 D0 <CLKIN GAIN> INPUT CLOCK BUFFER GAIN PROGRAMMABILITY D5 - D0 <CLKIN GAIN> Clock Buffer Gain 110010 Gain 4, maximum gain 101010 Gain 3 100110 Gain 2 100000 Gain1, default after reset 100011 Gain 0 minimum gain Submit Documentation Feedback 19 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 Table 15. Serial Register G A7 - A0 (hex) D7 D6 D5 D4 D3 D2 <ODI> OUTPUT DATA INTERFACE - DDR LVDS OR PARALLEL CMOS 6C D1 <RST> Software resets the ADC 1 Resets all registers to default values D4 - D3 <ODI> Output Interface 00 DDR LVDS outputs, default after reset 01 DDR LVDS outputs 11 Parallel CMOS outputs D1 D0 <RST> SOFTWARE RESET Table 16. Serial Register H A7 - A0 6D D7 D6 D5 <SCALING> POWER SCALING D4 D3 D2 D1 D0 D1 D0 <REF> INTERNAL or EXTERNAL REFERENCE D4 <REF> Reference 0 Internal reference 1 External reference mode, force voltage on Vcm to set reference. D7 - D5 <SCALING> Power Scaling Modes 001 Use for Fs > 150 MSPS, default after reset 011 Power Mode 1, use for 105 < Fs 150 MSPS 101 Power Mode 2, use for 50 < Fs 105 111 Power Mode 3, use for Fs 50 MSPS Table 17. Serial Register I A7 - A0 7E D7 D6 D5 <DATA TERM> INTERNAL TERMINATION - DATA OUTPUTS D4 D3 <CLKOUT TERM> INTERNAL TERMINATION - OUTPUT CLOCK D1 - D0 <LVDS CURR> LVDS Buffer Current Programmability 00 3.5 mA, default 01 2.5 mA 10 4.5 mA 11 1.75 mA 20 D2 Submit Documentation Feedback <LVDS CURR> LVDS CURRENT PROGRAMMABILITY ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 D4 - D2 <CLKOUT TERM> LVDS Internal Termination for Output Clock Pin (CLKOUT) 000 No internal termination 001 325 010 200 011 125 100 170 101 120 110 100 111 75 D7 - D5 <DATA TERM> LVDS Internal Termination for Output Data Pins 000 No internal termination 001 325 010 200 011 125 100 170 101 120 110 100 111 75 Table 18. Serial Register J A7 - A0 7F D7 D6 D5 D4 D3 D2 D1 D0 <CURR DOUBLE> LVDS CURRENT DOUBLE D7 - D6 <CURR DOUBLE> LVDS Buffer Current Double 00 Value specified by <LVDS CURR> 01 2x data, 2x clockout currents 10 1x data, 2x clockout currents 11 2x data, 4x clockout currents Submit Documentation Feedback 21 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 PIN CONFIGURATION (LVDS MODE) 37 D2_D3_M 38 D2_D3_P 39 D4_D5_M 40 D4_D5_P 41 D6_D7_M 42 D6_D7_P 43 D8_D9_M 44 D8_D9_P 45 D10_D11_M 46 D10_D11_P 47 D12_D13_M 48 D12_D13_P RGZ PACKAGE (TOP VIEW) DRGND 1 36 DRGND DRVDD 2 35 DRVDD Thermal Pad OVR 3 34 D0_D1_P CLKOUTM 4 33 D0_D1_M CLKOUTP 5 32 NC DFS 6 31 NC OE 7 30 RESET AVDD 8 29 SCLK AGND 9 28 SDATA AVDD 24 MODE 23 AVDD 22 IREF 21 AVDD 20 AGND 19 AVDD 18 25 AGND AGND 17 AGND 12 INM 16 26 AVDD INP 15 CLKM 11 AGND 14 27 SEN VCM 13 CLKP 10 Figure 7. LVDS Mode Pinout PIN ASSIGNMENTS - LVDS Mode PIN NAME DESCRIPTION PIN TYPE PIN NUMBER NUMBER OF PINS AVDD Analog power supply I 8, 18, 20, 22, 24, 26 6 AGND Analog ground I 9, 12, 14, 17, 19, 25 6 CLKP, CLKM Differential clock input I 10, 11 2 INP, INM Differential analog input I 15, 16 2 VCM Internal reference mode - Common-mode voltage output. External reference mode - Reference input. The voltage forced on this pin sets the internal references. I/O 13 1 IREF Current-set resistor, 56.2-k resistor to ground. I 21 1 RESET Serial interface RESET input. When using the serial interface mode, the user MUST initialize internal registers through hardware RESET by applying a high-going pulse on this pin, or by using the software reset option. See the SERIAL INTERFACE section. In parallel interface mode, the user has to tie the RESET pin permanently HIGH. (SDATA and SEN are used as parallel pin controls in this mode) The pin has an internal 100-k pull-down resistor. I 30 1 22 Submit Documentation Feedback ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 PIN CONFIGURATION (LVDS MODE) (continued) PIN ASSIGNMENTS - LVDS Mode (continued) DESCRIPTION PIN TYPE PIN NUMBER NUMBER OF PINS This pin functions as serial interface clock input when RESET is low. It functions as LOW SPEED mode control pin when RESET is tied high. Tie SCLK to LOW for Fs > 50 MSPS and SCLK to HIGH for Fs 50 MSPS. See Table 3. The pin has an internal 100-k pull-down resistor. I 29 1 I 28 1 SEN This pin functions as serial interface enable input when RESET is low. It functions as CLKOUT edge programmability when RESET is tied high. See Table 5 for detailed information. The pin has an internal 100-k pull-up resistor to DRVDD. I 27 1 OE Output buffer enable input, active high. The pin has an internal 100-k pull-up resistor to DRVDD. I 7 1 DFS Data Format Select input. This pin sets the DATA FORMAT (Twos complement or Offset binary) and the LVDS/CMOS output mode type. See Table 6 for detailed information. I 6 1 MODE Mode select input. This pin selects the Internal or External reference mode. See Table 7 for detailed information. I 23 1 CLKOUTP Differential output clock, true O 5 1 CLKOUTM Differential output clock, complement O 4 1 D0_D1_P Differential output data D0 and D1 multiplexed, true O 34 1 D0_D1_M Differential output data D0 and D1 multiplexed, complement. O 33 1 D2_D3_P Differential output data D2 and D3 multiplexed, true O 38 1 D2_D3_M Differential output data D2 and D3 multiplexed, complement O 37 1 D4_D5_P Differential output data D4 and D5 multiplexed, true O 40 1 D4_D5_M Differential output data D4 and D5 multiplexed, complement O 39 1 D6_D7_P Differential output data D6 and D7 multiplexed, true O 42 1 D6_D7_M Differential output data D6 and D7 multiplexed, complement O 41 1 D8_D9_P Differential output data D8 and D9 multiplexed, true O 44 1 D8_D9_M Differential output data D8 and D9 multiplexed, complement O 43 1 D10_D11_P Differential output data D10 and D11 multiplexed, true O 46 1 D10_D11_M Differential output data D10 and D11 multiplexed, complement O 45 1 D12_D13_P Differential output data D12 and D13 multiplexed, true O 48 1 D12_D13_M Differential output data D12 and D13 multiplexed, complement O 47 1 OVR Out-of-range indicator, CMOS level signal O 3 1 DRVDD Digital and output buffer supply I 2, 35 2 DRGND Digital and output buffer ground I 1, 36 2 NC Do not connect 31, 32 2 PAD Connect the pad to ground plane. See Board Design Considerations in application information section. 0 1 PIN NAME SCLK This pin functions as serial interface data input when RESET is low. It functions as STANDBY control pin when RESET is tied high. SDATA See Table 4 for detailed information. The pin has an internal 100 k pull-down resistor. Submit Documentation Feedback 23 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 PIN CONFIGURATION (CMOS MODE) 37 D2 38 D3 39 D4 40 D5 41 D6 42 D7 43 D8 44 D9 45 D10 46 D11 47 D12 48 D13 RGZ PACKAGE (TOP VIEW) DRGND 1 36 DRGND DRVDD 2 35 DRVDD Thermal Pad OVR 3 34 D1 UNUSED 4 33 D0 CLKOUT 5 32 NC DFS 6 31 NC OE 7 30 RESET AVDD 8 29 SCLK AGND 9 28 SDATA AVDD 24 MODE 23 AVDD 22 IREF 21 AVDD 20 AGND 19 AVDD 18 25 AGND AGND 17 AGND 12 INM 16 26 AVDD INP 15 CLKM 11 AGND 14 27 SEN VCM 13 CLKP 10 Figure 8. CMOS Mode Pinout PIN ASSIGNMENTS - CMOS Mode PIN NAME DESCRIPTION PIN TYPE PIN NUMBER NUMBER OF PINS AVDD Analog power supply I 8, 18, 20, 22, 24, 26 6 AGND Analog ground I 9, 12, 14, 17, 19, 25 6 CLKP, CLKM Differential clock input I 10, 11 2 INP, INM Differential analog input I 15, 16 2 VCM Internal reference mode - Common-mode voltage output. External reference mode - Reference input. The voltage forced on this pin sets the internal references. I/O 13 1 IREF Current-set resistor, 56.2-k resistor to ground. I 21 1 I 30 1 I 29 1 Serial interface RESET input. RESET When using the serial interface mode, the user MUST initialize internal registers through hardware RESET by applying a high-going pulse on this pin, or by using the software reset option. See the SERIAL INTERFACE section. In parallel interface mode, the user has to tie RESET pin permanently HIGH. (SDATA and SEN are used as parallel pin controls in this mode). The pin has an internal 100-k pull-down resistor. SCLK 24 This pin functions as serial interface clock input when RESET is low. It functions as LOW SPEED mode control pin when RESET is tied high. Tie SCLK to LOW for Fs > 50 MSPS and SCLK to HIGH for Fs 50 MSPS. See Table 3. The pin has an internal 100-k pull-down resistor. Submit Documentation Feedback ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 PIN CONFIGURATION (CMOS MODE) (continued) PIN ASSIGNMENTS - CMOS Mode (continued) PIN NAME DESCRIPTION PIN TYPE PIN NUMBER NUMBER OF PINS I 28 1 I 27 1 This pin functions as serial interface data input when RESET is low. It functions as STANDBY control pin when RESET is tied high. SDATA See Table 4 for detailed information. The pin has an internal 100 k pull-down resistor. SEN This pin functions as serial interface enable input when RESET is low. It functions as CLKOUT edge programmability when RESET is tied high. See Table 5 for detailed information. The pin has an internal 100-k pull-up resistor to DRVDD. OE Output buffer enable input, active high. The pin has an internal 100-k pull-up resistor to DRVDD. I 7 1 DFS Data Format Select input. This pin sets the DATA FORMAT (Twos complement or Offset binary) and the LVDS/CMOS output mode type. See Table 6 for detailed information. I 6 1 MODE Mode select input. This pin selects the internal or external reference mode. See Table 7 for detailed information. I 23 1 CLKOUT CMOS output clock O 5 1 D0 CMOS output data D0 O 33 1 D0 CMOS output data D1 O 34 1 D2 CMOS output data D2 O 37 1 D2 CMOS output data D3 O 38 1 D4 CMOS output data D4 O 39 1 D4 CMOS output data D5 O 40 1 D6 CMOS output data D6 O 41 1 D7 CMOS output data D7 O 42 1 D8 CMOS output data D8 O 43 1 D9 CMOS output data D9 O 44 1 D10 CMOS output data D10 O 45 1 D11 CMOS output data D11 O 46 1 D12 CMOS output data D12 O 47 1 D13 CMOS output data D13 O 48 1 OVR Out-of-range indicator, CMOS level signal O 3 1 DRVDD Digital and output buffer supply I 2, 35 2 DRGND Digital and output buffer ground I 1, 36 2 UNUSED Unused pin in CMOS mode 4 1 NC Do not connect 31, 32 2 PAD Connect the pad to ground plane. See Board Design Considerations in application information section. 0 1 Submit Documentation Feedback 25 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 TYPICAL CHARACTERISTICS All plots are at 25C, AVDD = DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, -1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS data output (unless otherwise noted) FFT for 10 MHz INPUT SIGNAL FFT for 40 MHz INPUT SIGNAL 0 0 SFDR = 91.4 dBc, SNR = 74.2 dBFS, SINAD = 74 dBFS -40 SFDR = 89.2 dBc, SNR = 74 dBFS, SINAD = 73.7 dBFS -20 Amplitude - dB Amplitude - dB -20 -60 -80 -100 -120 -40 -60 -80 -100 -120 -140 -140 0 10 20 30 40 50 60 70 80 0 90 10 20 f - Frequency - MHz 30 FFT for 70 MHz INPUT SIGNAL 70 80 90 80 90 FFT for 100 MHz INPUT SIGNAL 0 SFDR = 87.8 dBc, SNR = 73.7 dBFS, SINAD = 73.3 dBFS -40 SFDR = 86.9 dBc, SNR = 73.2 dBFS, SINAD = 72.8 dBFS -20 Amplitude - dB -20 Amplitude - dB 60 Figure 10. 0 -60 -80 -100 -120 -40 -60 -80 -100 -120 -140 -140 0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 f - Frequency - MHz f - Frequency - MHz Figure 11. Figure 12. FFT for 130 MHz INPUT SIGNAL FFT for 150 MHz INPUT SIGNAL 0 0 SFDR = 86.5 dBc, SNR = 72.8 dBFS, SINAD = 72.3 dBFS -40 SFDR = 85.2 dBc, SNR = 72.4 dBFS, SINAD = 71.9 dBFS -20 Amplitude - dB -20 Amplitude - dB 50 f - Frequency - MHz Figure 9. -60 -80 -100 -120 -40 -60 -80 -100 -120 -140 -140 0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 f - Frequency - MHz f - Frequency - MHz Figure 13. 26 40 Figure 14. Submit Documentation Feedback 70 80 90 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 TYPICAL CHARACTERISTICS (continued) All plots are at 25C, AVDD = DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, -1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS data output (unless otherwise noted) FFT for 200 MHz INPUT SIGNAL FFT for 225 MHz INPUT SIGNAL 0 0 SFDR = 77.2 dBc, SNR = 71.7 dBFS, SINAD = 69.4 dBFS -40 SFDR = 74 dBc, SNR = 71 dBFS, SINAD = 69.9 dBFS -20 Amplitude - dB Amplitude - dB -20 -60 -80 -100 -40 -60 -80 -100 -120 -120 -140 -140 0 10 20 30 40 50 60 70 80 0 90 10 20 30 Figure 15. 60 70 80 90 Figure 16. FFT for 300 MHz INPUT SIGNAL FFT for 375 MHz INPUT SIGNAL 0 0 SFDR = 72.1 dBc, SNR = 70.1 dBFS, SINAD = 66.3 dBFS -40 SFDR = 65.6 dBc, SNR = 68.7 dBFS, SINAD = 62.3 dBFS -20 Amplitude - dB -20 Amplitude - dB 50 f - Frequency - MHz f - Frequency - MHz -60 -80 -100 -40 -60 -80 -100 -120 -120 -140 -140 0 10 20 30 40 50 60 70 80 0 90 10 20 30 40 50 60 70 80 90 f - Frequency - MHz f - Frequency - MHz Figure 17. Figure 18. FFT for 500 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY 0 0 SFDR = 59 dBc, SNR = 66 dBFS, SINAD = 56.3 dBFS -40 FIN1 = 50.09 MHz, -7 dBFS, FIN2 = 46.09 MHz, -7 dBFS, 2-Tone IMD, 95 dBFS -20 Amplitude - dB -20 Amplitude - dB 40 -60 -80 -100 -120 -40 -60 -80 -100 -120 -140 -140 0 10 20 30 40 50 60 70 80 90 0 f - Frequency - MHz 10 20 30 40 50 60 70 80 90 f - Frequency - MHz Figure 19. Figure 20. Submit Documentation Feedback 27 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 TYPICAL CHARACTERISTICS (continued) All plots are at 25C, AVDD = DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, -1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS data output (unless otherwise noted) INTERMODULATION DISTORTION (IMD) vs FREQUENCY SFDR vs INPUT FREQUENCY 94 0 FIN1 = 135.08 MHz, -7 dBFS, FIN2 = 130.08 MHz, -7 dBFS, 2-Tone IMD, 89 dBFS 90 86 -40 SFDR - dBc Amplitude - dB -20 -60 -80 -100 82 78 74 70 66 -120 62 -140 58 0 10 20 30 40 50 60 70 80 0 90 50 100 150 200 250 300 350 400 450 500 fIN - Input Frequency - MHz f - Frequency - MHz Figure 21. Figure 22. SNR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY 75 LVDS Mode 73 72 SNR - dBFS SNR - dBFS 74 71 70 69 68 67 66 65 0 50 100 150 200 250 300 350 400 450 500 75 74 73 72 71 70 69 68 67 66 65 64 63 10 DDR LVDS CMOS Data Position 3 CMOS Data Position 2 CMOS Data Position 1 CMOS Data Position 4 20 30 fIN - Input Frequency - MHz 40 Figure 23. SNR vs GAIN 75 5 dB 0 dB 6 dB 4 dB 3 dB 2 dB 1 dB Input Adjusted to -1 dBFS for Each Gain Setting 30 50 70 74 1 dB 73 2 dB 72 3 dB 71 4 dB 70 5 dB 69 6 dB 68 0 dB 10 SNR - dBFS SFDR - dBc 70 100 130 170 230 300 Figure 24. SFDR vs GAIN 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 50 fIN - Input Frequency - MHz 67 10 30 90 110 130 150 170 190 210 230 50 70 90 110 130 150 170 190 210 230 fIN - Input Frequency - MHz fIN - Input Frequency - MHz Figure 25. 28 Figure 26. Submit Documentation Feedback ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 TYPICAL CHARACTERISTICS (continued) All plots are at 25C, AVDD = DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, -1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS data output (unless otherwise noted) PERFORMANCE vs AVDD PERFORMANCE vs DRVDD 73.6 FIN = 70 MHz DRVDD = 3.3 V SNR 87 73.3 86 SFDR - dBc 73.4 88 3 3.1 3.2 3.3 3.4 3.5 73.2 87 86 73.1 85 72.4 72.0 3.1 3.2 3.4 3.5 Figure 27. Figure 28. PERFORMANCE vs TEMPERATURE SNR vs SAMPLING FREQUENCY ACROSS POWER SCALING MODES 90 73 74.5 87 74 86 SNR - dBFS SFDR 88 SNR - dBFS 75 89 73.5 10 35 50 72 Default 71 Power Mode 1 70 Power Mode 3 69 68 SNR -15 3.6 74 75.5 fIN = 70 MHz SFDR - dBc 3.3 DRVDD - Supply Voltage - V AVDD - Supply Voltage - V 85 -40 72.8 SNR 3.0 3.6 73.6 SFDR 88 73.2 SFDR 85 fIN = 70 MHz AVDD = 3.3 V 89 73.5 SNR - dBFS SFDR - dBc 89 74.0 90 SNR - dBFS 90 Power Mode 2 73 85 67 fIN = 70 MHz 66 40 TA - Free-Air Temperature - oC 60 80 100 120 140 160 180 200 FS - Sampling Frequency - MSPS Figure 29. Figure 30. PERFORMANCE vs CLOCK AMPLITUDE 84 95 74.8 83 74.5 82 81 SFDR (dBFS) 85 75 74.3 SNR 74.0 65 73.8 55 SFDR (dBc) 45 73.5 35 25 -60 73.3 fIN = 10 MHz -50 73.0 -40 -30 -20 -10 0 75 SFDR 74 SNR 80 73 79 72 78 77 fIN = 150 MHz Sine Wave Input Clock 76 75 74 0.34 0.64 Input Amplitude - dBFS Figure 31. 0.94 1.24 1.54 1.84 2.14 Clock Amplitude - VPP SNR - dBFS 75.0 SFDR - dBc 105 SNR - dBFS SFDR - dBc, dBFS PERFORMANCE vs INPUT AMPLITUDE 71 2.44 70 2.74 Figure 32. Submit Documentation Feedback 29 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 TYPICAL CHARACTERISTICS (continued) All plots are at 25C, AVDD = DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, -1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS data output (unless otherwise noted) OUTPUT NOISE HISTOGRAM WITH INPUTS SHORTED TO COMMON-MODE PERFORMANCE vs INPUT CLOCK DUTY CYCLE 35 75.5 FIN = 10 MHz 15 10 SNR 73.5 55 60 65 Input Clock Duty Cycle - % Output Code Figure 33. Figure 34. PERFORMANCE IN EXTERNAL REFERENCE MODE 76 88 75 SFDR 74 86 SNR 84 73 82 72 80 1.4 71 COMMON-MODE REJECTION RATIO vs FREQUENCY -35 -40 CMRR - dBc 90 SNR - dBFS SFDR - dBc 8200 50 8198 45 8199 40 8197 0 73.0 35 8196 80 30 5 8195 82 8194 74.0 8193 84 20 8192 74.5 25 8191 86 Occurence - % SFDR SNR - dBFS SFDR - dBc 30 75.0 88 8190 90 -45 -50 -55 -60 -65 1.45 1.5 1.55 -70 0 1.6 1.21 1.16 1.11 1.06 1.01 0.96 0.91 0.86 0.81 0.76 0.71 0.66 0.61 60 80 100 Figure 36. POWER DISSIPATION vs SAMPLING FREQUENCY (DDR LVDS outputs) DRVDD CURRENT vs SAMPLING FREQUENCY (Parallel CMOS outputs) 100 Default Power Mode 1 Power Mode 2 Power Mode 3 20 40 60 80 100 120 140 160 180 200 CMOS 10-pF Load Cap 90 80 70 60 50 40 DDR LVDS 30 20 10 0 10 FS - Sampling Frequency - MSPS Figure 37. 30 40 Figure 35. LVDS Mode 0 20 f - Frequency of AC Common-Mode Voltage - MHz DRVDD Current - mA PD - Power Dissipation - W Voltage Forced on the CM Pin - V CMOS 5-pF Load Cap 30 50 70 90 110 130 150 170 190 f - Frequency - MSPS Figure 38. Submit Documentation Feedback CMOS 0-pF Load Cap ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 TYPICAL CHARACTERISTICS (continued) All plots are at 25C, AVDD = DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, -1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS data output (unless otherwise noted) 160 66 68 60 70 120 66 72 73 74 140 68 70 100 64 70 66 72 80 73 74 62 fS - Sampling Frequency - MSPS 62 70 72 74 180 73 190 65 64 68 10 50 100 150 200 250 300 350 400 450 500 72 74 fIN - Input Frequency - MHz 56 58 60 62 64 66 68 70 SNR - dBFS Figure 39. SNR Contour in dBFS 70 80 85 190 55 65 85 85 85 75 80 90 85 60 75 160 50 65 85 55 90 70 60 90 70 75 90 120 85 70 140 90 70 80 100 10 50 100 150 200 70 75 90 65 65 80 85 fS - Sampling Frequency - MSPS 180 250 300 60 350 400 450 500 80 85 90 95 fIN - Input Frequency - MHz 45 50 55 60 65 70 75 SFDR - dBc Figure 40. SFDR Contour in dBc Submit Documentation Feedback 31 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 APPLICATION INFORMATION THEORY OF OPERATION ADS5546 is a low power 14-bit 190 MSPS pipeline ADC in a CMOS process. ADS5546 is based on switched capacitor technology and runs off a single 3.3-V supply. The conversion process is initiated by a rising edge of the external input clock. Once the signal is captured by the input sample and hold, the input sample is sequentially converted by a series of lower resolution stages, with the outputs combined in a digital correction logic block. At every clock edge, the sample propagates through the pipeline resulting in a data latency of 14 clock cycles. The output is available as 14-bit data, in DDR LVDS or CMOS and coded in either straight offset binary or binary 2's complement format. ANALOG INPUT The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in Figure 41. This differential topology results in good ac-performance even for high input frequencies at high sampling rates. The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V, available on VCM pin 13. For a full-scale differential input, each input pin (INP, INM) has to swing symmetrically between VCM + 0.5 V and VCM - 0.5 V, resulting in a 2-VPP differential input swing. The maximum swing is determined by the internal reference voltages REFP (2.5 V nominal) and REFM (0.5 V, nominal). Sampling Switch Lpkg 6 nH Sampling Capacitor R-C-R Filter INP Cbond 2 pF 25 W Resr 200 W 4 pF Lpkg 6 nH Cpar2 1 pF 50 W Ron 15 W Ron 10 W Cpar1 0.8 pF 50 W Ron 15 W 25 W Csamp 3.2 pF Csamp 3.2 pF INM Cbond 2 pF Resr 200 W Sampling Capacitor Cpar2 1 pF Sampling Switch Figure 41. Input Stage The input sampling circuit has a 3-dB bandwidth that extends up to 500 MHz, see Figure 42 (measured from the input pins to the voltage across the sampling capacitors). 32 Submit Documentation Feedback ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 APPLICATION INFORMATION (continued) ADC Input Impedance, ZI 2 500 0 450 400 350 -2 Magnitude - W Magnitude - dB Transfer Function - ADC Only -4 -6 -8 -10 -12 -14 -16 0 100 200 300 400 500 600 700 800 900 1000 300 250 200 150 100 50 0 0 100 200 300 400 500 600 700 800 900 1000 f - Frequency - MHz f - Frequency - MHz Figure 42. Analog Input Bandwidth (Data From Actual Silicon) Figure 43. Impedance Looking Into INP, INM (Data From Simulation) Drive Circuit Requirements A 5- resistor in series with each input pin is recommended to damp out ringing caused by the package parasitics. It is also necessary to present a low impedance (< 50 ) for the common-mode switching currents. For example, this is achieved by using two resistors from each input terminated to the common-mode voltage (VCM). In addition to the above ADC requirements, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. For this, the ADC input impedance has to be considered, see Figure 43. Example Drive Circuits A configuration suitable for low input frequency ranges (< 100 MHz) is shown in Figure 44. Note the 5- series resistors and the low common-mode impedance (using 25- resistors terminated to VCM). In addition, the circuit has low insertion loss, and good impedance match at low input frequencies, see Figure 45. ADS5546 0.1 mF ADT1-1WT 5W INP 0.1 mF 25 W 25 W INM 5W 1:1 S11, ZI VCM Figure 44. Configuration for Low Input Frequencies Submit Documentation Feedback 33 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 APPLICATION INFORMATION (continued) S11 0 -10 S11 - dB -20 -30 -40 S(1, 1) -50 -60 -70 0 50 100 150 200 250 f - Frequency - MHz Transfer Function - Source To ADC Output (Including the Transformer) Frequency (100 kHz to 500 MHz) 3 Frequency = 100 MHz S(1, 1) = 0.11/-1.19E2 Impedance = 44.07 - j8.63 Magnitude - dB 1 -1 -3 -5 -7 -9 0 50 100 150 200 250 f - Frequency - MHz Figure 45. S11, Input Impedance and Transfer Function for the Configuration in Figure 44 For high input frequencies, the previous configuration has been modified to improve the insertion loss and impedance matching (see Figure 46). The S11 curve shows that the matching is good from 100 MHz to 300 MHz. 34 Submit Documentation Feedback ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 APPLICATION INFORMATION (continued) ADS5546 TC4-1W 0.1 mF 12 nH (Note A) TC4-1W 5W INP 0.1 mF 50 W 50 W INM 1:2 12 nH (Note A) 2:1 5W S11, ZI A. VCM Includes transformer leakage inductances. Figure 46. Configuration for Higher Input Frequencies S11 0 -5 S11 - dB -10 S(1, 1) -15 -20 -25 0 100 200 300 400 500 600 700 800 900 1000 f - Frequency - MHz Transfer Function - Source to ADC Output (Including the Transformer) Frequency (100 kHz to 500 MHz) 2 Frequency = 200 MHz S(1, 1) = 0.09/50.92 Impedance = 55.57 + j8.03 Magnitude - dB 0 -2 -4 -6 -8 -10 0 50 100 150 200 250 300 350 400 450 500 f - Frequency - MHz Figure 47. S11, Input Impedance and Transfer Function for the Configuration in Figure 46 Submit Documentation Feedback 35 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 APPLICATION INFORMATION (continued) Using RF Transformer-Based Drive Circuits For optimum performance, the analog inputs must be driven differentially. This improves the common-mode noise immunity and even order harmonic rejection. Some examples of input configurations using RF transformers suitable for low and high input frequencies are shown in Figure 46 and Figure 47. The single-ended signal is fed to the primary winding of the RF transformer. The transformer is terminated on the secondary side. Putting the termination on the secondary side helps to shield the kickbacks caused by the sampling circuit from the RF transformer's leakage inductances. The termination is accomplished by two resistors connected in series, with the center point connected to the 1.5 V common-mode (VCM pin 13). The value of the termination resistors (connected to common-mode) has to be low (< 100 ) to provide a low-impedance path for the ADC common-mode switching current. At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch, and good performance is obtained for high frequency input signals. An additional termination resistor pair (enclosed within the shaded box in Figure 46) may be required between the two transformers to improve the balance between the P and M sides. The center point of this termination must be connected to ground. (Note that the drive circuit has to be tuned to account for this additional termination, to get the desired S11 and impedance match). Using Differential Amplifier Drive Circuits Figure 48 shows a drive circuit using a differential amplifier (TI's THS4509) to convert a single-ended input to differential output that can be interface to the ADC analog input pins. In addition to the single-ended to differential conversion, the amplifier also provides gain (10 dB in Figure 48). RFIL helps to isolate the amplifier outputs from the switching input of the ADC. Together with CFIL it also forms a low-pass filter that band-limits the noise (and signal) at the ADC input. As the amplifier output is ac-coupled, the common-mode voltage of the ADC input pins is set using two 200 resistors connected to VCM. The amplifier output can also be dc-coupled. Using the output common-mode control of the THS4509, the ADC input pins can be biased to 1.5V. In this case, use +4 V and -1 V supplies for the THS4509 so that its output common-mode voltage (1.5 V) is at mid-supply. RF +VS 500 W 0.1 mF RS 0.1 mF 10 mF RFIL 0.1 mF 5W INP RG 0.1 mF RT CFIL 200 W CFIL 200 W CM THS4509 RG RFIL INM RS || RT 0.1 mF 5W 0.1 mF 500 W VCM -VS 0.1 mF 10 mF 0.1 mF RF Figure 48. Drive Circuit Using the THS4509 See the EVM User Guide (SLWU028) for more information. 36 Submit Documentation Feedback ADS5546 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 APPLICATION INFORMATION (continued) Input Common-Mode To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1-F low-inductance capacitor connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC sinks a common-mode current in the order of 310 A (at 190 MSPS). Equation 1 describes the dependency of the common-mode current and the sampling frequency. (310 mA) x Fs 190 MSPS (1) This equation helps to design the output capability and impedance of the CM driving circuit accordingly. Reference ADS5546 has built-in internal references REFP and REFM, requiring no external components. Design schemes are used to linearize the converter load seen by the references; this and the integration of the requisite reference capacitors on-chip eliminates the need for external decoupling. The full-scale input range of the converter can be controlled in the external reference mode as explained below. The internal or external reference modes can be selected by controlling the MODE pin 23 (see Table 7 for details) or by programming the serial interface register bit <REF> (Table 16). INTREF Internal Reference VCM INTREF EXTREF REFM REFP ADS5546 S0165-01 Figure 49. Reference Section Internal Reference When the device is in internal reference mode, the REFP and REFM voltages are generated internally. Common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog input pins. Submit Documentation Feedback 37 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 APPLICATION INFORMATION (continued) External Reference When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential input voltage corresponding to full-scale is given by Equation 2. Full-scale differential input pp + (Voltage forced on VCM) 1.33 (2) In this mode, the 1.5 V common-mode voltage to bias the input pins has to be generated externally. There is no change in performance compared to internal reference mode. Low Sampling Frequency Operation For best performance at high sampling frequencies, ADS5546 uses a clock generator circuit to derive internal timing for the ADC. The clock generator operates from 190 MSPS down to 50 MSPS in the DEFAULT SPEED mode. The ADC enters this mode after applying reset (with serial interface configuration) or by tying SCLK pin to low (with parallel configuration). For low sampling frequencies (below 50 MSPS), the ADC must be put in the LOW SPEED mode. This mode can be entered by: * setting the register bit <LOW SPEED> (Table 10) through the serial interface, OR * tying the SCLK pin to high (see Table 3) using the parallel configuration. Clock Input ADS5546 clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS), with little or no difference in performance between configurations. The common-mode voltage of the clock inputs is set to VCM using internal 5-k resistors as shown in Figure 50. This allows the use of transformer-coupled drive circuits for sine wave clock, or ac-coupling for LVPECL, LVDS clock sources (Figure 51 and Figure 52) VCM VCM 5 kW 5 kW CLKP CLKM ADS5546 S0166-01 Figure 50. Internal Clock Buffer 38 Submit Documentation Feedback ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 APPLICATION INFORMATION (continued) For best performance, it is recommended to drive the clock inputs differentially, reducing susceptibility to common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with 0.1-F capacitors, as shown in Figure 51. 0.1 mF CLKP Differential Sine-Wave or PECL or LVDS Clock Input 0.1 mF CLKM ADS5546 Figure 51. Differential Clock Driving Circuit A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin 11) connected to ground with a 0.1-F capacitor, as shown in Figure 52. 0.1 mF CMOS Clock Input CLKP 0.1 mF CLKM ADS5546 Figure 52. Single-Ended Clock Driving Circuit For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode noise. For high input frequency sampling, the use a clock source with very low jitter is recommended. Bandpass filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a non-50% duty cycle clock input. Figure 33 shows the performance variation of the ADC versus clock duty cycle Clock Buffer Gain When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude is increased. Therefore, using a large amplitude clock is recommended. In addition, the clock buffer has a programmable gain option to amplify the input clock. The clock buffer gain can be set by programming the register bits <CLKIN GAIN> (Table 14). The clock buffer gain decreases monotonically from Gain 4 to Gain 0 settings. Submit Documentation Feedback 39 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 APPLICATION INFORMATION (continued) Programmable Gain ADS5546 has programmable gain from 0 dB to 6 dB in steps of 1 dB. The corresponding full-scale input range varies from 2 VPP down to 1 VPP, with 0 dB being the default gain. At high IF, this is especially useful as the SFDR improvement is significant with marginal degradation in SNR. The gain can be programmed using the chapter bits <GAIN> (Table 12). Table 19. Full-scale Range Across Gains Gain Corresponding full-scale range, Vpp 0 dB 2.00 1 dB 1.78 2 dB 1.59 3 dB 1.42 4 dB 1.26 5 dB 1.12 6 dB 1.00 Power Down ADS5546 has three power-down modes - global STANDBY, output buffer disabled, and input clock stopped. Global STANDBY This mode can be initiated by controlling SDATA (pin 28) or by setting the register bit <STBY> (Table 10) through the serial interface. In this mode, the A/D converter, reference block and the output buffers are powered down and the total power dissipation reduces to about 100 mW. The output buffers are in high impedance state. The wake-up time from the global power down to data becoming valid normal mode is maximum 100 s. Output Buffer Disable The output buffers can be disabled using OE pin 7 in both the LVDS and CMOS modes, reducing the total power by about 100 mW. With the buffers disabled, the outputs are in high impedance state. The wake-up time from this mode to data becoming valid in normal mode is maximum 1 s in LVDS mode and 50 ns in CMOS mode. Input Clock Stop The converter enters this mode when the input clock frequency falls below 1 MSPS. The power dissipation is about 100 mW and the wake-up time from this mode to data becoming valid in normal mode is maximum 100 s. 40 Submit Documentation Feedback ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 Power Scaling Modes ADS5546 has a power scaling mode in which the device can be operated at reduced power levels at lower sampling frequencies with no difference in performance. (See Figure 30) (1) There are four power scaling modes for different sampling clock frequency ranges, using the serial interface register bits <SCALING> (Table 16). Only the AVDD power is scaled, leaving the DRVDD power unchanged. Table 20. Power Scaling vs Sampling Speed Sampling Frequency MSPS (1) Power Scaling Mode Analog Power (Typical) Analog Power in Default Mode > 150 Default 960 mW at 190 MSPS 960 mW at 190 MSPS 105 to 150 Power Mode 1 841 mW at 150 MSPS 917 mW at 150 MSPS 50 to 105 Power Mode 2 670 mW at 105 MSPS 830 mW at 105 MSPS < 50 Power Mode 3 525 mW at 50 MSPS 760 mW at 50 MSPS The performance in the power scaling modes is from characterization and not tested in production. Power Supply Sequence During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are separated inside the device. Externally, they can be driven from separate supplies or from a single supply. Digital Output Information ADS5546 provides 14-bit data, an output clock synchronized with the data and an out-of-range indicator that goes high when the output reaches the full-scale limits. In addition, output enable control (OE pin 7) is provided to power down the output buffers and put the outputs in high-impedance state. Output Interface Two output interface options are available - Double Data Rate (DDR) LVDS and parallel CMOS. They can be selected using the DFS (see Table 6) or the serial interface register bit <ODI>(Table 15). DDR LVDS Outputs In this mode, the 14 data bits and the output clock are available as LVDS (Low Voltage Differential Signal) levels. Two successive data bits are multiplexed and output on each LVDS differential pair as shown in Figure 53. So, there are 7 LVDS output pairs for the 14 data bits and 1 LVDS output pair for the output clock. Submit Documentation Feedback 41 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 Pins CLKOUTP Output Clock CLKOUTM D0_D1_P Data Bits D0. D1 D0_D1_M D2_D3_P Data Bits D2, D3 D2_D3_M D4_D5_P Data Bits D4, D5 D4_D5_M D6_D7_P Data Bits D6, D7 D6_D7_M D8_D9_P Data Bits D8, D9 D8_D9_M D10_D11_P Data Bits D10, D11 D10_D11_M D12_D13_P Data Bits D12, D13 D12_D13_M OVR Out-of-Range Indicator ADS5546 S0169-01 Figure 53. DDR LVDS Outputs Even data bits D0, D2, D4, D6, D8, D10, and D12 are output at the falling edge of CLKOUTP and the odd data bits D1, D3, D5, D7, D9, D11, and D13 are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP have to be used to capture all the 14 data bits (see Figure 54). 42 Submit Documentation Feedback ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 CLKOUTP CLKOUTM D0_D1_P, D0_D1_M D0 D1 D0 D1 D2_D3_P, D2_D3_M D2 D3 D2 D3 D4_D5_P, D4_D5_M D4 D5 D4 D5 D6_D7_P, D6_D7_M D6 D7 D6 D7 D8_D9_P, D8_D9_M D8 D9 D8 D9 D10_D11_P, D10_D11_M D10 D11 D10 D11 D12_D13_P, D12_D13_M D12 D13 D12 D13 Sample N Sample N+1 T0110-01 Figure 54. DDR LVDS Interface LVDS Buffer Current Programmability The default LVDS buffer output current is 3.5 mA. When terminated by 100 , this results in a 350-mV single-ended voltage swing (700-mVPP differential swing). The LVDS buffer currents can also be programmed to 2.5 mA, 4.5 mA, and 1.75 mA using the register bits <LVDS CURR> (Table 17). In addition, there exists a current double mode, where this current is doubled for the data and output clock buffers (register bits <CURR DOUBLE> (Table 18). LVDS Buffer Internal Termination An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially terminated inside the device. The termination resistances available are - 325, 200, and 170 (nominal with 20% variation). Any combination of these three terminations can be programmed; the effective termination is the parallel combination of the selected resistances. This results in eight effective terminations from open (no termination) to 75 . The internal termination helps to absorb any reflections coming from the receiver end, improving the signal integrity. With 100- internal and 100- external termination, the voltage swing at the receiver end is halved (compared to no internal termination). The voltage swing can be restored by using the LVDS current double mode. The termination can be programmed using register bits <DATA TERM> and <CLKOUT TERM> (Table 17). Submit Documentation Feedback 43 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 Parallel CMOS In this mode, the 14 data outputs and the output clock are available as 3.3-V CMOS voltage levels. Each data bit and the output clock is available on a separate pin in parallel. By default, the data outputs are valid during the rising edge of the output clock. The output clock is CLKOUT (pin 5). CMOS Mode Power Dissipation With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every output pin (see Figure 38). The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined by the average number of output bits switching, which is a function of the sampling frequency and the nature of the analog input signal. Digital current due to CMOS output switching = CL x VDRVDD x (N x FAVG) where CL = load capacitance, N x FAVG = average number of output bits switching Figure 38 shows the current with various load capacitances across sampling frequencies at 2MHz analog input frequency. Output Switching Noise and Data Position Programmability (in CMOS mode ONLY) Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant of sampling and degrade the SNR. To minimize this, the device includes programmable options to move the output data transitions with respect to the output clock. This can be used to position the data transitions at the optimum place away from the sampling instant and improve the SNR. Figure 24 shows the variation of SNR for different CMOS output data positions at 190 MSPS. Note that the optimum output data position varies with the sampling frequency. The data position can be programmed using the register bits <DATA POSN> (Table 9). It is recommended to put series resistors (50 to 100 ) on each output line placed very close to the converter pins. This helps to isolate the outputs from seeing large load capacitances and in turn reduces the amount of switching noise. For example, the data in Figure 24 was taken with 50 series resistors on each output line. Output Clock Position Programmability In both the LVDS and CMOS modes, the output clock can be moved around its default position. This can be done using SEN pin 27 (as described in Table 5) or using the serial interface register bits <CLKOUT POSN> (Table 9). Using this allows to trade-off the setup and hold times leading to reliable data capture. There also exists an option to align the output clock edge with the data transition. Note that programming the output clock position also affects the clock propagation delay times. Output Data Format Two output data formats are supported - 2's complement and offset binary. They can be selected using the DFS (pin 6) or the serial interface register bit <DF> (Table 10). In the event of an input voltage overdrive, the digital outputs go to the appropriate full scale level. For a positive overdrive, the output code is 0x3FFF in offset binary output format, and 0x1FFF in 2's complement output format. For a negative input overdrive, the output code is 0x0000 in offset binary output format and 0x2000 in 2's complement output format. Overvoltage Signal When the input voltage exceeds the full-scale range of the ADC, OVR (pin 3) goes high and the output code gets clamped to the appropriate full-scale level for the duration of the overload. For a positive overdrive, the output code is 0x3FFF in offset binary output format, and 0x1FFF in 2's complement output format. For a negative input overdrive, the output code is 0x0000 in offset binary output format and 0x2000 in 2's complement output format. shows the behaviour of OVR during the overload. Note that OVR and the output code react to the overload after a latency of 14 clock cycles. 44 Submit Documentation Feedback ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 Output Timing For the best performance at high sampling frequencies, ADS5546 uses a clock generator circuit to derive internal timing for ADC. This results in optimal setup and hold times of the output data and 50% output clock duty cycle for sampling frequencies from 80 MSPS to 190 MSPS. See Table 21 for timing information above 80 MSPS. Table 21. Timing Characteristics (80 MSPS to 190 MSPS) Fs, MSPS tsu DATA SETUP TIME, ns th DATA HOLD TIME, ns MIN TYP MAX MIN 190 1.3 1.8 0.5 150 1.6 2.1 0.6 130 2.0 2.5 0.8 80 3.6 4.1 190 2.5 150 2.8 130 80 TYP (1) tPDI CLOCK PROPAGATION DELAY, ns MAX MIN TYP MAX 1 3.9 4.6 5.3 1.1 4.3 5 5.7 1.3 4.5 5.2 5.9 1.6 2.1 4.7 5.7 6.7 3.3 0.8 1.2 1.9 2.7 3.5 3.6 1.2 1.6 1.7 2.5 3.3 3.3 4.1 1.7 2.1 1.1 1.9 2.7 6 7 3.7 4.1 10.8 12 13.2 DDR LVDS PARALLEL CMOS (1) Timing parameters are specified by design and characterization and not tested in production. Below 80 MSPS, the setup and hold times do not scale with the sampling frequency. The output clock duty cycle also progressively moves away from 50% as the sampling frequency is reduced from 80 MSPS. See Table 22 for detailed timings at sampling frequencies below 80 MSPS. Figure 55 shows the clock duty cycle across sampling frequencies in the DDR LVDS and CMOS modes. Table 22. Timing Characteristics (1 MSPS to 80 MSPS) Fs, MSPS tsu DATA SETUP TIME, ns MIN TYP th DATA HOLD TIME, ns MAX MIN TYP (1) tPDI CLOCK PROPAGATION DELAY, ns MAX MIN TYP MAX DDR LVDS 1 to 80 3.6 1.6 5.7 6 3.7 12 PARALLEL CMOS 1 to 80 Timing parameters are specified by design and characterization and not tested in production. Output Clock Duty Cycle - % (1) 100 90 80 70 60 DDR LVDS 50 40 CMOS 30 20 10 0 0 20 40 60 80 100 120 140 160 180 Sampling Frequency - MHz Figure 55. Output Clock Duty Cycle (typical) vs Sampling Frequency The latency of ADS5546 is 14 clock cycles from the sampling instant (input clock rising edge). In the LVDS mode, the latency remains constant across sampling frequencies. In the CMOS mode, the latency is 14 clock cycles above 80 MSPS and 13 clock cycles below 80 MSPS. Submit Documentation Feedback 45 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 Board Design Considerations Grounding A single ground plane is sufficient to give good performance, provided the analog, digital and clock sections of the board are cleanly partitioned. Refer to the EVM User Guide (SLWU028) for details on layout and grounding. Supply Decoupling As the ADS5546 already includes internal decoupling, minimal external decoupling can be used without loss in performance. Note that decoupling capacitors can help to filter external power supply noise, so the optimum number of capacitors would depend on the actual application. The decoupling capacitors should be placed very close to the converter supply pins. It is recommended to use separate supplies for the analog and digital supply pins to isolate digital switching noise from sensitive analog circuitry. In case only a single 3.3V supply is available, it should be routed first to AVDD. It can then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, before being routed to DRVDD. Series Resistors on Data Outputs It is recommended to put series resistors (50 to 100 ) on each output line placed very close to the converter pins. This helps to isolate the outputs from seeing large load capacitances and in turn reduces the amount of switching noise. Exposed Thermal Pad It is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermal performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and QFN/SON PCB Attachment (SLUA271). 46 Submit Documentation Feedback ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low frequency value. Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle. Maximum Conversion Rate The maximum sampling rate at which certified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Minimum Conversion Rate The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs Integral Nonlinearity (INL) The INL is the deviation of the ADC's transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Gain Error The gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Offset Error The offset error is the difference, given in number of LSBs, between the ADC's actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV. Temperature Drift The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter across the TMIN to TMAX range by the difference TMAX-TMIN. Submit Documentation Feedback 47 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 DEFINITION OF SPECIFICATIONS (continued) Signal-to-Noise Ratio SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc and the first nine harmonics. P SNR + 10Log 10 s PN (4) SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's full-scale range. Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. Ps SINAD + 10Log 10 PN ) PD (5) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's full-scale range. Effective Number of Bits (ENOB) The ENOB is a measure of a converter's performance as compared to the theoretical limit based on quantization noise. ENOB + SINAD * 1.76 6.02 (6) Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD). P THD + 10Log 10 s PN (7) THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR) The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1-f2 or 2f2-f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's full-scale range. DC Power Supply Rejection Ratio (DC PSRR) The DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The DC PSRR is typically given in units of mV/V. 48 Submit Documentation Feedback ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 DEFINITION OF SPECIFICATIONS (continued) AC Power Supply Rejection Ratio (AC PSRR) AC PSRR is the measure of rejection of variations in the supply voltage of the ADC. If VSUP is the change in the supply voltage and VOUT is the resultant change in the ADC output code (referred to the input), then DVOUT PSRR = 20Log 10 (Expressed in dBc) DVSUP (8) Common Mode Rejection Ratio (CMRR) CMRR is the measure of rejection of variations in the input common-mode voltage of the ADC. If Vcm is the change in the input common-mode voltage and VOUT is the resultant change in the ADC output code (referred to the input), then DVOUT CMRR = 20Log10 (Expressed in dBc) DVCM (9) Voltage Overload Recovery The number of clock cycles taken to recover to less than 1% error for a 6-dB overload on the analog inputs. A 6-dBFS sine wave at Nyquist frequency is used as the test stimulus. Submit Documentation Feedback 49 ADS5546 www.ti.com SLWS183D - NOVEMBER 2005 - REVISED APRIL 2007 ADS5546 Revision history Revision Date Description A 11/05 Added new graphs to the Typical Characteristics. B 6/06 New Timing Characteristics table. New text for the Device Mode Configuration Parallel Pin Control section changed to Parallel Configuration Only section. Added Serial Interface Configuration Only section. Added Configuration Using Both the Serial Interface and Parallel Controls New text for the Serial Interface section Added Register Reset section Additions to Table 8, <RST> and <GAIN> Revised Typical Characteristics graphs. Added Programmable gain section in the Application Information C 10/06 Added DEFAULT and LOW SPEED modes to the Clock Input of the Recommended Operating Conditions Changed the max Standby power specifications. Changed the max Clock stop power specifications. Changed Analog Input information and Figures. Changed Drive Circuit and Example Drive Circuit information and Figures. Added Using RF Transformer-Based Drive Circuits information. D 4/07 Thermal Pad to pinout (Figure 7 and Figure 8) Added graph - DRVDD CURRENT (Figure 38) Revised Serial Register and Application Information Added section in Application Information - Using Differential Amplifier Drive Circuits Added section in Application Information - CMOS Mode Power Dissipation Added min/max specs for Offset error and Gain error Added Board Design Considerations in application section Added Using Differential Amplifier Drive Circuits information and figure. 50 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) ADS5546IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ5546 ADS5546IRGZTG4 ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 AZ5546 PADS5546IRGZT PREVIEW VQFN RGZ 48 TBD Call TI Call TI -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS5546IRGZT Package Package Pins Type Drawing VQFN RGZ 48 SPQ 250 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 16.4 Pack Materials-Page 1 7.3 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 7.3 1.5 12.0 16.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS5546IRGZT VQFN RGZ 48 250 336.6 336.6 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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