ISPLSI 1016-80LJN - LATTICE SEMICONDUCTOR

Features

•Multi Channel Half-duplex Transceiver with Approximately ±2.5 MHz Programmable

Tuning Range

•High FSK Sensitivity: –106 dBm at 20 Kbit/s/–109.5 dBm at 2.4 Kbit/s (433.92 MHz)

•High ASK Sensitivity: –112.5 dBm at 10 Kbit/s/–116.5 dBm at 2.4 Kbit/s (433.92 MHz)

•Low Supply Current: 10.5 mA in RX and TX Mode (3V/TX with 5 dBm)

•Data Rate: 1 to 20 Kbit/s Manchester FSK, 1 to 10 Kbit/s Manchester ASK

•ASK/FSK Receiver Uses a Low-IF Architecture with High Selectivity, Blocking, and Low

Intermodulation (Typical Blocking 55 dB at ±750 kHz/61 dB at ±1.5 MHz and

70 dB at ±10 MHz, System I1dBCP = –30 dBm/System IIP3 = –20 dBm)

•226 kHz/237 kHz IF Frequency with 30 dB Image Rejection and 170 kHz Usable IF

Bandwidth

•Transmitter Uses Closed Loop Fractional-N Synthesizer for FSK Modulation with a

High PLL Bandwidth and an Excellent Isolation between PLL/VCO and PA

•Tolerances of XTAL Compensated by Fractional-N Synthesizer with 800 Hz RF

Resolution

•Integrated RX/TX-Switch, Single-ended RF Input and Output

•RSSI (Received Signal Strength Indicator)

•Communication to Microcontroller with SPI Interface Working at Maximum 500 kBit/s

•Configurable Self Polling and RX/TX Protocol Handling with FIFO-RAM Buffering of

Received and Transmitted Data

•5 Push Button Inputs and One Wake-up Input are Active in Power-down Mode

•Integrated XTAL Capacitors

•PA Efficiency: up to 38% (433.92 MHz/10 dBm/3V)

•Low In-band Sensitivity Change of Typically ±1.8 dB within ±58 kHz Center Frequency

Change in the Complete Temperature and Supply Voltage Range

•Supply Voltage Switch, Supply Voltage Regulator, Reset Generation, Clock/Interrupt

Generation and Low Battery Indicator for Microcontroller

•Fully Integrated PLL with Low Phase Noise VCO, PLL Loop Filter and Full Support of

Multi-channel Operation with Arbitrary Channel Distance Due to Fractional-N

Synthesizer

•Sophisticated Threshold Control and Quasi-peak Detector Circuit in the Data Slicer

•Power Management via Different Operation Modes

•315 MHz, 345 MHz, 433.92 MHz, 868.3 MHz and 915 MHz without External VCO and PLL

Components

•Inductive Supply with Voltage Regulator if Battery is Empty (AUX Mode)

•Efficient XTO Start-up Circuit (> –1.5 kΩ Worst Case Real Start-up Impedance)

•Changing of Modulation Type ASK/FSK and Data Rate without Component Changes

•Minimal External Circuitry Requirements for Complete System Solution

•Adjustable Output Power: 0 to 10 dBm Adjusted and Stabilized with External Resistor

•ESD Protection at all Pins (1.5 kV HBM, 200V MM, 1 kV FCDM)

•Supply Voltage Range: 2.4V to 3.6V or 4.4V to 6.6V

•Temperature Range: –40°C to +85°C

•Small 7 × 7 mm QFN48 Package

UHF ASK/FSK

Transceiver

ATA5423

ATA5425

ATA5428

ATA5429

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

Applications

•Consumer Industrial Segment

•Access Control Systems

•Remote Control Systems

•Alarm and Telemetry Systems

•Energy Metering

•Home Automation

Benefits

•Low System Cost Due to Very High System Integration Level

•Only One Crystal Needed in System

•Less Demanding Specification for the Microcontroller Due to Handling of Power-down Mode,

Delivering of Clock, Reset, Low Battery Indication and Complete Handling of Receive/Transmit

Protocol and Polling

•Single-ended Design with High Isolation of PLL/VCO from PA and the Power Supply Allows a

Loop Antenna in the Remote Control Unit to Surround the Whole Application

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

1. General Description

The ATA5423/25/28/29 is a highly integrated UHF ASK/FSK multi-channel half-duplex trans-

ceiver with low power consumption supplied in a small 7 x 7 mm QFN48 package. The receive

part is built as a fully integrated low-IF receiver, whereas direct PLL modulation with the frac-

tional-N synthesizer is used for FSK transmission and switching of the power amplifier for ASK

transmission.

The device supports data rates of 1 Kbit/s to 20 Kbit/s (FSK) and 1 Kbit/s to 10 Kbit/s (ASK) in

Manchester, Bi-phase and other codes in transparent mode. The ATA5428 can be used in the

431.5 MHz to 436.5 MHz and in the 862 MHz to 872 MHz bands, the ATA5423 in the 312.5 MHz

to 317.5 MHz band, the ATA5425 in the 342.5 MHz to 347.5 MHz band and the ATA5429 in the

912.5 MHz to 917.5 MHz band. The very high system integration level results in a small number

of external components needed.

Due to its blocking and selectivity performance, together with the additional 15 dB to 20 dB loss

and the narrow bandwidth of a typical loop antenna in a remote control unit, a bulky blocking

SAW is not needed in the remote control unit. Additionally, the building blocks needed for a typi-

cal remote control and access control system on both sides (the base and the mobile stations)

are fully integrated.

Its digital control logic with self-polling and protocol generation enables a fast challenge-

response system without using a high-performance microcontroller. Therefore, the

ATA5423/ATA5425/ATA5428/ATA5429 contains a FIFO buffer RAM and can compose and

receive the physical messages themselves. This provides more time for the microcontroller to

carry out other functions such as calculating crypto algorithms, composing the logical messages,

and controlling other devices. Therefore, a standard 4-/8-bit microcontroller without special

periphery and clocked with the CLK output of about 4.5 MHz is sufficient to control the communi-

cation link. This is especially valid for passive entry and access control systems, where within

less than 100 ms several challenge-response communications with arbitration of the communi-

cation partner have to be handled.

It is hence possible to design bi-directional remote control and access control systems with a

fast challenge-response crypto function, with the same PCB board size and with the same cur-

rent consumption as uni-directional remote control systems.

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

Figure 1-1. System Block Diagram

Figure 1-2. Pinning QFN48

XTO

ATA5423/ATA5425/ATA5428/ATA5429

Antenna

4 to 8

Power

Supply

ATmega

44/88/168

Matching/

RF Switch

Digital Control

Logic

RF Transceiver

Microcontroller

interface

RSSI

SCK

SDI_TMDI

SDO_TMDO

ATA5423/ATA5425

ATA5428/ATA5429 CLK

VSINT

XTAL2

N_RESET

IRQ

DEM_OUT

RF_IN

433_N868

RF_OUT

PWR_H

R_PWR

AVCC

VS2

VS1

VAUX

TEST1

DVCC

VSOUT

TEST2

TXAL1

RX_ACTIVE

PWR_ON

RX_TX1

RX_TX2

CDEM

NC 12

47 46 45 44 38 373941 404243

NC NC

13 15 16 17 23 242220 211918

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

Table 1-1. Pin Description

Pin Symbol Function

1 NC Not connected

2 NC Not connected

3 NC Not connected

4 RF_IN RF input

5 NC Not connected

6 433_N868 Selects RF input/output frequency range

7 NC Not connected

8 R_PWR Resistor to adjust output power

9 PWR_H Pin to select output power

10 RF_OUT RF output

11 NC Not connected

12 NC Not connected

13 NC Not connected

14 NC Not connected

15 NC Not connected

16 AVCC Blocking of the analog voltage supply

17 VS2 Power supply input for voltage range 4.4V to 6.6V

18 VS1 Power supply input for voltage range 2.4V to 3.6V

19 VAUX Auxiliary supply voltage input

20 TEST1 Test input, at GND during operation

21 DVCC Blocking of the digital voltage supply

22 VSOUT Output voltage power supply for external devices

23 TEST2 Test input, at GND during operation

24 XTAL1 Reference crystal

25 XTAL2 Reference crystal

26 NC Not connected

27 VSINT Microcontroller interface supply voltage

28 N_RESET Output pin to reset a connected microcontroller

29 IRQ Interrupt request

30 CLK Clock output to connect a microcontroller

31 SDO_TMDO Serial data out/transparent mode data out

32 SDI_TMDI Serial data in/transparent mode data in

33 SCK Serial clock

34 DEM_OUT Demodulator open drain output signal

35 CS Chip select for serial interface

36 RSSI Output of the RSSI amplifier

37 CDEM Capacitor to adjust the lower cut-off frequency data filter

38 RX_TX2 GND pin to decouple LNA in TX mode

39 RX_TX1 Switch pin to decouple LNA in TX mode

40 PWR_ON Input to switch on the system (active high)

41 T5 Key input 5 (can also be used to switch on the system (active low))

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

Figure 1-3. Block Diagram

42 T4 Key input 4 (can also be used to switch on the system (active low))

43 T3 Key input 3 (can also be used to switch on the system (active low))

44 T2 Key input 2 (can also be used to switch on the system (active low))

45 T1 Key input 1 (can also be used to switch on the system (active low))

46 RX_ACTIVE Indicates RX operation mode

47 NC Not connected

48 NC Not connected

GND Ground/backplane

Table 1-1. Pin Description (Continued)

Pin Symbol Function

Signal

Processing

(Mixer

IF-filter

IF-amplifier

FSK/ASK

Demodulator,

Data filter

Data Slicer)

TX/RX - Data buffer

Control register

Status register

Polling circuit

Bit-check logic

Digital Control Logic Power

Supply

Switches

Regulators

Wake-up

Reset

RF transceiver

Fractional-N

frequency

synthesizer

VS2

VAUX

VSOUT

VS1

433_N868

PWR_H

SDO_TMDO

IRQ

N_RESET

CLK

DEM_OUT

XTAL2

XTAL1

RSSI

CDEM

RF_IN

RX_TX2

RX_TX1

RF_OUT

R_PWR

DVCCRX_ACTIVEAVCC

GNDVSINT

LNA

SPI

XTO

Reset

RX/TX

switch

Frontend Enable

PA_Enable (ASK)

Demod_Out

FREF

FREQ

RX/TX

TX_DATA (FSK)

Microcontroller

interface

SCK

SDI_TMDI

TEST2

TEST1

PWR_ON

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

2. Application Circuits

2.1 Typical Remote Control Unit Application with 1 Li Battery (3V)

Figure 2-1 shows a typical 433.92 MHz Remote Control Unit application with one battery. The

external components are 11 capacitors, 1 resistor, 2 inductors and a crystal. C1 to C4 are 68 nF

voltage supply blocking capacitors. C5 is a 10 nF supply blocking capacitor. C6 is a 15 nF fixed

capacitor used for the internal quasi-peak detector and for the high-pass frequency of the data

filter. C7 to C11 are RF matching capacitors in the range of 1 pF to 33 pF. L1 is a matching induc-

tor of about 5.6 nH to 56 nH. L2 is a feed inductor of about 120 nH. A load capacitor of 9 pF for

the crystal is integrated. R1 is typically 22 kΩ and sets the output power to about 5.5 dBm. The

loop antenna’s quality factor is somewhat reduced by this application due to the quality factor of

L2 and the RX/TX switch. On the other hand, this lower quality factor is necessary to have a

robust design with a bandwidth that is broad enough for production tolerances. Due to the sin-

gle-ended and ground-referenced design, the loop antenna can be a free-form wire around the

application as it is usually employed in remote control uni-directional systems. The

ATA5423/ATA5425/ATA5428/ATA5429 provides sufficient isolation and robust pulling behavior

of internal circuits from the supply voltage as well as an integrated VCO inductor to allow this.

Since the efficiency of a loop antenna is proportional to the square of the surrounded area it is

beneficial to have a large loop around the application board with a lower quality factor in order to

relax the tolerance specification of the RF components and to get a high antenna efficiency in

spite of their lower quality factor.

Figure 2-1. Typical Remote Control Unit Application, 433.92 MHz, 1 Li Battery (3V)

RSSI

CDEM

SCK

DEM_OUT

SDI_TMDI

SDO_TMDO

ATA5423/ATA5425

ATA5428/ATA5429 CLK

VCC VSS

Sensor

VSINT

XTAL2

+ Lithium cell

Loop antenna

AVCC

20 mm x 0.4 mm

ATmega

48/88/168

13.25311 MHz

N_RESET

IRQ

RF_IN

C11 C6

433_N868

RF_OUT

PWR_H

R_PWR

AVCC

VS2

VS1

VAUX

TEST1

DVCC

VSOUT

TEST2

TXAL1

RX_ACTIVE

PWR_ON

RX_TX1

RX_TX2

C10

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

2.2 Typical Base-station Application (5V)

Figure 2.2 shows a typical 433.92 MHz VCC = 4.75V to 5.25V Base-station Application (5V). The

external components are 12 capacitors, 1 resistor, 4 inductors, a SAW filter, and a crystal. C1

and C3 to C4 are 68 nF voltage supply blocking capacitors. C2 and C12 are 2.2 µF supply block-

ing capacitors for the internal voltage regulators. C5 is a 10 nF supply blocking capacitor. C6 is a

15 nF fixed capacitor used for the internal quasi-peak detector and for the high-pass frequency

of the data filter. C7 to C11 are RF matching capacitors in the range of 1 pF to 33 pF. L2 to L4 are

matching inductors of about 5.6 nH to 56 nH. A load capacitor for the crystal of 9 pF is inte-

grated. R1 is typically 22 kΩ and sets the output power at RF_OUT to about 10 dBm. Since a

quarter wave or PCB antenna, which has high efficiency and wide band operation, is typically

used here, it is recommended to use a SAW filter to achieve high sensitivity in case of powerful

out-of-band blockers. L1, C9 and C10 together form a low-pass filter, which is needed to filter out

the harmonics in the transmitted signal to meet regulations. An internally regulated voltage at pin

VSOUT can be used in case the microcontroller only supports 3.3V operation, a blocking capac-

itor with a value of C12 = 2.2 µF has to be connected to VSOUT in any case.

Figure 2-2. Typical Base-station Application (5V), 433.92 MHz

RSSI

CDEM

SCK

DEM_OUT

SDI_TMDI

SDO_TMDO

CLK

VSINT

XTAL2

AVCC

50Ω

connector

SAW-Filter

20 mm x 0.4 mm

13.25311 MHz

VCC = 4.75V to 5.25V

N_RESET

IRQ

RF_IN

C11 C6

C1C4

C12

433_N868

RF_OUT

PWR_H

R_PWR

AVCC

VS2

VS1

VAUX

TEST1

DVCC

VSOUT

TEST2

TXAL1

RX_ACTIVE

PWR_ON

RX_TX1

RX_TX2

C10 C9

RFOUT

VCC VSS

Sensor

ATmega

48/88/168

ATA5423/ATA5425

ATA5428/ATA5429

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

2.3 Typical Remote Control Unit Application, 2 Li Batteries (6V)

Figure 2-3 shows a typical 433.92 MHz 2 Li battery Remote Control Unit application. The exter-

nal components are 11 capacitors, 1 resistor, 2 inductors and a crystal. C1 and C4 are 68 nF

voltage supply blocking capacitors. C2 and C3 are 2.2 µF supply blocking capacitors for the inter-

nal voltage regulators. C5 is a 10 nF supply blocking capacitor. C6 is a 15 nF fixed capacitor

used for the internal quasi-peak detector and for the high-pass frequency of the data filter. C7 to

C11 are RF matching capacitors in the range of 1 pF to 33 pF. L1 is a matching inductor of about

5.6 nH to 56 nH. L2 is a feed inductor of about 120 nH. A load capacitor for the crystal of 9 pF is

integrated. R1 is typically 22 kΩ and sets the output power to about 5.5 dBm.

Figure 2-3. Typical Remote Control Unit Application, 433.92 MHz, 2 Li Batteries (6V)

RSSI

CDEM

SCK

DEM_OUT

SDI_TMDI

SDO_TMDO

ATA5423/ATA5425

ATA5428/ATA5429 CLK

VCC VSS

Sensor

VSINT

XTAL2

+ Lithium cell

Loop antenna

AVCC

20 mm x 0.4 mm

ATmega

48/88/168

13.25311 MHz

N_RESET

IRQ

RF_IN

C11 C6

433_N868

RF_OUT

PWR_H

R_PWR

AVCC

VS2

VS1

VAUX

TEST1

DVCC

VSOUT

TEST2

TXAL1

RX_ACTIVE

PWR_ON

RX_TX1

RX_TX2

C10

+ Lithium cell

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

3. RF Transceiver

As seen in Figure 1-3 on page 6, the RF transceiver consists of an LNA (Low-noise Amplifier),

PA (Power Amplifier), RX/TX switch, fractional-N frequency synthesizer and the signal process-

ing part with mixer, IF filter, IF amplifier with analog RSSI, FSK/ASK demodulator, data filter, and

data slicer.

In receive mode the LNA pre-amplifies the received signal which is converted down to 226 kHz

(ATA5423/ATA5428) and 235 kHz (ATA5425/ATA5429), filtered and amplified before it is fed

into an FSK/ASK demodulator, data filter, and data slicer. The RSSI (Received Signal Strength

Indicator) signal and the raw digital output signal of the demodulator are available at the pins

RSSI and DEM_OUT. The demodulated data signal Demod_Out is fed to the digital control logic

where it is evaluated and buffered as described in the section “Digital Control Logic” .

In transmit mode, the fractional-N frequency synthesizer generates the TX frequency which is

fed to the PA. In ASK mode the PA is modulated by the signal PA_Enable. In FSK mode the PA

is enabled and the signal TX_DATA (FSK) modulates the fractional-N frequency synthesizer.

The frequency deviation is digitally controlled and internally fixed to about ±16 kHz (see Table

4-1 on page 28 for exact values). The transmit data can also be buffered as described in the

section “Digital Control Logic” . A lock detector within the synthesizer ensures that the transmis-

sion will start only if the synthesizer is locked.

The RX/TX switch can be used to combine the LNA input and the PA output to a single antenna

with a minimum of losses.

Transparent modes without buffering of RX and TX data are also available to allow protocols

and coding schemes other than the internally supported Manchester encoding.

3.1 Low-IF Receiver

The receive path consists of a fully integrated low-IF receiver. It fulfills the sensitivity, blocking,

selectivity, supply voltage and supply current specification needed to manufacture, for example,

an automotive remote control unit without the use of SAW blocking filter (see Figure 2-1 on page

7). In a Base-station Application (5V) the receiver can be used with an additional blocking SAW

front-end filter as shown in Figure 2.2 on page 8.

At 433.92 MHz the receiver has a typical system noise figure of 7.0 dB, a system I1dBCP of

-30 dBm and a system IIP3 of –20 dBm. There is no AGC or switching of the LNA needed; thus,

a better blocking performance is achieved. This receiver uses an IF (Intermediate Frequency) of

226 kHz, the typical image rejection is 30 dB and the typical 3 dB IF filter bandwidth is 185 kHz

(fIF = 226 kHz ±92.5 kHz, flo_IF = 133.5 kHz and fhi_IF = 318.5 kHz). The demodulator needs a

signal to Gaussian noise ratio of 8 dB for 20 Kbit/s Manchester with ±16 kHz frequency deviation

in FSK mode; thus, the resulting sensitivity at 433.92 MHz is typically –106 dBm at 20 Kbit/s

Manchester.

Due to the low phase noise and spurious emissions of the synthesizer in receive mode(1)

together with the eighth order integrated IF filter, the receiver has a better selectivity and block-

ing performance than more complex double superhet receivers but without external components

and without numerous spurious receiving frequencies.

11
4841D–WIRE–10/07
ATA5423/ATA5425/ATA5428/ATA5429
A low-IF architecture is also less sensitive to second-order intermodulation (IIP2) than direct
conversion receivers, where every pulse or AM-modulated signal (especially the signals from
TDMA systems like GSM) demodulates to the receiving signal band at second-order
non-linearities.
Note: –120 dBC/Hz at ±1 MHz and –75 dBC at ±FREF at 433.92 MHz 
3.2 Input Matching at RF_IN
The measured input impedances as well as the values of a parallel equivalent circuit of these
impedances can be seen in Table 3-1. The highest sensitivity is achieved with power matching
of these impedances to the source impedance of 50Ω
The matching of the LNA Input to 50Ω was done with the circuit shown in Figure 3-1 and with the
values given in Table 3-2 on page 12. The reflection coefficients were always ≤10 dB. Note that
value changes of C1 and L1 may be necessary to compensate for individual board layouts. The
measured typical FSK and ASK Manchester code sensitivities with a Bit Error Rate (BER) of 10-3
are shown in Table 3-3 and Table 3-4 on page 12. These measurements were done with induc-
tors having a quality factor according to Table 3-2, resulting in estimated matching losses of
0.8 dB at 315 MHz, 0.8 dB at 345 MHz, 0.7 dB at 433.92 MHz, 0.7 dB at 868.3 MHz and 0.7 at
915 MHz. These losses can be estimated when calculating the parallel equivalent resistance of
the inductor with Rloss =2×π×f×L×QL and the matching loss with 10 log(1 + Rp/Rloss).
With an ideal inductor, for example, the sensitivity at 433.92 MHz/FSK/20 Kbit/s/
±16 kHz/Manchester can be improved from –106 dBm to –106.7 dBm. The sensitivity depends
on the control logic which examines the incoming data stream. The examination limits must be
programmed in control registers 5 and 6. The measurements in Table 3-3 and Table 3-4 on
page 12 are based on the values of registers 5 and 6 according to Table 9-3 on page 61.
Figure 3-1. Input Matching to 50Ω 
Table 3-1. Measured Input Impedances of the RF_IN Pin
fRF/MHz Z(RF_IN) Rp//Cp
315 (44-j233)Ω1278Ω//2.1 pF
345 (40-j211)Ω1153Ω//2.1 pF
433.92 (32-j169)Ω925Ω//2.1 pF
868.3 (21-j78)Ω311Ω//2.2 pF
915 (18-j70)Ω290Ω//2.3 pF
L1
C14RF_IN
ATA5423/ATA5425
ATA5428/ATA5429

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

3.3 Sensitivity versus Supply Voltage, Temperature and Frequency Offset

To calculate the behavior of a transmission system it is important to know the reduction of the

sensitivity due to several influences. The most important are frequency offset due to crystal

oscillator (XTO) and crystal frequency (XTAL) errors, temperature and supply voltage depen-

dency of the noise figure and IF filter bandwidth of the receiver. Figure 3-2 shows the typical

sensitivity at 433.92 MHz/FSK/20 Kbit/s/±16 kHz/Manchester versus the frequency offset

between transmitter and receiver with Tamb = –40°C, +25°C and +105°C and supply voltage

VS1 = VS2 = 2.4V, 3.0V and 3.6V.

Table 3-2. Input Matching to 50Ω

fRF/MHz C1/pF L1/nH QL1

315 2.4 47 66

345 1.8 43 67

433.92 1.8 27 70

868.3 1.2 6.8 50

915 1.3 5.6 52

Table 3-3. Measured Sensitivity FSK, ±16 kHz, Manchester, dBm, BER = 10–3

Frequency

BR_Range_0

1.0 Kbit/s

BR_Range_0

2.4 Kbit/s

BR_Range_1

5.0 Kbit/s

BR_Range_2

10 Kbit/s

BR_Range_3

20 Kbit/s

315 MHz –110.0 dBm –110.5 dBm –109.0 dBm –108.0 dBm –107.0 dBm

345 MHz –109.5 dBm –110.5 dBm –109.0 dBm –107.5 dBm –107.0 dBm

433.92 MHz –109.0 dBm –109.5 dBm –108.0 dBm –107.0 dBm –106.0 dBm

868.3 MHz –106.0 dBm –106.5 dBm –105.5 dBm –104.0 dBm –103.5 dBm

915 MHz –105.5 dBm –106.0 dBm –105.0 dBm –103.5 dBm –103.0 dBm

Table 3-4. Measured Sensitivity 100% ASK, Manchester, dBm, BER = 10–3

RF Frequency

BR_Range_0

1.0 Kbit/s

BR_Range_0

2.4 Kbit/s

BR_Range_1

5.0 Kbit/s

BR_Range_2

10 Kbit/s

315 MHz –117.0 dBm –117.5 dBm –115.0 dBm –113.5 dBm

345 MHz –117.0 dBm –117.5 dBm –115.0 dBm –113.0 dBm

433.92 MHz –116.0 dBm –116.5 dBm –114.0 dBm –112.5 dBm

868.3 MHz –112.5 dBm –113.0 dBm –111.5 dBm –109.5 dBm

915 MHz –112.5 dBm –113.0 dBm –111.0 dBm –109.0 dBm

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

Figure 3-2. Measured Sensitivity 433.92 MHz/FSK/20 Kbit/s/±16 kHz/Manchester versus

Frequency Offset, Temperature and Supply Voltage

As can be seen in Figure 3-2 on page 13 the supply voltage has almost no influence. The tem-

perature has an influence of about +1.5/–0.7 dB, and a frequency offset of ±65 kHz also

influences by about ±1 dB. All these influences, combined with the sensitivity of a typical IC, are

then within a range of –103.7 dBm and –107.3 dBm over temperature, supply voltage and fre-

quency offset which is –105.5 dBm ±1.8dB. The integrated IF filter has an additional production

tolerance of only ±7 kHz, hence, a frequency offset between the receiver and the transmitter of

±58 kHz can be accepted for XTAL and XTO tolerances.

Note: For the demodulator used in the ATA5423/ATA5425, the tolerable frequency offset does not

change with the data frequency, hence, the value of ±58 kHz is valid for up to 1 Kbit/s.

This small sensitivity spread over supply voltage, frequency offset and temperature is very

unusual in such a receiver. It is achieved by an internal, very fast and automatic frequency cor-

rection in the FSK demodulator after the IF filter, which leads to a higher system margin. This

frequency correction tracks the input frequency very quickly; if, however, the input frequency

makes a larger step (for example, if the system changes between different communication part-

ners), the receiver has to be restarted. This can be done by switching back to IDLE mode and

then again to RX mode. For that purpose, an automatic mode is also available. This automatic

mode switches to IDLE mode and back into RX mode every time a bit error occurs. (See “Digital

Control Logic” on page 36.)

-109

-108

-107

-106

-105

-104

-103

-102

-101

-100

-99

-98

-97

-96

-95

-110

-60 40 60 10080-40-80-100 0

Frequenc

Offset (kHz)

Sensitivity (dBm)

20-20

VS = 3.0V Tamb = -40°C

VS = 3.6V Tamb = -40°C

VS = 3.0V Tamb = +25°C

VS = 3.6V Tamb = +25°C

VS = 2.4V Tamb = +105°C

VS = 3.0V Tamb = +105°C

VS = 3.6V Tamb = +105°C

VS = 2.4V Tamb = +25°C

VS = 2.4V Tamb = -40°C

14
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3.4 Frequency Accuracy of the Crystals
The XTO is an amplitude regulated Pierce oscillator with integrated load capacitors. The initial
tolerances (due to the frequency tolerance of the XTAL, the integrated capacitors on XTAL1,
XTAL2 and the XTO’s initial transconductance gm) can be compensated to a value within
±0.5 ppm by measuring the CLK output frequency and programming the control registers 2 and
3 (see Table 7-7 on page 39 and Table 7-10 on page 40). The XTO then has a remaining influ-
ence of less than ±2 ppm over temperature and supply voltage due to the band gap controlled
gm of the XTO.
The needed frequency stability of the used crystals over temperature and aging is hence
±58 kHz/315 MHz – 2 ×±2.5 ppm = ±179.2 ppm for 315 MHz, 
±58 kHz/345 MHz – 2 ×±2.5 ppm = ±163.2 ppm for 345 MHz, 
±58kHz/433.92MHz–2×±2.5 ppm = ±128.6 ppm for 433.92 MHz, 
±58 kHz/868.3 MHz – 2 ×±2.5 ppm = ±61.8 ppm for 868.3 MHz and 
±58 kHz/915 MHz – 2 ×±2.5 ppm = ±58.4 ppm for 915 MHz.
Thus, the used crystals in receiver and transmitter each need to be better than ±89.6 ppm for
315 MHz, ±81.6 ppm for 345 MHz, ±64.3 ppm for 433.92 MHz, ±30.9 ppm for 868.3 MHz and
±29.2 ppm for 915 MHz. In access control systems it may be advantageous to have a more tight
tolerance at the Base-station in order to relax the requirement for the remote control unit.
3.5 RX Supply Current versus Temperature and Supply Voltage
Table 3-5 shows the typical supply current at 433.92 MHz of the transceiver in RX mode versus
supply voltage and temperature with VS = VS1 = VS2. As can be seen, the supply current at
2.4 V and –40°C is less than the typical supply current; this is useful because this is also the
operation point where a lithium cell has the worst performance. The typical supply current at
315 MHz, 345 MHz, 868.3 MHz or 915 MHz in RX mode is about the same as for 433.92 MHz.
3.6 Blocking, Selectivity
As can be seen in Figure 3-3 and Figure 3-4 on page 15, the receiver can receive signals 3 dB
higher than the sensitivity level in the presence of very large blockers of –47 dBm/–34 dBm with
small frequency offsets of ±1/±10 MHz.
Figure 3-3 shows narrow band blocking and Figure 3-4 wide band blocking characteristics. The
measurements were done with a signal of 433.92 MHz/FSK/20 Kbit/s/±16 kHz/ Manchester, and
with a level of –106 dBm + 3 dB = –103 dBm which is 3 dB above the sensitivity level. The fig-
ures show how much larger than –103dBm a continuous wave signal can be before the BER is
higher than 10–3. The measurements were done at the 50Ω input according to Figure 3-1 on
page 11. At 1 MHz, for example, the blocker can be 56 dB higher than –103 dBm which is
-103 dBm + 56 dB = –47 dBm. These values, together with the good intermodulation perfor-
mance, avoid the need for a SAW filter in the remote control unit application.
Table 3-5. Measured 433.92 MHz Receive Supply Current in FSK Mode
VS = VS1 = VS2 2.4V 3.0V 3.6V
Tamb = –40°C 8.4 mA 8.8 mA 9.2 mA
Tamb = 25°C 9.9 mA 10.3 mA 10.8 mA
Tamb = 85°C 10.9 mA 11.3 mA 11.8 mA

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Figure 3-3. Narrow Band 3 dB Blocking Characteristic at 433.92 MHz

Figure 3-4. Wide Band 3 dB Blocking Characteristic at 433.92 MHz

Figure 3-5 on page 16 shows the blocking measurement close to the received frequency to illus-

trate the selectivity and image rejection. This measurement was done 6 dB above the sensitivity

level with a useful signal of 433.92 MHz/FSK/20 Kbit/s/±16 kHz/ Manchester with a level of

–106 dBm + 6 dB = –100 dBm. The figure shows to which extent a continuous wave signal can

surpass –100 dBm until the BER is higher than 10-3. For example, at 1 MHz the blocker can then

be 59 dB higher than –100 dBm which is –100 dBm + 59 dB = –41 dBm.

Table 3-6 on page 16 shows the blocking performance measured relative to –100 dBm for some

other frequencies. Note that sometimes the blocking is measured relative to the sensitivity level

(dBS) instead of the carrier (dBC).

-1 0 1 2-5 -4 -3 -2

Distance of Interfering to Receiving Signal (MHz)

Blocking Level (dBC)

-10

Blocking Level (dBC)

-10

-10 0 10 20-50 -40 -30 -20

Distance of Interfering to Receiving Signal (MHz)

30 40 50

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The ATA5423/ATA5425/ATA5428/ATA5429 can also receive FSK and ASK modulated signals if

they are much higher than the I1dBCP. It can typically receive useful signals at 10 dBm. This is

often referred to as the nonlinear dynamic range which is the maximum to minimum receiving

signal and is 116 dB for 20 Kbit/s Manchester. This value is useful if two transceivers have to

communicate and are very close to each other.

Figure 3-5. Close In 6 dB Blocking Characteristic and Image Response at 433.92 MHz

This high blocking performance even makes it possible for some applications using quarter

wave whip antennas to use a simple LC band-pass filter instead of a SAW filter in the receiver.

When designing such an LC filter take into account that the 3 dB blocking at

433.92 MHz/2 = 216.96 MHz is 43 dBC and at 433.92 MHz/3 = 144.64 MHz is 48 dBC and at

2×(433.92 MHz + 226 kHz) + –226 kHz = 868.066 MHz/868.518 MHz is 56 dBC. And espe-

cially that at 3 ×(433.92 MHz + 226 kHz) + 226 kHz = 1302.664 MHz the receiver has its

second LO harmonic receiving frequency with only 12 dBC blocking.

Table 3-6. Blocking 6 dB Above Sensitivity Level with BER < 10–3

Frequency Offset Blocker Level Blocking

+0.75 MHz –45 dBm 55 dBC/61 dBS

–0.75 MHz –45 dBm 55 dBC/61 dBS

+1.5 MHz –38 dBm 62 dBC/68 dBS

–1.5 MHz –38 dBm 62 dBC/68 dBS

+10 MHz –30 dBm 70 dBC/76 dBS

–10 MHz –30 dBm 70 dBC/76 dBS

Blocking Level (dBC)

-10

-0.2 0 0.2 0.4-1.0 -0.8 -0.6 -0.4

Distance of Interfering to Receiving Signal (MHz)

0.6 0.8 1.0

Distance of Interfering to Receiving Signal (MHz)

Blocking Level (dBC)

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3.7 In-band Disturbers, Data Filter, Quasi-peak Detector, Data Slicer

If a disturbing signal falls into the received band or a blocker is not continuous wave, the perfor-

mance of a receiver strongly depends on the circuits after the IF filter. The demodulator, data

filter and data slicer are important, in that case.

The data filter of the ATA5423/ATA5425/ATA5428/ATA5429 implies a quasi-peak detector. This

results in a good suppression of the above mentioned disturbers and exhibits a good carrier to

Gaussian noise performance. The required useful signal to disturbing signal ratio to be received

with a BER of 10–3 is less than 12 dB in ASK mode and less than 3 dB (BR_Range_0 to

BR_Range_2)/6 dB (BR_Range_3) in FSK mode. Due to the many different waveforms possible

these numbers are measured for signal as well as for disturbers with peak amplitude values.

Note that these values are worst case values and are valid for any type of modulation and mod-

ulating frequency of the disturbing signal as well as the receiving signal. For many combinations,

lower carrier to disturbing signal ratios are needed.

3.8 DEM_OUT Output

The internal raw output signal of the demodulator Demod_Out is available at pin DEM_OUT.

DEM_OUT is an open drain output and must be connected to a pull-up resistor if it is used (typi-

cally 100 kΩ) otherwise no signal is present at that pin.

3.9 RSSI Output

The output voltage of the pin RSSI is an analog voltage, proportional to the input power level.

Using the RSSI output signal, the signal strength of different transmitters can be distinguished.

The usable dynamic range of the RSSI amplifier is 70 dB, the input power range P(RFIN) is

–115 dBm to –45 dBm and the gain is 8 mV/dB. Figure 3-6 shows the RSSI characteristic of a

typical device at 433.92 MHz with VS1 = VS2 = 2.4 to 3.6 V and Tamb = –40°C to +85°C with a

matched input according to Table 3-2 on page 12 and Figure 3-1 on page 11. At 915 MHz about

3.3 dB and at 868.3 MHz about 2.7 dB more signal level, at 345 MHz about 0.8 dB and at

315 MHz about 1 dB less signal level is needed for the same RSSI results.

Figure 3-6. Typical RSSI Characteristic versus Temperature and Supply Voltage

400

500

600

700

800

900

1000

1100

-80 -70 -60 -50-120 -110 -100 -90

PRF_IN (dBm)

VRSSI (mV)

-40

max.

min. typ.

18
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3.10 Frequency Synthesizer
The synthesizer is a fully integrated fractional-N design with internal loop filters for receive and
transmit mode. The XTO frequency fXTO is the reference frequency FREF for the synthesizer.
The bits FR0 to FR12 in control registers 2 and 3 (see Table 7-7 on page 39 and Table 7-10 on
page 40) are used to adjust the deviation of fXTO. In transmit mode, at 433.92 MHz, the carrier
has a phase noise of –111 dBC/Hz at 1 MHz and spurious emissions at FREF of –66 dBC with a
high PLL loop bandwidth allowing the direct modulation of the carrier with 20 Kbit/s Manchester
data. Due to the closed loop modulation any spurious emissions caused by this modulation are
effectively filtered out as can be seen in Figure 3-9 on page 20. In RX mode the synthesizer has
a phase noise of –120 dBC/Hz at 1 MHz and spurious emissions of –75 dBC.
The initial tolerances of the crystal oscillator due to crystal tolerances, internal capacitor toler-
ances and the parasitics of the board have to be compensated at manufacturing setup with
control registers 2 and 3 as can be seen in Table 4-1 on page 28. The other control words for the
synthesizer needed for ASK, FSK and receive/transmit switching are calculated internally. The
RF (Radio Frequency) resolution is equal to the XTO frequency divided by 16384 which is
777.1 Hz at 315.0 MHz, 851.1 Hz at 345.0 MHz, 808.9 Hz at 433.92 MHz, 818.6 Hz at
868.3 MHz and 862.6 Hz at 915.0 MHz.
For the multi-channel system the frequency control word FREQ in control registers 2 and 3 can
be programmed in the range of 1000 to 6900, this is equivalent to a programmable tuning range
of ±2.5 MHz hence every frequency within the 315 MHz, 345 MHz, 433 MHz, 868 MHz and
915 MHz ISM bands can be programmed as receive and as transmit frequency, and the position
of channels within these ISM bands can be chosen arbitrarily (see Table 4-1).
Care must be taken as to the harmonics of the CLK output signal as well as to the harmonics
produced by a microprocessor clocked with it, since these harmonics can disturb the reception
of signals. In a single-channel system, using FREQ = 3803 to 4053 ensures that harmonics of
this signal do not disturb the receive mode.
3.11 FSK/ASK Transmission
Due to the fast modulation capability of the synthesizer and the high resolution, the carrier can
be internally FSK modulated, which simplifies the application of the transceiver. The deviation of
the transmitted signal is ±20 digital frequency steps of the synthesizer which is equal to
±15.54 kHz for 315 MHz, ±17.02 kHz for 345 MHz, ±16.17 kHz for 433.92 MHz, ±16.37 kHz for
868.3 MHz and ±17.25 kHz for 915 MHz.
Due to closed loop modulation with PLL filtering the modulated spectrum is very clean, meeting
ETSI and CEPT regulations when using a simple LC filter for the power amplifier harmonics as it
is shown in Figure 2.2 on page 8. In ASK mode the frequency is internally connected to the cen-
ter of the FSK transmission and the power amplifier is switched on and off to perform the
modulation. Figure 3-7 on page 19 to Figure 3-9 on page 20 show the spectrum of the FSK mod-
ulation with pseudo-random data with 20 Kbit/s/±16.17 kHz/Manchester and 5 dBm output
power.

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Figure 3-7. FSK-modulated TX Spectrum (433.92MHz/20 Kbit/s/±16.17 kHz/Manchester Code)

Figure 3-8. Unmodulated TX Spectrum 433.92 MHz – 16.17 kHz (fFSK_L)

Atten 20 dB

VAvg

S3 FC

W1 S2

Ref 10 dB

Span 30 MHz

Swee

7.5 ms

(

401

)

Center 433.92 MHz

VBW 100 kHzRes BW 100 kHz

Samp

Log

dB/

Atten 20 dB

Span 1 MHz

Sweep 27.5 ms (401 pts)

Center 433.92 MHz

VBW 10 kHzRes BW 10 kHz

VAvg

S3 FC

W1 S2

Ref 10 dB

Samp

Log

dB/

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Figure 3-9. FSK-modulated TX Spectrum (433.92 MHz/20 Kbit/s/±16.17 kHz/Manchester Code)

3.12 Output Power Setting and PA Matching at RF_OUT

The Power Amplifier (PA) is a single-ended open collector stage which delivers a current pulse

which is nearly independent of supply voltage, temperature and tolerances due to band gap sta-

bilization. Resistor R1, see Figure 3-10 on page 21, sets a reference current which controls the

current in the PA. A higher resistor value results in a lower reference current, a lower output

power and a lower current consumption of the PA. The usable range of R1 is 15 kΩ to 56 kΩ. Pin

PWR_H switches the output power range between about 0 dBm to 5 dBm (PWR_H = GND) and

5 dBm to 10 dBm (PWR_H = AVCC) by multiplying this reference current by a factor 1

(PWR_H = GND) and 2.5 (PWR_H = AVCC), which corresponds to about 5 dB more output

power.

If the PA is switched off in TX mode, the current consumption without output stage with

VS1 = VS2 = 3 V, Tamb = 25°C is typically 6.5 mA for 868.3 MHz and 6.95 mA for 315 MHz and

433.92 MHz.

The maximum output power is achieved with optimum load resistances RLopt according to Table

3-7 on page 22 with compensation of the 1.0 pF output capacitance of the RF_OUT pin by

absorbing it into the matching network consisting of L1, C1, C3 as shown in Figure 3-10 on page

21. There must also be a low resistive DC path to AVCC to deliver the DC current of the power

amplifier's last stage. The matching of the PA output was done with the circuit shown in Figure

3-10 on page 21 with the values in Table 3-7 on page 22. Note that value changes of these ele-

ments may be necessary to compensate for individual board layouts.

Span 1 MHz

Swee

27.5 ms

(

401

)

Center 433.92 MHz

VBW 10 kHzRes BW 10 kHz

Atten 20 dB

VAvg

S3 FC

W1 S2

Ref 10 dB

Samp

Log

dB/

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Example:

According to Table 3-7 on page 22, with a frequency of 433.92 MHz and output power of

11 dBm the overall current consumption is typically 17.8 mA; hence, the PA needs

17.8 mA - 6.95 mA = 10.85 mA in this mode, which corresponds to an overall power amplifier

efficiency of the PA of (10(11dBm/10) × 1 mW)/(3 V ×10.85 mA) × 100% = 38.6% in this case.

Using a higher resistor in this example of R1=1.091×22 kΩ=24kΩ results in 9.1% less cur-

rent in the PA of 10.85 mA/1.091 = 9.95 mA and 10 × log(1.091) = 0.38 dB less output power if

using a new load resistance of 300Ω× 1.091 = 327Ω. The resulting output power is then

11 dBm – 0.38 dB = 10.6 dBm and the overall current consumption is

6.95 mA + 9.95 mA = 16.9 mA.

The values of Table 3-7 on page 22 were measured with standard multi-layer chip inductors with

quality factors Q according to Table 3-7 on page 22. Looking to the 433.92 MHz/11 dBm case

with the quality factor of QL1 = 43 the loss in this inductor is estimated with the parallel equivalent

resistance of the inductor Rloss =2×π×f×L×QL1 and the matching loss with

10 log (1 + RLopt/Rloss) which is equal to 0.32 dB losses in this inductor. Taking this into account,

the PA efficiency is then 42% instead of 38.6%.

Be aware that the high power mode (PWR_H = AVCC) can only be used with a supply voltage

higher than 2.7V, whereas the low power mode (PWR_H = GND) can be used down to 2.4V as

can be seen in the “Electrical Characteristics: General” on page 67.

The supply blocking capacitor C2 (10 nF) has to be placed close to the matching network

because of the RF current flowing through it.

Figure 3-10. Power Setting and Output Matching

OUT

10 RF_OUT

VPWR_H

AVCC

ATA5423/ATA5425/

ATA5428/ATA5429

PWR_H

8R_PWR

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3.13 Output Power and TX Supply Current versus Supply Voltage and Temperature

Table 3-8 on page 22 shows the measurement of the output power for a typical device with

VS = VS1 = VS2 in the 433.92 MHz and 6.2 dBm case versus temperature and supply voltage

measured according to Figure 3-10 on page 21 with components according to Table 3-7. As

opposed to the receiver sensitivity, the supply voltage has here the major impact on output

power variations because of the large signal behavior of a power amplifier. Thus, a two battery

system with voltage regulator or a 5V system shows much less variation than a 2.4V to 3.6V one

battery system because the supply voltage is then well within 3.0V and 3.6V.

The reason is that the amplitude at the output RF_OUT with optimum load resistance is

AVCC – 0.4V and the power is proportional to (AVCC – 0.4V)2 if the load impedance is not

changed. This means that the theoretical output power reduction if reducing the supply voltage

from 3.0V to 2.4V is 10 log ((3 V – 0.4 V)2/(2.4 V – 0.4 V)2)=2.2dB. Table 3-8 shows that prin-

ciple behavior in the measurement. This is not the same case for higher voltages, since here

increasing the supply voltage from 3V to 3.6V should theoretical increase the power by 1.8 dB;

but a gain of only 0.8 dB in the measurement shows that the amplitude does not increase with

the supply voltage because the load impedance is optimized for 3V and the output amplitude

stays more constant.

Table 3-7. Measured Output Power and Current Consumption with VS1 = VS2 = 3V, Tamb = 25°C

Frequency (MHz) TX Current (mA) Output Power (dBm) R1 (kΩ) VPWR_H RLopt (Ω)L1 (nH) Q

L1 C1 (pF) C3 (pF)

315 8.5 0.4 56 GND 2500 82 28 1.5 0

315 10.5 5.7 27 GND 920 68 32 2.2 0

315 16.7 10.5 27 AVCC 350 56 35 3.9 0

345 8.8 1.6 56 GND 2400 82 75 1.2 0

345 10.4 5.9 27 GND 900 68 74 1.8 0

345 16.9 10.7 27 AVCC 320 43 65 3.9 0

433.92 8.6 0.1 56 GND 2300 56 40 0.75 0

433.92 11.2 6.2 22 GND 890 47 38 1.5 0

433.92 17.8 11 22 AVCC 300 33 43 2.7 0

868.3 9.3 -0.3 33 GND 1170 12 58 1.0 3.3

868.3 11.5 5.4 15 GND 471 15 54 1.0 0

868.3 16.3 9.5 22 AVCC 245 10 57 1.5 0

915 9.6 0.1 33 GND 1100 12 62 0.7 0

915 11.8 4.9 15 GND 465 12 62 1.5 0

915 20.3 10.2 15 AVCC 230 10 60 1.5 0

Table 3-8. Measured Output Power and Supply Current at 433.92 MHz, PWR_H = GND

VS = 2.4 V 3.0 V 3.6 V

Tamb = –40°C 10.19 mA

3.8 dBm

10.19 mA

5.5 dBm

10.78 mA

6.2 dBm

Tamb = +25°C 10.62 mA

4.6 dBm

11.19 mA

6.2 dBm

11.79 mA

7.1 dBm

Tamb = +85°C 11.4 mA

3.9 dBm

12.02 mA

5.5 dBm

12.73 mA

6.6 dBm

23
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Table 3-9 shows the relative changes of the output power of a typical device compared to
3.0V/25°C. As can be seen, a temperature change to –40°C as well as to +85°C reduces the
power by less than 1 dB due to the band gap regulated output current. Measurements of all the
cases in Table 3-7 on page 22 over temperature and supply voltage have shown about the same
relative behavior as shown in Table 3-9.
3.14 RX/TX Switch
The RX/TX switch decouples the LNA from the PA in TX mode, and directs the received power
to the LNA in RX mode. To do this, it has a low impedance to GND in TX mode and a high
impedance to GND in RX mode. To design a proper RX/TX decoupling, a linear simulation tool
for radio frequency design together with the measured device impedances of Table 3-1 on page
11, Table 3-7 on page 22, Table 3-10 and Table 3-11 on page 24 should be used, but the exact
element values have to be found on-board. Figure 3-11 shows an approximate equivalent circuit
of the switch. The principal switching operation is described here according to the application of
Figure 2-1 on page 7. The application of Figure 2.2 on page 8 works similarly. 
Figure 3-11. Equivalent Circuit of the Switch 
Table 3-9. Measurements of Typical Output Power Relative to 3V/25°C
VS =  2.4V 3.0V 3.6V
Tamb = –40°C –2.4 dB –0.7 dB 0 dB
Tamb = +25°C –1.6 dB 0 dB +0.9 dB
Tamb = +85°C –2.3 dB –0.7 dB +0.4 dB
Table 3-10. Impedance of the RX/TX Switch RX_TX2 Shorted to GND
Frequency Z(RX_TX1) TX Mode Z(RX_TX1) RX Mode
315 MHz (4.8 + j3.2)Ω(11.3 – j214)Ω
345 MHz (4.7 + j3.4)Ω(11.1 – j181)Ω
433.92 MHz (4.5 + j4.3)Ω(10.3 – j153)Ω
868.3 MHz (5 + j9)Ω(8.9 – j73)Ω
915 MHz (5 + j9.2)Ω(9 – j65)Ω
1.6 nH
2.5 pF
RX_TX1
TX
11Ω5Ω

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3.15 Matching Network in TX Mode

In TX mode the 20 mm long and 0.4 mm wide transmission line which is much shorter than λ/4 is

approximately switched in parallel to the capacitor C9 to GND. The antenna connection between

C8 and C9 has an impedance of about 50Ω locking from the transmission line into the loop

antenna with pin RF_OUT, L2, C10, C8 and C9 connected (using a C9 without the added 7.6 pF

as discussed later). The transmission line can be approximated with a 16 nH inductor in series

with a 1.5Ω resistor, the closed switch can be approximated according to Table 3-10 on page 23

with the series connection of 1.6 nH and 5Ω in this mode. To have a parallel resonant high

impedance circuit with little RF power going into it looking from the loop antenna into the trans-

mission line a capacitor of about 7.6 pF to GND is needed at the beginning of the transmission

line (this capacitor is later absorbed into C9 which is then higher, as needed for 50Ω transforma-

tion). To keep the 50Ω impedance in RX mode at the end of this transmission line, C7 also has to

be about 7.6 pF. This reduces the TX power by about 0.5 dB at 433.92 MHz compared to the

case the where the LNA path is completely disconnected.

3.16 Matching Network in RX Mode

In RX mode the RF_OUT pin has a high impedance of about 7 kΩ in parallel with 1.0 pF at

433.92 MHz as can be seen in Table 3-11. This, together with the losses of the inductor L2 with

120 nH and QL2 = 25, gives about 3.7 kΩ loss impedance at RF_OUT. Since the optimum load

impedance in TX mode for the power amplifier at RF_OUT is 890 Ω the loss associated with the

inductor L2 and the RF_OUT pin can be estimated to be 10 ×log(1 + 890/3700) = 0.95 dB com-

pared to the optimum matched loop antenna without L2 and RF_OUT. The switch represents, in

this mode at 433.92 MHz, approximately an inductor of 1.6 nH in series with the parallel connec-

tion of 2.5 pF and 2.0 kΩ. Since the impedance level at pin RX_TX1 in RX mode is about 50Ω

this only negligibly dampens the received signal (by about 0.1 dB). When matching the LNA to

the loop antenna, the transmission line and the 7.6 pF part of C9 have to be taken into account

when choosing the values of C11 and L1 so that the impedance seen from the loop antenna into

the transmission line with the 7.6 pF capacitor connected is 50Ω. Since the loop antenna in RX

mode is loaded by the LNA input impedance, the loaded Q of the loop antenna is lowered by

about a factor of 2 in RX mode; hence the antenna bandwidth is higher than in TX mode.

Note that if matching to 50Ω, like in Figure 2.2 on page 8, a high Q wire-wound inductor with a

Q > 70 should be used for L2 to minimize its contribution to RX losses that will otherwise be

dominant. The RX and TX losses will be in the range of 1.0 dB there.

Table 3-11. Impedance RF_OUT Pin in RX Mode

Frequency Z(RF_OUT)RX RP//CP

315 MHz 36Ω – j 502Ω7kΩ//1.0 pF

345 MHz 33Ω – j 480Ω7kΩ//1.0 pF

433.92 MHz 19Ω – j 366Ω7kΩ//1.0 pF

868.3 MHz 2.8Ω – j 141Ω7kΩ//1.3 pF

915 MHz 2.6Ω – j 135Ω7kΩ//1.3 pF

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4. XTO

The XTO is an amplitude-regulated Pierce oscillator type with integrated load capacitances

(2 ×18 pF with a tolerance of ±17%) hence CLmin = 7.4 pF and CLmax = 10.6 pF. The XTO oscil-

lation frequency fXTO is the reference frequency FREF for the fractional-N synthesizer. When

designing the system in terms of receiving and transmitting frequency offset, the accuracy of the

crystal and XTO have to be considered.

The synthesizer can adjust the local oscillator frequency for the initial frequency error in fXTO.

This is done at nominal supply voltage and temperature with the control registers 2 and 3 (see

Table 7-7 and Table 7-10). The remaining local oscillator tolerance at nominal supply voltage

and temperature is then < ±0.5 ppm. The XTO’s gm has very low influence of less than ±2 ppm

on the frequency at nominal supply voltage and temperature.

In a single channel system less than ±150 ppm should be corrected to avoid that harmonics of

the CLK output disturb the receive mode. If the CLK is not used or if it is carefully laid out on the

application PCB (as needed for multi channel systems), more than ±150 ppm can be

compensated.

Over temperature and supply voltage, the XTO's additional pulling is only ±2 ppm. The XTAL

versus temperature and its aging is then the main source of frequency error in the local

oscillator.

The XTO frequency depends on XTAL properties and the load capacitances CL1, 2 at pin XTAL1

and XTAL2. The pulling of fXTO from the nominal fXTAL is calculated using the following formula:

ppm.

Cm is the crystal's motional, C0 the shunt and CLN the nominal load capacitance of the XTAL

found in its data sheet. CL is the total actual load capacitance of the crystal in the circuit and con-

sists of CL1 and CL2 in series connection.

Figure 4-1. XTAL with Load Capacitance

With Cm≤14 fF, C0≥1.5 pF, CLN = 9 pF and CL= 7.4 pF to 10.6 pF, the pulling amounts to

P≤±100 ppm and with Cm≤7fF, C

0≥1.5 pF, CLN = 9 pF and CL= 7.4 pF to 10.6 pF, the pulling

is P ≤ ±50 ppm.

Since typical crystals have less than ±50 ppm tolerance at 25°C, the compensation is not criti-

cal, and can in both cases be done with the ±150 ppm.

PCm

--------CLN CL

–

C0CLN

+()C0CL

+()×

-------------------------------------------------------------

×106

×=

CL2

CL1

LmRm

CL = CL1 × CL2/ (CL1 + CL2)

XTAL

Crystal equivalent circuit

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

C0 of the XTAL has to be lower than CLmin/2 = 3.7 pF for a Pierce oscillator type in order to not

enter the steep region of pulling versus load capacitance where there is a risk of an unstable

oscillation.

To ensure proper start-up behavior the small signal gain, and thus the negative resistance, pro-

vided by this XTO at start is very large; for example, oscillation starts up even in worst case with

a crystal series resistance of 1.5 kΩ at C0≤2.2 pF with this XTO. The negative resistance is

approximately given by

with Z1, Z2 as complex impedances at pin XTAL1 and XTAL2, hence

Z1 =–j/(2×π×fXTO ×CL1) + 5Ω and Z2 = –j/(2 × π × fXTO × CL2) + 5Ω.

Z3 consists of crystals C0 in parallel with an internal 110 kΩ resistor hence

Z3=–j/(2×π×fXTO ×C0) /110 kΩ, gm is the internal transconductance between XTAL1 and

XTAL2 with typically 19 mS at 25°C.

With fXTO = 13.5 MHz, gm = 19 mS, CL= 9 pF, and C0= 2.2 pF, this results in a negative resis-

tance of about 2 kΩ. The worst case for technological, temperature and supply voltage variations

is then for C0≤2.2 pF always higher than 1.5 kΩ.

Due to the large gain at startup, the XTO is able to meet a very low start-up time. The oscillation

start-up time can be estimated with the time constant τ.

After 10 τ to 20 τ an amplitude detector detects the oscillation amplitude and sets XTO_OK to

High if the amplitude is large enough. This sets N_RESET to High and activates the CLK output

if CLK_ON in control register 3 is High (see Table 7-7). Note that the necessary conditions of the

VSOUT and DVCC voltage also have to be fulfilled (see Figure 4-2 and Figure 5-1).

To save current in IDLE and Sleep modes, the load capacitors are partially switched off in these

modes with S1 and S2, as seen in Figure 4-2.

It is recommended to use a crystal with Cm= 3.0 fF to 7.0 fF, CLN =9 pF, R

m<120Ω and

C0= 1.0 pF to 2.2 pF.

Lower values of Cm can be used, this increases the start-up time slightly. Lower values of C0 or

higher values of Cm (up to 15 fF) can also be used, this has only little influence on pulling.

Re ZXTOcore

{}Re Z1Z3Z2Z3Z1

+Z2

×Z3gm

×××+×

Z1Z2Z3Z1Z2

×gm

×+++

------------------------------------------------------------------------------------------------------

⎩⎭

⎨⎬

⎧⎫

τ2

4π2

×fm

×Cm

×Re ZXTOcore

()Rm

+()×

-----------------------------------------------------------------------------------------------------------=

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

Figure 4-2. XTO Block Diagram

To find the right values used in control registers 2 and 3 (see Table 7-7 and Table 7-10), the

relationship between fXTO and the fRF is shown in Table 4-1 on page 28. To determine the right

content, the frequency at pin CLK as well as the output frequency at RF_OUT in ASK mode can

be measured, then the FREQ value can be calculated according to Table 4-1 on page 28 so that

fRF is exactly the desired radio frequency.

8 pF 8 pF

XTAL1

Divider

/16

CLK_ON

(control

VSOUT_OK

(from power supply)

DVCC_OK

(from power supply)

Baud1

In IDLE mode and during Sleep mode (RX_Polling)

the switches S1 and S2 are open.

XLim

Baud0

Divider

XTO_OK

(to reset logic)

Divider

/16

10 pF10 pF

Amplitude

detector

S2S1

fXDCLK

XTAL2 CLK

CL2

CL1

fXTO

fDCLK

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The variable FREQ depends on FREQ2 and FREQ3, which are defined by the bits FR0 to FR12

in control register 2 and 3, and is calculated as follows:

FREQ = FREQ2 + FREQ3

Care must be taken to the harmonics of the CLK output signal fCLK as well as to the harmonics

produced by an microprocessor clocked with it, since these harmonics can disturb the reception

of signals if they get to the RF input. In a single channel system, using FREQ = 3803 to 4053

ensures that the harmonics of this signal do not disturb the receive mode. In a multichannel sys-

tem, the CLK signal can either be not used or carefully laid out on the application PCB. The

supply voltage of the microcontroller must also be carefully blocked in a multichannel system.

Table 4-1. Calculation of fRF

Frequency

(MHz)

Pin 6

433_N868

CREG1

Bit(4)

FS fXTO (MHz) fRF = fTX_ASK = fRX fTX_FSK_L fTX_FSK_H

Frequency

Resolution

315 AVCC 1 12.73193 fRF –15.54 kHz fRF +

15.54 kHz 777.1 Hz

345 AVCC 0 13.94447 fRF –17.02 kHz fRF +

17.02 kHz 851.1 Hz

433.92 AVCC 0 13.25311 fRF –16.17 kHz fRF +

16.17 kHz 808.9 Hz

868.3 GND 0 13.41191 fRF –16.37 kHz fRF +

16.37 kHz 818.6 Hz

915 GND 0 14.13324 fRF –17.25 kHz fRF +

17.25 kHz 862.6 Hz

fXTO 24.5 FREQ 20.5+

16384

----------------------------------+

⎝⎠

⎛⎞

fXTO 24.5 FREQ 20.5+

16384

----------------------------------+

⎝⎠

⎛⎞

fXTO 32.5 FREQ 20.5+

16384

----------------------------------+

⎝⎠

⎛⎞

fXTO 64.5 FREQ 20.5+

16384

----------------------------------+

⎝⎠

⎛⎞

fXTO 64.5 FREQ 20.5+

16384

----------------------------------+

⎝⎠

⎛⎞

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ATA5423/ATA5425/ATA5428/ATA5429

4.1 Pin CLK

Pin CLK is an output to clock a connected microcontroller. The clock frequency fCLK is calculated

as follows:

Because the enabling of pin CLK is asynchronous, the first clock cycle may be incomplete. The

signal at CLK output has a nominal 50% duty cycle.

Figure 4-3. Clock Timing

4.2 Basic Clock Cycle of the Digital Circuitry

The complete timing of the digital circuitry is derived from one clock. As shown in Figure 4-2

on page 27, this clock cycle TDCLK is derived from the crystal oscillator (XTO) in combination with

a divider.

TDCLK controls the following application relevant parameters:

• Timing of the polling circuit including bit check

• TX bit rate

The clock cycle of the bit check and the TX bit rate depends on the selected bit-rate range

(BR_Range) which is defined in control register 6 (see Table 7-20 on page 42) and XLim which

is defined in control register 4 (see Table 7-13 on page 40). This clock cycle TXDCLK is defined by

the following formulas for further reference:

BR_Range ⇒BR_Range 0: TXDCLK = 8 × TDCLK × XLim

BR_Range 1: TXDCLK = 4 × TDCLK × XLim

BR_Range 2: TXDCLK = 2 × TDCLK × XLim

BR_Range 3: TXDCLK = 1 × TDCLK × XLim

fCLK

fXTO

-----------=

CLK_ON

(Control register 3)

N_RESET

CLK

VSOUT

Thres_2

= 2.38V (typically)

Thres_1

= 2.3V (typically)

fDCLK

fXTO

-----------=

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ATA5423/ATA5425/ATA5428/ATA5429

5. Power Supply

Figure 5-1. Power Supply

The supply voltage range of the ATA5423/ATA5425/ATA5428/ATA5429 is 2.4V to 3.6V or 4.4V

to 6.6V.

Pin VS1 is the supply voltage input for the range 2.4V to 3.6V and is used in 1 Li battery applica-

tions (3V) using a single lithium 3V cell. Pin VS2 is the voltage input for the range 4.4V to 6.6V

(2 Li battery application (6V) and Base-station Application (5V); in this case, the voltage regula-

tor V_REG1 regulates VS1 to typically 3.25V. If the voltage regulator is active, a blocking

capacitor of 2.2 µF has to be connected to VS1.

Pin VAUX is an input for an additional auxiliary voltage supply and can be connected, for exam-

ple, to an inductive supply (see Figure 5-6 on page 36). This input can only be used together

with a rectifier or as in the application shown in Figure 2.2 on page 8 and must otherwise be left

open.

Pin VSINT is the voltage input for the Microcontoller_Interface and must be connected to the

power supply of the microcontroller. The voltage range of VVSINT is 2.4V to 5.25V (see Figure 5-5

on page 35 and Figure 5-6 on page 36).

V_REG2

3.25V typ.

V_Monitor

(2.3V/

2.38V typ.)

V_Monitor

(1.5V typ.)

V_REG1

3.25V typ.

SW_DVCC

Low_Batt

(Status Register

and Reset Logic)

VSOUT_OK

(to XTO and

Reset Logic)

DVCC_OK

(to XTO and

Reset Logic)

SW_VSOUT

VSOUT_EN

VAUX

SW_AVCC

OUT

VS1+

0.55V

typ.

FF1

PWR_ON

VSINT

AVCC_EN

DVCC_OK

OFFCMD

P_On_Aux

(Command via SPI)

(Status register)

no change

(Control register 3)

(Control register 1)

AVCC

VSOUT

DVCC

VS2

VS1

OUTIN

and

≥ 1

31
4841D–WIRE–10/07
ATA5423/ATA5425/ATA5428/ATA5429
AVCC is the internal operation voltage of the RF transceiver and is fed by VS1 via the switch
SW_AVCC. AVCC must be blocked with a 68 nF capacitor (see Figure 2-1 on page 7, Figure 2.2
on page 8 and Figure 2-3 on page 9).
DVCC is the internal operation voltage of the digital control logic and is fed by VS1 or VSOUT
via the switch SW_DVCC. DVCC must be blocked on pin DVCC with 68 nF (see Figure 2-1 on
page 7, Figure 2.2 on page 8 and Figure 2-3 on page 9).
Pin VSOUT is a power supply output voltage for external devices (for example, microcontrollers)
and is fed by VS1 via the switch SW_VSOUT, or by the auxiliary voltage supply VAUX via
V_REG2. The voltage regulator V_REG2 regulates VSOUT to typically 3.25V. If the voltage reg-
ulator is active, a blocking capacitor of 2.2 µF has to be connected to VSOUT. VSOUT can be
switched off by the VSOUT_EN bit in control register 3 and is then reactivated by conditions
found in Figure 5-2 on page 32.
Pin N_RESET is set to low if the voltage VVSOUT at pin VSOUT drops below 2.3V (typically) and
can be used as a reset signal for a connected microcontroller (see Figure 5-3 on page 34 and
Figure 5-4 on page 35).
Pin PWR_ON is an input to switch on the transceiver (active high).
Pin T1 to T5 are inputs for push buttons and can also be used to switch on the transceiver
(active low).
For current consumption reasons it is recommended to set T1 to T5 to GND, or PWR_ON to
VCC only temporarily. Otherwise, an additional current flows because of a 50 kΩ pull-up resistor.
There are two voltage monitors generating the following signals (see Figure 5-1 on page 30):
• DVCC_OK if DVCC > 1.5V typically
• VSOUT_OK if VSOUT > VThres1 (2.3V typically)
• Low_Batt if VSOUT < VThres2 (2.38V typically)

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Figure 5-2. Operation Modes Flow Chart

5.1 OFF Mode

If the power supply (battery) is connected to pin VS1 and/or VS2, and if the voltage on pin VAUX

VVAUX < 3.5V (typically), then the transceiver is in OFF mode. In OFF mode AVCC, DVCC and

VSOUT are disabled, resulting in very low power consumption (IS_OFF is typically 10 nA). In OFF

mode the transceiver is not programmable via the 4-wire serial interface.

AVCC = VS1

DVCC = VS1

VSOUT = OFF

IDLE Mode

AVCC = VS1

DVCC = VS1

VSOUT = VS1

or V_REG2

TX Mode

AVCC = VS1

DVCC = VS1

VSOUT = VS1

or V_REG2

AVCC = VS1

DVCC = VS1

VSOUT = VS1

or V_REG2

RX Polling Mode

AVCC = VS1

DVCC = VS1

VSOUT = OFF

RX Polling Mode

RX Mode

AVCC = VS1

DVCC = VS1

VSOUT = VS1 VVAUX > VS1 + 0.5V

VVAUX < VS1 + 0.5V

VVAUX > 3.5V (typ)

VVAUX < 3.5V (typ)

IDLE Mode

AVCC = VS1

DVCC = VS1

VSOUT = V_REG2

IDLE Mode

AVCC = OFF

DVCC = OFF

VSOUT = OFF

OFF Mode

AVCC = OFF

DVCC = V_REG2

VSOUT = V_REG2

AUX Mode

Pin PWR_ON = 1 or

Pin T1, T2, T3, T4 or

Pin T5

Pin PWR_ON = 1 or

Pin T1, T2, T3, T4 or

Pin T5 or

Bit AVCC_EN = 1

OPM1 = 0 and OPM0 = 1

OPM1 = 0 and OPM0 = 0

OPM1

OPM0

TX Mode

RX Polling Mode

RX Mode

OPM1 = 1 and OPM0 = 1

or Bit check ok

VSOUT_EN = 0

Bit check ok

OPM1 = 1 and OPM0 = 1

OPM1 = 1 and OPM0 = 0

OPM1 = 1 and OPM0 = 0OPM1 = 0 and OPM0 = 1

VSOUT_EN = 0

Status bit Power_On = 1

Event on Pin T1, T2, T3, T4 or T5

Statusbit Power_On = 1

Event on Pin T1, T2, T3, T4 or T5

Bit AVCC_EN = 0 and

OFF Command and

Pin PWR_ON = 0 and

Pin T1, T2, T3, T4 and

T5 = 1

Bit AVCC_EN = 0 and OFF Command and

Pin PWR_ON = 0 and

Pin T1, T2, T3, T4 and T5 = 1

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5.2 AUX Mode

The transceiver changes from OFF mode to AUX mode if the voltage at pin VAUX VVAUX >3.5V

(typically). In AUX mode DVCC and VSOUT are connected to the auxiliary power supply input

(VAUX) via the voltage regulator V_REG2. In AUX mode the transceiver is programmable via

the 4-wire serial interface, but no RX or TX operations are possible because AVCC = OFF.

The state transition OFF mode to AUX mode is indicated by an interrupt at pin IRQ and the sta-

tus bit P_On_Aux = 1.

5.3 IDLE Mode

In IDLE mode AVCC and DVCC are connected to the battery voltage (VS1).

From OFF mode the transceiver changes to IDLE mode if pin PWR_ON is set to 1 or pin T1, T2,

T3, T4 or T5 is set to “0”. This state transition is indicated by an interrupt at pin IRQ and the sta-

tus bits Power_On = 1 or ST1, ST2, ST3, ST4 or ST5 = 1.

From AUX mode the transceiver changes to IDLE mode by setting AVCC_EN = 1 in control

is set to “0”.

VSOUT is either connected to VS1 or to the auxiliary power supply (V_REG2).

If VVAUX < VS1 + 0.5V, VSOUT is connected to VS1. If VVAUX > VS1 + 0.5V, VSOUT is connected

to V_REG2 and the status bit P_On_Aux is set to “1”.

In IDLE mode, the RF transceiver is disabled and the power consumption IS_IDLE is about 230 µA

(VSOUT OFF and CLK output OFF and VS = VS1 = VS2 = 3V). The exact value of this current

is strongly dependent on the application and the exact operation mode, therefore check the sec-

tion “Electrical Characteristics: General” on page 67 for the appropriate application case.

Via the 4-wire serial interface a connected microcontroller can program the required parameter

and enable the TX, RX polling or RX mode.

The transceiver can be set back to OFF mode by an OFF command via the 4-wire serial inter-

face (the bit AVCC_EN must be set to “0”, the input level of pin PWR_ON must be “0” and pin

T1, T2, T3, T4 and T5 = 1 before writing the OFF command).

5.4 Reset Timing and Reset Logic

If the transceiver is switched on (OFF mode to IDLE mode, OFF mode to AUX mode) DVCC and

VSOUT ramp up as illustrated in Figure 5-3 on page 34 (AVCC only ramps up if the transceiver

is set to the IDLE mode). The internal signal DVCC_RESET resets the digital control logic and

sets the control register to default values.

A voltage monitor generates a low level at pin N_RESET until the voltage at pin VSOUT

exceeds 2.38V (typically) and the start-up time of the XTO has elapsed (amplitude detector, see

Figure 4-2 on page 27). After the voltage at pin VSOUT exceeds 2.3V (typically) and the start-up

time of the XTO has elapsed, the output clock at pin CLK is available. Because the enabling of

pin CLK is asynchronous, the first clock cycle may be incomplete.

Table 5-1. Control Register 1

OPM1 OPM0 Function

0 0 IDLE mode

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The status bit Low_Batt is set to “1” if the voltage at pin VSOUT VVSOUT drops below VThres_2

(typically 2.38V). Low_Batt is set to “0” if VVSOUT exceeds VThres_2 and the status register is read

via the 4-wire serial interface or N_RESET is set to low.

If VVSOUT drops below VThres_1 (typically 2.3V), N_RESET is set to low. If bit VSOUT_EN in con-

trol register 3 is “1”, a DVCC_RESET is also generated. If VVSOUT was already disabled by the

connected microcontroller by setting bit VSOUT_EN = 0, no DVCC_RESET is generated.

Note: If VSOUT < VThres_1 (typically 2.3 V) the output of the pin CLK is low, the Microcontroller_Interface

is disabled and the transceiver is not programmable via the 4-wire serial interface.

Figure 5-3. Reset Timing

N_RESET

VSOUT_EN

(Control Register 3)

LOW_Batt

(Status Register)

DVCC_RESET

VSOUT

DVCC

(AVCC)

VThres_1 = 2.3V (typ)

1.5V (typically)

VThres_2 = 2.38V (typ)

VSOUT > 2.3V and the XTO is running

VSOUT > 2.38V and the XTO is running

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ATA5423/ATA5425/ATA5428/ATA5429

Figure 5-4. Reset Logic, SR Latch Generates the Hysteresis in the NRESET Signal

5.5 1 Li Battery Application (3V)

The supply voltage range is 2.4V to 3.6V and VAUX is not used.

Figure 5-5. 1 Li Battery Application (3V)

≥ 1

and

XTO_OK

LOW_BATT

VSOUT_OK

DVCC_OK

VSOUT_EN

DVCC_RESET

N_RESE

and

no change

OUT

VSOUT

VSINT

NRESET

CLK

IRQ

SCK

SDI_TMDI

SDO_TMDO

DVCC

RF Transceiver

ATA5423/ATA5425/

ATA5428/ATA5429

ATmega

48/88/168

Microcontroller_Interface

Digital Control

Logic

AVCC

VAUX

VS2

2.4V to 3.6VVS1

DEM_OUT

4841D–WIRE–10/07

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5.6 2 Li Battery Application (6V)

The supply voltage range is 4.4V to 6.6V and VAUX is connected to an inductive supply.

Figure 5-6. 2 Li Battery Application (6V) with Inductive Emergency Supply

6. Microcontroller Interface

The microcontroller interface is a level converter which converts all internal digital signals that

are referred to the DVCC voltage into the voltage used by the microcontroller. Therefore, the pin

VSINT has to be connected to the supply voltage of the microcontroller.

This makes it possible to use the internal voltage regulator/switch at pin VSOUT as in Figure 2-1

on page 7 and Figure 2-3 on page 9 or to connect the microcontroller and the pin VSINT directly

to the supply voltage of the microcontroller as in Figure 2.2 on page 8.

7. Digital Control Logic

7.1 Register Structure

The configuration of the transceiver is stored in RAM cells. The RAM contains a 16 ×8-bit

TX/RX data buffer and a 6 ×8-bit control register and is writable and readable via a 4-wire serial

interface (CS, SCK, SDI_TMDI, SDO_TMDO).

The 1 ×8-bit status register is not part of the RAM and is readable via the 4-wire serial interface.

The RAM and the status information are stored as long as the transceiver is in any active mode

(DVCC = VS1 or DVCC = V_REG2) and are lost when the transceiver switches to OFF mode

(DVCC =OFF).

OUT

VSOUT

VSINT

NRESET

CLK

IRQ

SCK

SDI_TMDI

SDO_TMDO

DVCC

RF Transceiver

ATA5423/ATA5425/

ATA5428/ATA5429

ATmega

48/88/168

Microcontroller_Interface

Digital Control

Logic

AVCC

VAUX

VS2 4.4V to 6.6V

VS1

DEM_OUT

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After the transceiver is turned on via pin PWR_ON = High, T1 = Low, T2 = Low, T3 = Low,

T4 = Low or T5 = Low or the voltage at pin VAUX VVAUX > 3.5V (typically), the control registers

are in the default state.

Figure 7-1. Register Structure

7.2 TX/RX Data Buffer

The TX/RX data buffer is used to handle the data transfer during RX and TX operations.

IR1 -FSIR0 OPM1 OPM0 Control Register 1 (ADR 0)

Control Register 2 (ADR 1)

Control Register 3 (ADR 2)

Control Register 4 (ADR 3)

Control Register 5 (ADR 4)

Control Register 6 (ADR 5)

Status Register (ADR 8)

AVCC

_EN

MODE

TX/RX Data Buffer:

16 × 8 Bit

LSBMSB

FR3 FR2 FR0FR1FR6 FR5 FR4 P_

MODE

FR9 FR8

XLimXSleep

FR7FR12 FR11 FR10 VSOUT

_EN

CLK_

ST2 ST1ST5 ST4 ST3 Power_

Low_

Batt

P_On

_Aux

Sleep

ASK/

NFSK

Lim_

min5

Lim_

min3

Lim_

min0

Lim_

min1

Lim_

min2

Lim_

min4

BitChk

Lim_

max5

Lim_

max3

Lim_

max0

Lim_

max1

Lim_

max2

Lim_

max4

Baud

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7.3 Control Register

To use the transceiver in different applications, it can be configured by a connected microcon-

troller via the 4-wire serial interface.

7.3.1 Control Register 1 (ADR 0)

Table 7-1. Control Register 1 (Function of Bit 7 and Bit 6 in RX Mode)

IR1 IR0 Function (RX Mode)

Pin IRQ is set to “1” if 4 received bytes are in the TX/RX data buffer or a receiving error

occurred

Pin IRQ is set to “1” if 8 received bytes are in the TX/RX data buffer or a receiving error

occurred

Pin IRQ is set to “1” if 12 received bytes are in the TX/RX data buffer or a receiving error

occurred (default)

1 1 Pin IRQ is set to “1” if a receiving error occurred

Table 7-2. Control Register 1 (Function of Bit 7 and Bit 6 in TX Mode)

IR1 IR0 Function (TX Mode)

0 0 Pin IRQ is set to “1” if 4 bytes remain in the TX/RX data buffer or the TX data buffer is empty

0 1 Pin IRQ is set to “1” if 8 bytes remain in the TX/RX data buffer or the TX data buffer is empty

Pin IRQ is set to “1” if 12 bytes remain in the TX/RX data buffer or the TX data buffer is

empty (default)

1 1 Pin IRQ is set to “1” if the TX data buffer is empty

Table 7-3. Control Register 1 (Function of Bit 5)

AVCC_EN Function

0 (default)

1 Enables AVCC, if the ATA5423/ATA5425 is in AUX mode

Table 7-4. Control Register 1 (Function of Bit 4)

FS Function (RX Mode, TX Mode)

0 Selected frequency 345/433/868/915 MHz (default)

1 Selected frequency 315 MHz

Table 7-5. Control Register 1 (Function of Bit 2 and Bit 1)

OPM1 OPM0 Function

0 0 IDLE mode (default)

0 1 TX mode

1 0 RX polling mode

11RX mode

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ATA5423/ATA5425/ATA5428/ATA5429

7.3.2 Control Register 2 (ADR 1)

Table 7-6. Control Register 1 (Function of Bit 0)

T_MODE Function

0 TX and RX function via TX/RX data buffer (default)

1Transparent mode, TX/RX data buffer disabled, TX modulation data stream via pin

SDI_TMDI, RX modulation data stream via pin SDO_TMDO

Table 7-7. Control Register 2 (Function of Bit 7, Bit 6, Bit 5, Bit 4, Bit 3, Bit 2 and Bit 1)

FR6

26FR5

25FR4

24FR3

23FR2

22FR1

21FR0

20Function

0000000FREQ2 = 0

0000001FREQ2 = 1

.......

1011000FREQ2 = 88 (default)

.......

1111111FREQ2 = 127

Note: Tuning of fRF LSBs (total 13 bits), frequency trimming resolution of fRF is fXTO/16384, which is

approximately 800 Hz (see section “XTO”, Table 4-1 on page 28)

Table 7-8. Control Register 2 (Function of Bit 0 in RX Mode)

P_MODE Function (RX Mode)

0 Pin IRQ is set to “1” if the bit check is successful (default)

1 No effect on pin IRQ if the bit check is successful

Table 7-9. Control Register 2 (Function of Bit 0 in TX Mode)

P_MODE Function (TX Mode)

0 Manchester modulator on (default)

1 Manchester modulator off (NRZ mode)

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7.3.3 Control Register 3 (ADR 2)

7.3.4 Control Register 4 (ADR 3)

Table 7-10. Control Register 3 (Function of Bit 7, Bit 6, Bit 5, Bit 4, Bit 3 and Bit 2)

FR12

212 FR11

211 FR10

210 FR9

29FR8

28FR7

27Function

000000FREQ3 = 0

000001FREQ3 = 128

000010FREQ3 = 256

.......

0 1 1 1 1 0 FREQ3 = 3840 (default)

.......

111110FREQ3 = 7936

111111FREQ3 = 8064

Note: Tuning of fRF MSBs

Table 7-11. Control Register 3 (Function of Bit 1)

VSOUT_EN Function

0 Output voltage power supply for external devices off (pin VSOUT)

1 Output voltage power supply for external devices on (default)

Note: This bit is set to “1” if the bit check is OK (RX_Polling, RX mode), an event at pin T1, T2, T3, T4 or

T5 occurs or the bit Power_On in the status register is “1”.

Setting VSOUT_EN = 0 in AUX mode is not allowed

Table 7-12. Control Register 3 (Function of Bit 0)

CLK_ON Function

0 Clock output off (pin CLK)

1 Clock output on (default)

Note: This bit is set to “1” if the bit check is OK (RX_Polling, RX mode), an event at pin T1, T2, T3, T4 or

T5 occurs or the bit Power_On in the status register is “1”.

Table 7-13. Control Register 4 (Function of Bit 7)

ASK_NFSK Function (TX Mode, RX Mode)

0 FSK mode (default)

1 ASK mode

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7.3.5 Control Register 5 (ADR 4)

Table 7-14. Control Register 4 (Function of Bit 6, Bit 5, Bit 4, Bit 3 and Bit 2)

Sleep4

24Sleep3

23Sleep2

22Sleep1

21Sleep0

Function (RX Mode)

Sleep

(TSleep = Sleep × 1024 × TDCLK × XSleep)

00000 0

00001 1

.....

01010

(TSleep = 10 × 1024 × TDCLK × XSleep)

(default)

.....

11111 31

Table 7-15. Control Register 4 (Function of Bit 1)

XSleep Function

Sleep = 1; extended TSleep off (default)

Sleep = 8; extended TSleep on

Table 7-16. Control Register 4 (Function of Bit 0)

XLim Function

Lim = 1; extended TLim_min, TLim_max off (default)

Lim = 2; extended TLim_min, TLim_max on

Table 7-17. Control Register 5 (Function of Bit 7 and Bit 6)

BitChk1 BitChk0 Function

00N

Bit-check = 0 (0 bits checked during bit check)

01N

Bit-check = 3 (3 bits checked during bit check) (default)

10N

Bit-check = 6 (6 bits checked during bit check)

11N

Bit-check = 9 (9 bits checked during bit check)

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7.3.6 Control Register 6 (ADR 5)

Table 7-18. Control Register 5 (Function of Bit 5, Bit 4, Bit 3, Bit 2, Bit 1 and Bit 0 in RX Mode)

Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0

Function (RX Mode)

Lim_min

(Lim_min < 10 are not applicable)

(TLim_min = Lim_min × TXDCLK)

001010 10

001011 11

......

010000

(TLim_min = 16 × TXDCLK)

(default)

......

111111 63

Table 7-19. Control Register 5 (Function of Bit 5, Bit 4, Bit 3, Bit 2, Bit 1 and Bit 0 in TX Mode)

Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0

Function (TX Mode) Lim_min

(Lim_min < 10 are not applicable)

(TX_Bitrate = 1/((Lim_min + 1) × TXDCLK × 2)

001010 10

001011 11

......

010000

(TX_Bitrate = 1/((16 + 1) × TXDCLK × 2)

(default)

......

111111 63

Table 7-20. Control Register 6 (Function of Bit 7 and Bit 6)

Baud1 Baud0 Function

Bit-rate range 0 (B0) 1.0 Kbit/s to 2.5 Kbit/s;

TXDCLK = 8 × TDCLK × XLim

Bit-rate range 1 (B1) 2.0 Kbit/s to 5.0 Kbit/s;

TXDCLK = 4 × TDCLK × XLim

Bit-rate range 2 (B2) 4.0 Kbit/s to 10.0 Kbit/s;

TXDCLK = 2 × TDCLK × XLim; (default)

Bit-rate range 3 (B3) 8.0 Kbit/s to 20.0 Kbit/s;

TXDCLK = 1 × TDCLK × XLim

Note that the receiver does not work with >10 Kbit/s in ASK mode

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7.4 Status Register

The status register indicates the current status of the transceiver and is readable via the 4-wire

serial interface. Setting Power_On or P_On_Aux or an event on ST1, ST2, ST3, ST4 or ST5 is

indicated by an IRQ.

Reading the status register resets the bits Power_On, Low_Batt, P_On_Aux and the IRQ.

7.4.1 Status Register (ADR 8)

Table 7-21. Control Register 6 (Function of Bit 5, Bit 4, Bit 3, Bit 2, Bit 1 and Bit 0)

Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0

Function Lim_max

(Lim_max < 12 is not Applicable)

(TLim_max = (Lim_max – 1) × TXDCLK)

001100 12

001101 13

......

011100

(TLim_max = (28 – 1) × TXDCLK)

(default)

......

111111 63

Table 7-22. Status Register

Status Bit Function

ST5

Status of pin T5

Pin T5 = 0 →ST5 = 1

Pin T5 = 1 →ST5 = 0

(see Figure 7-3 on page 45)

ST4

Status of pin T4

Pin T4 = 0 →ST4 = 1

Pin T4 = 1 →ST4 = 0

(see Figure 7-3 on page 45)

ST3

Status of pin T3

Pin T3 = 0 →ST3 = 1

Pin T3 = 1 →ST3 = 0

(see Figure 7-3 on page 45)

ST2

Status of pin T2

Pin T2 = 0 →ST2 = 1

Pin T2 = 1 →ST2 = 0

(see Figure 7-3 on page 45)

ST1

Status of pin T1

Pin T1 = 0 →ST1 = 1

Pin T1 = 1 →ST1 = 0

(see Figure 7-3 on page 45)

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7.5 Pin Tn

To switch the transceiver from OFF to IDLE mode, pin Tn must be set to “0” (maximum

0.2 ×VVS2) for at least TTn_IRQ (see Figure 7-2). The transceiver recognizes the negative edge,

sets pin N_RESET to low and switches on DVCC, AVCC and the power supply for external

devices VSOUT.

If VDVCC exceeds 1.5V (typically) and the XTO is settled, the digital control logic is active and

sets the status bit STn to “1” and an interrupt is issued (TTn_IRQ).

After the voltage on pin VSOUT exceeds 2.3V (typically) and the start-up time of the XTO is

elapsed, the output clock on pin CLK is available. Because the enabling of pin CLK is asynchro-

nous, the first clock cycle may be incomplete. N_RESET is set to high if VVSOUT exceeds 2.38V

(typically) and the XTO is settled.

Figure 7-2. Timing Pin Tn, Status Bit STn

Power_On

Indicates that the transceiver was woken up by pin PWR_ON (rising edge on pin

PWR_ON). During Power_On = 1, the bits VSOUT_EN and CLK_ON in control register 3

are set to “1”.

(see Figure 7-4 on page 46)

Low_Batt

Indicates that output voltage on pin VSOUT is too low

(VVSOUT < 2.38V typically)

(see Figure 7-5 on page 47)

P_On_Aux

Indicates that the auxiliary supply voltage on pin VAUX is high enough to operate.

State transition:

a) OFF mode →AUX mode (see Figure 5-2 on page 32)

b) IDLE mode (VSOUT = VS1) →IDLE mode (VSOUT = V_REG2)

(see Figure 7-6 on page 48)

Table 7-22. Status Register (Continued)

Status Bit Function

STn

(Status register)

IRQ

CLK

N_RESET

DVCC, AVCC

VSOUT

IDLE

Mode

OFF

Mode

VThres_2 = 2.38V (typ)

VThres_1 = 2.3V (typ)

TTn_IRQ

1.5V (typ)

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If the transceiver is in any active mode (IDLE, AUX, TX, RX, RX_Polling), an integrated

debounce logic is active. If there is an event on pin Tn a debounce counter is set to 0 (T = 0) and

started. The status is updated, an interrupt is issued and the debounce counter is stopped after

reaching the counter value T = 8195 × TDCLK.

An event on the same key input before reaching T = 8195 × TDCLK stops the debounce counter.

An event on an other key input before reaching T = 8195 × TDCLK resets and restarts the

debounce counter.

While the debounce counter is running, the bits VSOUT_EN and CLK_ON in control register 3

are set to “1”.

The interrupt is deleted after reading the status register or executing the command Delete_IRQ.

If pin Tn is not used, it can be left open because of an internal pull-up resistor (typically 50 kΩ).

Figure 7-3. Timing Flow Pin Tn, Status Bit STn

IDLE Mode or

AUX Mode or

TX Mode or

RX Polling Mode or

RX Mode

Stop debounce counter

STn = 1

IRQ = 1

Stop debounce counter

STn = 0

IRQ = 1

Stop debounce counter

Tn = STn ? Pin Tn = 0 ?

T = 0

Start debounce counter

Event on Pin Tn ?

T = 8195 × T ?

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7.6 Pin PWR_ON

To switch the transceiver from OFF to IDLE mode, pin PWR_ON must be set to “1” (minimum

0.8 ×VVS2) for at least TPWR_ON (see Figure 7-4). The transceiver recognizes the positive edge,

sets pin N_RESET to low, and switches on DVCC, AVCC and the power supply for external

devices VSOUT.

If VDVCC exceeds 1.5V (typically) and the XTO is settled, the digital control logic is active and

sets the status bit Power_On to “1” and an interrupt is issued (TPWR_ON_IRQ_1).

After the voltage on pin VSOUT exceeds 2.3V (typically) and the start-up time of the XTO is

elapsed the output clock on pin CLK is available. Because the enabling of pin CLK is asynchro-

nous, the first clock cycle may be incomplete. N_RESET is set to high if VVSOUT exceeds 2.38V

(typically) and the XTO is settled.

If the transceiver is in any active mode (IDLE, AUX, RX, RX_Polling, TX), a positive edge on pin

PWR_ON sets Power_On to “1” (after TPWR_ON_IRQ_2). The state transition Power_On 0 → 1 gen-

erates an interrupt. If Power_On is still “1” during the positive edge on pin PWR_ON no interrupt

is issued. Power_On and the interrupt are deleted after reading the status register.

During Power_On = 1, the bits VSOUT_EN and CLK_ON in control register 3 are set to “1”.

Note: It is not possible to set the transceiver to OFF mode by setting pin PWR_ON to “0”. If pin

PWR_ON is not used, it must be connected to GND.

Figure 7-4. Timing Pin PWR_ON, Status Bit Power_On

Power_ON

(Status register)

IRQ

CLK

N_RESET

DVCC, AVCC

VSOUT

PWR_ON

OFF

Mode

IDLE

Mode

IDLE, AUX, RX, RX Polling, TX

Mode

TPWR_ON > TPWR_ON_IRQ_2

TPWR_ON > TPWR_ON_IRQ_1

TPWR_ON_IRQ_2

TPWR_ON_IRQ_1

1.5V (typ)

VThres_2 = 2.38V (typ)

VThres_1 = 2.V

(typ)

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7.7 Low Battery Indicator

The status bit Low_Batt is set to “1” if the voltage VVSOUT on pin VSOUT drops below 2.38V

(typically).

Low_Batt is set to “0” if VVSOUT exceeds VThres_2 and the status register is read via the 4-wire

serial interface (see Figure 5-3 on page 34).

Figure 7-5. Timing Status Bit Low_Batt

7.8 Pin VAUX

To switch the transceiver from OFF to AUX mode, the voltage VVAUX on pin VAUX must exceed

3.5V (typically) (see Figure 7-6 on page 48). If VVAUX exceeds 2V (typically) pin N_RESET is set

to low, and DVCC and the power supply for external devices VSOUT are switched on.

If VVAUX exceeds 3.5V (typically) the status bit P_On_Aux is set to “1” and an interrupt is issued.

After the voltage on pin VSOUT exceeds 2.3V (typically) and the start-up time of the XTO is

elapsed, the output clock on pin CLK is available. Because the enabling of pin CLK is asynchro-

nous, the first clock cycle may be incomplete. N_RESET is set to high if VVSOUT exceeds 2.38V

(typically) and the XTO is settled.

If the transceiver is in any active mode (IDLE, TX, RX, RX_Polling), a positive edge on pin VAUX

and VVAUX > VS1 + 0.5V sets P_On_Aux to “1”. The state transition P_On_Aux 0 → 1 generates

an interrupt. If P_On_Aux is still “1” during the positive edge on pin VAUX no interrupt is issued.

P_On_Aux and the interrupt are deleted after reading the status register.

IDLE, AUX, TX, RX

RX Polling Mode

Read Status Register

VVSOUT < 2.38V (typ)

Low_Batt = 1

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Figure 7-6. Timing Pin VAUX, Status Bit P_On_Aux

P_ON_AUX

(Status register)

IRQ

CLK

N_RESET

DVCC

VSOUT

VAUX

OFF

Mode

AUX

Mode

IDLE, TX, RX, RX polling

Mode

2.0V (typ)

3.5V (typ)

VThres_2 = 2.38V (typ)

VThres_1 = 2.3V (typ)

VVAUX > VS1 + 0.5V (typ) VVAUX > VS1 + 0.5V (typ)

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8. Transceiver Configuration

The configuration of the transceiver takes place via a 4-wire serial interface (CS, SCK,

SDI_TMDI, SDO_TMDO) and is organized in 8-bit units. The configuration is initiated with an

8-bit command. While shifting the command into pin SDI_TMDI, the number of bytes in the

TX/RX data buffer are available on pin SDO_TMDO. The read and write commands are followed

by one or more 8-bit data units. Each 8-bit data transmission begins with the MSB. The serial

interface is in the reset state if the level on pin CS = Low.

8.1 Command: Read TX/RX Data Buffer

During a RX operation, the user can read the received bytes in the TX/RX data buffer

successively.

Figure 8-1. Read TX/RX Data Buffer

8.2 Command: Write TX/RX Data Buffer

During a TX operation the user can write the bytes in the TX/RX data buffer successively. An

echo of the command and the TX data bytes are provided for the microcontroller on pin

SDO_TMDO.

Figure 8-2. Write TX/RX Data Buffer

8.3 Command: Read Control/Status Register

The control and status registers can be read individually or successively.

Figure 8-3. Read Control/Status Register

SCK

SDO_TMDO

SDI_TMDI

RX Data Byte 1RX Data Byte 1No. Bytes in the TX/RX Data Buffer

Command: Read TX/RX Data Buffer X

MSB MSBLSB LSB LSBMSB

SCK

SDO_TMDO

SDI_TMDI

TX Data Byte 1Write TX/RX Data BufferNo. Bytes in the TX/RX Data Buffer

Command: Write TX/RX Data Buffer TX Data Byte 1

MSB MSBLSB LSB LSBMSB

TX Data Byte 2

SCK

SDO_TMDO

SDI_TMDI

Data C/S Register X Data C/S Register YNo. Bytes in the TX/RX Data Buffer

Command: Read C/S Register X

MSB MSBLSB LSB LSBMSB

Command: Read C/S Register ZCommand: Read C/S Register Y

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8.4 Command: Write Control Register

The control registers can be written individually or successively. An echo of the command and

the data bytes are provided for the microcontroller on pin SDO_TMDO.

Figure 8-4. Write Control Register

8.5 Command: OFF Command

If AVCC_EN in control register 1 is “0”, the input level on pin PWR_ON is low and on the key

inputs Tn is high, then the OFF command sets the transceiver in the OFF mode.

Figure 8-5. OFF Command

8.6 Command: Delete IRQ

The delete IRQ command sets pin IRQ to low.

Figure 8-6. Delete IRQ

8.7 Command Structure

The three most significant bits of the command (bit 5 to bit 7) indicate the command type. Bit 0 to

bit 4 describe the target address when reading or writing a control or status register. In all other

commands bit 0 to bit 4 have no effect and should be set to “0” for compatibility with future

products.

SCK

SDO_TMDO

SDI_TMDI

Write Control Register X Data Control Register XNo. Bytes in the TX/RX Data Buffer

Command: Write Control Register X

MSB MSBLSB LSB LSBMSB

Command: Write Control Register YData Control Register X

SCK

SDO_TMDO

SDI_TMDI

No. Bytes in the TX/RX Data Buffer

Command: OFF Command

LSBMSB

SCK

SDO_TMDO

SDI_TMDI

No. Bytes in the TX/RX Data Buffer

Command: Delete IRQ

LSBMSB

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8.8 4-wire Serial Interface

The 4-wire serial interface consists of the Chip Select (CS), the Serial Clock (SCK), the Serial

Data Input (SDI_TMDI) and the Serial Data Output (SDO_TMDO). Data is transmitted/received

bit by bit in synchronization with the serial clock.

Note: If the output level on pin N_RESET is low, no data communication with the microcontroller is

possible.

When CS is low and the transparent mode is inactive (T_MODE = 0), SDO_TMDO is in a high

impedance state. When CS is low and the transparent mode is active (T_MODE = 1), the RX

data stream is available on pin SDO_TMDO.

Figure 8-7. Serial Timing

Table 8-1. Command Structure

Command

MSB LSB

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Read TX/RX data buffer 0 0 0 x x x x x

Write TX/RX data buffer 0 0 1 x x x x x

Read control/status register 0 1 0 A4 A3 A2 A1 A0

Write control register 0 1 1 A4 A3 A2 A1 A0

OFF command 100XXXXX

Delete IRQ 1 0 1 X X X X X

Not used 110XXXXX

Not used 111XXXXX

MSB MSB-1

LSBMSB MSB-1

X XXX

SCK

SDO_TMDO

SDI_TMDI

TCS_disable

TSCK_setup2

TSCK_hold

TSCK_setup1

TCycle

X can be either ViL or ViH

TCS_setup

TOut_enable TOut_delay

TSetup

THold

TOut_disable

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9. Operation Modes

9.1 RX Operation

The transceiver is set to RX operation with the bits OPM0 and OPM1 in control register 1.

The transceiver is designed to consume less than 1 mA in RX operation while remaining sensi-

tive to signals from a corresponding transmitter. This is achieved via the polling circuit. This

circuit enables the signal path periodically for a short time. During this time the bit-check logic

verifies the presence of a valid transmitter signal. Only if a valid signal is detected does the

transceiver remain active and transfer the data to the connected microcontroller. This transfer

takes place either via the TX/RX data buffer or via the pin SDO_TMDO. When there is no valid

signal present, the transceiver is in sleep mode most of the time, resulting in low current con-

sumption. This condition is called RX polling mode. A connected microcontroller can be disabled

during this time.

All relevant parameters of the polling logic can be configured by the connected microcontroller.

This flexibility enables the user to meet the specifications in terms of current consumption, sys-

tem response time, data rate, etc.

In RX mode the RF transceiver is enabled permanently and the bit-check logic verifies the pres-

ence of a valid transmitter signal. When a valid signal is detected the transceiver transfers the

data to the connected microcontroller. This transfer take place either via the TX/RX data buffer

or via the pin SDO_TMDO.

9.1.1 RX Polling Mode

When the transceiver is in RX polling mode it stays in a continuous cycle of three different

modes. In sleep mode the RF transceiver is disabled for the time period TSleep while consuming

low current of IS = IIDLE_X. During the start-up period, TStartup_PLL and TStartup_Sig_Proc, all signal pro-

cessing circuits are enabled and settled. In the following bit-check mode, the incoming data

stream is analyzed bit by bit to see if it is a valid transmitter signal. If no valid signal is present,

the transceiver is set back to sleep mode after the period TBit-check. This period varies check by

check as it is a statistical process. An average value for TBit-check is given in the electrical charac-

teristics. During TStartup_PLL the current consumption is IS = IStartup_PLL_X. During TStartup_Sig_Proc

and TBit-check the current consumption is IS = IRX_X. The condition of the transceiver is indicated

on pin RX_ACTIVE (see Figure 9-1 on page 54 and Figure 9-2 on page 55). The average cur-

rent consumption in RX polling mode IP is different in 1 Li battery application (3V), 2 Li battery

application (6V) or Base-station Application (5V). To calculate IP the index X must be replaced

by VS1,VS2 in 1 Li battery application (3V), VS2 in 2 Li battery application (6V) or VS2,VAUX in

Base-station Application (5V) (see section “Electrical Characteristics: General” on page 67).

Table 9-1. Control Register 1

OPM1 OPM0 Function

1 0 RX polling mode

11 RX mode

IIDLE_X TSleep IStartup_PLL_X T×Startup_PLL IRX_X TStartup_Sig_Proc TBitcheck

+()×++×

TSleep TStartup_PLL TStartup_Sig_Proc TBit_check

++ +

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

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To save current it is recommended that CLK and VVSOUT be disabled during RX polling mode. IP

does not include the current of the Microcontroller_Interface, IVSINT, or the current of an external

device connected to pin VSOUT (for example, microcontroller). If CLK and/or VSOUT is enabled

during RX polling mode the current consumption is calculated as follows:

During TSleep, TStartup_PLL and TStartup_Sig_Proc, the transceiver is not sensitive to a transmitter sig-

nal. To guarantee the reception of a transmitted command, the transmitter must start the

telegram with an adequate preburst. The required length of the preburst, TPreburst, depends on

the polling parameters TSleep, TStartup_PLL, TStartup_Sig_Proc and TBit-check. Thus, TBit-check depends on

the actual bit rate and the number of bits (NBit-check) to be tested.

9.1.2 Sleep Mode

The length of period TSleep is defined by the 5-bit word sleep in control register 4, the extension

factor XSleep defined by the bit XSleep in control register 4, and the basic clock cycle TDCLK. It is

calculated to be:

In US and European applications, the maximum value of TSleep is about 38 ms if XSleep is set to 1

(which is done by setting the bit XSleep in control register 4 to “0”). The time resolution is about

1.2 ms in that case. The sleep time can be extended to about 300 ms by setting XSleep to 8

(which is done by setting XSleep in control register 4 to “1”), the time resolution is then about

9.6 ms.

9.1.3 Start-up Mode

During TStartup_PLL the PLL is enabled and starts up. If the PLL is locked, the signal processing

circuit starts up (TStartup_Sig_Proc). After the start-up time all circuits are in stable condition and

ready to receive.

IS_Poll IPIVSINT IEXT

++=

TPreburst TSleep TStartup_PLL TStartup_Sig_Proc TBit_check

++ +≥

TSleep Sleep 1024 TDCLK XSleep

×××=

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Figure 9-1. Flow Chart Polling Mode/RX Mode (T_MODE = 0, Transparent Mode Inactive)

Start RX Mode

Start RX Polling Mode

Start-up PLL:

The PLL is enabled and locked.

Output level on pin RX_ACTIVE ⇒ High; IS = IStartup_PLL_X; IStartup_PLL

Start-up signal processing:

The signal processing circuit are enabled.

Output level on pin RX_ACTIVE ⇒ High; IS = IRX_X; TStartup_Sig_proc

The incomming data stream is analyzed. If the timing indicates a valid transmitter signal,

the control bits VSOUT_EN, CLK_ON and OPM0 are set to 1 and the transceiver is set to

receiving mode. Otherwise it is set to Sleep mode or to Start_up mode.

Output level on pin RX_ACTIVE ⇒ High

Bit-check mode:

Sleep: Defined by bits Sleep 0 to Sleep 4 in Control

798.5 × TDCLK (typ)TStartup_PLL:

(BR_Range 0)

Is defined by the selected baud rate range and

TDCLK .The baud-rate range is defined by bit

Baud 0 and Baud 1 in Control Register 6.

If the bit check is ok, TBit-check depends on the

number of bits to be checked (NBit-check) and

on the utilized data rate.

882 × TDCLK (BR_Range 1)498 × TDCLK (BR_Range 2)306 × TDCLK (BR_Range 3)210 × TDCLK

TStartup_Sig_Proc:

Defined by bit XSleep in Control register 4

Basic clock cycle

TDCLK:

XSleep:

Depends on the result of the bit check.TBit-check:

All circuits for analog signal processing are disabled. Only XTO and Polling logic is enabled.

Output level on pin RX_ACTIVE ⇒ Low; IS = IIDLE_X

TSleep = Sleep × 1024 × TDCLK × XSleep

Sleep mode:

Start-up mode:

P_MODE = 0

Bit check

OK ?

Set IRQ

YES

Set VSOUT_EN = 1

Set CLK_ON = 1

Set OPM0 = 1

TSLEEP = 0

OPM0 = 1

IS = IRX_X; TBit-check

The incomming data stream is passed via the TX/RX Data Buffer to the connected

microcontroller. If an bit error occurs the transceiver is set back to Start-up mode.

Output level on pin RX_ACTIVE ⇒ High

Receiving mode:

Bit error ?

Start bit

detected ?

YES

RX data stream is

written into the TX/RX

Data Buffer

IS = IRX_X

If the bit check fails, the average time period for

that check despends on the selected bit-rate

range and on TXDCLK. The bit-rate range is

defined by bit Baud 0 and Baud 1 in Control

If the transceiver detects a bit errror after a

successful bit check and before the start bit is

detected pin IRQ will be set to high (only if

P_MODE = 0) and the transceiver is set back to

start-up mode.

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Figure 9-2. Flow Chart Polling Mode/RX Mode (T_MODE = 1, Transparent Mode Active)

Start RX Mode

Start RX Polling Mode

Start-up PLL:

The PLL is enabled and locked.

Output level on pin RX_ACTIVE ⇒ High; IS = IStartup_PLL_X; IStartup_PLL

Start-up signal processing:

The signal processing circuit are enabled.

Output level on pin RX_ACTIVE ⇒ High; IS = IRX_X; TStartup_Sig_proc

The incomming data stream is analyzed. If the timing indicates a valid transmitter signal,

the control bits VSOUT_EN, CLK_ON and OPM0 are set to 1 and the transceiver is set to

receiving mode. Otherwise the transceiver is set to Sleep mode

(if OPM0 = 0 and TSleep > 0) or stays in Bit-check mode.

Output level on pin RX_ACTIVE ⇒ High

Bit-check mode:

Sleep: Defined by bits Sleep 0 to Sleep 4 in Control

798.5 × TDCLK (typ)TStartup_PLL:

(BR_Range 0)

Is defined by the selected baud rate range and

TDCLK .The baud-rate range is defined by bit

Baud 0 and Baud 1 in Control Register 6.

If the bit check is ok, TBit-check depends on the

number of bits to be checked (NBit-check) and

on the utilized data rate.

882 × TDCLK (BR_Range 1)498 × TDCLK (BR_Range 2)306 × TDCLK (BR_Range 3)210 × TDCLK

TStartup_Sig_Proc:

Defined by bit XSleep in Control register 4

Basic clock cycle

TDCLK:

XSleep:

Depends on the result of the bit check.TBit-check:

All circuits for analog signal processing are disabled. Only XTO and Polling logic is enabled.

Output level on pin RX_ACTIVE ⇒ Low; IS = IIDLE_X

TSleep = Sleep × 1024 × TDCLK × XSleep

Sleep mode:

Start-up mode:

Bit check

OK ?

NO YES

YES

Set VSOUT_EN = 1

Set CLK_ON = 1

Set OPM0 = 1

TSLEEP = 0

OPM0 = 1

IS = IRX_X; TBit-check

The incomming data stream is passed via PIN SDO_TMDO to the connected

microcontroller. If an bit error occurs the transceiver is not set back to Start-up mode.

Output level on pin RX_ACTIVE ⇒ High

Receiving mode:

Level on pin

CS = Low ?

YES

RX data stream

available on pin

SDO_TMDO

IS = IRX_X

If the bit check fails, the average time period for

that check despends on the selected bit-rate

range and on TXDCLK. The bit-rate range is

defined by bit Baud 0 and Baud 1 in Control

If in FSK mode the datastream is interrupted the

FSK-Demodulator-PLL tends to lock out and is

further not able to lock in, even there is a valid

data stream available.

In this case the transceiver must be set back to

IDLE mode.

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9.1.4 Bit-check Mode

In bit-check mode the incoming data stream is examined to distinguish between a valid signal

from a corresponding transmitter and signals due to noise. This is done by subsequent time

frame checks where the distance between 2 signal edges are continuously compared to a pro-

grammable time window. The maximum count of this edge-to-edge test before the transceiver

switches to receiving mode is also programmable.

9.1.5 Configuration of the Bit Check

Assuming a modulation scheme that contains 2 edges per bit, two time frame checks verify one

bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The maximum

count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable NBit-check in control

higher value, the transceiver is less likely to switch to receiving mode due to noise. In the pres-

ence of a valid transmitter signal, the bit check takes less time if NBit-check is set to a lower value.

In RX polling mode, the bit-check time is not dependent on NBit-check if no valid signal is present.

Figure 9-3 shows an example where 3 bits are tested successfully.

Figure 9-3. Timing Diagram for Complete Successful Bit Check (Number of Checked Bits: 3)

As seen in Figure 9-4, the time window for the bit check is defined by two separate time limits. If

the edge-to-edge time tee is in between the lower bit-check limit TLim_min and the upper bit-check

limit TLim_max, the check will be continued. If tee is smaller than limit TLim_min or exceeds TLim_max,

the bit check will be terminated and the transceiver switches to sleep mode.

Figure 9-4. Valid Time Window for Bit Check

Bit check mode

Bit check ok

Start-up mode Receiving mode

1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit1/2 Bit 1/2 Bit

RX_ACTIVE

Demod_Out

Bit check

TStartup_Sig_Proc TBit-check

Demod_Out

1/fSig

tee

TLim_min

TLim_max

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For the best noise immunity, use of a low span between TLim_min and TLim_max is recommended.

This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst: a

“11111...” or a “10101...” sequence in Manchester or Bi-phase is a good choice. A good compro-

mise between sensitivity and susceptibility to noise regarding the expected edge-to-edge time,

tee, is a time window of ±38%; to get the maximum sensitivity the time window should be ±50%

and then NBit-check ≥ 6. Using preburst patterns that contain various edge-to-edge time periods,

the bit-check limits must be programmed according to the required span.

The bit-check limits are determined by means of the formula below:

TLim_min = Lim_min ×TXDCLK

TLim_max = (Lim_max -1) ×TXDCLK

Lim_min is defined by the bits Lim_min 0 to Lim_min 5 in control register 5.

Lim_max is defined by the bits Lim_max 0 to Lim_max 5 in control register 6.

Using the above formulas, Lim_min and Lim_max can be determined according to the required

TLim_min, TLim_max and TXDCLK. The time resolution defining TLim_min and TLim_max is TXDCLK. The

minimum edge-to-edge time tee is defined in the section “Receiving Mode” on page 59. The

lower limit should be set to Lim_min ≥ 10. The maximum value of the upper limit is

Lim_max = 63.

Figure 9-5, Figure 9-6, and Figure 9-7 illustrate the bit check for the bit-check limits

Lim_min = 14 and Lim_max = 24. The signal processing circuits are enabled during TStartup_PLL

and TStartup_Sig_Proc. The output of the ASK/FSK demodulator (Demod_Out) is undefined during

that period. When the bit check becomes active, the bit-check counter is clocked with the cycle

TXDCLK.

Figure 9-5 shows how the bit check proceeds if the bit-check counter value CV_Lim is within the

limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In Figure 9-6 on

page 58 the bit check fails because the value CV_Lim is lower than the limit Lim_min. The bit

check also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 9-7 on page 58.

Figure 9-5. Timing Diagram During Bit Check

Bit check okBit check ok

Bit check modeStart-up mode

1/2 Bit 1/2 Bit1/2 Bit

RX_ACTIVE

(Lim_min = 14, Lim_max = 24)

Demod_Out

Bit-check counter

Bit check

TStartup_Sig_Proc TBit-check

TXDCLK

123456781234567891011121314151617181234567891011012131415 1 2 3 4 5 67

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Figure 9-6. Timing Diagram for Failed Bit Check (Condition CV_Lim < Lim_min)

Figure 9-7. Timing Diagram for Failed Bit Check (Condition: CV_Lim ≥ Lim_max)

9.1.6 Duration of the Bit Check

If no transmitter is present during the bit check, the output of the ASK/FSK demodulator delivers

random signals. The bit check is a statistical process and TBit-check varies for each check. There-

fore, an average value for TBit-check is given in the electrical characteristics. TBit-check depends on

the selected bit-rate range and on TXDCLK. A higher bit-rate range causes a lower value for

TBit-check, resulting in a lower current consumption in RX polling mode.

Start-up mode

TSleep

TBit_check

TStartup_Sig_Proc

Bit check mode Sleep mode

1/2 Bit

RX_ACTIVE

Demod_Out

Bit-check counter

Bit check

(Lim_min = 14, Lim_max = 24)

Bit check failed (CV_Lim < Lim_min)

12345678123456789101112 00

Start-up mode

TSleep

TBit_check

TStartup_Sig_Proc

Bit check mode Sleep mode

1/2 Bit

RX_ACTIVE

Demod_Out

Bit-check counter

Bit check

(Lim_min = 14, Lim_max = 24)

Bit check failed (CV_Lim < Lim_min)

12345678123456789101112

131415161718192021222324

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In the presence of a valid transmitter signal, TBit-check is dependent on the frequency of that sig-

nal, fSignal, and the count of the bits, NBit-check. A higher value for NBit-check therefore results in a

longer period for TBit-check, requiring a higher value for the transmitter pre-burst, TPreburst.

9.1.7 Receiving Mode

If the bit check was successful for all bits specified by NBit-check, the transceiver switches to

receiving mode. To activate a connected microcontroller, the bits VSOUT_EN and CLK_ON in

control register 3 are set to “1”. An interrupt is issued at pin IRQ if the control bits T_MODE = 0

and P_MODE = 0.

If the transparent mode is active (T_MODE = 1) and the level on pin CS is low (no data transfer

via the serial interface), the RX data stream is available on pin SDO_TMDO (Figure 9-8).

Figure 9-8. Receiving Mode (TMODE = 1)

If the transparent mode is inactive (T_MODE = 0), the received data stream is buffered in the

TX/RX data buffer (see Figure 9-9 on page 60). The TX/RX data buffer is only usable for

Manchester and Bi-phase coded signals. It is always possible to transfer the data from the data

buffer via the 4-wire serial interface to a microcontroller (see Figure 8-1 on page 49).

Buffering of the data stream:

After a successful bit check, the transceiver switches from bit-check mode to receiving mode. In

receiving mode the TX/RX data buffer control logic is active and examines the incoming data

stream. This is done, as in the bit check, by subsequent time frame checks where the distance

between two edges is continuously compared to a programmable time window as illustrated in

Figure 9-9 on page 60. Only two time differences between two edges in Manchester and

Bi-phase coded signals are valid (T and 2T).

The limits for T are the same as used for the bit check. They can be programmed in control

The limits for 2T are calculated as follows:

Lower limit of 2T:

Upper limit of 2T:

If the result of Lim_min_2T or Lim_max_2T is not an integer value, it will be rounded up.

SDO_TMDO

Demod_Out

Bit check ok

Preburst Byte 2

Byte 1

Start

bit

'0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1''0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '0' '0' '1' '1' '0' '1' '0' '1' '1' '0' '0'

Bit-check mode Receiving mode

Byte 3

Lim_min_2T Lim_min Lim_max+()Lim_max Lim_min–()/2–=

TLim_min_2T Lim_min_2T TXDCLK

×=

Lim_max_2T Lim_min Lim_max+()Lim_max Lim_min–()/2+=

TLim_max_2T Lim_max_2T - 1()TXDCLK

×=

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If the TX/RX data buffer control logic detects the start bit, the data stream is written in the TX/RX

data buffer byte by byte. The start bit is part of the first data byte and must be different from the

bits of the preburst. If the preburst consists of a sequence of “00000...”, the start bit must be a

“1”. If the preburst consists of a sequence of “11111...”, the start bit must be a “0”.

If the data stream consists of more than 16 bytes, a buffer overflow occurs and the TX/RX data

buffer control logic overwrites the bytes already stored in the TX/RX data buffer. Therefore, it is

very important to ensure that the data is read in time so that no buffer overflow occurs (see Fig-

ure 8-1 on page 49). There is a counter that indicates the number of received bytes in the TX/RX

data buffer (see section “Transceiver Configuration” on page 49). If a byte is transferred to the

microcontroller, the counter is decremented; if a byte is received, the counter is incremented.

The counter value is available via the 4-wire serial interface.

An interrupt is issued if the counter (while counting up) reaches the value defined by the control

bits IR0 and IR1 in control register 1.

Figure 9-9. Receiving Mode (TMODE = 0)

If the TX/RX data buffer control logic detects a bit error, an interrupt is issued and the transceiver

is set back to the start-up mode (see Figure 9-1 on page 54, Figure 9-2 on page 55 and

Figure 9-10 on page 61).

Bit error: a) tee < TLim_min or TLim_max < tee < TLim_min_2T or tee > TLim_max_2T

b) Logical error (no edge detected in the bit center)

Note: The byte consisting of the bit error will not be stored in the TX/RX data buffer. Thus, it is not avail-

able via the 4-wire serial interface.

Writing the control register 1, 4, 5 or 6 during receiving mode resets the TX/RX data buffer con-

trol logic and the counter which indicates the number of received bytes. If the bits OPM0 and

OPM1 are still “1” after writing to a control register, the transceiver changes to the start-up mode

(start-up signal processing).

Demod_Out

Bit check ok

Preburst Byte 2

LSB

Readable via 4-wire serial interface

TX/RX Data Buffer

MSB

Byte 1

Start

bit

T2T

'0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1''0' '0' '0' '0' '0'

Byte 14, Byte 30, ...

Byte 13, Byte 29, ...

Byte 10, Byte 26, ...

Byte 9, Byte 25, ...

Byte 8, Byte 24, ...

Byte 3, Byte 19, ...

Byte 1, Byte 17, ...

Byte 2, Byte 18, ...

Byte 4, Byte 20, ...

Byte 5, Byte 21, ...

Byte 6, Byte 22, ...

Byte 7, Byte 23, ...

Byte 11, Byte 27, ...

Byte 12, Byte 28, ...

Byte 16, Byte 32, ...

Byte 15, Byte 31, ...

11 111001

11 000000

'0' '1' '1' '1' '1' '0' '0' '1' '1' '0' '1' '0' '1' '1' '0' '0'

Bit-check mode Receiving mode

Byte 3

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Figure 9-10. Bit Error (TMODE = 0)

9.1.8 Recommended Lim_min and Lim_max for Maximum Sensitivity

The sensitivity measurements in the section “Low-IF Receiver” in Table 3-3 on page 12 and

Table 3-4 on page 12 have been done with the Lim_min and Lim_max values according to Table

9-3. These values are optimized for maximum sensitivity. Note that since these limits are opti-

mized for sensitivity, the number of checked bits, NBit-check, has to be at least 6 to prevent the

circuit from waking up to often in polling mode due to noise.

Demod_Out

Bit check ok

Byte n-1 Byte 1

Byte n+1 Preburst

Byte n

Start-up mode Bit-check modeReceiving mode Receiving mode

Bit error

Table 9-2. RX Modulation Scheme

Mode ASK/_NFSK T_MODE RFIN

Bit in TX/RX Data

Buffer

Level on Pin

SD0_TMDO

FSK_L →fFSK_H 1X

FSK_H →fFSK_L 0X

FSK_H –1

FSK_L –0

ASK off →fASK on 1 X

ASK on →fASK off 0 X

ASK on –1

ASK off –0

Table 9-3. Recommended Lim_min and Lim_max Values for Different Bit Rates

fRF (fXTAL)/

MHz

1.0 Kbit/s

BR_Range_0

XLim = 1

2.4 Kbit/s

BR_Range_0

XLim = 0

5 Kbit/s

BR_Range_1

XLim = 0

10 Kbit/s

BR_Range_2

XLim = 0

20 Kbit/s

BR_Range_3

XLim = 0

315

(12.73193)

Lim_min = 13 (261 µs)

Lim_max = 38 (744 µs)

Lim_min = 12 (121 µs)

Lim_max = 34 (332 µs)

Lim_min = 11 (55 µs)

Lim_max = 32 (156 µs)

Lim_min = 11 (28 µs)

Lim_max = 32 (78 µs)

Lim_min = 11 (14 µs)

Lim_max = 31 (38 µs)

345

(13.94447)

Lim_min = 13 (239 µs)

Lim_max = 38 (679 µs)

Lim_min = 12 (110 µs)

Lim_max = 34 (303 µs)

Lim_min = 11 (50 µs)

Lim_max = 32 (142 µs)

Lim_min = 11 (25 µs)

Lim_max = 32 (71 µs)

Lim_min = 11 (13 µs)

Lim_max = 31 (34 µs)

433.92

(13.25311)

Lim_min = 13 (251 µs)

Lim_max = 38 (715 µs)

Lim_min = 12 (116 µs)

Lim_max = 34 (319 µs)

Lim_min = 11 (53 µs)

Lim_max = 32 (150 µs)

Lim_min = 11 (27 µs)

Lim_max = 32 (75 µs)

Lim_min = 11 (13 µs)

Lim_max = 32 (37 µs)

868.3

(13.41191)

Lim_min = 13 (248 µs)

Lim_max = 38 (706 µs)

Lim_min = 12 (115 µs)

Lim_max = 34 (315 µs)

Lim_min = 11 (52 µs)

Lim_max = 32 (148 µs)

Lim_min = 11 (26 µs)

Lim_max = 32 (74 µs)

Lim_min = 11 (13 µs)

Lim_max = 32 (37 µs)

915

(14.13324)

Lim_min = 13 (235 µs)

Lim_max = 38 (670 µs)

Lim_min = 12 (109 µs)

Lim_max = 34 (299 µs)

Lim_min = 11 (50 µs)

Lim_max = 32 (140 µs)

Lim_min = 11 (25 µs)

Lim_max = 32 (70 µs)

Lim_min = 11 (12 µs)

Lim_max = 32 (35 µs)

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9.2 TX Operation

The transceiver is set to TX operation by using the bits OPM0 and OPM1 in the control

Before activating TX mode, the TX parameters (bit rate, modulation scheme, etc.) must be

selected as illustrated in Figure 9-11 on page 63. The bit rate depends on Baud 0 and Baud 1 in

control register 6, Lim_min0 to Lim_min5 in control register 5 and XLIM in control register 4 (see

section “Control Register” on page 38). The modulation is selected with ASK/_NFSK in control

Manchester modulator is disabled and pattern mode is active (NRZ, see Table 9-5 on page 65).

After the transceiver is set to TX mode, the start-up mode is active and the PLL is enabled. If the

PLL is locked, the TX mode is active.

If the transceiver is in start-up or TX mode, the TX/RX data buffer can be loaded via the 4-wire

serial interface. After the first byte is in the buffer and the TX mode is active, the transceiver

starts transmitting automatically (beginning with the MSB). While transmitting it is always possi-

ble to load new data in the TX/RX data buffer. To prevent a buffer overflow or interruptions

during transmitting, the user must ensure that data is loaded at the same speed as it is

transmitted.

There is a counter that indicates the number of bytes to be transmitted (see section “Transceiver

Configuration” on page 49). If a byte is loaded, the counter is incremented, if a byte is transmit-

ted, the counter is decremented. The counter value is available via the 4-wire serial interface. An

IRQ is issued if the counter (while counting down) reaches the value defined by the control bits

IR0 and IR1 in control register 1.

Note: Writing to the control register 1, 4, 5 or 6 during TX mode resets the TX/RX data buffer and the

counter which indicates the number of bytes to be transmitted.

If T_Mode in control register 1 is set to “1”, the transceiver is in TX transparent mode. In this

mode the TX/RX data buffer is disabled and the TX data stream must be applied on pin

SDI_TMDI. Figure 9-11 on page 63 illustrates the flow chart of the TX transparent mode.

Table 9-4. Control Register 1

OPM1 OPM0 Function

01TX mode

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Figure 9-11. TX Operation (T_MODE = 0)

Write TX/RX Data Buffer (max. 16 - number of bytes still

in the TX/RX Data Buffer)

Write TX/RX Data Buffer (max. 16 byte)

Baud1, BAUD0:

Lim_max0 to Lim_max5:

Select baud rate range

Don't care

Write Control Register 6

Lim_min0 to Lim_min5:

Bit_ck0, Bit_ck1:

Select the baud rate

Don't care

Write Control Register 5

Set IDLEOPM1, OPM0:

Write Control Register 1

NPin IRQ = 1 ?

Idle Mode

TX Mode

Start-up

Mode (TX)

Idle Mode

Command: Delete_IRQ

TX more Data

Bytes ?

FR7, FR8:

VSOUT_EN:

CLK_ON:

Adjust fRF

Set VSOUT_EN = 1

Don't care

Write Control Register 3

FR0 to FR6:

P_mode:

Adjust fRF

Enable or disable the

Manchester modulator

Write Control Register 2

IR1, IR0:

AVCC_EN:

FS:

OPM1, OPM0:

T_mode:

Select an event which activates

an interrupt

Don't care

Select operation frequency

Set OPM1 = 0 and OPM0 = 1

Set T_mode = 0

Write Control Register 1

XLim:

ASK/_NFSK:

Sleep0 to Sleep4:

XSleep:

Select the bit rate

Select modulation

Don't care

Write Control Register 4

Pin IRQ = 1 ?

TStartup = 331.5 × TDCL

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Figure 9-12. TX Transparent Mode (T_MODE = 1)

Apply TX Data on Pin SDI_TMDI

Set IDLE (OPM1 = 0, OPM0 = 1OPM1, OPM0:

Write Control Register 1

Idle Mode

TX Mode

Start-up

Mode (TX)

Idle Mode

FR7, FR8:

VSOUT_EN:

CLK_ON:

Adjust fRF

Set VSOUT_EN = 1

Don't care

Write Control Register 3

FR0 to FR6:

P_mode:

Adjust fRF

Don't care

Write Control Register 2

IR1, IR0:

AVCC_EN:

FS:

OPM1, OPM0:

T_mode:

Don't care

Select operation frequency

Set OPM1 = 0 and OPM0 = 1

Set T_mode = 1

Write Control Register 1

XLim:

ASK/_NFSK:

Sleep0 to Sleep4:

XSleep:

Don't care

Select modulation

Don't care

Write Control Register 4

TStartup = 331.5 × TDCL

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9.3 Interrupts

Via pin IRQ, the transceiver signals different operating conditions to a connected microcontrol-

ler. If a specific operating condition occurs, pin IRQ is set to high.

If an interrupt occurs, it is recommended to delete the interrupt immediately by reading the sta-

tus register, so that a further potential interrupt doesn’t get lost. If the Interrupt pin doesn’t switch

to low by reading the status register, the interrupt was triggered by the RX/TX data buffer. In this

case read or write the RX/TX data buffer according to Table 9-6.

Table 9-5. TX Modulation Schemes

Mode ASK/_NFSK P_Mode T_Mode

Bit in TX/RX

Data Buffer

Level on Pin

SDI_TMDI RFOUT

001Xf

FSK_L →fFSK_H

000Xf

FSK_H →fFSK_L

101X f

FSK_H

100X f

FSK_L

X1X1 f

FSK_H

X1X0 f

FSK_L

001Xf

ASK off →fASK on

000Xf

ASK on →fASK off

101X f

ASK on

100X f

ASK off

X1X1 f

ASK on

X1X0 f

ASK off

Table 9-6. Interrupt Handling

Operating Conditions Which Set Pin IRQ to High

Level Operations Which Set Pin IRQ to Low Level

Events in Status Register

State transition of status bit STn

(0 →1; 1 →0)

Read status register or

Command Delete IRQ

Appearance of status bit Power_On

(0 →1)

Appearance of status bit P_On_Aux

(0 →1)

Events During TX Operation (T_MODE = 0)

4, 8 or 12 Bytes are in the TX data buffer or the TX

data buffer is empty (depends on IR0 and IR1 in

control register 1).

Write TX data buffer or

Write control register 1 or

Write control register 4 or

Write control register 5 or

Write control register 6 or

Command delete IRQ

Events During RX Operation (T_MODE = 0)

4, 8 or 12 received bytes are in the RX data buffer or a

receiving error is occurred (depends on IR0 and IR1

in control register 1).

Read RX data buffer(1) or

Write control register 1 or

Write control register 4 or

Write control register 5 or

Write control register 6 or

Command delete IRQ

Successful bit check (P_MODE = 0)

Note: 1. During reading of the RX/TX buffer, no IRQ is issued, due to the received bytes or a receiving

error.

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10. Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameters Symbol Min. Max. Unit

Junction temperature Tj150 °C

Storage temperature Tstg –55 +125 °C

Ambient temperature Tamb –40 +85 °C

Supply voltage VS2 VMaxVS2 –0.3 +7.2 V

Supply voltage VS1 VMaxVS1 –0.3 +4 V

Supply voltage VAUX VMaxVAUX –0.3 +7.2 V

Supply voltage VSINT VMaxVSINT –0.3 +5.5 V

ESD (Human Body Model ESD S 5.1)

every pin HBM –1.5 + 1.5 kV

ESD (Machine Model JEDEC A115A)

every pin MM –200 +200 V

ESD (Field Induced Charge Device Model ESD

STM 5.3.1–1999)

every pin

FCDM –1 +1 kV

Maximum input level, input matched to 50 ΩPin_max 10 dBm

11. Thermal Resistance

Parameters Symbol Value Unit

Junction ambient RthJA 25 K/W

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12. Electrical Characteristics: General

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may

meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive

application.

All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)

and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details

about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.

No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type*

1 RX_TX_IDLE Mode

1.1 RF operating frequency

range

ATA5423

V433_N868 =AVCC 4, 10 fRF 312.5 317.5 MHz A

ATA5425

V433_N868 =AVCC 4, 10 fRF 342.5 347.5 MHz A

ATA5428

V433_N868 =AVCC 4, 10 fRF 431.5 436.5 MHz A

ATA5428

V433_N868 =GND 4, 10 fRF 862 872 MHz A

ATA54 2 9

V433_N868 =GND 4, 10 fRF 912.5 917.5 MHz A

1.2 Supply current

OFF mode

VVS1 =V

VS2 =3V,

VVSINT =0V

(1 battery) and

VVS2 = 6V (2 battery)

OFF mode is not

available if

VVS2 =V

VAUX =5V

VVSINT =0V (base

station)

IS_OFF < 10 nA A

1.3 Supply current

IDLE mode

VVSOUT disabled,

XTO running

VVS1 = VVS2 = 3V

(1 battery)

IS_IDLE 220 µA B

VVS2 = 6V (2 battery) IS_IDLE 310 µA B

VVS2 = VVAUX = 5V

(base station) IS_IDLE 310 µA B

1.4 System start-up time

From OFF mode to

IDLE mode including

reset and XTO start-up

(see Figure 7-4 on page

46)

XTAL: Cm = 5 fF,

C0 = 1.8 pF, Rm =15Ω

TPWR_ON_IRQ_1 0.3 ms C

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with

component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21

with component values according to Table 3-7 on page 22.

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1.5 RX start-up time

From IDLE mode to

receiving mode

NBit-check = 3

Bit rate = 20 Kbit/s,

BR_Range_3

(see Figure 9-1 on page

54, Figure 9-2 on page

55 and Figure 9-3 on

page 56)

TStartup_PLL +

TStartup_Sig_Proc

+ TBit-chek

1.39 ms A

1.6 TX start-up time

From IDLE mode to TX

mode (see Figure 9-11

on page 63)

TStartup 0.4 ms A

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may

meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive

application.

All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)

and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details

about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.

No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with

component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21

with component values according to Table 3-7 on page 22.

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2 Receiver/RX Mode

2.1 Supply current RX mode

fRF = 315 MHz

fRF = 345 MHz

fRF = 433.92 MHz

17, 18 IS_RX 10.5 mA A

fRF = 868 MHz

fRF = 915 MHz 17, 18 IS_RX 10.3 mA A

2.2 Supply current

RX polling mode

TSleep = 49.45 ms

XSLEEP = 8, Sleep = 5

Bit rate = 20 Kbit/s FSK,

VVSOUT disabled

17, 18 IP444 µA B

2.3 Input sensitivity FSK

fRF = 433.92 MHz

FSK deviation

fDEV = ±16 kHz

limits according to

Table 9-3 on page 61,

BER = 10-3

Tamb = 25°C

Bit rate 20 Kbit/s (4) PREF_FSK –104.0 –106.0 –107.5 dBm B

Bit rate 2.4 Kbit/s (4) PREF_FSK –107.5 –109.5 –111.0 dBm B

2.4 Input sensitivity ASK

fRF = 433.92 MHz

ASK 100%, level of

carrier limits according

to Table 9-3 on page

61, BER = 10-3

Tamb = 25°C

Bit rate 10 Kbit/s (4) PREF_ASK –110.5 –112.5 –114.0 dBm B

Bit rate 2.4 Kbit/s (4) PREF_ASK –114.5 –116.5 –118.0 dBm B

2.5

Sensitivity change at

fRF = 315 MHz

fRF = 345 MHz

fRF = 868.3 MHz

fRF = 915 MHz

compared to

fRF = 433.92 MHz

to fRF = 315 MHz

fRF = 433.92 MHz

to fRF = 345 MHz

fRF = 433.92 MHz

to fRF = 868.3 MHz

fRF = 433.92 MHz

to fRF = 915 MHz

P = PREF_ASK + ∆PREF1 +

∆PREF2

P = PREF_FSK + ∆PREF1 +

∆PREF2

(4) ∆PREF1

–1.0

–0.8

+2.7

+3.3 dB B

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may

meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive

application.

All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)

and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details

about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.

No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with

component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21

with component values according to Table 3-7 on page 22.

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2.6 Maximum frequency

offset in FSK mode

Maximum frequency

difference of fRF

between receiver and

transmitter in FSK

mode (fRF is the center

frequency of the FSK

signal with

fDEV = ±16 kHz)

(4) ∆fOFFSET –58 +58 kHz B

2.7 Supported FSK frequency

deviation

With up to 2 dB

loss of sensitivity.

Note that the tolerable

frequency offset is for

fDEV = ±22 kHz, 6 kHz

lower than for

fDEV = ±16 kHz hence

∆fOFFSET ≤±52 kHz

(4) fDEV ±14 ±16 ±22 kHz B

2.8 System noise figure

fRF = 315 MHz (4) NF 6.0 dB B

fRF = 345 MHz (4) NF 6.2 dB B

fRF = 433.92 MHz (4) NF 7.0 dB B

fRF = 868.3 MHz (4) NF 9.7 dB B

fRF = 915 MHz (4) NF 10.3 dB B

2.9 Intermediate frequency

fRF = 315 MHz fIF 227 kHz A

fRF = 345 MHz fIF 235 kHz A

fRF = 433.92 MHz fIF 223 kHz A

fRF = 868.3 MHz fIF 226 kHz A

fRF = 915 MHz fIF 238 kHz A

2.10 System bandwidth

This value is for

information only!

Note that for crystal and

system frequency offset

calculations, ∆fOFFSET

must be used.

(4) SBW 185 kHz A

2.11

System outband

2nd-order input intercept

point with respect to fIF

∆fmeas1 = 1,800 MHz

∆fmeas2 = 2,026 MHz

fIF = ∆fmeas2 – ∆fmeas1

(4) IIP2 +50 dBm C

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may

meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive

application.

All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)

and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details

about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.

No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with

component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21

with component values according to Table 3-7 on page 22.

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2.12

System outband

3rd-order input intercept

point

∆fmeas1 = 1.8 MHz

∆fmeas2 = 3.6 MHz

fRF = 315 MHz

(4) IIP3 –22 dBm

fRF = 345 MHz (4) IIP3 –22 dBm C

fRF = 433.92 MHz (4) IIP3 –21 dBm C

fRF = 868.3 MHz (4) IIP3 –17 dBm C

fRF = 915 MHz (4) IIP3 –16 dBm C

2.13 System outband input

1 dB compression point

∆fmeas1 = 1 MHz

fRF = 315 MHz (4) I1dBCP –31 dBm C

fRF = 345 MHz (4) I1dBCP –31 dBm C

fRF = 433.92 MHz (4) I1dBCP –30 dBm C

fRF = 868.3 MHz (4) I1dBCP –27 dBm C

fRF = 915 MHz (4) I1dBCP –26 dBm C

2.14 LNA input impedance

fRF = 315 MHz 4 Zin_LNA (44 – j233) ΩC

fRF = 345 MHz 4 Zin_LNA (40 – j211) ΩC

fRF = 433.92 MHz 4 Zin_LNA (32 – j169) ΩC

fRF = 868.3 MHz 4 Zin_LNA (21 – j78) ΩC

fRF = 915 MHz 4 Zin_LNA (18 – j70) ΩC

2.15 Allowable peak RF input

level, ASK and FSK

BER < 10-3, ASK: 100% (4) PIN_max +10 –10 dBm C

FSK: fDEV = ±16 kHz (4) PIN_max +10 –10 dBm C

2.16 LO spurious emission at

LNA_IN

f < 1 GHz (4) –57 dBm C

f >1 GHz (4) –47 dBm C

fRF = 315 MHz (4) –100 dBm C

fRF = 345 MHz (4) –100 dBm C

fRF = 433.92 MHz (4) –97 dBm C

fRF = 868.3 MHz (4) –84 dBm C

fRF = 915 MHz (4) –84 dBm C

2.17 Image rejection Within the complete

image band (4) 20 30 dB A

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may

meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive

application.

All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)

and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details

about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.

No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with

component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21

with component values according to Table 3-7 on page 22.

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2.18 Useful signal to interfering

signal ratio

Peak level of useful

signal to peak level of

interferer for BER < 10-3

with any modulation

scheme of interferer

FSK BR_Ranges 0, 1, 2 (4) SNRFSK0-2 23dBB

FSK BR_Range_3 (4) SNRFSK3 46dBB

ASK (PRF < PRFIN_High)(4) SNR

ASK 10 12 dB B

2.19 RSSI output

Dynamic range (4), 36 DRSSI 70 dB A

Lower level of range

fRF = 315 MHz

fRF = 345 MHz

fRF = 433.92 MHz

fRF = 868.3 MHz

fRF = 915 MHz

(4), 36 PRFIN_Low

–116

–115

–112

–111

dBm

Upper level of range

fRF = 315 MHz

fRF = 345 MHz

fRF = 433.92 MHz

fRF = 868.3 MHz

fRF = 915 MHz

(4), 36 PRFIN_High

–46

–45

–42

–41

dBm

Gain (4), 36 5.5 8.0 10.5 mV/dB A

Output voltage range (4), 36 OVRSSI 400 1100 mV A

2.20 Output resistance RSSI

RX mode

TX mode 36 RRSSI 8

12.5

50 kΩC

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may

meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive

application.

All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)

and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details

about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.

No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with

component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21

with component values according to Table 3-7 on page 22.

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2.21 Blocking

Sensitivity (BER = 10–3)

is reduced by 6 dB if a

continuous wave

blocking signal at ±∆f is

∆PBlock higher than the

useful signal level

(bit rate = 20 Kbit/s,

FSK, fDEV ±16kHz,

Manchester code)

fRF = 315 MHz

∆f ±0.75 MHz

∆f ±1.0 MHz

∆f ±1.5 MHz

∆f ±5 MHz

∆f ±10 MHz

(4) ∆PBlock

dBC C

fRF = 345 MHz

∆f ±0.75 MHz

∆f ±1.0 MHz

∆f ±1.5 MHz

∆f ±5 MHz

∆f ±10 MHz

(4) ∆PBlock

dBC C

fRF = 433.92 MHz

∆f ±0.75 MHz

∆f ±1.0 MHz

∆f ±1.5 MHz

∆f ±5 MHz

∆f ±10 MHz

(4) ∆PBlock

dBC C

fRF = 868.3 MHz

∆f ±0.75 MHz

∆f ±1.0 MHz

∆f ±1.5 MHz

∆f ±5 MHz

∆f ±10 MHz

(4) ∆PBlock

dBC C

fRF = 915 MHz

∆f ±0.75 MHz

∆f ±1.0 MHz

∆f ±1.5 MHz

∆f ±5 MHz

∆f ±10 MHz

(4) ∆PBlock

dBC C

2.22 CDEM Capacitor connected to

pin 37 (CDEM) 37 –5% 15 +5% nF D

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may

meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive

application.

All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)

and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details

about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.

No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with

component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21

with component values according to Table 3-7 on page 22.

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3 Power Amplifier/TX Mode

3.1 Supply current TX mode

power amplifier OFF

fRF = 868.3 MHz

fRF = 915 MHz IS_TX_PAOFF 6.50 mA A

fRF = 315 MHz

fRF = 345 MHz

fRF = 433.92 MHz

IS_TX_PAOFF 6.95 mA A

3.2 Output power 1

VVS1 = VVS2 = 3V

Tamb = 25°C

VPWR_H = 0V

fRF = 315 MHz

RR_PWR = 56 kΩ

RLopt = 2.5 kΩ

fRF = 345 MHz

RR_PWR = 56 kΩ

RLopt = 2.4 kΩ

fRF = 433.92 MHz

RR_PWR = 56 kΩ

RLopt = 2.3 kΩ

fRF = 868.3 MHz

RR_PWR = 30 kΩ

RLopt = 1.3 kΩ

fRF = 915 MHz

RR_PWR = 33 kΩ

RLopt = 1.1 kΩ

RF_OUT matched to

RLopt //

j/(2 × π × fRF × 1.0 pF)

(10) PREF1 –2.5 0 +2.5 dBm B

3.3 Supply current TX mode

power amplifier ON 1

PA on/0 dBm

fRF = 315 MHz 17, 18 IS_TX_PAON1 8.5 mA B

fRF = 345 MHz 17, 18 IS_TX_PAON1 8.6 mA B

fRF = 433.92 MHz 17, 18 IS_TX_PAON1 8.6 mA B

fRF = 868.3 MHz 17, 18 IS_TX_PAON1 9.6 mA B

fRF = 915 MHz 17, 18 IS_TX_PAON1 9.6 mA B

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may

meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive

application.

All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)

and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details

about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.

No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with

component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21

with component values according to Table 3-7 on page 22.

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3.4 Output power 2

VVS1 = VVS2 = 3V

Tamb = 25°C

VPWR_H = 0V

fRF = 315 MHz

RR_PWR = 30 kΩ

RLopt = 1.0 kΩ

fRF = 345 MHz

RR_PWR = 33 kΩ

RLopt = 1.1 kΩ

fRF = 433.92 MHz

RR_PWR = 27 kΩ

RLopt = 1.1 kΩ

fRF = 868.3 MHz

RR_PWR = 16 kΩ

RLopt = 0.5 kΩ

fRF = 915 MHz

RR_PWR = 15 kΩ

RLopt = 0.25 kΩ

RF_OUT matched to

RLopt//

j/(2 × π × fRF × 1.0 pF)

(10) PREF2 3.5 5.0 6.5 dBm B

3.5 Supply current TX mode

power amplifier ON 2

PA on/5 dBm

fRF = 315 MHz 17, 18 IS_TX_PAON2 10.3 mA B

fRF = 345 MHz 17, 18 IS_TX_PAON2 10.4 mA B

fRF = 433.92 MHz 17, 18 IS_TX_PAON2 10.5 mA B

fRF = 868.3 MHz 17, 18 IS_TX_PAON2 11.2 mA B

fRF = 915 MHz 17, 18 IS_TX_PAON2 11.8 mA B

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may

meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive

application.

All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)

and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details

about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.

No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with

component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21

with component values according to Table 3-7 on page 22.

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3.6 Output power 3

VVS1 = VVS2 = 3V

Tamb = 25°C

VPWR_H = AVCC

fRF = 315 MHz

RR_PWR = 30 kΩ

RLopt = 0.38 kΩ

fRF = 345 MHz

RR_PWR = 31 kΩ

RLopt = 0.38 kΩ

fRF = 433.92 MHz

RR_PWR = 27 kΩ

RLopt = 0.36 kΩ

fRF = 868.3 MHz

RR_PWR = 20 kΩ

RLopt = 0.22 kΩ

fRF = 915 MHz

RR_PWR = 16 kΩ

RLopt = 0.24 kΩ

RF_OUT matched to

RLopt//

j/(2 × π × fRF × 1.0 pF)

(10) PREF3 8.5 10 11.5 dBm B

3.7 Supply current TX mode

power amplifier ON 3

PA on/10dBm

fRF = 315 MHz 17, 18 IS_TX_PAON3 15.7 mA B

fRF = 345 MHz 17, 18 IS_TX_PAON3 15.8 mA B

fRF = 433.92 MHz 17, 18 IS_TX_PAON3 15.8 mA B

fRF = 868.3 MHz 17, 18 IS_TX_PAON3 17.3 mA B

fRF = 915 MHz 17, 18 IS_TX_PAON3 19.3 mA B

3.8

Output power variation for

full temperature and

supply voltage range

Tamb = –40°C to +85°C

Pout = PREFX + ∆PREFX

X = 1, 2 or 3

VVS1 = VVS2 = 3.0V

(10) ∆PREF –0.8 –1.5 dB B

VVS1 = VVS2 = 2.7V (10) ∆PREF –2.5 dB B

VVS1 = VVS2 = 2.4V (10) ∆PREF –3.5 dB B

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may

meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive

application.

All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)

and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details

about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.

No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with

component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21

with component values according to Table 3-7 on page 22.

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3.9 Impedance RF_OUT in

RX mode

fRF = 315 MHz 10 ZRF_OUT_RX (36 – j502) ΩC

fRF = 345 MHz 10 ZRF_OUT_RX (33 – j480) ΩC

fRF = 433.92 MHz 10 ZRF_OUT_RX (19 – j366) ΩC

fRF = 868.3 MHz 10 ZRF_OUT_RX (2.8 – j141) ΩC

fRF = 915 MHz 10 ZRF_OUT_RX (2.6 – j135) ΩC

3.10 Noise floor power

amplifier

at ±10 MHz/at 5 dBm

fRF = 315 MHz (10) LTX10M –127 dBC/Hz C

fRF = 345 MHz (10) LTX10M –126 dBC/Hz C

fRF = 433.92 MHz (10) LTX10M –126 dBC/Hz C

fRF = 868.3 MHz (10) LTX10M –125 dBC/Hz C

fRF = 915 MHz (10) LTX10M –125 dBC/Hz C

3.11 ASK modulation rate

This corresponds to

10 Kbit/s Manchester

coding and 20 Kbit/s

NRZ coding

fData_ASK 110kHzC

4XTO

4.1 Pulling XTO due to XTO,

CL1 and CL2 tolerances

Pulling at nominal

temperature and supply

voltage

fXTAL = resonant

frequency of the XTAL

C0 ≥ 1.0 pF

Rm ≤120Ω

24, 25

∆fXTO1

Cm ≤7.0 fF

Cm ≤14 fF

–50

–100 fXTAL +50

+100 ppm

4.2 Transconductance XTO at

start

At start-up; after

start-up the amplitude

is regulated to VPPXTAL

24, 25 gm, XTO 19 ms B

4.3 XTO start-up time

C0 ≤2.2 pF

Cm < 14fF

Rm ≤120Ω24, 25 TPWR_ON_IRQ_1 300 800 µs A

4.4 Maximum C0 of XTAL

Required for stable

operation with internal

load capacitors

24, 25 C0max 3.8 pF D

4.5 Internal capacitors CL1 and CL2 24, 25 CL1, CL2 14.8 18 pF 21.2 pF B

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may

meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive

application.

All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)

and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details

about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.

No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with

component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21

with component values according to Table 3-7 on page 22.

4841D–WIRE–10/07

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4.6

Pulling of radio frequency

fRF due to XTO, CL1 and

CL2 versus temperature

and supply changes

1.0 pF ≤ C0 ≤ 2.2 pF

Cm ≤14.0 fF

Rm ≤120Ω

PLL adjusted with

FREQ at nominal

temperature and supply

voltage

4, 10 ∆fXTO2 –2+2ppmC

4.7 Amplitude XTAL after

start-up

Cm = 5 fF, C0 = 1.8 pF

Rm =15Ω

V(XTAL1, XTAL2)

peak-to-peak value 24, 25 VPPXTAL 700 mVpp C

V(XTAL1)

peak-to-peak value 24, 25 VPPXTAL 350 mVpp C

4.8 Real part of XTO

impedance at start-up

C0 ≤2.2 pF, small signal

start impedance, this

value is important for

crystal oscillator startup

24, 25 ReXTO –2,000 –1,500 ΩB

4.9

Maximum series

resistance Rm of XTAL

after start-up

C0 ≤2.2 pF

Cm ≤14 fFΩ24, 25 Rm_max 15 120 ΩB

4.10 Nominal XTAL load

resonant frequency

fRF = 315 MHz

fRF = 345 MHz

fRF = 433.92 MHz

fRF = 868.3 MHz

fRF = 915 MHz

24, 25 fXTAL

12.73193

13.94447

13.25311

13.41191

14.13324

MHz

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may

meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive

application.

All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)

and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details

about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.

No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with

component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21

with component values according to Table 3-7 on page 22.

4841D–WIRE–10/07

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4.11 External CLK frequency

fRF = 315 MHz

CLK division ratio = 3

CLK has nominal 50%

duty cycle

30 fCLK 4.244 MHz D

fRF = 345 MHz

CLK division ratio = 3

CLK has nominal 50%

duty cycle

30 fCLK 4.648 MHz D

fRF = 433.92 MHz

CLK division ratio = 3

CLK has nominal 50%

duty cycle

30 fCLK 4.418 MHz D

fRF = 868.3 MHz

CLK division ratio = 3

CLK has nominal 50%

duty cycle

30 fCLK 4.471 MHz D

fRF = 915 MHz

CLK division ratio = 3

CLK has nominal 50%

duty cycle

30 fCLK 4.711 MHz D

4.12 DC voltage after start-up

VDC(XTAL1, XTAL2)

XTO running

(IDLE mode, RX mode

and TX mode)

24, 25 VDCXTO –150 –30 mV C

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may

meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive

application.

All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)

and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details

about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.

No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with

component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21

with component values according to Table 3-7 on page 22.

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5 Synthesizer

5.1 Spurious TX mode

At ±fCLK, CLK enabled

fRF = 315 MHz

fRF = 345 MHz

fRF = 433.92 MHz

fRF = 868.3 MHz

fRF = 915 MHz

SPTX

–72

–74

–68

–70

–69

dBC C

At ±fXTO

fRF = 315 MHz

fRF = 345 MHz

fRF = 433.92 MHz

fRF = 868.3 MHz

fRF = 915 MHz

SPTX

–70

–68

–66

–60

dBC C

5.2 Spurious RX mode

At ±fCLK, CLK enabled

fRF = 315 MHz

fRF = 345 MHz

fRF = 433.92 MHz

fRF = 868.3 MHz

fRF = 915 MHz

SPRX

< –75

dBC C

At ±fXTO

fRF = 315 MHz

fRF = 345 MHz

fRF = 433.92 MHz

fRF = 868.3 MHz

fRF = 915 MHz

SPRX

–75

–73

–75

–68

–67

dBC C

5.3 In loop phase noise

TX mode

Measured at 20 kHz

distance to carrier

fRF = 315 MHz

fRF = 345 MHz

fRF = 433.92 MHz

fRF = 868.3 MHz

fRF = 915 MHz

LTX20k

–85

–80

–75

dBC/Hz A

5.4 Phase noise at 1M

RX mode

fRF = 315 MHz

fRF = 345 MHz

fRF = 433.92 MHz

fRF = 868.3 MHz

fRF = 915 MHz

LRX1M

–121

–120

–113

dBC/Hz C

5.5 Phase noise at 1M

TX mode

fRF = 315 MHz

fRF = 345 MHz

fRF = 433.92 MHz

fRF = 868.3 MHz

fRF = 915 MHz

LTX1M

–113

–111

–107

dBC/Hz C

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may

meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive

application.

All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)

and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details

about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.

No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with

component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21

with component values according to Table 3-7 on page 22.

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5.6 Phase noise at 10M

RX mode Noise floor PLL LRX10M –135 dBC/Hz C

5.7 Loop bandwidth PLL

TX mode

Frequency where the

absolute value loop

gain is equal to 1

fLoop_PLL 70 kHz B

5.8 Frequency deviation

TX mode

fRF = 315 MHz

fRF = 345 MHz

fRF = 433.92 MHz

fRF = 868.3 MHz

fRF = 915 MHz

fDEV_TX

±15.54

±17.02

±16.17

±16.37

±17.25

kHz D

5.9 Frequency resolution

fRF = 315 MHz

fRF = 345 MHz

fRF = 433.92 MHz

fRF = 868.3 MHz

fRF = 915 MHz

4, 10 ∆fStep_PLL

777.1

851.1

808.9

818.6

862.6

Hz D

5.10 FSK modulation rate

This correspond to

20 Kbit/s Manchester

coding and 40 Kbit/s

NRZ coding

fData_FSK 120kHzB

6 RX/TX Switch

6.1 Impedance RX mode

RX mode, pin 38 with

short connection to

GND, fRF = 0 Hz (DC)

39 ZSwitch_RX 23000 ΩA

fRF = 315 MHz

fRF = 345 MHz

fRF = 433.92 MHz

fRF = 868.3 MHz

fRF = 915 MHz

39 ZSwitch_RX

(11.3 – j214)

(11.1 – j181)

(10.3 – j153)

(8.9 – j73)

(9 – j65)

ΩC

6.2 Impedance TX mode

TX mode, pin 38 with

short connection to

GND, fRF = 0 Hz (DC)

39 ZSwitch_TX 5ΩA

fRF = 315 MHz

fRF = 345 MHz

fRF = 433.92 MHz

fRF = 868.3 MHz

fRF = 915 MHz

39 ZSwitch_RX

(4.8 + j3.2)

(4.7 + j3.4)

(4.5 + j4.3)

(5 + j9)

(5 + j9.2)

ΩC

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may

meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive

application.

All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)

and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details

about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.

No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with

component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21

with component values according to Table 3-7 on page 22.

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7 Microcontroller Interface

7.1 Voltage range for

microcontroller interface

IVSINT < 10 µA if CLK is

disabled and all

interface pins are in

stable condition and

unloaded

27, 28,

29, 30,

31, 32,

33, 34,

2.4 5.25 V A

7.2 CLK output rise and fall

time

fCLK < 4.5 MHz

CL = 10 pF

CL = Load capacitance

on pin CLK

2.4V ≤VVSINT ≤5.25V

20% to 80% VVSINT

trise

tfall

ns B

7.4

Current consumption of

the microcontroller

interface

CLK enabled

VVSOUT enabled

CLK disabled

VVSOUT enabled

VVSOUT disabled

CL = Load capacitance

on pin CLK

(All interface pins,

except pin CLK, are in

stable condition and

unloaded)

27 IVSINT

< 10 µA

7.5 Internal equivalent

capacitance

Used for current

calculation 30, 27 CCLK 8pFB

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may

meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive

application.

All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)

and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details

about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.

No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with

component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21

with component values according to Table 3-7 on page 22.

IVSINT

CCLK CL

+()VVSINT fXTO

××

----------------------------------------------------------------------------=

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8 Power Supply General Definitions and AUX Mode

8.1

Current consumption of

an external device

connected to pin VSOUT

IEXT

IEXT = IVSOUT – IVSINT

IEXT = IVSOUT

8.2 AUX mode

8.3 Power supply output

voltage

AUX mode

VVAUX ≥ 4V

IVSOUT ≤13.5 mA

(3.25V regulator mode,

V_REG2, see

Figure 5-1 on page 30)

22 VVSOUT 2.7 3.5 V A

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may

meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive

application.

All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)

and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details

about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.

No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with

component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21

with component values according to Table 3-7 on page 22.

VSINT

VSOUT

EXT

VSINT

VSOUT

VSINT

EXT

= I

VSOUT

VAUX

IAUX_VAUX

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8.4 Current in AUX mode on

pin VAUX

IVSOUT = 0

VVAUX = 6V

VVAUX = 4V to 7V

19 IAUX_VAUX 380 500

500

µA

8.5 Supply current

AUX mode

CLK enabled

VVSOUT enabled

CLK disabled

VVSOUT enabled

19, 22,

27 IS_AUX

IS_AUX = IAUX_VAUX + IVSINT + IEXT

IS_AUX = IAUX_VAUX + IEXT

8.6 Supported voltage range

VAUX 19 VVAUX 467V

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may

meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive

application.

All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)

and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details

about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.

No. Parameters Test Conditions Pin(1) Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with

component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21

with component values according to Table 3-7 on page 22.

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

13. Electrical Characteristics: 1 Li Battery Application (3V)

All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V. Application according to Figure 2-1 on page 7.

fRF = 315 MHz/345 MHz/433.92 MHz/868.3 MHz/915 MHz unless otherwise specified

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

9 1 Li Battery Application (3V)

9.1

Supported voltage

range (every mode

except high power TX

mode)

1 Li battery application

(3V)

PWR_H = GND

17, 18 VVS1, VVS2 2.4 3.6 V A

9.2

Supported voltage

range (high power TX

mode)

1 Li battery application

(3V)

PWR_H = AVCC

17, 18 VVS1, VVS2 2.7 3.6 V A

9.3 Power supply output

voltage

1 Li battery application

(3V)

VVS1 =V

VS2 ≥2.6V

VAUX open(1)

IVSOUT ≤13.5 mA

(no voltage regulator to

stabilize VVSOUT)

VVS1 = VVS2 ≥ 2.425V

VAUX open(1)

IVSOUT ≤1.5 mA

(no voltage regulator to

stabilize VVSOUT)

22 VVSOUT 2.4 VVS1 VB

9.4

Supply voltage for

microcontroller

interface

27 VVSINT 2.4 5.25 V A

9.5 Threshold hysteresis VThres_2 – VThres_1 22 ∆VThres 60 80 100 mV B

9.6

Reset threshold voltage

at pin VSOUT

(N_RESET)

22 VThres_1 2.18 2.3 2.42 V A

9.7

Reset threshold voltage

at pin VSOUT

(Low_Batt)

22 VThres_2 2.26 2.38 2.5 V A

9.8 Supply current

OFF mode

VVS1 = VVS2 ≤3.6V

VVSINT = 0V

17, 18,

22, 27 IS_OFF 2 350 nA A

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. The voltage of VAUX may rise up to 2V. The current IVAUX may not exceed 100 µA.

IDLE_VS1,2

RX_VS1,2

Startup_PLL_VS1,2

TX_VS1,2

VS1

VS2

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9.9 Current in IDLE mode

on pin VS1 and VS2

VVS1 = VVS2 ≤3V

IVSOUT = 0

CLK enabled

VVSOUT enabled

CLK disabled

VVSOUT enabled

VVSOUT disabled

17, 18 IIDLE_VS1, 2

312

260

225

430

370

320

µA

9.10 Supply current

IDLE mode

17, 18,

22, 27 IS_IDLE IS_IDLE = IIDLE_VS1, 2 + IVSINT + IEXT

9.11 Current in RX mode on

pin VS1and VS2

VVS1 = VVS2 ≤3V

IVSOUT = 0 17, 18 IRX_VS1, 2 10.5 14 mA A

9.12 Supply current

RX mode

CLK enabled

VVSOUT enabled

17, 18,

22, 27 IS_RX IS_RX = IRX_VS1, 2 + IVSINT + IEXT

9.13

Current during

TStartup_PLL on pin VS1

and VS2

VVS1 = VVS2 ≤3V

IVSOUT = 0 17, 18 IStartup_PLL_VS1, 2 8.8 11.5 mA C

9.14

Current in

RX polling mode on pin

VS1 and VS2

9.15 Supply current

RX polling mode

CLK enabled

VVSOUT enabled

CLK disabled

VVSOUT enabled

VVSOUT disabled

17, 18,

22, 27 IS_Poll

IS_Poll = IP + IVSINT + IEXT

IS_Poll = IP + IEXT

IS_Poll = IP

9.16 Current in TX mode on

pin VS1 and VS2

VVS1 = VVS2 ≤3V

IVSOUT = 0

Pout = 5 dBm/10 dBm

315 MHz/5 dBm

315 MHz/10 dBm

345 MHz/5 dBm

345 MHz/10 dBm

433.92 MHz/5 dBm

433.92 MHz/10 dBm

868.3 MHz/5 dBm

868.3 MHz/10 dBm

915 MHz/5 dBm

915 MHz/10 dBm

17, 18 ITX_VS1_VS2

10.3

15.7

10.4

15.8

10.5

15.8

11.2

17.3

11.8

19.3

13.4

20.5

13.5

20.6

13.5

20.5

14.5

22.5

15.3

25.1

mA B

9.17 Supply current

TX mode

CLK enabled

VVSOUT enabled

CLK disabled

VVSOUT enabled

17, 18,

22, 27 IS_TX

IS_TX = ITX_VS1, 2 + IVSINT + IEXT

IS_TX = ITX_VS1, 2 + IEXT

13. Electrical Characteristics: 1 Li Battery Application (3V) (Continued)

All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V. Application according to Figure 2-1 on page 7.

fRF = 315 MHz/345 MHz/433.92 MHz/868.3 MHz/915 MHz unless otherwise specified

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. The voltage of VAUX may rise up to 2V. The current IVAUX may not exceed 100 µA.

IIDLE_VS1,2 TSLEEP IStartup_PLL_VS1,2 TStartup_PLL IRX_VS1,2 TStartup_Sig_Proc TBitcheck

+()×+×+×

TSleep TStartup_PLL TStartup_Sig_Proc TBitcheck

++ +

4841D–WIRE–10/07

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14. Electrical Characteristics: 2 Li Battery Application (6V)

All parameters refer to GND and are valid for Tamb = 25°C, VVS2 = 6.0V. Application according to Figure 2-3 on page 9

fRF =315MHz/345MHz/433.92MHz/868.3MHz/915 MHz unless otherwise specified

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

10 2 Li Battery Application (6V)

10.1 Supported voltage

range

2 Li battery

application (6V) 17 VVS2 4.4 6.6 V A

10.2 Power supply output

voltage

2 Li battery

application (6V)

VVS2 ≥ 4.4V

VAUX open(1)

IVSOUT ≤13.5 mA

(3.3V regulator mode,

V_REG1, see Figure

5-1 on page 30)

22 VVSOUT 3.0 3.5 V A

10.3

Supply voltage for

microcontroller

interface

27 VVSINT 2.4 5.25 V A

10.4 Threshold hysteresis VThres_2 – VThres_1 22 ∆VThres 60 80 100 mV B

10.5

Reset threshold

voltage at pin VSOUT

(N_RESET)

22 VThres_1 2.18 2.3 2.42 V A

10.6

Reset threshold

voltage at pin VSOUT

(Low_Batt)

22 VThres_2 2.26 2.38 2.5 V A

10.7 Supply current

OFF mode

VVS2 ≤6.6V

VVSINT = 0V

17,

22, 27 IS_OFF 10 350 nA A

10.8 Current in IDLE mode

on pin VS2

VVS2 ≤6V

IVSOUT = 0

CLK enabled

VVSOUT enabled

CLK disabled

VVSOUT enabled

VVSOUT disabled

17 IIDLE_VS2 410

348

309

560

490

430

µA

10.9 Supply current IDLE

mode

17,

22, 27 IS_IDLE IS_IDLE = IIDLE_VS2 + IVSINT + IEXT

10.10 Current in RX mode

on pin VS2 IVSOUT = 0 17 IRX_VS2 10.8 14.5 mA B

10.11 Supply current

RX mode

CLK enabled

VVSOUT enabled

17,

22, 27 IS_RX IS_RX = IRX_VS2 + IVSINT + IEXT

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. The voltage of VAUX may rise up to 2 V. The current IVAUX may not exceed 100 µA.

VS2

IDLE_VS2

RX_VS2

Startup_PLL_VS2

TX_VS2

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ATA5423/ATA5425/ATA5428/ATA5429

10.12 Current during

TStartup_PLL on pin VS2 IVSOUT = 0 17 IStartup_PLL_VS2 9.1 12 mA C

10.13

Current in

RX polling mode on

on pin VS2

10.14 Supply current

RX polling mode

CLK enabled

VVSOUT enabled

CLK disabled

VVSOUT enabled

VVSOUT disabled

17,

22, 27 IS_Poll

IS_Poll = IP + IVSINT + IEXT

IS_Poll = IP + IEXT

IS_Poll = IP

10.15 Current in TX mode

on pin VS2

IVSOUT = 0

Pout = 5 dBm/10 dBm

315 MHz/5 dBm

315 MHz/10 dBm

345 MHz/5 dBm

345 MHz/10 dBm

433.92 MHz/5 dBm

433.92 MHz/10 dBm

868.3 MHz/5 dBm

868.3 MHz/10 dBm

915 MHz/5 dBm

915 MHz/10 dBm

17, 19 ITX_VS2

10.7

16.2

10.8

16.3

10.9

16.3

11.6

17.8

12.3

20.0

13.9

21.0

14.0

21.2

14.0

21.0

15.0

23.0

16.0

26.0

mA B

10.16 Supply current

TX mode

CLK enabled

VVSOUT enabled

CLK disabled

VVSOUT enabled

17,

22, 27 IS_TX

IS_TX = ITX_VS2 + IVSINT + IEXT

IS_TX = ITX_VS2 + IEXT

14. Electrical Characteristics: 2 Li Battery Application (6V) (Continued)

All parameters refer to GND and are valid for Tamb = 25°C, VVS2 = 6.0V. Application according to Figure 2-3 on page 9

fRF =315MHz/345MHz/433.92MHz/868.3MHz/915 MHz unless otherwise specified

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. The voltage of VAUX may rise up to 2 V. The current IVAUX may not exceed 100 µA.

IIDLE_VS2 TSLEEP IStartup_PLL_VS2 TStartup_PLL IRX_VS2 TStartup_Sig_Proc TBitcheck

+()×+×+×

TSleep TStartup_PLL TStartup_Sig_Proc TBitcheck

++ +

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

15. Electrical Characteristics: Base-station Application (5V)

All parameters refer to GND and are valid for Tamb = 25°C, VVS2 = 5.0V. Application according to Figure 2.2 on page 8

fRF =315MHz/345MHz/433.92MHz/868.3MHz/915 MHz unless otherwise specified.

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

11 Base-station Application (5V)

11.1 Supported voltage

range

Base-station

application (5V)

17,

19, 27 VVS2, VAUX 4.75 5.25 V A

11.2 Power supply output

voltage

Base-station

application (5V)

VVS2 = VVAUX

IVSOUT ≤13.5 mA

(3.25V regulator

mode, V_REG2, see

Figure 5-1 on page

30)

22 VVSOUT 3.0 3.5 V A

11.3

Supply voltage for

microcontroller-

interface

27 VVSINT 2.4 5.25 V A

11.4 Threshold hysteresis VThres_2 – VThres_1 22 ∆VThres 60 80 100 mV B

11.5

Reset threshold

voltage at pin VSOUT

(N_RESET)

22 VThres_1 2.18 2.3 2.42 V A

11.6

Reset threshold

voltage at pin VSOUT

(Low_Batt)

22 VThres_2 2.26 2.38 2.5 V A

11.7 Current in IDLE mode

on pin VS2 and VAUX

IVSOUT = 0

CLK enabled

VVSOUT enabled

CLK disabled

VVSOUT enabled

VVSOUT disabled

17, 19 IIDLE_VS2_VAUX

444

380

310

580

500

400

µA B

11.8 Supply current in

IDLE mode

17,

19,

22, 27

IS_IDLE IS_IDLE = IIDLE_VS2_VAUX + IVSINT + IEXT

11.9 Current in RX mode

on pin VS2 and VAUX IVSOUT = 0 17, 19 IRX_VS2_VAUX 10.8 14.5 mA B

11.10 Supply current in RX

mode

CLK enabled VVSOUT

enabled

17,

19,

22, 27

IS_RX IS_RX = IRX_VS2_VAUX + IVSINT + IEXT

11.11

Current during

TStartup_PLL on pin VS2

and VAUX

IVSOUT = 0 17, 19 IStartup_PLL_VS2,

VAUX 9.1 12 mA C

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

VAUX

VS2

IDLE_VS2,VAUX

or I

RX_VS2,VAUX

or I

Startup_PLL_VS2,VAUX

or I

TX_VS2,VAUX

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

11.12

Current in RX_Polling_Mode on pin VS2 and VAUX

11.13 Supply current in RX

polling mode

CLK enabled

VVSOUT enabled

CLK disabled

VVSOUT enabled

VVSOUT disabled

17,

19,

22, 27

IS_Poll

IS_Poll = IP + IVSINT + IEXT

IS_Poll = IP + IEXT

IS_Poll = IP

11.14 Current in TX mode

on pin VS2 and VAUX

IVSOUT = 0

Pout = 5dBm/10dBm

315 MHz/5dBm

315 MHz/10dBm

345 MHz/5dBm

345 MHz/10dBm

433.92 MHz/5dBm

433.92 MHz/10dBm

868.3 MHz/10dBm

915 MHz/5dBm

915 MHz/10dBm

17, 19 ITX_VS2_VAUX

10.7

16.2

10.8

16.3

10.9

16.3

11.6

17.8

12.3

20.0

13.9

21.0

14.0

21.2

14.0

21.0

15.0

23.0

16.0

26.0

mA B

11.15 Supply current in

TX mode

CLK enabled

VVSOUT enabled

CLK disabled

VVSOUT enabled

17,

19,

22, 27

IS_TX

IS_TX = ITX_VS2_VAUX + IVSINT + IEXT

IS_TX = ITX_VS2_VAUX + IEXT

15. Electrical Characteristics: Base-station Application (5V) (Continued)

All parameters refer to GND and are valid for Tamb = 25°C, VVS2 = 5.0V. Application according to Figure 2.2 on page 8

fRF =315MHz/345MHz/433.92MHz/868.3MHz/915 MHz unless otherwise specified.

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

IIDLE_VS2,VAUX TSLEEP IStartup_PLL_VS2,VAUX TStartup_PLL IRX_VS2,VAUX TStartup_Sig_Proc TBitcheck

+()×+×+×

TSleep TStartup_PLL TStartup_Sig_Proc TBitcheck

++ +

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

16. Digital Timing Characteristics

All parameters refer to GND and are valid for Tamb =25°C. V

VS1 =V

S2 = 3.0V (1 Li battery application (3V)), VVS2 = 6.0V (2 Li battery

application (6V)) and VVS2 =5.0V (Base-station Application(5V)) unless otherwise specified.

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

12 Basic Clock Cycle of the Digital Circuitry

12.1 Basic clock cycle TDCLK 16/fXTO 16/fXTO µs A

12.2 Extended basic clock

cycle

XLIM = 0

BR_Range_0

BR_Range_1

BR_Range_2

BR_Range_3

XLIM = 1

BR_Range_0

BR_Range_1

BR_Range_2

BR_Range_3

TXDCLK

× TDCLK

µs A

13 RX Mode/RX Polling Mode

13.1 Sleep time

Sleep and XSleep are

defined in control

TSleep

Sleep ×

XSleep ×

1024 ×

TDCLK

Sleep ×

XSleep ×

1024 ×

TDCLK

ms A

13.2 Start-up PLL RX mode from IDLE mode TStartup_PLL 798.5 ×

TDCLK

798.5 ×

TDCLK µs A

13.3 Start-up signal

processing

BR_Range_0

BR_Range_1

BR_Range_2

BR_Range_3

TStartup_Sig_Proc

882

498

306

210

× TDCLK

882

498

306

210

× TDCLK

13.4 Time for bit check

Average time during

polling. No RF signal

applied.

fSignal = 1/(2 × tee)

Signal data rate

Manchester

(Lim_min and Lim_max

up to ±50% of tee, see

Figure 9-4 on page 56)

Bit-check time for a valid

input signal fSignal

NBit-check = 0

NBit-check = 3

NBit-check = 6

NBit-check = 9

TBit_check

3/fSignal

6/fSignal

9/fSignal

1/fSignal

3.5/fSignal

6.5/fSignal

9.5/fSignal

ms C

13.5 Bit-rate range

BR_Range =

BR_Range0

BR_Range1

BR_Range2

BR_Range3

BR_Range

1.0

2.0

4.0

8.0

2.5

5.0

10.0

20.0

Kbit/s A

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

13.6

Minimum time period

between edges at pin

SDO_TMDO in RX

transparent mode

XLIM = 0

BR_Range_0

BR_Range_1

BR_Range_2

BR_Range_3

XLIM = 1

BR_Range_0

BR_Range_1

BR_Range_2

BR_Range_3

31 TDATA_min 10 ×

TXDCLK µs A

13.7

Edge-to-edge time

period of the data signal

for full sensitivity in RX

mode

BR_Range_0

BR_Range_1

BR_Range_2

BR_Range_3

TDATA

200

100

500

250

125

62.5

µs B

14 TX Mode

14.1 Start-up time From IDLE mode TStartup 331.5

× TDCLK

331.5

× TDCLK µs A

15 Configuration of the Transceiver with 4-wire Serial Interface

15.1 CS set-up time to rising

edge of SCK 33, 35 TCS_setup 1.5 ×

TDCLK µs A

15.2 SCK cycle time 33 TCycle 2µsA

15.3 SDI_TMDI set-up time

to rising edge of SCK 32, 33 TSetup 250 ns C

15.4 SDI_TMDI hold time

from rising edge of SCK 32, 33 THold 250 ns C

15.5

SDO_TMDO enable

time from rising edge of

31, 35 TOut_enable 250 ns C

15.6

SDO_TMDO output

delay from falling edge

of SCK

CL = 10 pF 31, 35 TOut_delay 250 ns C

15.7

SDO_TMDO disable

time from falling edge of

31, 33 TOut_disable 250 ns C

15.8 CS disable time period 35 TCS_disable 1.5 ×

TDCLK µs A

15.9 Time period SCK low to

CS high 33, 35 TSCK_setup1 250 ns C

15.10 Time period SCK low to

CS low 33, 35 TSCK_setup2 250 ns C

15.11 Time period CS low to

SCK high 33, 35 TSCK_hold 250 ns C

16. Digital Timing Characteristics (Continued)

All parameters refer to GND and are valid for Tamb =25°C. V

VS1 =V

S2 = 3.0V (1 Li battery application (3V)), VVS2 = 6.0V (2 Li battery

application (6V)) and VVS2 =5.0V (Base-station Application(5V)) unless otherwise specified.

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

16 Start Time Push Button Tn and PWR_ON

Timing of Wake-up via PWR_ON or Tn

16.1

PWR_ON high to

positive edge on pin

IRQ (see Figure 7-4 on

page 46)

From OFF mode to IDLE

mode, applications

according to Figure 2-1

on page 7, Figure 2.2 on

page 8 and Figure 2-3

on page 9

XTAL:

Cm < 14 fF (typ. 5 fF)

C0 < 2.2 pF (typ. 1.8 pF)

Rm ≤ 120Ω (typ. 15Ω)

1 Li battery application

(3V)

C1 = C2 = 68 nF

C3 = C4 = 68 nF

C5 = 10 nF

2 Li battery application

(6V)

C1 = C4 = 68 nF

C2 = C3 = 2.2 µF

C5 = 10 nF

Base-station Application

(5V)

C1 = C3 = C4 = 68 nF

C2 = C12 = 2.2 µF

C5 = 10 nF

29, 40 TPWR_ON_IRQ_1 0.3

0.45

0.8

1.3

16. Digital Timing Characteristics (Continued)

All parameters refer to GND and are valid for Tamb =25°C. V

VS1 =V

S2 = 3.0V (1 Li battery application (3V)), VVS2 = 6.0V (2 Li battery

application (6V)) and VVS2 =5.0V (Base-station Application(5V)) unless otherwise specified.

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

94
4841D–WIRE–10/07
ATA5423/ATA5425/ATA5428/ATA5429
16.2
PWR_ON high to 
positive edge on pin 
IRQ (see Figure 7-4 on 
page 46)
Every mode except OFF 
mode 29, 40 TPWR_ON_IRQ_2 2 × 
TDCLK µs A
16.3
Tn low to positive edge 
on pin IRQ (see Figure 
7-2 on page 44)
From OFF mode to IDLE 
mode, applications 
according to Figure 2-1 
on page 7, Figure 2.2 on 
page 8 and Figure 2-3 
on page 9
XTAL: 
Cm < 14 fF (typ 5 fF)
C0 < 2.2  pF (typ 1.8 pF)
Rm ≤120Ω (typ 15Ω)
1 Li battery application 
(3V)
C1 = C2 = 68 nF 
C3 = C4 = 68 nF
C5 = 10 nF
2 Li battery application 
(6V)
C1 = C4 = 68 nF 
C2 = C3 = 2.2 µF 
C5 = 10 nF
Base-station Application 
(5V)
C1 = C3 = C4 = 68 nF 
C2 = C12 = 2.2 µF 
C5 = 10 nF
29, 41, 
42, 43, 
44, 45
TTn_IRQ 0.3
0.45
0.45
0.8
1.3
1.3
ms
ms
ms
B
16.4 Push button debounce 
time
Every mode except OFF 
mode
29, 41, 
42, 43, 
44, 45
TDebounce 8195
× TDCLK
8195
× TDCLK µs A
16. Digital Timing Characteristics (Continued)
All parameters refer to GND and are valid for Tamb =25°C. V
VS1 =V
S2 = 3.0V (1 Li battery application (3V)), VVS2 = 6.0V (2 Li battery 
application (6V)) and VVS2 =5.0V (Base-station Application(5V)) unless otherwise specified.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

17. Digital Port Characteristics

All parameters refer to GND and are valid for Tamb = –40°C to +85 °C, VVS1 = VS2 = 2.4V to 3.6V (1 Li battery application (3V)) and

VVS2 = 4.4V to 6.6 V (2 Li battery application (6V)) and VVS2 = 4.75V to 5.25V (Base-station Application (5V)). Typical values at

VVS1 =V

VS2 = 3V and Tamb = 25°C unless otherwise specified.

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

17 Digital Ports

17.1

CS input

Low level input voltage VVSINT = 2.4V to 5.25V 35 VIl 0.2 ×

VVSINT VA

High level input voltage VVSINT = 2.4V to 5.25V 35 VIh 0.8 ×

VVSINT VVSINT VA

17.2

SCK input

Low level input voltage VVSINT = 2.4V to 5.25V 33 VIl 0.2 ×

VVSINT VA

High level input voltage VVSINT = 2.4V to 5.25V 33 VIh 0.8 ×

VVSINT VVSINT VA

17.3

SDI_TMDI input

Low level input voltage VVSINT = 2.4V to 5.25V 32 VIl 0.2 ×

VVSINT VA

High level input voltage VVSINT = 2.4V to 5.25V 32 VIh 0.8 ×

VVSINT VVSINT VA

17.4 TEST1 input

TEST1 input must

always be directly

connected to GND

20 0 0 V

17.5 TEST2 input

TEST2 input must

always be direct

connected to GND

23 0 0 V

17.6

PWR_ON input

Low level input voltage

Internal pull-down with

series connection of

40 kΩ ±20% resistor

and diode

40 VIl 0.4 V A

High level input

voltage(1)

Internal pull-down with

series connection of

40 kΩ ±20% resistor

and diode

40 VIh 0.8

× VVS2 VA

17.7

Tn input

Low level input voltage

Internal pull-up resistor

of 50 kΩ ±20%

41, 42,

43, 44,

VIl 0.2

× VVS2 VA

High level input

voltage(1) Internal pull-up resistor

of 50 kΩ ±20%

41, 42,

43, 44,

VIh × VVS2

–0.5V VA

17.8

433_N868 input

Low level input voltage 6V

Il 0.25 V A

Input current low 6 IIl –5µA A

High level input voltage 6 VIh 1.7 AVCC V A

Input current high 6 IIh 1µAA

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. If a logic high level is applied to this pin, a minimum serial impedance of 100Ω must be ensured for proper operation over full

temperature range.

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

17.9

PWR_H input

Low level input voltage 9V

Il 0.25 V A

Input current low 9 IIl –5µA A

High level input voltage 9 VIh 1.7 AVCC V A

Input current high 9 IIh 1µAA

17.10

SDO_TMDO output

Saturation voltage low

VVSINT = 2.4V to 5.25V

ISDO_TMDO = 250 µA 31 Vol 0.15 0.4 V B

Saturation voltage high VVSINT = 2.4V to 5.25V

ISDO_TMDO = –250 µA 31 Voh VVSINT –

0.4

VVSINT –

0.15 VB

17.11

IRQ output

Saturation voltage low

VVSINT = 2.4V to 5.25V

IIRQ = 250 µA 29 Vol 0.15 0.4 V B

Saturation voltage high VVSINT = 2.4V to 5.25V

IIRQ = –250 µA 29 Voh VVSINT –

0.4

VVSINT –

0.15 VB

17.12

CLK output

Saturation voltage low

VVSINT = 2.4V to 5.25V

ICLK = 100 µA

internal series resistor

of 1 kΩ for spurious

emission reduction in

PLL

30 Vol 0.15 0.4 V B

Saturation voltage high

VVSINT = 2.4V to 5.25V

ICLK = –100 µA

internal series resistor

of 1 kΩ for spurious

emission reduction in

PLL

30 Voh VVSINT –

0.4

VVSINT –

0.15 VB

17.13

N_RESET output

Saturation voltage low

VVSINT = 2.4V to 5.25V

IN_RESET = 250 µA 28 Vol 0.15 0.4 V B

Saturation voltage high VVSINT = 2.4V to 5.25V

IN_RESET = –250 µA 28 Voh VVSINT –

0.4

VVSINT –

0.15 VB

17.14

RX_ACTIVE output

Saturation voltage low

VVSINT = 2.4V to 5.25V

IRX_ACTIVE = 25 µA 46 Vol 0.25 0.4 V B

Saturation voltage high VVSINT = 2.4V to 5.25V

IRX_ACTIVE = –1500 µA 46 Voh VAVCC

–0.5

VAVCC

–0.15 VB

17.15 DEM_OUT output

Saturation voltage low

Open drain output

IDEM_OUT = 250 µA 34 Vol 0.15 0.4 V B

17. Digital Port Characteristics (Continued)

All parameters refer to GND and are valid for Tamb = –40°C to +85 °C, VVS1 = VS2 = 2.4V to 3.6V (1 Li battery application (3V)) and

VVS2 = 4.4V to 6.6 V (2 Li battery application (6V)) and VVS2 = 4.75V to 5.25V (Base-station Application (5V)). Typical values at

VVS1 =V

VS2 = 3V and Tamb = 25°C unless otherwise specified.

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. If a logic high level is applied to this pin, a minimum serial impedance of 100Ω must be ensured for proper operation over full

temperature range.

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

19. Package Information

18. Ordering Information

Extended Type Number Package Remarks Delivery

ATA5423-PLQW QFN48 7 mm × 7 mm Taped and reeled + Dry pack

ATA5425-PLQW QFN48 7 mm × 7 mm Taped and reeled + Dry pack

ATA5428-PLQW QFN48 7 mm × 7 mm Taped and reeled + Dry pack

ATA5429-PLQW QFN48 7 mm × 7 mm Taped and reeled + Dry pack

ATA5423-PLSW QFN48 7 mm × 7 mm Tubes + Dry pack

ATA5425-PLSW QFN48 7 mm × 7 mm Tubes + Dry pack

ATA5428-PLSW QFN48 7 mm × 7 mm Tubes + Dry pack

ATA5429-PLSW QFN48 7 mm × 7 mm Tubes + Dry pack

Note: W = RoHS compliant

0.4±0.1

5.5

5.1

0.5 nom.

4837

1324

specifications

according to DIN

technical drawings

Issue: 1; 14.01.03

Drawing-No.: 6.543-5089.02-4

Package: QFN 48 - 7 x 7

Exposed pad 5.1 x 5.1

Dimensions in mm

Not indicated tolerances ± 0.05

0.23

0.05-0.05

1 max.

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

20. Revision History

Please note that the following page numbers referred to in this section refer to the specific revision

mentioned, not to this document.

Revision No. History

4841D-WIRE-10/07 • Put datasheet in a new template

4841C-WIRE-05/06

• Put datasheet in a new template

• kBaud replaced through Kbit/s

• Baud replaced through bit

• Table 9-6 “Interrupt Handling” on page 65 changed

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

21. Table of Contents

Features ..................................................................................................... 1

Applications .............................................................................................. 2

Benefits...................................................................................................... 2

1 General Description ................................................................................. 3

2 Application Circuits ................................................................................. 7

3 RF Transceiver ....................................................................................... 10

4 XTO .......................................................................................................... 25

5 Power Supply ......................................................................................... 30

6 Microcontroller Interface ....................................................................... 36

7 Digital Control Logic .............................................................................. 36

8 Transceiver Configuration .................................................................... 49

9 Operation Modes .................................................................................... 52

10 Absolute Maximum Ratings .................................................................. 66

11 Thermal Resistance ............................................................................... 66

12 Electrical Characteristics: General ...................................................... 67

13 Electrical Characteristics: 1 Li Battery Application (3V) .................... 85

14 Electrical Characteristics: 2 Li Battery Application (6V) .................... 87

15 Electrical Characteristics: Base-station Application (5V) .................. 89

16 Digital Timing Characteristics .............................................................. 91

17 Digital Port Characteristics ................................................................... 95

18 Ordering Information ............................................................................. 97

19 Package Information ............................................................................. 97

20 Revision History ..................................................................................... 98

4841D–WIRE–10/07

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