DCDC Converter Single-input Voltage, 30 A Buck Regulators with PVID FEATURES OptiMOSTM IPOL IR38263 DESCRIPTION Internal LDO allows single 16 V operation Output Voltage Range: 0.5V to 0.875*PVin 0.5% accurate Reference Voltage Enhanced line/load regulation with Feedforward Frequency programmable by PMBusTM up to 1.5 MHz Enable input with Voltage Monitoring Capability Remote Sense Amplifier with True Differential Voltage Sensing 3 pins (PVID) to program output voltage Fast mode I2C and 400 kHz PMBusTM interface for programming, sequencing and margining output voltage, and for monitoring input voltage, output voltage, output current and temperature. PMBusTM configurable fault thresholds for input UVLO, output OVP, OCP and thermal shutdown. Thermally compensated pulse-by-pulse current limit and Hiccup Mode Over Current Protection Dedicated output voltage sensing for power good indication and overvoltage protection which remains active even when Enable is low. Enhanced Pre-Bias Start up Integrated MOSFET drivers and Bootstrap diode Operating junction temp: -40oC<Tj<125oC Thermal Shut Down Post Package trimmed rising edge dead-time PMBusTM Programmable Power Good Output Small Size 5 mmx 7mm PQFN Pb-Free (RoHS Compliant) External resistor allows setting up to 16 PMBusTM addresses This family of OptiMOSTM IPOL devices offers easy-to-use, fully integrated and highly efficient DC/DC regulators with PVID and I2C/PMBusTM interface. The on-chip PWM controller and co-packaged low duty cycle optimized MOSFETs make these devices a space-efficient solution, providing accurate power delivery for low output voltage and high current applications that require a parallel VID interface. These versatile devices offer programmability of switching frequency, output voltage, and fault/warning thresholds and fault responses while operating over a wide input range. Thus, they offer flexibility as well as system level security in event of fault conditions. The switching frequency is programmable from 150 kHz to 1.5 MHz for an optimum solution. The on-chip sensors and ADC along with the PVID and PMBusTM interfaces make it easy to monitor and report input voltage, output voltage, output current and temperature. APPLICATIONS Intel(R) VR13 and VR12.5 based systems Servers and High End Desktop CPU VRs for noncore applications Telecom and storage applications BASIC APPLICATION 5.5V <Vin<16V For applications in which Pvin>14V, a 1 ohm resistor is required in series with the boot capacitor. P1V8 Enable Vin PVin Vcc/ LDO_out Boot Optional placeholder for boot resistor. Default should be 0 ohm For PVin >14V, a 1 ohm resistor is required Vo SW Vsns RS+ PGood PGood RS- VIDSEL0 RSo VIDSEL1 SCL ADDR SAlert Fb VIDSEL2 SDA 3 bit PVID Comp PGnd LGnd i2C/ PMBus lines; pull up to 3.3V Placeholder for capacitor Figure 1: Typical application circuit 1 Rev 3.4 Sept 12, 2018 IR38263 PIN DIAGRAM Figure 2: IR38263 Package Top View 5mm X 7mm PQFN ORDERING INFORMATION Package PQFN 2 Tape and Reel Qty 4000 Rev 3.4 Part Number IR38263MTRPbF Description 30A Buck Regulator with PVID and PMBusTM for PVNN Sept 12, 2018 IR38263 FUNCTIONAL BLOCK DIAGRAM VCC Vin P1V8 LDO VLDOref LDO LGND - OT_Fault + VCC UVcc UVcc BOOT OC_Fault FAULT CONTROL UVEN PVIN Fault COMP Fault VDAC2 + E/A - HDrv PVin HDin FB OV_Fault FCCM GATE DRIVE LOGIC SW VCC Enable OT_Fault UV_EN OC_Fault LDrv LDin PGND PGOOD_OFFSET_DAC VIN_OFF_DAC VIN_ON_DAC IOUT_OC_FAULT_DAC VIN_UV_DAC Rso VIN_OV_DAC VDAC2 OVin VDAC1 UVin OFF OC Fault VOUT OV PGood VOUT_OV_OFFSET_DAC CONTROL AND FAULT LOGIC RSRS+ ISense SDA SVID Interface, SMBus Interface, Logic, Command and Status registers SCL TMON Current Sense Temperature Sense SALERT# VIDSEL0 VIDSEL1 VIDSEL2 Vsns P1V8 ADDR UVP1V8 Vcc Vsns Figure 3: Simplified Block Diagram for IR38263 3 Rev 3.4 Sept 12, 2018 IR38263 PIN DESCRIPTIONS PIN # PIN NAME 1 PVIN 2 Boot 3 ENABLE 4 ADDR A resistor should be connected from this pin to LGnd to set the PMBusTM address offset for the device. It is recommended to provide a placement for a 10 nF capacitor in parallel with the offset resistor. 5 Vsns 6 FB 7 COMP 8 RSo Sense pin for OVP and PGood. Typically connected to a local Vout capacitor at the output of the inductor. Inverting input to the error amplifier. This pin is connected directly to the output of the regulator or to the output of the remote sense amplifier, via resistor divider to set the output voltage and provide feedback to the error amplifier. Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to FB to provide loop compensation. Remote Sense Amplifier Output. When the remote sense amplifier is used, this is connected to the feedback compensation network 9 RS- Remote Sense Amplifier input. Connect to ground at the load. 10 RS+ Remote Sense Amplifier input. Connect to output at the load. 11 PGood 12,25 PGND 13 LGND 14 VIDSEL0 15 VIDSEL1 16 VIDSEL2 17 SAlert# 18 SDA 4 PIN DESCRIPTION Input voltage for power stage. Bypass capacitors between PVin and PGND should be connected very close to this pin and PGND. Typical applications use four22 uF input capacitors and a low ESR, low ESL 0.1uF decoupling capacitor in a 0603/0402 case size. A 3.3nF capacitor may also be used in parallel with these input capacitors to reduce ringing on the Sw node. Supply voltage for high side driver. A 0.1uF capacitor should be connected from this pin to the Sw pin. It is recommended to provide a placement for a 0 ohm resistor in series with the capacitor. For applications in which PVin>14V, a 1 ohm resistor is required in series with boot capacitor. Enable pin to turn on and off the IC Power Good status pin. Output is open drain. Connect a pull up resistor from this pin to VCC. If the power good voltage before VCC UVLO needs to be limited to < 500 mV, use a 49.9K pullup, otherwise a 4.99K pullup will suffice. Power ground. This pin should be connected to the system's power ground plane. Bypass capacitors between PVin and PGND should be connected very close to PVIN pin (pin 1) and this pin. Signal ground for internal reference and control circuitry. This should be connected to the PGnd plane at a quiet location using a single point connection. Used to select VID voltage registers. This is the LSB of the 3 bit PVID code that is internally decoded to select the register containing the target voltage. Only connect to Vcc via a 4.99K resistor and do not use a direct connection. Do not exceed 6V. Used to select VID voltage registers. Only connect to Vcc via a 4.99K resistor and do not use a direct connection. Do not exceed 6V. Used to select VID voltage registers. This is the MSB of the 3 bit PVID code that is internally decoded to select the register containing the target voltage. Only connect to Vcc via a 4.99K resistor and do not use a direct connection. Do not exceed 6V. SMBus Alert line; open drain SMBALERT# pin. This should be pulled up to 3.3V-5V with a 1K-5K resistor. SMBus data serial input/output line. This should be pulled up to 3.3V-5V with a 1K-5K resistor Rev 3.4 Sept 12, 2018 IR38263 PIN # PIN NAME 19 SCL 20 P1V8 21 Vin 22 VCC 23,26 NC NC 24 SW Switch node. This pin is connected to the output inductor. 5 PIN DESCRIPTION SMBus clock line. This should be pulled up to 3.3V-5V with a 1K-5K resistor This is the supply for the digital circuits; bypass with a 10uF capacitor to PGnd. A 2.2uF capacitor is valid however a10uF capacitor is recommended. Input Voltage for LDO. A 1 uF capacitor is placed from this pin to PGnd. If the internal bias LDO is used, tie this pin to PVin. If an external bias voltage (typically 5V) is available for Vcc, tie the Vin pin to Vcc. Bias Voltage for IC and driver section, output of LDO. Add 10 uF bypass cap from this pin to PGnd. Rev 3.4 Sept 12, 2018 IR38263 ABSOLUTE MAXIMUM RATINGS Stresses beyond these listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. PVin, Vin -0.3V to 25V VCC -0.3V to 6V P1V8 -0.3V to 2 V SW -0.3V to 25V (DC), -4V to 25V (AC, 100ns) BOOT -0.3V to 31V BOOT to SW -0.3V to 6V (DC) (Note 1), -0.3V to 6.5V (AC, 100ns) PGD, other Input/output pins -0.3V to 6V (Note 1) PGND to GND, RS- to GND -0.3V to + 0.3V THERMAL INFORMATION Junction to Ambient Thermal Resistance JA 11.1 C/W (Note 2) Junction to case top Thermal Resistance JC(top) 18.9 C/W (Note 3) Junction to PCB Thermal Resistance JB 4.16 C/W (Note 4) Junction to case top parameter JT (top) 0.32 C/W (Note 2) Storage Temperature Range -55C to 150C Junction Temperature Range -40C to 150C (Voltages referenced to GND unless otherwise specified) Note 1: Must not exceed 6V. Note 2: Value obtained via thermal simulation under natural convention on a PVNN, IR38263 demo board. 10 layer, 7"x5.5"x0.072" PCB with 1.5 oz copper at the top and bottom layer. Inner layers 2, 3, 8 and 9 have 1 oz copper and layers 4,5,6,7 have 2 oz copper. Ta = 25C was used for the simulation. Note 3: PCB from note 2 and package is considered in thermal simulation with Ta=25 C. Pin 12 is considered. Note 4: Only package is considered. Simulation is used with a cold plate that fixes top of package at Ta=25 C. 6 Rev 3.4 Sept 12, 2018 IR38263 ELECTRICAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS SYMBOL DEFINITION MIN MAX UNITS PVin Input Bus Voltage 1.5 16* V Vin LDO supply voltage 5.3 16 LDO output/Bias supply voltage 4.5 5.5 High Side driver gate voltage 4.5 5.5 VO Output Voltage 0.5 0.875*PVin IO Output Current 0 30 A Fs Switching Frequency 150 1500 kHz TJ Junction Temperature -40 125 C VCC Boot to SW * SW Node must not exceed 25V PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT MOSFET Rds(on) Top Switch Rds(on)_Top VBoot - VSW = 5V, ID = 30A, Tj = 25C 2.2 Bottom Switch Rds(on)_Bot Vcc =5V, ID = 30A, Tj = 25C 0.78 m Reference Voltage Accuracy 00C<Tj<850C Accuracy -400C<Tj<1250C 1.25V<VFB<2.555V VOUT_SCALE_LOOP=1; -1 +1 0.75V<VFB<1.25V VOUT_SCALE_LOOP=1; -0.75 +0.75 0.45V<VFB<0.75V VOUT_SCALE_LOOP=1; -0.5 +0.5 1.25V<VFB<2.555V VOUT_SCALE_LOOP=1; -1.6 +1.6 0.75V<VFB<1.25V VOUT_SCALE_LOOP=1; -1.0 +1.0 % 0.45V<VFB<0.75V VOUT_SCALE_LOOP=1; -2.0 +2.0 % % % % Supply Current PVin range (using external Vcc=5V) Vin range (using internal LDO) 7 Rev 3.4 Fsw=600kHz 1.516 V 5.316 V Sept 12, 2018 IR38263 PARAMETER SYMBOL CONDITIONS MIN MAX UNIT 5.0 5.5 V Enable low, No Switching, Vin=16V, low power mode enabled 2.7 4 mA Enable high, Fs = 600kHz, Vin=16V 39 50 mA Enable low, No Switching, Vcc=5.5V, low power mode enabled 2.7 5 mA Enable high, Fs = 600kHz, Vcc=5.5V 39 50 mA Fsw=1.5MHz Vin range (when Vin=Vcc) 5.516 4.5 Vin Supply Current (Standby) (internal Vcc) Iin(Standby) Vin Supply Current (Dyn)(internal Vcc) Iin(Dyn) VCC Supply Current (Standby)(external Vcc) Icc(Standby) VCC Supply Current (Dyn)(external Vcc) Icc(Dyn) TYP Under Voltage Lockout VCC - Start - Threshold VCC_UVLO_Start VCC Rising Trip Level 4.0 4.2 4.4 VCC - Stop - Threshold VCC_UVLO_Stop VCC Falling Trip Level 3.7 3.9 4.1 Enable - Start - Threshold Enable_UVLO_Start Supply ramping up 0.55 0.6 0.65 Enable - Stop - Threshold Enable_UVLO_Stop Supply ramping down Enable leakage current Ien Enable=5.5V Vramp PVin=5V, D=Dmax, Note 2 0.71 PVin=12V, D=Dmax, Note 2 1.84 V V 0.35 0.4 0.45 1 uA Oscillator Ramp Amplitude Vp-p PVin=16V,D=Dmax, Note 2 2.46 Ramp Offset Ramp (os) Note 2 0.22 Min Pulse Width Dmin (ctrl) Note 2 35 50 ns Note 2 Fs=1.5MHz 100 150 ns 87.5 89 % +0.5 A Fixed Off Time Dmax Max Duty Cycle Fs=400kHz 86 V Error Amplifier Input Bias Current IFb(E/A) -0.5 Sink Current Isink(E/A) 0.6 1.1 1.8 mA Source Current Isource(E/A) 8 13 25 mA Slew Rate SR Note 2 7 12 20 V/s Gain-Bandwidth Product GBWP Note 2 20 30 40 MHz DC Gain Gain Note 2 100 110 120 dB Maximum Voltage Vmax(E/A) 2.8 3.9 4.3 V Minimum Voltage Vmin(E/A) 100 mV 8 Rev 3.4 Sept 12, 2018 IR38263 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT 3 6.4 MHz 110 dB Remote Sense Differential Amplifier Unity Gain Bandwidth BW_RS Note 2 DC Gain Gain_RS Note 2 Offset Voltage 0.5V<RS+<2.555V, 4kOhm load 270C<Tj<850C -1.6 0.5V<RS+<2.555V, 4kOhm load -400C<Tj<1250C -3 3 V_RSO=1.5V, V_RSP=4V 11 16 0 1.6 mV Offset_RS Source Current Isource_RS Sink Current Isink_RS Slew Rate Slew_RS RS+ input impedance Rin_RS+ RS- input impedance Rin_RS- Maximum Voltage Vmax_RS Minimum Voltage Min_RS mA 0.4 1 2 mA 2 4 8 V/s 36 55 74 Kohm Note 2 36 55 74 Kohm V(VCC) - V(RS+) 0.5 1 1.5 V 4 20 mV 300 450 mV Note 2, Cload = 100pF Bootstrap Diode Forward Voltage I(Boot) = 40mA 150 Switch Node SW Leakage Current lsw SW = 0V, Enable = 0V Isw_En SW=0; Enable= 2V 1 A 18 Internal Regulator (VCC/LDO) VCC Output Voltage VCC dropout VCC_drop Short Circuit Current Ishort Internal Regulator (P1V8) Output Voltage P1V8 1.8V UVLO Start 1.8V UVLO Stop Vin(min) = 5.5V, Io=0mA, Cload = 10uF 4.8 5.15 5.4 Vin(min) = 5.5V, Io=70mA, Cload = 10uF 4.5 4.99 5.2 V Io=0-70mA, Cload = 10uF, Vin=5.1V 0.7 V 110 mA 1.795 1.83 1.905 V P1V8_UVLO_Start Vin(min) = 4.5V, Io = 0 1mA, Cload = 2.2uF 1.8V Rising Trip Level 1.66 1.72 1.78 V P1V8_UVLO_Stop 1.8V Falling Trip Level 1.59 1.63 1.68 V -4 -1 2 Adaptive On time Mode Zero-crossing comparator threshold ZC_Vth Zero-crossing comparator delay ZC_Tdly 9 Rev 3.4 8/Fs mV s Sept 12, 2018 IR38263 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT FAULTS Power Good Power Good High threshold Power_Good_High Power Good Low Threshold Power_Good_Low Power Good High Threshold Rising Delay TPDLY Vsns rising, Vsns > Power_Good_High Power Good Low Threshold Falling delay VPG_low_Dly Vsns falling, Vsns < Power_Good_Low PGood Voltage Low PG (voltage) Vsns rising, VOUT_SCALE_LOOP=1, Vout=0.5V, PMBusTM mode 0.45 V Vsns falling, VOUT_SCALE_LOOP=1, Vout=0.5V, PMBusTM mode 0.43 V 0 ms 150 175 IPGood = -5mA 200 us 0.5 V 0.63 V Over Voltage Protection (OVP) OVP Trip Threshold OVP (trip) Vsns rising, VOUT_SCALE_LOOP=1, Vout=0.5V 0.57 0.60 5 Vsns falling, VOUT_SCALE_LOOP=1, Vout=0.5V 20 30 OVP comparator Hysteresis OVP (hyst) OVP Fault Prop Delay OVP (delay) Vsns rising, VsnsOVP(trip)>200 mV ITRIP OC limit=40, VCC = 5.05V, Tj=250C 40 200 mV ns Over-Current Protection OC Trip Current OC limit=16A, VCC = 5.05V, Tj=250C OCset Current Temperature coefficient OCSET(temp) -400C to 1250C, VCC=5.05V, Note 2 Hiccup blanking time Tblk_Hiccup 36 40 44 A 12.5 16 19.5 A 5900 ppm/C Note 2 20 ms Thermal Shutdown Note 2 145 C Hysteresis Note 2 25 C Thermal Shutdown Input Over-Voltage Protection PVin overvoltage threshold PVinOV PVin overvoltage Hysteresis PVin ov hyst 22 23.7 25 2.4 V V MONITORING AND REPORTING I2C Bus Speed1 100 Iout & Vout filter 78 10 Rev 3.4 400 kHz Hz Sept 12, 2018 IR38263 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Iout & Vout Update rate 31.2 5 kHz Vin & Temperature filter 78 Hz Vin & Temperature update rate 31.2 5 kHz 1/256 V 0 V Output Voltage Reporting Resolution Lowest reported Vout Highest reported Vout NVout Note 2 Vomon_low Vsns=0V Vomon_high VOUT_SCALE_LOOP=1, Vsns=3.3V 3.3 V VOUT_SCALE_LOOP=0.5, Vsns=3.3V 6.6 V VOUT_SCALE_LOOP=0.25, Vsns=3.3V 13.2 V VOUT_SCALE_LOOP=0.125 , Vsns=3.3V 26.4 V 00C to 850C, 4.5V<Vcc<5.5V, 1V<Vsns 1.5V VOUT_SCALE_LOOP=1 +/0.6 00C to 850C, 4.5V<Vcc<5.5V, Vsns> 1.5V VOUT_SCALE_LOOP=1 +/-1 00C to 1250C, 4.5V<Vcc<5.5V, Vsns>0.9V VOUT_SCALE_LOOP=1 +/1.5 00C to 1250C, 4.5V<Vcc<5.5V, 0.5V<Vsns<0.9V VOUT_SCALE_LOOP=1 +/-3 Vout reporting accuracy % Iout Reporting NIout Resolution Note 2 Iout_dig Iout (digital) monitoring Range I Iout_dig Accuracy 0.06 25 0 00C to 1250C, 4.5V<Vcc<5.5V, 5A < Iout <30A A 40 A +/-5 % 1 C Temperature Reporting Resolution NTmon Temperature Monitoring Range Tmon_dig Thermal shutdown hysteresis 11 Note 2 -40 Note 2 Rev 3.4 150 25 C C Sept 12, 2018 IR38263 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Input Voltage Reporting Resolution NPVin Monitoring Range PMBVinmon Monitoring accuracy Note 2 1/32 V 0 21 00C to 850C, 4.5V<Vcc<5.5V, PVin>10V -1.5 1.5 -400C to 1250C, 4.5V<Vcc<5.5V, PVin>14V -1.5 1.5 -400C to 1250C, 4.5V<Vcc<5.5V, 7V<PVin<14V V % -4 4 PMBusTM Interface Timing Specifications PMBusTM Operating frequency FSMB Bus Free time between Start and Stop condition TBUF Hold time after (Repeated) Start Condition. After this period, the first clock is generated. THD:STA Repeated start condition setup time TSU:STA Stop condition setup time TSU:STO 400 kHz 1.3 us 0.6 us 0.6 us 0.6 us Data Rising Threshold 1.339 1.766 V Data Falling Threshold 1.048 1.495 V Clock Rising Threshold 1.339 1.766 V Clock Falling Threshold 1.048 1.499 V Data Rising Threshold LVT 0.7 0.9 V Data Falling Threshold LVT 0.45 0.65 V Clock Rising Threshold LVT 0.7 0.9 V Clock Falling Threshold LVT 0.45 0.65 V 900 ns Data Hold Time THD:DAT 300 Data Setup Time TSU:DAT 100 Data pulldown resistance 12 8 Rev 3.4 ns 11 16 Sept 12, 2018 IR38263 PARAMETER SYMBOL CONDITIONS SALERT# pulldown resistance MIN TYP MAX UNIT 9 12 17 35 ms Clock low time out TTIMEOUT 25 Clock low period TLOW 1.3 Clock High Period THIGH 0.6 us 50 us Digital Inputs - Low Vth Type 2 (VIDSELx) Input High Voltage 0.65 - - V Input Low Voltage - - 0.45 V Hysteresis - 95 - mV - - 1 A Input Leakage Current Vpad = 0 to 2V Notes 2. Guaranteed by design but not tested in production 3. Guaranteed by statistical correlation, but not tested in production 13 Rev 3.4 Sept 12, 2018 IR38263 TYPICAL APPLICATION DIAGRAMS 5.5V <Vin<16V P1V8 Enable Vin PVin Vcc/ LDO_out Boot Optional placeholder for boot resistor. Default should be 0 ohm For PVin >14V, a 1 ohm resistor is required Vo SW Vsns RS+ PGood PGood RS- VIDSEL0 3 bit PVID RSo VIDSEL1 Fb SAlert SDA ADDR SCL VIDSEL2 Comp PGnd LGnd i2C/ PMBus lines; pull up to 3.3V Placeholder for capacitor Figure 4: Using the internal LDO, Vo < 2.555V For applications in which Pvin>14V, a 1 ohm resistor is required in series with the boot capacitor . 5.5V <Vin<16V P1V8 Enable Vin PVin Vcc/ LDO_out Optional placeholder for boot resistor. Default should be 0 ohm Boot Vo SW Vsns RS+ PGood PGood R2 RS- VIDSEL0 CPU serial bus RSo VIDSEL1 SAlert SDA SCL ADDR Recommend R2=499 ohm Fb VIDSEL2 Comp PGnd LGnd i2C/ PMBus lines; pull up to 3.3/5V Placeholder for capacitor Figure 5: Using the internal LDO, Vo > 2.555V 14 Rev 3.4 Sept 12, 2018 IR38263 TYPICAL APPLICATION DIAGRAMS 1.5V <PVin<16V P1V8 Enable Vin PVin Vcc=5V Vcc/ LDO_out Optional placeholder for boot resistor. Default should be 0 ohm For PVin >14V, a 1 ohm resistor is required Boot Vo SW Vsns RS+ PGood PGood RS- VIDSEL0 3 bit PVID RSo VIDSEL1 SDA SCL ADDR SAlert Fb VIDSEL2 Comp PGnd LGnd i2C/ PMBus lines; pull up to 3.3/5V Placeholder for capacitor Figure 6: Using external Vcc, Vo<2.555V PVin=Vin=Vcc= 5V P1V8 Enable Vin PVin Vcc/ LDO_out Vsns RS+ RS- PGood VIDSEL0 RSo VIDSEL1 SCL SDA SAlert Fb VIDSEL2 ADDR Vo SW PGood 3 bit PVID Optional placeholder for boot resistor. Default should be 0 ohm Boot Comp PGnd LGnd i2C/ PMBus lines; pull up to 3.3/5V Placeholder for capacitor Figure 7: Single 5V application, Vo<2.555V 15 Rev 3.4 Sept 12, 2018 IR38263 TYPICAL OPERATING CHARACTERISTICS (-40C TO +125C) 16 Rev 3.4 Sept 12, 2018 IR38263 TYPICAL OPERATING CHARACTERISTICS (-40C TO +125C) 17 Rev 3.4 Sept 12, 2018 IR38263 TYPICAL OPERATING CHARACTERISTICS (-40C TO +125C) 18 Rev 3.4 Sept 12, 2018 IR38263 TYPICAL OPERATING CHARACTERISTICS (-40C TO +125C) 19 Rev 3.4 Sept 12, 2018 IR38263 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = Vin = 12V, VCC = 5V, Io=0-30A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table below shows the indicator used for each of the output voltages in the efficiency measurement. VOUT (V) LOUT (uH) P/N DCR (m) 0.8 0.15 HCB178380D-151 (Delta) 0.15 1 0.15 HCB138380D-151 (Delta) 0.15 1.2 0.15 HCB138380D-151 (Delta) 0.15 1.5 0.15 HCB138380D-151 (Delta) 0.15 1.8 0.15 HCB138380D-101 (Delta) 0.15 3.3 0.32 FP1308R3-R32-R (Cooper) 0.32 5 0.32 FP1308R3-R32-R (Cooper) 0.32 20 Rev 3.4 Sept 12, 2018 IR38263 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = Vin = 12V, Internal LDO, Io=0-30A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table below shows the indicator used for each of the output voltages in the efficiency measurement. VOUT (V) LOUT (uH) P/N DCR (m) 0.8 0.15 HCB178380D-151 (Delta) 0.15 1 0.15 HCB138380D-151 (Delta) 0.15 1.2 0.15 HCB138380D-151 (Delta) 0.15 1.5 0.15 HCB138380D-151 (Delta) 0.15 1.8 0.15 HCB138380D-101 (Delta) 0.15 3.3 0.32 FP1308R3-R32-R (Cooper) 0.32 5 0.32 FP1308R3-R32-R (Cooper) 0.32 21 Rev 3.4 Sept 12, 2018 IR38263 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = Vin = VCC = 5V, Io=0-30A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table below shows the indicator used for each of the output voltages in the efficiency measurement. VOUT (V) LOUT (uH) P/N DCR (m) 0.8 0.1 HCB138380D-101 (Delta) 0.15 1 0.1 HCB138380D-101 (Delta) 0.15 1.2 0.15 HCB138380D-101 (Delta) 0.15 1.5 0.15 HCB138380D-151 (Delta) 0.15 1.8 0.15 HCB138380D-151 (Delta) 0.15 22 Rev 3.4 Sept 12, 2018 IR38263 THERMAL DERATING CURVES The measurements were done on an evaluation kit demo board. The PCB is 7.0" x 5.5" x 0.072" with 10-layers, FR4 material and 2 oz. copper. The conditions used were, PVin = Vin = 12V, Internal LDO, Io=30A, Fs= 978kHz. IR38263 Thermal Derating Curves PVin=12V, Vout=1V, Fsw=978kHz 31 29 Max Iout (A) 27 25 23 0 LFM 21 200 LFM 19 400 LFM 17 15 25 23 30 35 Rev 3.4 40 45 50 55 60 TAmb (C) 65 70 75 80 85 Sept 12, 2018 IR38263 THEORY OF OPERATION DESCRIPTION The IR38263 is a 30A rated synchronous buck converter that supports PMBusTM communication. This device also has 3 pins that function as a parallel VID interface that can be used to set the output voltage to one of eight preprogrammed settings. They use an externally compensated fast, analog, PWM voltage mode control scheme to provide good noise immunity as well as fast dynamic response in a wide variety of applications. At the same time, the digital communication interfaces allow complete configurability of output setting and fault functions, as well as telemetry. The switching frequency is programmable from 150 kHz to 1500 kHz and provides the capability of optimizing the design in terms of size and performance. It is recommended to operate at 500 kHz or higher. This device provides precisely regulated output voltages from 0.5V to 0.875*PVin programmed via two external resistors or through the communication interfaces. They operate with an internal bias supply (LDO), typically 5.2V. This allows operation with a single supply. The output of this LDO is brought out at the Vcc pin and must be bypassed to the system power ground with a 10 uF decoupling capacitor. The Vcc pin may also be connected to the Vin pin, and an external Vcc supply between 4.5V and 5.5V may be used, allowing an extended operating bus voltage (PVin) range from 1.5V to 16V. The device utilizes the on-resistance of the low side MOSFET (synchronous MOSFET) as current sense element. This method enhances the converter's efficiency and reduces cost by eliminating the need for external current sense resistor. The IR38263 includes two low Rds(on) MOSFETs using Infineon's OptiMOSTM technology. These are specifically designed for low duty cycle, high efficiency applications. DEVICE POWER-UP AND INITIALIZATION During the power-up sequence, when Vin is brought up, the internal LDO converts it to a regulated 5.2V at Vcc. There is another LDO which further converts this down to 1.8V to supply the internal digital circuitry. An undervoltage lockout circuit monitors the voltage of VCC pin and the P1V8 pin, and holds the Power-on-reset (POR) low until these voltages exceed their thresholds and the internal 48 MHz oscillator is stable. When the device comes out of reset, it initializes a multiple times programmable (MTP) memory load cycle, where the contents of the MTP are loaded into the working registers. Once the registers are loaded from MTP, the designer can use PMBusTM commands to re-configure the various parameters to suit the specific VR design requirements if desired, irrespective of the status of Enable. The typical default configuration utilizes the internal LDO to supply the VCC rail when PVin is brought up. For this configuration power conversion is enabled only when the Enable pin voltage exceeds it's under voltage threshold, the PVin bus voltage exceeds its under voltage threshold, the contents of the MTP have been fully loaded into the working registers and the device address has been read. The initialization sequence is shown in Figure 8. Another common default configuration uses an external power supply for the VCC rail. While in this configuration it is recommended to ensure the VCC rail reaches its target voltage prior the enable signal goes high. Additional options are available to enable the device power conversion through software and these options may be configured to override the default by using the I2C interface or PMBusTM. For further details see the UN0075 IR3816x_IR3826x_IR3836x_PMBusTM commandset user note. 24 Rev 3.4 Sept 12, 2018 IR38263 PVIN=VIN VCC P1V8 UVOK clkrdy POR Initialization done Enable Vout Figure 8: Initialization sequence showing PVin, Vin, Vcc, 1.8V, Enable and Vout signals as well as the internal logic signals I2C AND PMBUS COMMUNICATION The IR38263 have two 7-bit registers that are used to set the base I2C address and base PMBusTM address of the device, as shown below in Table 1. Table 1: Registers used to set device base address Register Description I2c_address[6:0] The chip I2C address. An address of 0 will disable I2C communication. Note that disabling I2C does not disable PMBusTM. Pmbus_address[6:0] The chip PMBusTM address. An address of 0 will disable PMBusTM communication. Note that disabling PMBusTM does not disable I2C. In addition, a resistor may be connected between the ADDR and LGND pins to set an offset from the default preconfigured I2C address (0x10) /PMBusTM address (0x40) in the MTP. Up to 16 different offsets can be set, allowing 16 devices with unique addresses in a single system. This offset, and hence, the device address, is read by the internal 10 bit ADC during the initialization sequence. Table 2 below provides the resistor values needed to set the 16 offsets from the base address. 25 Rev 3.4 Sept 12, 2018 IR38263 Table 2 : Address offset vs. External Resistor(RADDR) ADDR Resistor (Ohm) Address Offset 499 +0 1050 +1 1540 +2 2050 +3 2610 +4 3240 +5 3830 +6 4530 +7 5230 +8 6040 +9 6980 +10 7870 +11 8870 +12 9760 +13 10700 +14 >11800 +15 The device will then respond to I2C/PMbusTM commands sent to this address. There is also a register bit i2c_disable_addr_offset that may be set in order to instruct the device to ignore the resistor offset for both i2c and PMBusTM. If this bit is set, the device will always respond to commands sent to the base address. MODES FOR SETTING OUTPUT VOLTAGES The IR38263 provides a configuration bit that allows the user to choose between PMBusTM and PVID mode. When this bit is set, the output voltage will ramp to the voltage set in the register selected by the VIDSEL0, VIDSEL1 and VIDSEL2 lines. These lines select a MTP register which contains a VID code that sets the output voltage. The VID tables can be configured for 5 mV and 10 mV VID steps are these are shown in the tables below. Note that the same VID value can result in different voltages depending on which VID table, 5mV or 10mV has been selected. When this bit is zero, the regulation is determined by the output voltage set by PMBusTM. It should be noted that irrespective of the mode used to set the output voltage, telemetry information always remains available on the i2c/PMBusTM. Table 3 shows how the VIDSELx lines are used to select the register containing the target value. It is worth noting that the VIDSEL lines may be driven with logic gates or with Open drain devices. When driven by open drain devices, a pullup resistor of 4.99 K must be used. When driven by logic gates, a resistor of 4.99K is required in series with the pin. 26 Rev 3.4 Sept 12, 2018 IR38263 Table 3: Mapping the VIDSEL lines to MTP registers VIDSEL2 0 0 0 0 1 1 1 1 VIDSEL1 0 0 1 1 0 0 1 1 VIDSEL0 0 1 0 1 0 1 0 1 Selects MTP register address 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh Table 4: Intel 5mV VID table VID (Hex) FF FE FD FC FB FA F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 EF EE ED EC EB EA E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 27 Voltage (V) 1.52 1.515 1.51 1.505 1.5 1.495 1.49 1.485 1.48 1.475 1.47 1.465 1.46 1.455 1.45 1.445 1.44 1.435 1.43 1.425 1.42 1.415 1.41 1.405 1.4 1.395 1.39 1.385 1.38 1.375 1.37 1.365 1.36 1.355 1.35 1.345 1.34 1.335 1.33 1.325 1.32 1.315 1.31 1.305 VID (Hex) C5 C4 C3 C2 C1 C0 BF BE BD BC BB BA B9 B8 B7 B6 BB BA B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 AF AE AD AC AB AA A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Rev 3.4 Voltage (V) 1.23 1.225 1.22 1.215 1.21 1.205 1.2 1.195 1.19 1.185 1.18 1.175 1.17 1.165 1.16 1.155 1.18 1.175 1.17 1.165 1.16 1.155 1.15 1.145 1.14 1.135 1.13 1.125 1.12 1.115 1.11 1.105 1.1 1.095 1.09 1.085 1.08 1.075 1.07 1.065 1.06 1.055 1.05 1.045 VID (Hex) 91 90 8F 8E 8D 8C 8B 8A 89 88 87 86 85 84 83 82 81 80 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 Voltage (V) 0.97 0.965 0.96 0.955 0.95 0.945 0.94 0.935 0.93 0.925 0.92 0.915 0.91 0.905 0.9 0.895 0.89 0.885 0.88 0.875 0.87 0.865 0.86 0.855 0.85 0.845 0.84 0.835 0.83 0.825 0.82 0.815 0.81 0.805 0.8 0.795 0.79 0.785 0.78 0.775 0.77 0.765 0.76 0.755 VID (Hex) 57 56 55 54 53 52 51 50 4F 4E 4D 4C 4B 4A 49 48 47 58 57 56 55 54 53 52 51 50 4F 4E 4D 4C 4B 4A 49 48 47 46 45 44 43 42 41 40 3F 3E Voltage (V) 0.68 0.675 0.67 0.665 0.66 0.655 0.65 0.645 0.64 0.635 0.63 0.625 0.62 0.615 0.61 0.605 0.6 0.685 0.68 0.675 0.67 0.665 0.66 0.655 0.65 0.645 0.64 0.635 0.63 0.625 0.62 0.615 0.61 0.605 0.6 0.595 0.59 0.585 0.58 0.575 0.57 0.565 0.56 0.555 VID (Hex) 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10 F E D C B A 9 8 7 6 5 4 Voltage (V) 0.48 0.475 0.47 0.465 0.46 0.455 0.45 0.445 0.44 0.435 0.43 0.425 0.42 0.415 0.41 0.405 0.4 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Sept 12, 2018 IR38263 D3 D2 D1 D0 CF CE CD CC CB CA C9 C8 C7 C6 1.3 1.295 1.29 1.285 1.28 1.275 1.27 1.265 1.26 1.255 1.25 1.245 1.24 1.235 9F 9E 9D 9C 9B 9A 99 98 97 96 95 94 93 92 1.04 1.035 1.03 1.025 1.02 1.015 1.01 1.005 1 0.995 0.99 0.985 0.98 0.975 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A 59 58 0.75 0.745 0.74 0.735 0.73 0.725 0.72 0.715 0.71 0.705 0.7 0.695 0.69 0.685 3D 3C 3B 3A 39 38 37 36 35 34 33 32 31 30 0.55 0.545 0.54 0.535 0.53 0.525 0.52 0.515 0.51 0.505 0.5 0.495 0.49 0.485 3 2 1 0 N/A N/A N/A 0 VOLTAGE (V) 2.46 2.45 2.44 2.43 2.42 2.41 2.40 2.39 2.38 2.37 2.36 2.35 2.34 2.33 2.32 2.31 2.30 2.29 2.28 2.27 2.26 2.25 2.24 2.23 2.22 2.21 2.20 2.19 2.18 2.17 2.16 2.15 2.14 2.13 2.12 2.11 2.10 2.09 2.08 2.07 2.06 2.05 VID (HEX) 8B 8A 89 88 87 86 85 84 83 82 81 80 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 VOLTAGE (V) 1.88 1.87 1.86 1.85 1.84 1.83 1.82 1.81 1.80 1.79 1.78 1.77 1.76 1.75 1.74 1.73 1.72 1.71 1.70 1.69 1.68 1.67 1.66 1.65 1.64 1.63 1.62 1.61 1.60 1.59 1.58 1.57 1.56 1.55 1.54 1.53 1.52 1.51 1.50 1.49 1.48 1.47 VID (HEX) 51 50 4F 4E 4D 4C 4B 4A 49 48 47 46 45 44 43 42 41 40 3F 3E 3D 3C 3B 3A 39 38 37 36 35 34 33 32 31 30 2F 2E 2D 2C 2B 2A 29 28 VOLTAGE (V) 1.30 1.29 1.28 1.27 1.26 1.25 1.24 1.23 1.22 1.21 1.20 1.19 1.18 1.17 1.16 1.15 1.14 1.13 1.12 1.11 1.10 1.09 1.08 1.07 1.06 1.05 1.04 1.03 1.02 1.01 1.00 0.99 0.98 0.97 0.96 0.95 0.94 0.93 0.92 0.91 0.90 0.89 VID (HEX) 17 16 15 14 13 12 11 10 F E D C B A 9 8 7 6 5 4 3 2 1 VOLTAGE (V) 0.72 0.71 0.70 0.69 0.68 0.67 0.66 0.65 0.64 0.63 0.62 0.61 0.60 0.59 0.58 0.57 0.56 0.55 0.54 0.53 0.52 0.51 0.50 Table 4: Intel 10mV VID table VID (HEX) FF FE FD FC FB FA F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 EF EE ED EC EB EA E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 DF DE DD DC DB DA D9 D8 D7 D6 28 VOLTAGE (V) 3.04 3.03 3.02 3.01 3.00 2.99 2.98 2.97 2.96 2.95 2.94 2.93 2.92 2.91 2.90 2.89 2.88 2.87 2.86 2.85 2.84 2.83 2.82 2.81 2.80 2.79 2.78 2.77 2.76 2.75 2.74 2.73 2.72 2.71 2.70 2.69 2.68 2.67 2.66 2.65 2.64 2.63 VID (HEX) C5 C4 C3 C2 C1 C0 BF BE BD BC BB BA B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 AF AE AD AC AB AA A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 9F 9E 9D 9C Rev 3.4 Sept 12, 2018 IR38263 D5 D4 D3 D2 D1 D0 CF CE CD CC CB CA C9 C8 C7 C6 2.62 2.61 2.60 2.59 2.58 2.57 2.56 2.55 2.54 2.53 2.52 2.51 2.50 2.49 2.48 2.47 9B 9A 99 98 97 96 95 94 93 92 91 90 8F 8E 8D 8C 2.04 2.03 2.02 2.01 2.00 1.99 1.98 1.97 1.96 1.95 1.94 1.93 1.92 1.91 1.90 1.89 61 60 5F 5E 5D 5C 5B 5A 59 58 57 56 55 54 53 52 1.46 1.45 1.44 1.43 1.42 1.41 1.40 1.39 1.38 1.37 1.36 1.35 1.34 1.33 1.32 1.31 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 0.88 0.87 0.86 0.85 0.84 0.83 0.82 0.81 0.80 0.79 0.78 0.77 0.76 0.75 0.74 0.73 BUS VOLTAGE UVLO If the input to the Enable pin is derived from the bus voltage by a suitably programmed resistive divider, it can be ensured that the device does not turn on until the bus voltage reaches the desired level as shown in Figure 9. Only after the bus voltage reaches or exceeds this level and voltage at the Enable pin exceeds its threshold (typically 0.6V) will the device be enabled. Therefore, in addition to being logic input pin to enable the converter, the Enable feature, with its precise threshold, also allows the user to override the default under-Voltage Lockout for the bus voltage (PVin). This is desirable particularly for high output voltage applications, where we might want the device to be disabled at least until PVin exceeds the desired output voltage level. Alternatively, the default 8 V PVin UVLO threshold may be reconfigured/overridden using the VIN_ON and VIN_OFF PMBusTM commands or the corresponding registers. It should be noted that the input voltage is also fed to an ADC through a 21:1 internal resistive divider. However, the digitized input voltage is used only for the purposes of reporting the input voltage through the READ_VIN PMBusTM command. It has no impact on the bus voltage UVLO, input overvoltage faults and input undervoltage warnings, all of which are implemented by using analog comparators to compare the input voltage to the corresponding thresholds programmed by the PMBusTM commands VIN_ON, VIN_OFF, VIN_OV_FAULT_LIMIT and VIN_UV_WARN_LIMIT respectively. The bus voltage reading as reported by READ_VIN has no effect on the input feedforward function either. 12V 10.2V PVin 1V Vcc > 0.6V EN 0.6V EN_UVLO_START DAC2 (Reference DAC) Figure 9: Normal Start up, device turns on when the bus voltage reaches 10.2A. A resistor divider is used at EN pin from PVin to turn on the device at 10.2V. 29 Rev 3.4 Sept 12, 2018 IR38263 PVin=Vin Vcc > 0.6V EN DAC2 (Reference DAC) Figure 10: Recommended startup for Normal operation Figure 10 shows the recommended startup sequence for the normal operation of the device, when Enable is used as logic input. PRE-BIAS STARTUP The IR38263 can start up into a pre-charged output, which prevents oscillation and disturbances of the output voltage. The output starts in asynchronous fashion and keeps the synchronous MOSFET (Sync FET) off until the first gate signal for control MOSFET (Ctrl FET) is generated. Figure 11 shows a typical Pre-Bias condition at start up. The sync FET always starts with a narrow pulse width (12.5% of a switching period) and gradually increases its duty cycle with a step of 12.5%, with 16 cycles at each step, until it reaches the steady state value. Figure 12 shows the series of 16x8 startup pulses. [V] Vo Pre-Bias Voltage [Time] Figure 11: Pre-Bias startup ... HDRv 12.5% 16 ... 25% ... LDRv ... ... ... 16 ... 87.5% ... ... ... End of PB Figure 12: Pre-Bias startup pulses 30 Rev 3.4 Sept 12, 2018 IR38263 SOFT-START (REFERENCE DAC RAMP) An internal soft starting DAC controls the output voltage rise and limit the current surge at the start-up. To ensure correct start-up, the DAC sequence initiates only after power conversion is enabled when the Enable pin voltage exceeds its undervoltage threshold, the PVin bus voltage exceeds its undervoltage threshold and the contents of the MTP have been fully loaded into the working registers. Figure 13 shows the waveforms during soft start. It should be noted that the part may also be configured to require software Enable (set through the PMBusTM or the corresponding MTP register) instead of or in addition to a "hardware" signal at the Enable pin. In PMBusTM mode, the reference DAC soft-start may be delayed from the time power conversion is enabled. The range for this programmable delay is 0ms to 127 ms, and the resolution is 1 ms. Further, in this mode, the soft start time may be configured from 1ms to 127 ms with 1 ms resolution. The programmable turn on delay only applies in PMBusTM mode. In PVID mode, the output voltage rises with a slew rate of 0.625 mv/us. For more details on the PMBusTM commands TON_DELAY and TON_RISE used to program the startup sequence, please see the UN0075 IR3816x_IR3826x_IR3836x_PMBUS commandset user note.. Internal Enable Reference DAC Vout Ton_delay t1 t2 Ton_rise t3 Figure 13: DAC2 (VREF) Soft start During the startup sequence the over-current protection (OCP) and over-voltage protection (OVP) are active to protect the device against any short circuit or over voltage condition. OPERATING FREQUENCY Using the FREQUENCY_SWITCH PMBusTM command, or the corresponding registers, the switching frequency may be programmed between 150 kHz and 1.5 MHz. For best telemetry accuracy, it is recommended that the following switching frequencies be avoided: 250 kHz, 300 kHz, 400 kHz, 500 kHz, 600 kHz, 750 kHz, 800 kHz, 1 MHz, 1.2 MHz and 1.5 MHz. Instead, it is recommended to use the following values 251 kHz, 302 kHz, 403 kHz, 505 kHz, 607 kHz, 762 kHz, 813 kHz, 978 kHz, 1171 kHz and 1454 kHz respectively. 31 Rev 3.4 Sept 12, 2018 IR38263 SHUTDOWN In the default configuration, the device can be shutdown by pulling the Enable pin below its 0.4V threshold. During shutdown the high side and the low side drivers are turned off. By default, the device exhibits an immediate shutdown with no delay and no soft stop. Alternatively, in both PMBusTM and PVID modes, the part may be configured to allow shutdown using the OPERATION PMBusTM command or the corresponding register. It may also be configured to allow a soft or controlled turned off. In PMBusTM mode, if the soft-off option is used, the turn off may be delayed from the time the power conversion is disabled. The range for this programmable delay is 0ms to 127 ms, and the resolution is 1 ms. Further, in this mode, the soft stop time may be configured from 1ms to 127 ms with 1 ms resolution. The programmable turn off delay only applies in PMBusTM mode. In PVID mode, if the soft-stop option is used, the output voltage slews down at 0.625 mV/us. CURRENT SENSING, TELEMETRY AND OVER CURRENT PROTECTION Current sensing for both, telemetry as well as overcurrent protection is done by sensing the voltage across the sync FET RDson. This method enhances the converter's efficiency, reduces cost by eliminating a current sense resistor and any minimizes sensitivity to layout related noise issues. A novel, patented scheme allows reconstruction of the average inductor current from the voltage sensed across the Sync FET Rdson. It should be noted here that it is this reconstructed average inductor current that is digitized by the ADC and used for output current reporting as well as for overcurrent warning, the threshold for which may be set using the IOUT_OC_WARN_LIMIT command. The current is reported in 1/16A resolution using the READ_IOUT PMBusTM command. The current information may also be read back through the 8-bit register output_current_byte, which reports the current in 1/4 A resolution. The Over current (OC) fault protection circuit also uses the voltage sensed across the RDS(on) of the Synchronous MOSFET; however, the protection mechanism relies on a fast comparator to compare the sensed signal to the overcurrent threshold and does not depend on the ADC or reported current. The current limit scheme uses an internal temperature compensated current source that has the same temperature coefficient as the RDS(on) of the Synchronous MOSFET. As a result, the over-current trip threshold remains almost constant over temperature. Over Current Protection circuitry senses the inductor current flowing through the Synchronous FET closer to the valley point. The OCP circuit samples this current for 75 ns typically after the rising edge of the PWM set pulse which is an internal signal that has a width of 12.5% of the switching period. The PWM pulse that turns on the high side FET starts at the falling edge of the PWM set pulse. This makes valley current sense more robust as current is sensed close to the bottom of the inductor downward slope where transient and switching noise is low. This helps to prevent false tripping due to noise and transients. The actual DC output current limit point will be greater than the valley point by an amount equal to approximately half of the peak to peak inductor ripple current. The current limit point will be a function of the inductor value, input voltage, output voltage and the frequency of operation. On equation 1, I Limit is the value set when configuring the 38265 OCP value. The user should account for the inductor ripple to obtain the actual DC output current limit. I OCP I LIMIT 32 Rev 3.4 i 2 (1) Sept 12, 2018 IR38263 IOCP ILIMIT i = DC current limit hiccup point = Current Limit Valley Point = Inductor ripple current Current Limit Hiccup Tblk_Hiccup 20 ms IL 0 HDrv ... 0 LDrv ... 0 PGood 0 Figure 14: Timing Diagram for Current Limit Hiccup In the default configuration, if the overcurrent detection trips the OCP comparator for a total of 8 cycles, the device goes into a hiccup mode. The hiccup is performed by de-asserting the internal Enable signal to the analog and power conversion circuitry and holding it low for 20 ms. Following this, the OCP signal resets and the converter recovers. After every hiccup cycle, the converter stays in this mode until the overload or short circuit is removed. This behavior is shown in Figure 14. It should be noted that on some units, a false OCP maybe experienced during device start-up due to noise. The part will ride through this false OCP due to the pulse by pulse current limiting feature and successfully ramp to the correct output voltage. However, Infineon recommends sending a PMBUS Clear_Faults command after start-up to reset the PMBUS SAlert# to a high and to clear the PMBUS status register for faults. Note that the user can override the default overcurrent threshold using the PMBusTM command IOUT_OC_FAULT_LIMIT. It is recommended that the overcurrent threshold be programmed to at least 16A for good accuracy. While these devices will still offer overcurrent protection for thresholds programmed lower than these recommended values, the thresholds will not be as accurate. Also, using the PMBusTM command IOUT_OC_FAULT_RESPONSE or the corresponding registers, the part may be configured to respond to an overcurrent fault in one of two ways 1) Pulse by pulse current limiting for a programmed number of 8 switching cycles followed by a latched shutdown. 2) Pulse by pulse current limiting for a programmed number 8 switching cycles followed by hiccup. This is the default explained above. The pulse-by-pulse or constant current limiting mechanism is briefly explained below. 33 Rev 3.4 Sept 12, 2018 IR38263 IOUT_OC_FAULT_LIMIT IL 20 ms 0 HDrv 0 LDrv 0 CLK Fs 0 OCP High Internal Enable 1 2 4 3 5 6 7 8 Figure 15: Pulse by pulse current limiting for 8 cycles, followed by hiccup. Figure 15, the overcurrent response is set to pulse-by-pulse current limiting for 8 cycles followed by hiccup, the converter is operating at D<0.125 when the overcurrent condition occurs. In such a case, no duty cycle limiting is applied. IL IO UT _OC_FA ULT_LIM IT 0 HDrv 0 LDrv 0 CLK Fs 0 OCP High Internal Enable 1 2 3 4 5 6 7 8 9 10 11 ... Figure 16: Constant current limiting. Figure 16 depicts a case where the overcurrent condition happens when the converter is operating at D>0.5 and the overcurrent response has been set to Constant current operation through pulse by pulse current limiting. In such a case, after 3 consecutive overcurrent cycles are recognized, the pulse width is dropped such that D=0.5 and then after 3 more consecutive OCP cycles, to 0.25 and then finally to 0.125 at which it keeps running until the total OCP count reaches the programmed maximum following which the part enters hiccup mode. Conversely, when the overcurrent condition disappears, the pulse width is restored to its nominal value gradually, by a similar mechanism in reverse; every sequence of 4 consecutive cycles in which the current is below the overcurrent threshold doubles the duty cycle, so that D goes from 0.125 to 0.25, then to 0.5 and finally to its nominal value. 34 Rev 3.4 Sept 12, 2018 IR38263 DIE TEMPERATURE SENSING, TELEMETRY AND THERMAL SHUTDOWN On die temperature sensing is used for accurate temperature reporting and over temperature detection. The READ_TEMEPRATURE PMBusTM command reports this temperature in 10C resolution. The temperature may also be read back through the 8-bit register temp_byte, which reports the die temperature in 10C resolution, offset by 400C. Thus, the temperature is given by temp_byte +400C. The trip threshold is set by default to 125oC. The default over temperature response of the device is to inhibit power conversion while the fault is present, followed by automatic restart after the fault condition is cleared. Hence, in the default configuration, when trip threshold is exceeded, the internal Enable signal to the power conversion circuitry is de-asserted, turning off both MOSFETs. Automatic restart is initiated when the sensed temperature drops within the operating range. There is a 25oC hysteresis in the thermal shutdown threshold. The default overtemperature threshold as well as overtemperature response may be re-configured or overridden using the OT_FAULT_LIMIT and OT_FAULT_RESPONSE PMBusTM commands or the corresponding MTP registers. The devices support three types of responses to an over-temperature fault: 1) Ignore 2) Inhibit when over temperature condition exists and auto-restart when over temperature condition disappears 3) Latched shutdown. REMOTE VOLTAGE SENSING True differential remote sensing in the feedback loop is critical to high current applications where the output voltage across the load may differ from the output voltage measured locally across an output capacitor at the output inductor, and to applications that require die voltage sensing. The RS+ and RS- pins form the inputs to a remote sense differential amplifier with high speed, low input offset and low input bias current, which ensure accurate voltage sensing and fast transient response in such applications. The input range for the differential amplifier is limited to 1.5V below the VCC rail. Therefore, for applications in which the output voltage is more than 3V, it is recommended to use local sensing, or if remote sensing is a must, then the voltage between the RS+ and RS-pins must be divided down to less than 3V using a resistive voltage divider. Practically, since designs for output voltage greater than 2.555V require the use of a resistive divider anyway, it is recommended that this divider be placed at the input of the remote sense amplifier. Please note, however, that this modifies the open loop transfer function and requires a change in the compensation network to optimally stabilize the loop. FEED-FORWARD Feed-Forward (F.F.) is an important feature, because it can keep the converter stable and preserve its load transient performance when PVin varies over a wide range. The PWM ramp amplitude (Vramp) is proportionally changed with PVin to maintain PVin/Vramp almost constant throughout PVin variation range (as shown in Figure 17). Thus, the control loop bandwidth and phase margin can be maintained constant. The feed-forward function can also 35 Rev 3.4 Sept 12, 2018 IR38263 minimize impact on output voltage from fast PVin change. The feedforward is disabled for PVin<4.7V. Hence, for PVin<4.7V, a re-calculation of control loop parameters is needed for re-compensation. 21V 12V PVin 12V 5V 0 PWM Ramp 0 Ramp Offset Figure 17: Timing Diagram for Feed-Forward (F.F.) Function LIGHT LOAD EFFICIENCY ENHANCEMENT (AOT) These devices implement a diode emulation scheme with Adaptive On Time control or AOT to improve light load efficiency. It is based on a COT (Constant On Time) control scheme with some novel advancements that make the on-time during diode emulation adaptive and dependent upon the pulse width in constant frequency operation. This allows the scheme to be combined with a PWM scheme, while providing relatively smooth transition between the two modes of operation. In other words, the switching regulator can operate in AOT mode at light loads and automatically switch to PWM at medium and heavy loads and vice versa. Therefore, the regulator will benefit from the high efficiency of the AOT mode at light loads, and from the constant frequency and fast transient response of the PWM at medium to heavy loads. A MFR_SPECIFIC PMBusTM command (MFR_FCCM) or the corresponding MTP bit can be used to enable AOT operation at light load. Shortly after the reference voltage has finished ramping up, an internal circuit which is called the "calibration circuit" starts operation. It samples the Comp voltage (output of the error amplifier), digitizes it and stores it in a register. There is a DAC which converts the value of this register to an analog voltage which is equal to the sampled Comp voltage. At this time, the regulator is ready to enter AOT mode if the load condition is appropriate. If the load is so low that the inductor current becomes negative before the next SW pulse, the operation can be switched to AOT mode. The condition to enter AOT is the occurrence of 8 consecutive inductor current zero crossings in eight consecutive switching cycles. If this happens, operation is switched to AOT mode as shown in Figure 18Figure 18. The inductor current is sensed using the RDS_ON of the Sync-FET and no direct inductor current measuring is required. In AOT mode, just like COT operation, pulses with constant width are generated and diode emulation is utilized. This means that a pulse is generated and LDrv is held on until the inductor current becomes zero. Then both HDrv and LDrv remain off until the voltage of the sense pin comes down and reaches the reference voltage. At this moment the next pulse is generated. The sense pin is connected to the output voltage by a resistor divider which has the same ratio as the voltage divider which is connected to the feedback pin (Fb). 36 Rev 3.4 Sept 12, 2018 IR38263 ... Vout 0 8/Fs delay IL ... Diode Emulation 0 Ton ... SW ... 0 HDrv ... ... 0 LDrv ... ... 0 1/Fs Reduced Switching Frequency Figure 18: Timing Diagram for Reduced Switching Frequency and Diode Emulation in Light Load Condition (AOT mode) When the load increases beyond a certain value, the control is switched back to PWM through either of the following two mechanisms: 1) If due to the increase in load, the output voltage drops to 95% of the reference voltage. 2) If Vsense remains below the reference voltage for 3 consecutive inductor current zero-cross events It is worth mentioning that in AOT mode, when Vsense comes down to reference voltage level, a new pulse in generated only if the inductor current is already zero. If at this time the inductor current (sensed on the Sync-FET) is still positive, the new pulse generation is postponed till the current decays to zero. The second condition mentioned above usually happens when the load is gradually increased. It should be noted that in tracking mode, AOT operation is disabled and the device can only operate in continuous conduction mode even at light loads. AOT is disabled during output voltage transitions. It is enabled only after reference voltage finishes its ramp (up or down) and the calibration circuit has sampled and held the new Comp voltage. In general, AOT operation is more jittery and noisier than FCCM operation, where the switching frequency may vary from cycle to cycle, giving increased Vout ripple and noisier, inconsistent telemetry. Therefore, it is recommended to use FCCM mode of operation as far as possible. OUTPUT VOLTAGE SENSING, TELEMETRY AND FAULTS In the IR38263, the voltage sense and regulation circuits are decoupled, enabling ease of testing as well as redundancy. In order to do this, the device uses the sense voltage at the dedicated Vsns pin for output voltage reporting (in 1/256 V resolution, using the READ_VOUT PMBusTM command) as well as for power good detection and output overvoltage protection. Power good detection and output overvoltage detection rely on fast analog comparator circuits, whereas overvoltage warnings as well as undervoltage faults and warnings rely on comparing the digitized Vsns to the 37 Rev 3.4 Sept 12, 2018 IR38263 corresponding thresholds programmed using PMBusTM commands VOUT_OV_WARN_LIMIT, VOUT_UV_FAULT_LIMIT and VOUT_UV_WARN_LIMIT respectively (or the corresponding MTP registers). Power Good Output The Vsns voltage is an input to the window comparator with programmable thresholds. The PGood signal is high whenever Vsns voltage is within the PGood comparator window thresholds. The PGood pin is open drain and it needs to be externally pulled high. High state indicates that output is in regulation. The Power Good thresholds may be changed through the POWER_GOOD_ON and POWER_GOOD_OFF commands, which set the rising and falling PGood thresholds respectively. However, when no resistive divider is used, such as for output voltages lower than 2.555V, the Power Good thresholds must be programmed to within 630 mV of the output voltage, otherwise, the effective power good threshold changes from an absolute threshold to one that tracks the output voltage with a 630 mV offset. By default, the PGood signal will assert as soon as the Vsns signal enters the regulation window. In digital mode, this delay is programmable from 0 to 10ms with a 1 ms resolution, using the MFR_TPGDLY command. The threshold is set differently in PVID mode. In this mode, the thresholds set by the POWER_GOOD_ON and POWER_GOOD_OFF commands (or the corresponding registers) are ignored. Power Good is asserted when the output voltage is within the tolerance band of the target voltage set in the register selected by the VIDSELx pins. Following this, the Power Good signal remains asserted irrespective of any output voltage transitions and is deasserted only in the event of a fault that shuts down power conversion. Fault DAC 0 Reference DAC 0 Power Good upper threshold Vsns 0 Power Good lower threshold PGD 0 160us Figure 19: Power Good in PMBusTM mode 38 Rev 3.4 Sept 12, 2018 IR38263 Fault DAC 0 Reference DAC 0 Vset+/-TOB Vsns 0 PGD 0 Figure 20: Power Good in PVID mode, Vboot >0 V Over-Voltage Protection (OVP) Over-voltage protection is achieved by comparing sense pin voltage Vsns to a configurable overvoltage threshold. The OVP threshold may be reprogrammed to within 655 mV of the output voltage (for output voltages lower than 2.555V, without any resistive divider on the Fb pin), using the VOUT_OV_FAULT_LIMIT PMBusTM command or the corresponding registers. For an OVP threshold programmed to be more than 655 mV greater than the output voltage, the effective OV threshold ceases to be an absolute value and instead tracks the output voltage with a 655 mV offset. When Vsns exceeds the over voltage threshold, an over voltage trip signal asserts after 200 ns (typ.) delay. The default response is that the high side drive signal HDrv is latched off immediately and PGood flags are set low. The low side drive signal is kept on until the Vsns voltage drops below the threshold. HDrv remains latched off until a reset is performed by cycling either Vcc or Enable or the OPERATION command. The device allows the user to reconfigure this response by the use of the VOUT_OV_FAULT_RESPONSE PMBusTM command. In addition to the default response described above, this command can be used to configure the device such that Vout overvoltage faults are ignored and the converter remains enabled. (however, they will still be flagged in the STATUS_REGISTERS and by SAlert ). For further details on the corresponding PMBuTMs commands related to OVP, please refer to the UN0075 IR3816x_IR3826x_IR3836x_PMBusTM commandset user note. Vsns voltage is set by an external resistive voltage divider connected to the output. This divider ratio must match the divider used on the feedback pin or on the RS+ pin. It should be noted that the overvoltage threshold applies in PMBusTM mode as well as PVID mode. 39 Rev 3.4 Sept 12, 2018 IR38263 DAC1+OV_OFFSET_DAC Vout DAC1 hysteresis 0 HDrv 0 LDrv 0 Comp 0 PGood 0 200 ns 200 ns Figure 21: Timing Diagram for OVP in non-tracking mode MINIMUM ON TIME CONSIDERATIONS The minimum ON time is the shortest amount of time for Ctrl FET to be reliably turned on. This is a very critical parameter for low duty cycle, high frequency applications. In the conventional approach, when the error amplifier output is near the bottom of the ramp waveform with which it is compared to generate the PWM output, propagation delays can be high enough to cause pulse skipping, and hence limit the minimum pulse width that can be realized. Moreover, in the conventional approach, the bottom of the ramp often presents a high gain region to the error amplifier output, making the modulator more susceptible to noise and requiring the use of lower control loop bandwidth to prevent noise, jitter and pulse skipping. IR has developed a proprietary scheme to improve and enhance the minimum pulse width which minimizes these delays and hence, allows stable operation with pulse-widths as small as 35ns. At the same time, this scheme also has greater noise immunity, thus allowing stable, jitter free operation down to very low pulse widths even with a high control loop bandwidth, thus reducing the required output capacitance. Any design or application using these devices must ensure operation with a pulse width that is higher than the minimum on-time and at least 50 ns of on-time is recommended in the application. This is necessary for the circuit to operate without jitter and pulse-skipping, which can cause high inductor current ripple and high output voltage ripple. t on Vout D Fs PVin Fs (2) In any application that uses these devices, the following condition must be satisfied: t on(min) t on t on(min) 40 Rev 3.4 Vout PVin Fs (3) (4) Sept 12, 2018 IR38263 PVin Fs Vout t on(min) (5) The minimum output voltage is limited by the reference voltage and hence Vout(min) = 0.5V. Therefore, for Vout(min) = 0.5V, PVin Fs Vout t on(min) PVin Fs (6) 0.5V 10 V/s 50 ns Therefore, at the maximum recommended input voltage 16V and minimum output voltage, the converter should be designed at a switching frequency that does not exceed 625 kHz. Conversely, for operation at the maximum recommended operating frequency (1.5 MHz) and minimum output voltage (0.5V), the input voltage (PVin) should not exceed 6.67 V, otherwise pulse skipping may happen. MAXIMUM DUTY RATIO An upper limit on the operating duty ratio is imposed by the larger of a) A fixed off time (dominant at high switching frequencies) b) blanking provided by the PWMSet or clock pulse, which has a pulse width that is 1/8 of the switching period. The latter mechanism is dominant at lower switching frequencies (typically below 1.25 MHz). This upper limit ensures that the Sync FET turns on for a long enough duration to allow recharging the bootstrap capacitor and also allows current sensing. Figure 22 shows a plot of the maximum duty ratio vs. the switching frequency with built in input voltage feed forward mechanism. Figure 22: Maximum duty cycle vs. switching frequency 41 Rev 3.4 Sept 12, 2018 IR38263 BOOTSTRAP CAPACITOR To drive the Control FET, it is necessary to supply a gate voltage at least 4V greater than the voltage at the SW pin, which is connected to the source of the Control FET. This is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor (C1). Typically a 0.1uF capacitor is used. A layout placement for a 0 ohm resistor in series with the capacitor is also recommended. For PVin> 14V, a 1 ohm resistor is required. The operation of the circuit is as follows: When the sync FET is turned on, the capacitor node connected to SW is pulled down to ground. The capacitor charges towards Vcc through the internal bootstrap diode (Figure 23), which has a forward voltage drop VD. The voltage Vc across the bootstrap capacitor C1 is approximately given as: Vc Vcc VD (7) When the control FET turns on in the next cycle, the capacitor node connected to SW rises to the bus voltage PVin. However, if the value of C1 is appropriately chosen, the voltage Vc across C1 remains approximately unchanged and the voltage at the Boot pin becomes: VBoot PVin Vcc VD Cvin + VD - (8) PV IN Boot Vcc C1 IR38263 SW + Vc L PGnd Figure 23: Bootstrap circuit to generate high side drive voltage LOOP COMPENSATION Feedback loop compensation is achieved using standard Type III techniques and the compensation values can be easily calculated using Infineon's design tool. The design tool can also be used to predict the control bandwidth and phase margin for the loop for any set of user defined compensation component values. For a theoretical understanding of the calculations used, please refer to Infineon's Application Note AN-1162 "Compensator Design Procedure for Buck Converter with Voltage-Mode Error-Amplifier". 42 Rev 3.4 Sept 12, 2018 IR38263 DYNAMIC VID COMPENSATION This family of devices uses an analog control scheme with voltage mode control. In this scheme, the compensator acts on the Vout signal and not just on the error signal. For load and line transients, with a steady and unchanging reference voltage, this has the same dynamic characteristics as for a compensator that acts on only the error signal. However, for reference voltage changes, as in the case of Dynamic VID, the dynamics are altered. A proprietary dynamic VID compensation scheme allows the dynamic VID response to be tuned optimally to the feedback compensator values. Once properly optimized, the output voltage will follow the DAC more closely during a positive dynamic VID, irrespective of whether the new voltage is commanded by using PMBusTM or by using the 3 VIDSELx pins to select a different register and target voltage. Infineon's SupIRBuck design tool will allow the user to quickly and conveniently calculate the dynamic VID compensation parameters for optimal dynamic VID response. 43 Rev 3.4 Sept 12, 2018 IR38263 LAYOUT RECOMMENDATIONS The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Make the connections for the power components in the top layer with wide, copper filled areas or polygons. In general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. The input capacitors, inductor, output capacitors and the device should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place the input capacitor directly at the PVin pin of IR38x6x. Power vias should be at least 20/10 mil and a good rule of thumb is to design at 2A/via. The feedback part of the system should be kept away from the inductor and other noise sources. The critical bypass components such as capacitors for Vin, VCC and 1.8V should be close to their respective pins. It is important to place the feedback components including feedback resistors and compensation components close to Fb and Comp pins. In a multilayer PCB use one layer as a power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control functions. These two grounds must be connected together on the PC board layout at a single point. It is recommended to place all the compensation parts over the analog ground plane in top layer. The Power QFN is a thermally enhanced package. Based on thermal performance it is recommended to use at least a 6-layers PCB. To effectively remove heat from the device the exposed pad should be connected to the ground plane using vias. IR38263 has 3 pins, SCL, SDA and SALERT# that are used for I2C/PMBusTM communication. It is recommended that the traces used for these communication lines be at least 10 mils wide with spacing between the SCL and SDA traces that is at least 2-3 times the trace width. 44 Rev 3.4 Sept 12, 2018 IR38263 I2C PROTOCOLS All registers may be accessed using either I2C or PMBusTM protocols. I2C allows the use of a simple format whereas PMBusTM provides error checking capability. Figure 24 shows the I2C format employed by the IC. 1 S WRITE 1 W 7 Slave Address 1 A 8 1 A Register Address 8 1 A Data Byte S: Start Condition 1 P A: Acknowledge (0') N: Not Acknowledge (1') Sr: Repeated Start Condition READ P: Stop Condition 1 7 1 S Slave Address W A 8 1 1 7 1 Register Address A S Slave Address R A 8 1 1 R: Read (1') Data Byte N P W: Write (0') PEC: Packet Error Checking *: Present if PEC is enabled : Master to Slave : Slave to Master Figure 24: I2C Format SMBUS/PMBUS PROTOCOLS To access IR's configuration and monitoring registers, 4 different protocols are required: the SMBus Read/Write Byte/Word protocol with/without PEC (for status and monitoring) the SMBus Send Byte protocol with/without PEC (for CLEAR_FAULTS only) the SMBus Block Read protocol for accessing Model and Revision information the SMBus Process call (for accessing Configuration Registers) In addition, the IC supports: Alert Response Address (ARA) Bus timeout Group Command for writing to many VRs within one command BYTE 1 7 1 1 8 1 8 1 8 1 1 S Slave Address W A Command Code A Data Byte A* PEC* A P S: Start Condition A: Acknowledge (0') N: Not Acknowledge (1') Sr: Repeated Start Condition P: Stop Condition WORD 1 7 S Slave Address 1 W A 8 1 8 1 Command Code A Data Byte Low A 8 1 8 1 1 Data Byte High A* PEC* A P R: Read (1') W: Write (0') ... PEC: Packet Error Checking *: Present if PEC is enabled : Master to Slave : Slave to Master Figure 25: SMBus Write Byte/Word 45 Rev 3.4 Sept 12, 2018 IR38263 BYTE WORD 1 7 S Slave Address 1 7 S Slave Address 1 8 W A Command Code 1 1 8 A Command Code W 1 7 1 1 8 1 8 1 1 A Sr Slave Address R A Data Byte A* PEC* N P 1 1 7 1 1 8 1 Sr Slave Address A Data Byte Low A 1 1 A 8 1 8 1 1 Data Byte High A* PEC* N P R ... Figure 26: SMBus Read Byte/Word 1 7 S Slave Address 1 W 1 8 1 8 1 1 A Command Code A* PEC* A P Figure 27: SMBus Send Byte 1 7 S Slave Address W 1 7 1 1 8 1 Sr Slave Address R A Byte Count =1 A 1 1 8 1 A Command Code A ... 8 Data Byte 1 8 1 1 A* PEC* N P Figure 28: SMBus Block Read with Byte Count=1 S PMBus Address W Command D1h A A Register Address A Data Byte A PEC* A P Figure 29: MFR specific command to Write an internal Register S Sr PMBus Address PMBus Address W R A A Command D0h Data Byte A A Register Address A Address+1 Data Byte A* ... PEC* N P Figure 30: SMBus Custom Process Call to Read an internal Register 46 Rev 3.4 Sept 12, 2018 IR38263 1 7 S Slave Address 1 1 7 Sr Slave Address 2 1 1 8 1 8 W A Command Code 1 A Low Data Byte 1 1 8 A Command Code 2 1 A Low Data Byte W 8 1 8 High A Data Byte ... 1 or more bytes 1 A 8 ... High Data Byte 1 8 1 A PEC1* A* 1 A 8 1 PEC2* A* ... ... 1 or more bytes 1 7 Sr Slave Address n 1 W 1 8 A Command Code n 1 8 A Low Data Byte 1 8 1 8 1 1 A High Data Byte A PECn* A P ... 1 or more bytes Figure 31: Group Command 47 Rev 3.4 Sept 12, 2018 IR38263 PCB PADS AND COMPONENT 48 Rev 3.4 Sept 12, 2018 IR38263 PCB COPPER AND SOLDER RESIST (PAD SIZES) PCB COPPER AND SOLDER RESIST (PAD SPACING) 49 Rev 3.4 Sept 12, 2018 IR38263 SOLDER PASTE STENCIL (PAD SIZES) SOLDER PASTE STENCIL (PAD SPACING) 50 Rev 3.4 Sept 12, 2018 IR38263 MARKING INFORMATION FOR FINAL PRODUCTION 51 Rev 3.4 Sept 12, 2018 IR38263 MARKING INFORMATION FOR EARLY PRODUCTION 52 Rev 3.4 Sept 12, 2018 IR38263 PACKAGE INFORMATION 53 Rev 3.4 Sept 12, 2018 IR38263 54 Rev 3.4 Sept 12, 2018 IR38263 ENVIRONMENTAL QUALIFICATIONS Industrial Qualification Level Moisture Sensitivity Level Machine Model (JESD22-A115A) ESD Human Body Model (JESD22-A114F) Charged Device Model (JESD22-C101F) RoHS Compliant 5mm x 7mm PQFN MSL 2 260C JEDEC Class A JEDEC Class 1C JEDEC Class 3 Yes (with Exemption 7a) Qualification standards can be found at International Rectifier web site: http://www.irf.com 55 Rev 3.4 Sept 12, 2018 IR38263 SUPPORTED PMBUS COMMANDS Comma nd Code Command Name SMBus transactio n No. of bytes 01h OPERATION R/W Byte 1 02h ON_OFF_CONFIG R/W Byte 1 03h CLEAR_FAULTS Send Byte 0 Clear contents of Fault registers 10h WRITE_PROTECT R/W Byte 1 Used to control writing to the PMBusTM device. The intent of this command is to provide protection against accidental changes. 15h STORE_USER_ALL Send Byte 0 Burns the User section registers into OTP memory 16h RESTORE_USER_ALL Send Byte 0 Copies the OTP registers into User memory 19h CAPABILITY Read Byte 1 Returns 1011xxxx to indicate Packet Error Checking is supported, maximum bus speed is 400kHz and SMBAlert# is supported. 1Bh SMBALERT_MASK Write word/Block read Process call 2 May be used to prevent a warning or fault condition from asserting the SMBALERT# signal. 21h VOUT_COMMAND16 R/W Word 2 02.555V/VS 22h VOUT_TRIM16 R/W Word 2 -128+128V 24h VOUT_MAX16 R/W Word 2 25h VOUT_MARGIN_HIGH16 R/W Word 2 02.555V/VS 5mV/VS 26h VOUT_MARGIN_LOW16 R/W Word 2 02.555V/VS 5mV/VS 27h VOUT_TRANSITION_RATE11 R/W Word 2 0127ms/us 0.125mV /us 29h VOUT_SCALE_LOOP11 R/W Word 2 0.125-1 1 33h FREQUENCY_SWITCH11 R/W Word 2 1661500kHz 978kHz 35h VIN_ON11 R/W Word 2 0-16.5V 0.5V 8V 36h VIN_OFF11 R/W Word 2 0-16V 0.5V 7.0V 39h IOUT_CAL_OFFSET11 R/W Word 2 -128A+127.5A 0.25A 0A 40h VOUT_OV_FAULT_LIMIT16 R/W Word 2 (2510mV/VS 1.398V 655mV)/VS 41h VOUT_OV_FAULT_RESPONS E R/W Byte 1 Ignore/Shut down 42h VOUT_OV_WARN_LIMIT16 R/W Word 2 56 Rev 3.4 Range Resoluti Default Description on Value Enables or disables the device and controls margining Configures the combination of Enable pin input and serial bus commands needed to turn the unit on and off. 5mV/VS 1V Causes the device to set its output voltage to the commanded value. VS= VOUT_SCALE_LOOP 0V Available to the device user to trim the output voltage 2V Shutdow n 3.9mV Sets an upper limit on the output voltage the unit can command regardless of any other commands or combinations. Sets the MARGIN high voltage when commanded by OPERATION VS= VOUT_SCALE_LOOP Sets the MARGIN low voltage when commanded by OPERATION VL= VOUT_SCALE_LOOP Sets the rate in mV/s at which the output should change voltage. Exponent 0 to -4 allowed. Compensates for external resistor divider in feedback path and in the sense path. Values 1, 0.5, 0.25, 0.125 allowed. Exponent -3 allowed. Sets the switching frequency, in kHz. Exponent 0 to 1 allowed. Sets the value of the input voltage, in volts, at which the unit should start power conversion. Exponent -1 allowed. Sets the value of the input voltage, in volts, at which the unit, once operation has started, should stop power conversion. Exponent -1 allowed. Used to null out any offsets in the output current sensing circuit. Exponent -1 allowed. Sets the value of the output voltage measured at the sense pin that causes an output overvoltage fault. VS= VOUT_SCALE_LOOP Instructs the device on what action to take in response to an output overvoltage fault. 1.301V Sets the value of the output voltage at the Sept 12, 2018 IR38263 Comma nd Code SMBus transactio n Command Name No. of bytes Range Resoluti Default Description on Value 43h VOUT_UV_WARN_LIMIT16 R/W Word 2 3.9mV 44h VOUT_UV_FAULT_LIMIT16 R/W Word 2 3.9mV 45h VOUT_UV_FAULT_RESPONS E R/W Byte 1 Ignore/Shut down 46h IOUT_OC_FAULT_LIMIT11 R/W Word 2 3-52.5A 0.5A IOUT_OC_FAULT_RESPONSE R/W Byte 1 47h 4Ah IOUT_OC_WARN_LIMIT11 R/W Word 2 0-63.5A 0.5A 4Fh OT_FAULT_LIMIT11 R/W Word 2 0-150C 1C 50h OT_FAULT_RESPONSE R/W Byte 1 Ignore/Shut down/Inhibi it 51h OT_WARN_LIMIT11 R/W Word 2 0-150C 1C 55h VIN_OV_FAULT_LIMIT11 R/W Word 2 6.25V-24V 0.25V 56h VIN_OV_FAULT_RESPONSE R/W Byte 1 Ignore/Shut down 58h VIN_UV_WARN_LIMIT11 R/W Word 2 0-16V 5Eh POWER_GOOD_ON16 R/W Word 2 (010mV/VS 0.63V)/VS 5Fh POWER_GOOD_OFF16 R/W Word 2 (010mV/VS 0.63V)/VS 60h TON_DELAY11 R/W Word 2 0-127ms 1ms 61h TON_RISE11 R/W Word 2 0-127ms 1ms 62h TON_MAX_FAULT_LIMIT11 R/W Word 2 0-127ms 1ms 63h TON_MAX_FAULT_RESPONS E R/W Byte 1 Ignore/Shut down 57 Rev 3.4 sense pin that causes an output voltage high warning. Sets the value of the output voltage at the 0.75V Sense pin that causes an output voltage low warning. Sets the value of the output voltage at the 0.680V sense pin that causes an output undervoltage fault. Instructs the device on what action to Ignore take in response to an output undervoltage fault. Sets the value of the output current, in 40A amperes, that causes the overcurrent detector to indicate an overcurrent fault. Exponent -1 allowed. Pulse by pulse for 8 cycles followed Instructs the device on what action to by take in response to an output overcurrent fault. hiccup, retry after 20 ms Sets the value of the output current, in amperes, that causes the overcurrent detector to 35A indicate an overcurrent warning. Exponent -1 allowed. Set the temperature, in degrees Celsius, of the unit at 125C which it should indicate an Overtemperature Fault. Exponent 0 allowed. Autostart 0.5V Instructs the device on what action to take in response to an overtemperature fault. Set the temperature, in degrees Celsius, of the unit at 105C which it should indicate an Overtemperature Warning alarm. Exponent 0 allowed. Sets the value of the input voltage that causes an 15V input overvoltage fault. Exponent -2 allowed. Instructs the device on what action to take Ignore in response to an input overvoltage fault. Sets the value of the input voltage PVin, in volts, that causes an input overvoltage fault. Exponent -1 allowed. Sets the output voltage at which an optional 0.5V POWER_GOOD signal should be asserted. VS=VOUT_SCALE_LOOP Sets the output voltage at which an optional 0.25V POWER_GOOD signal should be negated. VS=VOUT_SCALE_LOOP Sets the time, in milliseconds, from when a start condition is received (as programmed by the 0ms ON_OFF_CONFIG command) until the output voltage starts to rise. Exponent 0 allowed. Sets the time, in milliseconds, from when the output 1ms starts to rise until the voltage has entered the regulation band. Exponent 0 allowed. Sets an upper limit, in milliseconds, on how long the 0 unit can attempt to power up the output without (Disable reaching the output undervoltage fault limit. d) Exponent 0 allowed. 9.0V Ignore Instructs the device on what action to Sept 12, 2018 IR38263 Comma nd Code SMBus transactio n Command Name No. of bytes Range Resoluti Default Description on Value take in response to a TON_MAX fault. 64h TOFF_DELAY R/W Word 2 0-127ms 1ms 0ms 65h TOFF_FALL R/W Word 2 0-127ms 1ms 2ms 78h STATUS BYTE Read Byte Sets the time, in milliseconds, from a stop condition is received (as programmed by the ON_OFF_CONFIG command) until the unit stops transferring energy to the output. Exponent 0 allowed. Sets the time, in milliseconds, in which the reference voltage ramps down to zero (If a soft off is allowed by the configuration of the ON_OFF_CONFIG command). Exponent 0 allowed.. 1 Returns 1 byte where the bit meanings are: Bit <7> device busy fault Bit <6> output off (due to fault or enable) Bit <5> Output over-voltage fault Bit <4> Output over-current fault Bit <3> Input Under-voltage fault Bit <2> Temperature fault Bit <1> Communication/Memory/Logic fault Bit <0>: None of the above 79h STATUS WORD Read Word 2 Returns 2 bytes where the Low byte is the same as the STATUS_BYTE data. The High byte has bit meanings are: Bit <7> Output high or low fault Bit <6> Output over-current fault Bit <5> Input under-voltage fault Bit <4> Reserved; hardcoded to 0 Bit <3> Output power not good Bit <2:0> Hardcoded to 0 7Ah STATUS_VOUT Read Byte 1 Reports types of VOUT related faults. 7Bh STATUS_IOUT Read Byte 1 Reports types of IOUT related faults. 7Ch STATUS_INPUT Read Byte 1 Reports types of INPUT related faults. 1 Returns Over Temperature warning and Over Temperature fault (OTP level). Does not report under temperature warning/fault. The bit meanings are: Bit <7> Over Temperature Fault Bit <6> Over Temperature Warning Bit <5> Under Temperature Warning Bit <4> Under Temperature Fault Bit <3:0> Reserved 7Dh STATUS_TEMPERATURE Read Byte 7Eh STATUS_CML Read Byte 1 Returns 1 byte where the bit meanings are: Bit <7> Command not Supported Bit <6> Invalid data Bit <5> PEC fault Bit <4> OTP fault Bit <3:2> Reserved Bit<1> Other communication fault Bit<0> Other memory or logic fault; hardcoded to 0 88h READ_VIN11 Read Word 2 Returns the input voltage in Volts 58 Rev 3.4 Sept 12, 2018 IR38263 Comma nd Code Command Name SMBus transactio n No. of bytes 8Bh READ_VOUT16 Read Word 2 Returns the output voltage in Volts Read Word 2 Returns the output current in Amperes 8Ch 8Dh READ_IOUT 11 Resoluti Default Description on Value Read Word 2 Returns the device temperature in degrees Celcius 96h READ_POUT11 Read Word 2 Returns the output power in Watts 98h PMBUS_REVISION Read Byte 1 Reports PMBusTM Part I rev 1.2 & PMBusTM Part II rev 1.2 99h MFR_ID Block Read/Write 2 9Ah MFR_MODEL Block Read/Write 3 9Bh MFR_REVISION Block Read/Write 3 ADh IC_DEVICE_ID Block Read 2 AEh IC_DEVICE_REV Block Read 1 Used to read the revision of the IC D0h MFR_READ_REG Custom 2 Manufacturer Specific: Read from configuration registers D1h MFR_WRITE_REG Custom 2 D8h MFR_TPGDLY R/W Word 2 0-10ms D9h MFR_FCCM R/W Byte 1 0-1 D6h MFR_I2C_address R/W Word 1 0-7Fh DBh MFR_VOUT_PEAK16 Read Word 2 DCh MFR_IOUT_PEAK11 Read Word 2 MFR_TEMPERATURE_PEAK11 Read Word 2 DDh READ_TEMPERATURE 11 Range IR Returns 2 bytes used to read the manufacturer's ID. User can overwrite with any value. If set to 0, returns a 1 byte code corresponding to Set IC_DEVICE_ID. 000000 Alternatively, user can set to any non-zero value If set to 0, returns a 1 byte code corresponding to Set IC_DEVICE_REV. 000000 Alternatively, user can set to any non-zero value Used to read the type or part number of an IC. IR38263: 65h 1ms Manufacturer Specific: Write to configuration & status registers Sets the delay in ms, between the output voltage 0ms entering the regulation window and the assertion of the PGood signal. Exponent 0 allowed. Allows the user to choose between forced continuous 1 (CCM) conduction mode and adaptive on-time operation at light load. 10h Sets and returns the device I2C base address Continuously records and reports the highest value of Read Vout. Continuously records and reports the highest value of Read Iout. Continuously records and reports the highest value of Read_Temperature Notes 11 Uses LINEAR11 format 16 Uses LINEAR16 format with exponent set to-8 59 Rev 3.4 Sept 12, 2018 IR38263 REVISION HISTORY 0.0 12/8/2014 Initial Release 0.1 12/8/2014 Changed current rating from 20A to 30A 0.2 4/14/2015 0.3 3/28/2016 0.4 7/14/2016 1.0 12/9/2016 added OCP curves, OCP spec, typical operating curves, efficiency curves, note discouraging AOT; added note about using a 4.99K pullup. 1.1 1/13/2017 Changed from concept to preliminary 3.0 3/9/2017 For DR3, added layout guidelines, removed Preliminary and added marking diagrams, added description of layout circuit 3.1 3/20/2017 changed 1.8V LDO regulation current to 1 mA, updated stencil drawings 3.2 5/8/2017 Added requirement of 1 ohm series resistor for PVin>14V 3.3 12/12/2017 3.4 9/12/2018 60 Added packaging info, new POD, PMBusTM commands, combined IR38263 and IR38265 datasheets Added SM_ALERT pin info and updated POD to show NC for IR38265 and SALERT for IR38263 Separate ds for IR38263. Added theory of operation. PVin rating=16V Changed from SupIRBuck to OptiMOSTM IPOL brand:RB Changed max duty chart to reflect 200 kHz to 1.5MHz range Changed min time calculation Change IOUT_OC_FAULT_LIMIT range in PMBusTM table Added Manhattan SVID IDs for IC_DEVICE_ID Added small section on dynamic VID and prefilter (called dynamic vid compensation just like the MP parts) Truncated Vboot table at 0.4V Removed min max spec for Rdson Fixed OCP description and diagram plus updated other functionality sections. Fixed P1V8 pin is grounded to PGND instead of LGND in Figure 4,5,6,7. Added recommendation to use 10uF bypass capacitor at P1V8 pin. Updated the default values on the PMBUS section. Updated application diagrams. Updated packaging markings, added thermal de-rating curves, corrected PMBUS revision. Rev 3.4 Sept 12, 2018 IR38263 Published by Infineon Technologies AG 81726 Munchen, Germany (c) Infineon Technologies AG 2015 All Rights Reserved. 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It is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office (www.infineon.com). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies' products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. 61 Rev 3.4 Sept 12, 2018