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ver. 1.3
Pin Assignment
Pin# Pin Name Description Pin# Pin Name Description
35 PERp0
PCI Express x1 data
interface: one differential
receive pair
36 No Connection No Connection
37 PERn0
PCI Express x1 data
interface: one differential
receive pair
38 Reserved -
39 GND GND 40 Reserved -
41 PETp0
PCI Express x1 data
interface: one differential
transmit pair
42 Reserved -
43 PETn0
PCI Express x1 data
interface: one differential
transmit pair
44 COEX3_ACTIVE
(OPT) No Connection
45 GND GND 46 COEX2_PRI(OPT) No Connection
47 REFCLK+
Input signal for PCI Express
differential reference clock
(100 MHz)
48 COEX1_SYNC
(OPT) No Connection
49 REFCLK-
Input signal for PCI Express
differential reference clock
(100 MHz)
50 SUSCLK(OPT)
32.768 kHz clock supply input that
is provided by PCH to reduce
power and cost for the module.
SUSCLK will have a duty cycle that
can be as low as 30% or as high as
70% 200ppm.
51 GND GND 52 PERST_L Input signal for functional reset to
the card
53 CLKREQ_L Output for reference clock
request signal 54 BT_ DISABLE_L
(OPT)
These pins are reserved for
definition with future revisions of
this specification.
55 WAKE_L
(OPT)
Output and open Drain
active Low signal. This signal
is used to request that the
system return from a
sleep/suspended state to
service a function initiated
wake event.
56 W_DISABLE_L
(OPT)
Input and active low signal. This
signal is used by the system to
disable radio operation on add-in
cards that implement radio
frequency applications. When
implemented, this signal requires a
pull-up resistor on the card