LTC1983ES6-5#TRPBF - ANALOG DEVICES

LTC1983-3/LTC1983-5

1983fc

For more information www.linear.com/LTC1983-3

Typical applicaTion

FeaTures DescripTion

100mA Regulated

Charge-Pump Inverters

in ThinSOT

The LT C

1983-3 and LTC1983-5 are inverting charge

pump DC/DC converters that produce negative regulated

outputs. The parts require only three tiny external capaci-

tors and can provide up to 100mA of output current. The

devices can operate in open loop mode (creating a –VIN

supply) or regulated output mode depending on the input

supply voltage and the output current.

The LTC1983-3/LTC1983-5 have many useful features for

portable applications including very low quiescent current

(25µA typical) and a zero current shutdown mode pro-

grammed through the SHDN pin.

The LTC1983-3/LTC1983-5 are over-temperature and

short-circuit protected. The parts are available in a 6-pin

low profile (1mm) ThinSOT package.

–3V at 100mA DC/DC Converter VOUT vs IOUT

applicaTions

n Fixed Output Voltages: –3V, –5V or Low Noise VIN

to –VIN Inverted Output

n ±4% Output Voltage Accuracy

n Low Quiescent Current: 25µA

n 100mA Output Current Capability

n 2.3V to 5.5V Operating Voltage Range

n Internal 900kHz Oscillator

n “Zero Current” Shutdown

n Short-Circuit and Over-Temperature Protected

n Low Profile (1mm) ThinSOT

Package

n –3V Generation in Single-Supply Systems

n Portable Equipment

n LCD Bias Supplies

n GaAs FET Bias Supplies

VIN

SHDN

C+

VOUT

GND

C–

LTC1983-3

VIN

3V TO 5.5V

VOUT = –3V

IOUT = UP TO 100mA

COUT

10µF

CIN

10µF

CF LY

1µF

OFF ON

CF LY : TAIYO YUDEN LMK212BJ105

CIN, COUT: TAIYO YUDEN JMK316BJ106ML

1983-3 TA01

IOUT (mA)

VOUT (V)

–3.3

–3.2

–3.1

–3.0

–2.9

–2.8

–2.7 20 40 60 80

1983 TA02

100

VIN = 5V

VIN = 3.3V

L, LT , LT C , LT M , Linear Technology, Burst Mode and the Linear logo are registered trademarks

and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

LTC1983-3/LTC1983-5

1983fc

For more information www.linear.com/LTC1983-3

absoluTe MaxiMuM raTings

VIN to GND ................................................... –0.3V to 6V

SHDN Voltage .............................................. –0.3V to 6V

VOUT to GND (LTC1983-3) ................... 0.2V to VOUT Max

VOUT to GND (LTC1983-5)................... 0.2V to VOUT Max

IOUT Max ..............................................................125mA

Output Short-Circuit Duration .......................... Indefinite

Operating Temperature Range (Note 2)....–40°C to 85°C

Storage Temperature Range ..................–65°C to 125°C

Lead Temperature (Soldering, 10 sec) ................... 300°C

(Note 1)

VCC 1

VOUT 2

C+ 3

6 SHDN

5 GND

4 C–

TOP VIEW

S6 PACKAGE

6-LEAD PLASTIC SOT-23

TJMAX = 125°C, θJA = 256°C/W

elecTrical characTerisTics

PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Operating Voltage (Regulated Output Mode) (LTC1983-3)

(LTC1983-5)

l3.0

5.0

5.5

VIN Minimum Startup Voltage 2.3 V

VOUT (LTC1983-3) VIN ≥ 3.3V, IOUT ≤ 25mA

VIN ≥ 5V, IOUT ≤ 100mA

–2.88

–3

–3.12

VOUT (LTC1983-5) VIN ≥ 5V, VIN –5V ≥ IOUT • ROUT l–4.8 –5 –5.2 V

VIN Operating Current VIN ≤ 5.5V, IOUT = 0µA, SHDN = VIN l25 60 µA

VIN Operating Current (Open-Loop Mode) (LTC1983-5) VIN = 3.3V

VIN = 4.75V

2.5

VIN Shutdown Current SHDN = 0V, VIN ≤ 5.5V l0.1 1 µA

Output Ripple 3.3 ≤ VIN ≤ 5.5 60 mVP-P

Open-Loop Output Impedance (LTC1983-3): ROUT VIN = 3.3V, VOUT = –3V 11 Ω

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. VIN = 5V, CF LY = 1µF, COUT = 10µF unless otherwise noted.

pin conFiguraTion

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC1983ES6-3#PBF LTC1983ES6-3#TRPBF LTPC 6-Lead Plastic TSOT-23 –40°C to 85°C

LTC1983ES6-5#PBF LTC1983ES6-5#TRPBF LTY B 6-Lead Plastic TSOT-23 –40°C to 85°C

Consult LT C Marketing for parts specified with wider operating temperature ranges.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

http://www.linear.com/product/LTC1983-3#orderinfo

LTC1983-3/LTC1983-5

1983fc

For more information www.linear.com/LTC1983-3

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC1983E-3/LTC1983E-5 are guaranteed to meet performance

speciﬁcations from 0°C to 70°C. Speciﬁcations over the –40°C to 85°C

operating temperature range are assured by design, characterization and

correlation with statistical process controls.

Typical perForMance characTerisTics

Output Impedance vs

Input Voltage

Output Impedance

vs IOUT (LTC1983-5)

Efficiency vs IOUT (LTC1983-5)

Efficiency vs I

OUT –3VOUT vs IOUT Over Temperature

–3VOUT vs IOUT Over Temperature

(VIN = 5V)

IOUT (mA)

EFFICIENCY (%)

40 80 100

1983 G01

20 60

VIN = 2.3V VIN = 3.3V

VIN = 5V

TA = 25°C

VIN (V)

2.35

ROUT (Ω)

4.35

12.5

12.0

11.5

11.0

10.5

10.0

9.5

9.0

8.5

8.0

1983 TA02

3.35 5.35

ROUT

IOUT = 25mA

TA = 25°C

IOUT (mA)

ROUT (Ω)

40 80 100

1983 G03

20 60

VIN = 2.3V

VIN = 3.3V

VIN = 5V

TA = 25°C

IOUT (mA)

0.01

100

010

1983 GO4

0.1 1 100

EFFICIENCY (%)

VIN = 5V

VIN = 3.3V

VOUT = –3V

TA = 25°C

OUTPUT CURRENT (mA)

–2.1

–2.3

–2.5

–2.7

–2.9

–3.1

–3.3

–3.5 60 100

1983 G05

20 40 80 120

VOUT (V)

120°C

–40°C, 0°C, 40°C

80°C

OUTPUT CURRENT (mA)

2.7

VOUT (–V)

2.8

2.9

3.0

3.1

3.3

20 40 60 80

1983 G06

100 120

3.2

–40°C 0°C

40°C

80°C

VIN = 5V

elecTrical characTerisTics

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. VIN = 5V, CF LY = 1µF, COUT = 10µF unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Open-Loop Output Impedance (LTC1983-5): ROUT VIN = 3.3V, IOUT ≈ 50mA

VIN = 5V, IOUT ≈ 60mA

8.5

Oscillator Frequency (Non Burst Mode

Operation) 900 kHz

SHDN Input High l1.1 V

SHDN Input Low l0.3 V

SHDN Input Current VSHDN = 5.5V l2.2 4 µA

LTC1983-3/LTC1983-5

1983fc

For more information www.linear.com/LTC1983-3

Typical perForMance characTerisTics

VIN (V)

3.1

26.5

INPUT CURRENT (µA)

27.0

28.0

28.5

29.0

4.1 5.1 5.5

31.0

1983 G10

27.5

3.6 4.6

29.5

30.0

30.5

TA = 25°C

TEMPERATURE (°C)

–50

ROUT (Ω)

150

1983 G11

0050 100

VIN = 5V

VIN = 3V

IOUT = 10mA

TEMPERATURE (°C)

–50

VTHRESHOLD (V)

0.1

0.3

0.4

0.5

1.0

0.7

050

1983 G12

0.2

0.8

0.9

0.6

100 150

TEMPERATURE (°C)

–50

2.0

2.5

3.5

100

1983 G13

1.5

1.0

0 50 150

0.5

3.0

ISHDN (µA)

Burst Mode Input Current

vs VIN (LTC1983-3)

ROUT vs Temperature

(IOUT = 10mA)

SHDN Pin Threshold Voltage

vs Temperature

SHDN Pin Input Current

vs Temperature ROUT vs CF LY (VIN = 5V)

CFLY (µF)

0.01

140

VIN = 5V

TA = 25°C

120

100

1983 G14

0.1 1

OUT

(Ω)

Open-Loop Current

vs Temperature (LTC1983-5)

Burst Mode Current

vs Temperature (LTC1983-3)

Open-Loop Input Current

vs VIN (LTC1983-5)

TEMPERATURE (°C)

–40

4.9

4.7

4.5

4.3

4.1

3.9

3.7

3.5

1983 G07

10 60 110

IIN (mA)

VIN = 5V

TEMPERATURE (°C)

–40

IIN (µA)

1983 G08

10 10 60

110

VIN = 5V

VIN (V)

2.3

1.5

IIN (mA)

2.0

2.5

3.0

3.5

4.5

2.8 3.3 3.3 4.3

1983 G09

4.8

4.0

TA = 25°C

LTC1983-3/LTC1983-5

1983fc

For more information www.linear.com/LTC1983-3

Typical perForMance characTerisTics

OUT

50µs/DIV

1983 G15

OUT

20mV

1µs/DIV

1983 G16

OUT

20mV

2.5µs/DIV 1983 G17

OUT

20mV

OUT

100mA

100µs/DIV 1983 G18

VOUT Start-Up into 100mA

Resistive Load VOUT Ripple at 100mA Load

VOUT Ripple at 30mA Load

VOUT Load Step Response from

IOUT = 0 to IOUT = 100mA

LTC1983-3/LTC1983-5

1983fc

For more information www.linear.com/LTC1983-3

pin FuncTions

VIN (Pin 1): Charge Pump Input Voltage. May be between

2.3V and 5.5V. VIN should be bypassed with a ≥4.7µF

low ESR capacitor as close as possible to the pin for best

performance.

VOUT (Pin 2): Regulated Output Voltage for the IC. VOUT

should be bypassed with a ≥4.7µF low ESR capacitor as

close as possible to the pin for best performance.

C+ (Pin 3): Charge Pump Flying Capacitor Positive Ter-

minal. This node is switched between VIN and GND (It is

connected to VCC during shutdown).

C– (Pin 4): Charge Pump Flying Capacitor Negative Ter-

minal. This node is switched between GND and VOUT (It

is connected to GND during shutdown).

GND (Pin 5): Signal and Power Ground for the 6-Pin

SOT-23 package. This pin should be tied to a ground plane

for best performance.

SHDN (Pin 6): Shutdown. Grounding this pin shuts down

the IC. Tie to VIN to enable. This pin should not be pulled

above the VIN voltage or below GND.

block DiagraM

CONTROL

LOGIC

CLOCK2

CLOCK1

S1A

S2A

S1B

S2B

–

VREF

CHARGE PUMP

SHDN

VIN

CIN

10µF

CF LY

1µF

COUT

10µF

LTC1983-X

C+

C–

VOUT

COMP1

1µA

1983 BD

LTC1983-3/LTC1983-5

1983fc

For more information www.linear.com/LTC1983-3

operaTion

The LTC1983-3/LTC1983-5 use a switched capacitor

charge pump to invert a positive input voltage to a regulated

–3V ±4% (LTC1983-3) or –5 ±4% (LTC1983-5) output

voltage. Regulation is achieved by sensing the output

voltage through an internal resistor divider and enabling

the charge pump when the output voltage droops above

the upper trip point of COMP1. When the charge pump

is enabled, a 2-phase, nonoverlapping clock controls the

charge pump switches. Clock 1 closes the S1 switches

which enables the flying capacitor to charge up to the

VIN voltage. Clock 2 closes the S2 switches that invert

the VIN voltage and connect the bottom plate of CF LY to

the output capacitor at VOUT. This sequence of charging

and discharging continues at a free-running frequency of

900kHz (typ) until the output voltage has been pumped

down to the lower trip point of COMP1 and the charge

pump is disabled. When the charge pump is disabled, the

LTC1983 draws only 25µA (typ) from VIN which provides

high efficiency at low load conditions.

In shutdown mode, all circuitry is turned off and the part

draws less than 1µA from the VIN supply. VOUT is also dis-

connected from VIN and CF LY . The SHDN pin has a threshold

of approximately 0.7V. The part enters shutdown when

a low is applied to the SHDN pin. The SHDN pin should

not be floated; it must be driven with a logic high or low.

Open-Loop Operation

The LTC1983-3/LTC1983-5 inverting charge pumps regu-

late at –3V/–5V respectively, unless the input voltage is

too low or the output current is too high. The equations

for output voltage regulation are as follows:

VIN –5.06V > IOUT • ROUT (LTC1983-5)

VIN –3.06V > IOUT • ROUT (LTC1983-3)

If this condition is not met, then the part will run in open

loop mode and act as a low output impedance inverter for

which the output voltage will be:

VOUT = –[VIN –(IOUT • ROUT)]

For all ROUT values, check the corresponding curves in

the Typical Performance Characteristics section (Note:

CF LY = 1µF for all ROUT curves). The ROUT value will be

different for different flying caps, as shown in the follow-

ing equation:

ROUT =ROUT(curve) – 1.11Ω + 1

fOSC •CFLY

⎛

⎝

⎜⎞

⎠

⎟

Short-Circuit/Thermal Protection

During short-circuit conditions, the LTC1983 will draw

several hundred milliamps from VIN causing a rise in the

junction temperature. On-chip thermal shutdown circuitry

disables the charge pump once the junction temperature

exceeds ≈155°C, and re-enables the charge pump once the

junction temperature falls back to ≈145°C. The LTC1983

will cycle in and out of thermal shutdown indefinitely

without latchup or damage until the VOUT short is removed.

Capacitor Selection

For best performance, it is recommended that low ESR

capacitors be used for both CIN and COUT to reduce noise

and ripple. The CIN and COUT capacitors should be either

ceramic or tantalum and should be 4.7µF or greater.

Aluminum electrolytic are not recommended because of

their high equivalent series resistance (ESR). If the source

impedance is very low, CIN may not be needed. Increas-

ing the size of COUT to 10µF or greater will reduce output

voltage ripple. The flying capacitor and COUT should also

have low equivalent series inductance (ESL). The board

layout is critical as well for inductance for the same reason

(the suggested board layout should be used).

A ceramic capacitor is recommended for the flying ca-

pacitor with a value in the range of 0.1µF to 4.7µF. Note

that a large value flying cap (>1µF) will increase output

ripple unless COUT is also increased. For very low load

applications, C1 may be reduced to 0.01µF to 0.047µF.

This will reduce output ripple at the expense of efficiency

and maximum output current.

(Refer to Block Diagram)

LTC1983-3/LTC1983-5

1983fc

For more information www.linear.com/LTC1983-3

operaTion

(Refer to Block Diagram)

There are many aspects of the capacitors that must be

taken into account. First, the temperature stability of the

dielectric is a main concern. For ceramic capacitors, a

three character code specifies the temperature stability

(e.g. X7R, Y5V, etc.). The first two characters represent

the temperature range that the capacitor is specified

and the third represents the absolute tolerance that the

capacitor is specified to over that temperature range.

The ceramic capacitor used for the flying and output

capacitors should be X5R or better. Second, the volt-

age coefficient of capacitance for the capacitor must be

checked and the actual value usually needs to be derated

for the operating voltage (the actual value has to be larger

than the value needed to take into account the loss of

capacitance due to voltage bias across the capacitor).

Third, the frequency characteristics need to be taken into

account because capacitance goes down as the frequency

of oscillation goes up. Typically, the manufacturers have

capacitance vs frequency curves for their products. This

curve must be referenced to be sure the capacitance will

not be too small for the application. Finally, the capacitor

ESR and ESL must be low for reasons mentioned in the

following section.

Output Ripple

Normal LTC1983 operation produces voltage ripple on the

VOUT pin. Output voltage ripple is required for the LTC1983

to regulate. Low frequency ripple exists due to the hyster-

esis in the sense comparator and propagation delays in the

charge pump enable/disable circuits. High frequency ripple

is also present mainly due to ESR of the output capacitor.

Typical output ripple under maximum load is 60mVP-P

with a low ESR 10µF output capacitor. The magnitude of

the ripple voltage depends on several factors. High input

voltage to negative output voltage differentials [(VIN +

VOUT) >1V] increase the output ripple since more charge

is delivered to COUT per clock cycle. A large flying capacitor

(>1µF) also increases ripple for the same reason. Large

output current load and/or a small output capacitor (<10µF)

results in higher ripple due to higher output voltage dV/dt.

High ESR capacitors (ESR > 0.1Ω) on the output pin cause

high frequency voltage spikes on VOUT with every clock

cycle.

There are several ways to reduce the output voltage ripple.

A larger COUT capacitor (22µF or greater) will reduce both

the low and high frequency ripple due to the lower COUT

charging and discharging dV/dt and the lower ESR typically

found with higher value (larger case size) capacitors. A

low ESR ceramic output capacitor will minimize the high

frequency ripple, but will not reduce the low frequency ripple

unless a high capacitance value is chosen. A reasonable

compromise is to use a 10µF to 22µF tantalum capacitor in

parallel with a 1µF to 4.7µF ceramic capacitor on VOUT to

reduce both the low and high frequency ripple. However,

the best solution is to use 10µF to 22µF, X5R ceramic

capacitors which are available in 1206 package sizes. An

RC filter may also be used to reduce high frequency volt-

age spikes (see Figure 1).

In low load or high VIN applications, smaller values for

CF LY may be used to reduce output ripple. A smaller fly-

ing capacitor (0.01µF to 0.047µF) delivers less charge

per clock cycle to the output capacitor resulting in lower

output ripple. However, the smaller value flying caps also

reduce the maximum IOUT capability as well as efficiency.

VOUT VOUT

LTC1983-X

10µF

TANTALUM

10µF

TANTALUM

VOUT VOUT

LTC1983-X

15µF

TANTALUM

1µF

CERAMIC

3.9Ω

1983 F01

Figure 1. Output Ripple Reduction Techniques

LTC1983-3/LTC1983-5

1983fc

For more information www.linear.com/LTC1983-3

operaTion

Inrush Currents

During normal operation, VIN will experience current

transients in the several hundred milliamp range whenever

the charge pump is enabled. During start-up, these inrush

currents may approach 1 to 2 amps. For this reason, it is

important to minimize the source resistance between the

input supply and the VIN pin. Too much source resistance

may result in regulation problems or even prevent start-

up. One way that this can be avoided (especially when

the source impedance can’t be lowered due to system

constraints) is to use a large VIN capacitor with low ESR

right at the VIN pin. If ceramic capacitors are used, you may

need to add 1µF to 10µF tantalum capacitor in parallel to

limit input voltage transients. Input voltage transients will

occur if VIN is applied via a switch or a plug. One example

of this situation is in USB applications.

Ultralow Quiescent Current Regulated Supply

The LTC1983 contains an internal resistor divider (refer

to the Block Diagram) that draws only 1µA (typ for the

3V version) from VOUT during normal operation. During

shutdown, the resistor divider is disconnected from the

output and the part draws only leakage current from the

output. During no-load conditions, applying a 1Hz to

100Hz, 2% to 5% duty cycle signal to the SHDN pin en-

sures that the circuit of Figure 2 comes out of shutdown

frequently enough to maintain regulation even under low-

load conditions. Since the part spends nearly all of its time

in shutdown, the no-load quiescent current is essentially

zero. However, the part will still be in operation during

the time the SHDN pin is high, so the current will not be

zero and can be calculated using the following equations

to determine the approximate maximum current: IIN(MAX)

= [(Time out of shutdown) • (Burst Mode operation qui-

escent current) + (Normal operating IIN) • (Time output

is being charged before the LTC1983 enters Burst Mode

operation)]/(Period of SHDN signal). This number will be

highly dependent on the amount of board leakage current

and how many devices are connected to VOUT (each will

draw some leakage current) and must be calculated and

verified for each different board design.

The LTC1983 must be out of shutdown for a minimum

duration of 200µs to allow enough time to sense the out-

put and keep it in regulation. A 1Hz, 2% duty cycle signal

will keep VOUT in regulation under no-load conditions.

Even though the term no-load is used, there will always

be board leakage current and leakage current drawn by

anything connected to VOUT. This is why it is necessary

to wake the part up every once in a while to verify regula-

tion. As the VOUT load current increases, the frequency

with which the part is taken out of shutdown must also

be increased to prevent VOUT from drooping below the

– 2.88V (for the 3V version) during the OFF phase (see

Figure 3). A 100Hz, 2% duty cycle signal on the SHDN pin

ensures proper regulation with load currents as high as

100µA. When load current greater than 100µA is needed,

the SHDN pin must be forced high as in normal operation.

Each time the LTC1983 comes out of shutdown, the part

delivers a minimum of one clock cycle worth of charge to

the output. Under high VIN (>4V) and/or low IOUT (<10µA)

conditions, this behavior may cause a net excess of charge

to be delivered to the output capacitor if a high frequency

signal is used on the SHDN pin (e.g., 50Hz to 100Hz). Under

such conditions, VOUT will slowly drift positive and may

even go out of regulation. To avoid this potential problem

VIN

GND

C+

SHDN

VOUT

C–

LTC1983-3

CFLY

1µF

CERAMIC

FROM MPU

SHDN

VIN

CIN

10µF

TANTALUM COUT

10µF

CERAMIC

SHDN PIN WAVEFORMS:

LOW IQ MODE

(IOUT ≤ 100µA)

VOUT LOAD ENABLE MODE

(IOUT = 100µA TO 100mA)

(1Hz TO 100Hz, 2% TO 5% DUTY CYCLE)

–3V ± 4%

1983 F02

3.3V TO 5.5V

Figure 2. Ultralow Quiescent Current Regulated Supply

(Refer to Block Diagram)

LTC1983-3/LTC1983-5

1983fc

For more information www.linear.com/LTC1983-3

operaTion

(Refer to Block Diagram)

in the low IQ mode, it is necessary to switch the part in

and out of shutdown at the minimum allowable frequency

(refer to Figure 3) for a given output load.

General Layout Considerations

Due to the high switching frequency and high transient

currents produced by the LTC1983, careful board layout

is a must. A clean board layout using a ground plane and

short connections to all capacitors will improve perfor-

mance and ensure proper regulation under all conditions

(refer to Figures 4a and 4b). You will not get advertised

performance with careless layout.

OUTPUT CURRENT (µA)

100

1000

MAXIMUM SHDN OFF TIME (ms)

1000

1983 F03b

1 10 100

SHDN ON PULSE WIDTH = 200µs

COUT = 10µF

1 VIN

2 VOUT

3 C+

SHDN 6

GND 5

C– 4

COUT

CFLY

VIN: 2.3V TO 5.5V

VOUT

1983 F04a

CIN

1 VIN

2 VOUT

3 C+

SHDN 6

GND 5

C– 4

CIN

COUT

CFLY

VOUT

1983 F04b

BOTTOM LAYER TOP LAYER

Figure 3

Figure 4a. Recommended Component

Placement for a Single Layer Board

Figure 4b. Recommended Component

Placement for a Double Layer Board

LTC1983-3/LTC1983-5

1983fc

For more information www.linear.com/LTC1983-3

Typical applicaTions

2.5V to –2.5V DC/DC Converter

100mA Inverting DC/DC Converter

VIN

SHDN

C+

VOUT

GND

C–

LTC1983-5

VIN

2.5V

VOUT

–2.5V

1µF

CERAMIC

4.7µF

CERAMIC

0.47µF

CERAMIC

OFF ON

1983 TA03

VIN

SHDN

C+

VOUT

GND

C–

LTC1983-5

VIN

2.5V TO 5.5V

VOUT

–VIN

10µF

CERAMIC

1µF

CERAMIC

OFF ON

1983 TA04

LTC1983-3/LTC1983-5

1983fc

For more information www.linear.com/LTC1983-3

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

package DescripTion

Please refer to http://www.linear.com/product/LTC1983#packaging for the most recent package drawings.

1.50 – 1.75

(NOTE 4)

2.80 BSC

0.30 – 0.45

6 PLCS (NOTE 3)

DATUM ‘A’

0.09 – 0.20

(NOTE 3) S6 TSOT-23 0302

2.90 BSC

(NOTE 4)

0.95 BSC

1.90 BSC

0.80 – 0.90

1.00 MAX 0.01 – 0.10

0.20 BSC

0.30 – 0.50 REF

PIN ONE ID

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

3.85 MA

0.62

MAX

0.95

REF

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

1.4 MIN

2.62 REF

1.22 REF

S6 Package

6-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1636)

LTC1983-3/LTC1983-5

1983fc

For more information www.linear.com/LTC1983-3

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER

B 06/16 Revised ROUT vs CF LY (VIN = 5V) graph. 4

C 09/16 Corrected Order Information table. 2

(Revision history begins at Rev B)

LTC1983-3/LTC1983-5

1983fc

For more information www.linear.com/LTC1983-3

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

 LINEAR TECHNOLOGY CORPORATION 2002

LT 0916 REV C • PRINTED IN USA

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC1983-3

relaTeD parTs

Typical applicaTion

PART NUMBER DESCRIPTION COMMENTS

LTC1261 Switched-Capacitor Regulated Voltage Inverter Selectable Fixed Output Voltages

LTC1261L Switched-Capacitor Regulated Voltage Inverter Adjustable and Fixed Output Voltages, Up to 20mA IOUT, MSOP

LTC1429 Clock-Synchronized Switched-Capacitor Voltage Inverter Synchronizable Up to 2MHz System Clock

LTC1514/LTC1515 Step-Up/Step-Down Switched-Capacitor DC/DC Converters VIN 2V to 10V, Adjustable or Fixed VOUT, IOUT to 50mA

LTC1516 Micropower Regulated 5V Charge Pump DC/DC Converter IOUT = 20mA (VIN ≥ 2V), IOUT = 50mA (VIN ≥ 3V)

LTC1522 Micropower Regulated 5V Charge Pump DC/DC Converter IOUT = 10mA (VIN ≥ 2.7V), IOUT = 20mA (VIN ≥ 3V)

LTC1550L/LTC1551L Low Noise, Switched-Capacitor Regulated Voltage Inverters 900kHz Charge Pump, 1mVP-P Ripple

LT1611 1.4MHz Inverting Mode Switching Regulator –5V at 150mA from a 5V Input, 5-Lead ThinSOT

LT1617/LT1617-1 Micropower, Switched-Capacitor Voltage Inverter VIN 1.2V/1V to 15V; 350mA/100mA Current Limit

LTC1682/-3.3/-5 Doubler Charge Pumps with Low Noise LDO MS8 and SO-8 Packages, IOUT = 80mA, Output Noise = 60µVRMS

LTC1751/-3.3/-5 Doubler Charge Pumps VOUT =5V at 100mA; VOUT =3.3V at 80mA; ADJ; MSOP Packages

LTC1754/-3.3/-5 Doubler Charge Pumps with Shutdown ThinSOT Package; IQ = 13µA; IOUT = 50mA

LTC1928-5 Doubler Charge Pump with Low Noise LDO ThinSOT Output Noise = 60µVRMS; VOUT = 5V; VIN = 2.7V to 4V

LTC3200 Constant Frequency Doubler Charge Pump Low Noise, 5V Output or Adjustable

C+C–

LTC1983-3/

LTC1983-5

CFLY

1µF

CERAMIC

CBOOST

1µF

OFF ON

COUT2

10µF

CERAMIC

COUT1

10µF

CERAMIC

CIN

10µF

CERAMIC

1983 TA05

VIN

VIN VOUT VOUT

SHDN GND

VBOOST

VBOOST = 2VIN –2(VD)

Combined Unregulated Doubler

and Regulated Inverter