CX72300/1/2
Phase Noise
Application Note
101348A
February 2001
101348A Conexant
© 2001, Conexant Systems, Inc.
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101348A Conexant iii
Table of Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Phase Noise Contributors in a PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Step Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Crystal Oscillator Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
CX7230x Synthesizer Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Phase/Frequency Detector and Divider Noise Floors . . . . . . . . . . . . . . . . . . . . . 5
Delta-Sigma Quantization Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VCO Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Effects of Larger Loop Bandwidths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table of Contents CX72300/1/2
Phase Noise
iv Conexant 101348A
CX72300/1/2 List of Figures
Phase Noise
101348A Conexant v
List of Figures
Figure 1. PLL Synthesizer Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Typical Delta-Sigma Quantization Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Typical VCO Free Running Phase Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Measured Total Phase Noise Performance of CX72300 Main Synthesizer. . . . . . . . . . . . . . 11
List of Figures CX72300/1/2
Phase Noise
vi Conexant 101348A
101348A Conexant 1
Phase Noise
This Application Note describes the total output phase noise performance of a PLL when using the
Conexant CX7230x family of synthesizer ICs.
Phase Noise Contributors in a PLL
In any oscillator, the intention is to generate a single tone sinewave that has constant amplitude and
frequency. In a real application, assuming the amplitude is constant, there would appear random
spectral components caused by thermal noise, 1/f noise of transistors and the finite Q of a resonant
circuit. These random spectral components can be collectively viewed on a spectrum analyzer as
phase noise.
The total output phase noise of a PLL is determined by three factors:
1. crystal oscillator phase noise,
2. synthesizer phase noise, and
3. VCO phase noise.
Step Size
The Conexant CX7230x family of synthesizers achieve their step size by using a ∆Σ fractional-N
modulator. As a result of this, there are some differences in calculating total phase noise compared
to the techniques applied to integer-N synthesizers. This will be closely examined in order to fully
appreciate the impact that step size has on the total phase noise of a PLL.
The Conexant CX72301 and CX72300 synthesizers features 18-bit fractionality on the main
synthesizer portion, which gives a resolution of 262,144 steps with respect to the internal reference
frequency. The CX72302 features a 16-bit resolution. These step sizes are related to the internal
reference and not to the output frequency, which means that there will be the same step size in the
1.0 GHz version or the 2.1 GHz version PLL.
The formula for computing the step size is:
[1]
where:
[2]
Step size [Hz] FXtal R
218
-------------------=
RF
Xtal Fref
=
Phase Noise CX72300/1/2
Phase Noise Contributors in a PLL Phase Noise
2Conexant 101348A
Example 1: Using a 20 MHz crystal and a reference division of R = 1 yields,
This represents the minimum step size achievable with a 20 MHz crystal oscillator and R=1.
Example 2: Using a 20 MHz crystal and a reference division of R = 32 yields,
This represents the minimum step size achievable with a 20 MHz crystal oscillator and R=32.
The 2.38 Hz and 76.29 Hz step sizes represent the minimum and maximum values when using
a 20 MHz crystal and 18-bit resolution. The difference is due to selecting a different value of R
which sets the internal reference frequency.
In an integer-N synthesizer, the crystal reference is divided by an integer number to achieve an
internal frequency which is equal to the step size.
In these conventional dual modulus loops, the step size is a result of the VCO being divided
down in frequency by a prescaler that only produces integer divisions.
The net result is that the step size is equal to the reference frequency at the phase detector.
Therefore, the divide ratio can be integers such as 46, 47, 48, etc.
In a ∆Σ-based synthesizer, the prescaler is modulated in a statistical fashion to realize division
ratios that are not restricted to integers.
An 18-bit ∆Σ fractional-N synthesizer can make the resolution 262144 finer in step size. In
other words, there are 262144 steps between 46 and 47 and so on.
Let us look at the differences in generating the step size in an integer-N and fractional-N and
what they mean to the resultant value of N in a PLL.
Example 3: Calculate the value of N in a 900 MHz integer-N PLL to generate a 6.25 kHz step
size using a 20 MHz crystal.
Step size in an integer-N PLL is determined by:
[3]
This means that the crystal frequency has been divided by 3200 to achieve a step size of
6.25 kHz.
In an integer-N PLL, step size is also equal to the internal reference frequency. Therefore, the
internal reference frequency is also 6.25 kHz.
Step size 20 MHz 1
262,144
--------------------------=
Step size 76.29 Hz=
Step size 20 MHz 32
262,144
-----------------------------=
Step size 2.38 Hz=
Step size FXtal
R
-----------=
6.25 kHz 20 MHz
R
-------------------=
R3200=
CX72300/1/2 Phase Noise
Phase Noise Phase Noise Contributors in a PLL
101348A Conexant 3
To calculate N, apply the following equation:
[4]
Therefore, an integer-N synthesizer PLL with an output of 900 MHz and a step size of 6.25 kHz
has N equal to 144,000.
Example 4: Calculate the value of N in a 900 MHz PLL using the CX72301 fractional-N
synthesizer to generate a 6.25 kHz step size using a 20 MHz crystal.
Using the formula [3] for calculating step size in a fractional-N and making R = 1,
As we can see the resultant step size is 76 Hz which exceeds the 6.25 kHz specification by 82
times.
To calculate N, use the following equation:
R = 1 means that Fref is equal to FXtal therefore,
Therefore, using the CX72301 fractional-N synthesizer to generate a 900 MHz output with a
76 Hz step size means that N is 45.
As a result, the integer-N PLL needed a large N value of 144,000 to achieve the required
6.25 kHz step size, where the 18-bit fractional-N PLL only needed N to be 45 while achieving a
76 Hz step size.
When using the Conexant synthesizers in fractional-N mode, it is recommended that a crystal
reference frequency of less than 25 MHz be divided down only to achieve extremely fine resolution
(see Delta Sigma Quantization Noise and Synthesizer Phase Noise below). This will ensure a
superior performance with respect to phase noise.
Reference division is required when a crystal frequency between 25 and 50 MHz is used, in
which case this crystal frequency must be divided down to 25 MHz or less by choosing a value of
R = 2. This ensures that the final value of the internal reference frequency is below the maximum of
25 MHz.
NFout
Fref
---------=
N900 MHz
6.25 kHz
----------------------=
N 144,000=
Step size 20 MHz 1
262,144
--------------------------=
N900 MHz
20 MHz
----------------------=
N45=
Phase Noise CX72300/1/2
Phase Noise Contributors in a PLL Phase Noise
4Conexant 101348A
Crystal Oscillator Phase Noise
The dominant close-in phase noise contributor to the total phase noise is the crystal oscillator phase
noise multiplied by the division ratio N divided by the internal reference divider. The N/R term
relates the internal reference back to the crystal frequency.
[5]
where:
Example 5: Calculate the added phase noise to a 20 MHz crystal in a PLL operating at
920 MHz with R = 1. As R = 1 the formula reduces to 20 log (N).
Therefore, the additional phase noise contribution of 33 dB is added to the original phase noise
of the crystal.
Example 6: Using the 33 dB additional phase noise, calculate the resultant phase noise of the
crystal at a 10 kHz offset where the original crystal oscillator phase noise was –130 dBc/Hz at the
10 kHz offset.
Therefore, measured at 10 kHz offset from the carrier, the multiplied phase noise contribution
of a 20 MHz crystal that has a –130 dBc/Hz phase noise brings the total phase noise of a 920 MHz
synthesizer PLL to –97 dBc/Hz.
The previous calculations were performed using an external crystal oscillator. The Conexant
CX7230x synthesizers have an integrated internal crystal oscillator that operates at up to 50 MHz
and has a phase noise floor of –130 dBc/Hz. The internal reference frequency Fref, has a maximum
frequency of 25 MHz.
Crystal phase noise contributions are typically greater in PLL systems with small step size
employing integer-N synthesizers. In this case, the internal reference of the synthesizer will be
divided down significantly to achieve a very fine step size.
Figure 1. PLL Synthesizer Loop
/ R
/ N
FXtal Fref VCO
V
Tune
Fout
∆Σ
A
B
C
101348_001
20 log (N/R)
NFout
Fref
---------=
Added Phase Noise 20 920 MHz
20 MHz
----------------------
èø
æö
log=
Added Phase Noise 33 dB=
130 dBc–Hz33dB+97 dBc–Hz=
CX72300/1/2 Phase Noise
Phase Noise Phase Noise Contributors in a PLL
101348A Conexant 5
As we saw earlier, when the crystal frequency is multiplied up, the phase noise increases by
20 log (N). However, when the crystal frequency is divided down as occurs when R is greater than
1, the divided down internal reference frequency Fref also has the phase noise decreased at the same
rate of 20 log (N). This means that if Fref has been divided down from FXtal, the phase noise seen at
Fref will have a better phase noise than that of the original crystal.
Example 7: Calculate the crystal phase noise contribution at the VCO output to the total phase
noise of a PLL when N has a value of 144,000 as in Example 3, R = 1 and a phase detector noise
floor of –150 dBc / Hz.
The resultant value of –46 dBc/Hz would make a very noisy PLL design.
CX7230x Synthesizer Phase Noise
The three sources of phase noise in a delta-sigma fractional-N synthesizer are the:
1. divider noise floor
2. multiplied phase/frequency detector noise floor, and
3. quantization noise of the delta-sigma modulator.
The divider phase noise and the multiplied phase/frequency detector noise floor normally
contribute phase noise inside the loop bandwidth. The quantization noise normally occurs around
1-10 MHz offset from the carrier.
Phase/Frequency Detector and Divider Noise Floors
The CX7230x Fractional-N Synthesizer family possesses internal VCO divider circuits. As such, it
is difficult to discern the divider noise from the phase/detector noise floor. This being the case, we
will refer to the combined divider and phase/frequency detector noise floor as simply the
phase/frequency detector noise floor (–135 dBc/Hz for the CX7230x series). This occurs at Point A
in Figure 1 of the PLL synthesizer diagram.
As in the case of the crystal phase noise example, systems employing integer-N require the
internal reference frequency to be very low in order to achieve the required step size. This causes the
multiplied phase detector noise to rise inside the loop bandwidth. In this case, the noise floor is set
by the noise floor of the phase/frequency detector plus the 20 log (N) factor.
Example 8: Calculate the phase noise contribution of an integer-N synthesizer used to generate
a 920 MHz output with a step size of 30 kHz.
The internal reference frequency is 30 kHz. We can now calculate the phase noise using
20 log (N).
Where N is:
Therefore,
VCO Output Phase Noise due to Crystal Oscillator Phase Noise 150 dBc Hz 20 log 144,000()+=
VCO Output Phase Noise due to Crystal Oscillator Phase Noise 46 dBc Hz=
NFout
Fref
---------=
2
0log 920 MHz
30 kHz
----------------------
èø
æö
89.7 dB=
Phase Noise CX72300/1/2
Phase Noise Contributors in a PLL Phase Noise
6Conexant 101348A
The value of N is 3833. The 89.7 dB result is now added to the phase/frequency detector noise
floor.
If the phase/frequency detector noise floor of the synthesizer is –150 dBc/Hz at an internal
reference frequency of 30 kHz, the resultant value would be:
The result of –60 dBc/Hz would be the phase/frequency detector noise contribution inside the
loop bandwidth to the total phase noise of the PLL. To determine the total output phase noise, the
multiplied noise contribution of the crystal oscillator must be added to this value.
Example 9: Calculate the phase noise contribution of the Conexant CX72301 fractional-N
synthesizer used to generate a 920 MHz output with a step size of 30 kHz.
As the CX72301 uses fractional-N to achieve step size, the internal reference is not a small
multiple of the required step size. The internal reference is determined by the crystal reference
frequency divided by R (see Crystal Oscillator Phase Noise). Therefore, we need to know the crystal
reference frequency and the value of the reference divider R. Assume a 20 MHz crystal and R = 1.
With the reference divider R = 1, the internal reference frequency is equal to the crystal reference
frequency of 20 MHz.
Now calculate 20 log (N) where:
The value of N is 46. The 33 dB result is now added to both the phase/frequency detector noise
floor and the crystal oscillator noise floor.
The phase/frequency detector noise floor of the CX72301 synthesizer is –135 dBc/Hz, while
the crystal oscillator noise floor is –130 dB/Hz, therefore:
The –102 dBc/Hz contribution of the phase/frequency detector must be added to the
–97 dBc/Hz noise contribution of the crystal oscillator, yielding an output phase noise at the VCO
of –95.8 dB/Hz measured inside the loop bandwidth (keep in mind that if the reference divider was
set to R = 2, then the crystal reference noise floor at the phase detector input would then be 6 dB
better, or –135 dBc/Hz.
This offers a significant improvement over the phase noise performance that an integer-N
solution could provide (compare with Example 8). What is more, the CX72301 Fractional-N
solution offers a step size of 76 Hz as an added benefit.
150 dBc–Hz89.7dBc+60 dBc–Hz=
NFout
Fref
---------=
20 log 920 MHz
20 MHz
----------------------
èø
æö
33 dB=
135 dBc–Hz33dB+102 dBc Hz phase detector noise contribution=
130 dBc–Hz33dB+97 dBc Hz crystal oscillator noise contribution=
CX72300/1/2 Phase Noise
Phase Noise Phase Noise Contributors in a PLL
101348A Conexant 7
Delta-Sigma Quantization Noise
Because the Conexant synthesizers use a ∆Σ modulator to achieve the fractionality, the designer
must be aware of the far-out quantization noise. This quantization noise occurs at point B in
Figure 1 of the PLL synthesizer diagram. The quantization noise is only added to the feedback loop
and not to the VCO noise; as a result, the quantization noise is attenuated by the loop filter.
The clock frequency of the ∆Σ modulator is set by the internal reference frequency.
where:
[6]
The formula is:
[7]
Example 10: Calculate the clock frequency of the ∆Σ modulator if the crystal frequency is 50
MHz crystal and R = 2,
This yields a 25 MHz ∆Σ modulator clock frequency.
Two factors are related to the internal reference that effect quantization noise.
The first is, as the internal reference frequency increases, the amplitude of the quantization
noise decreases. Increasing the internal reference frequency by a factor of 10, decreases the
quantization noise by approximately 70 dB.
The second is, as the internal reference frequency increases, the frequency at which the
quantization noise will occur increases proportionally as well. Increasing the internal reference
frequency by a factor of 10, increases the frequency of the quantization noise by 10.
These are two additional reasons for keeping the internal reference frequency high. Having a
low internal reference frequency would significantly raise the quantization noise and also move it
inside the loop bandwidth where the loop filter could not attenuate it.
Figure 2. Typical Delta-Sigma Quantization Noise
FModulator Fref
=
FModulator
FXtal
R
------------=
FModulator
50 MHz
2
-------------------=
SSB Phase Noise (dBc/Hz)
Frequency (Hz)
1 x 1041 x 1051 x 1061 x 1071 x 108
101348_003
20
40
60
80
100
120
140
160
Phase Noise CX72300/1/2
Phase Noise Contributors in a PLL Phase Noise
8Conexant 101348A
VCO Phase Noise
The free running phase noise of the VCO is typically the dominant contribution to the total phase
noise outside the loop bandwidth and sets the far-out phase noise of the PLL. This occurs at point C
in Figure 1.
Inside the loop bandwidth the VCO phase noise is attenuated by the loop filter. As the loop
bandwidth increases the VCO phase noise contribution inside the loop decreases.
In a single loop PLL architecture, the VCO free running phase noise cannot be corrected
outside the loop filter bandwidth. As a result, it is essential that VCO free running phase noise from
about 100 kHz to 10 MHz be below the required system phase noise mask, or to correct for the VCO
phase noise the loop filter bandwidth would have to be extremely large.
In a fractional-N synthesizer the loop bandwidth can be much larger than in traditional
synthesizers, however making the bandwidth too large would be impractical as the crystal oscillator
phase noise, synthesizer phase noise and quantization noise contributions would be affected.
Typical VCO free running phase noise is 150 to 140 dBc/Hz at a 10 MHz frequency offset
and 120 to 110 dBc/Hz at a 100 kHz frequency offset.
In selecting a VCO with poor phase noise, the designer may be faced with trading off the VCO
phase noise inside the loop against the crystal oscillator and synthesizer phase noise.
Figure 3. Typical VCO Free Running Phase Noise
SSB Phase Noise (dBc/Hz)
Frequency (Hz)
1 x 1031 x 1041 x 1051 x 1061 x 1071 x 108
101348_004
40
60
80
100
120
140
160
CX72300/1/2 Phase Noise
Phase Noise Phase Noise Contributors in a PLL
101348A Conexant 9
Loop Bandwidth
Loop bandwidth in this document refers to the unity gain open loop bandwidth.
Larger loop bandwidths can be achieved with Conexant CX7230x ICs over traditional
synthesizers due to the following four reasons:
1. Higher Internal Reference Frequency
PLL synthesizer loop bandwidth is normally limited to 1/10 the internal reference
frequency.
As the CX7230x series can have an internal reference frequency as high as 25 MHz while
maintaining very fine step size, this is not a limiting factor.
2. Crystal Oscillator Phase Noise
The relatively small value of 20 log (N) which is added to the crystal oscillator phase noise
reduces the PLL close-in phase noise.
3. Phase/Frequency Detector Noise Floor
The multiplied noise floor of the phase/frequency detector is below that of traditional
synthesizers because the value of N is relatively small. This reduces the resultant
synthesizer phase noise contribution inside the loop bandwidth.
Effects of Larger Loop Bandwidths
Increasing the loop bandwidth frequency has both positive and negative effects on the overall PLL
performance as indicated below.
Switching Time
The switching time of the PLL decreases as the loop bandwidth increases. To improve acquisition
time the loop bandwidth should be increased.
The speed is approximated using:
[8]
Example 11: Using a 35 kHz loop bandwidth,
which yields approximately 143 µs switching time.
VCO Phase Noise
The VCO phase noise is improved by the loop filter only inside the loop bandwidth. Therefore, as
the loop bandwidth is widened, the attenuation of the loop filter on the close-in VCO phase noise is
improved. To improve the close-in VCO phase noise the loop bandwidth frequency should be
increased.
Delta-Sigma Quantization Noise
The loop filter attenuates the quantization noise which typically occurs around 110 MHz.
Therefore, as the loop bandwidth increases, so does the quantization noise. To improve the
quantization noise the loop bandwidth frequency should be decreased.
Switching Time 5
Loop Bandwidth
----------------------------------------
Switching Time 5
35 kHz
-----------------
Phase Noise CX72300/1/2
Phase Noise Contributors in a PLL Phase Noise
10 Conexant 101348A
Crystal Oscillator Phase Noise
The loop filter attenuates the crystal oscillator phase noise outside the loop. Therefore, as the loop
bandwidth is increased, the point where the filter roll-off starts to attenuate the crystal oscillator
phase noise is moved higher in frequency as well. To improve the crystal oscillator phase noise, the
loop bandwidth frequency should be decreased.
Synthesizer Phase Noise
The loop filter attenuates the synthesizer phase noise outside the loop bandwidth frequency.
Therefore, as the loop bandwidth is increased, the point where the filter roll-off starts to attenuate
the synthesizer phase noise gets moved higher in frequency as well. To improve the synthesizer
phase noise the loop bandwidth frequency should be decreased.
Microphonics
Larger loop bandwidths help the PLL recover quickly from the effects of microphonics. The crystal
oscillator is a piezoelectric device, which means that it is susceptible to short term phenomenon
such as shock, vibration, and thermal earthquakes. Thermal earthquakes are caused by the
mismatching of the coefficients of thermal expansion in the materials. This mismatch causes a
buildup of stress that is periodically relieved by a sudden shift in mechanical alignment, thus
inducing a mechanical shock.
Load Pulling of the VCO
With a larger loop bandwidth, the VCO will be less susceptible to any variations in the load. As a
result, the synthesizer can correct the VCO more quickly.
Otherwise, in a narrow loop, it is the reverse isolation of the VCO that is critical to protecting
against load pull.
CX72300/1/2 Phase Noise
Phase Noise Phase Noise Contributors in a PLL
101348A Conexant 11
In Figure 4, we can see the measured phase noise performance of the CX72300 PLL
synthesizer. A typical performance crystal oscillator and VCO were used in this example.
The loop filter has been optimized to 80 kHz to minimize the effect of the crystal, VCO and
quantization noise.
Figure 4. Measured Total Phase Noise Performance of CX72300 Main Synthesizer
101348_005
10 dB/
RL –50 dBc/Hz 10.0 kHz
–94.17 dBc/Hz
100 Hz Frequency Offset
From 1.200 GHz Carrier
SSB Phase Noise (dBc/Hz)
10 MHz
SPOT FRQ =
Crystal Oscillator Frequency 24 MHz
Internal Reference Frequency 12 MHz
PLL Output Frequency 1200 MHz
Loop Filter Bandwidth 80 kHz
Step Size 46 Hz
Phase Noise CX72300/1/2
Phase Noise Contributors in a PLL Phase Noise
12 Conexant 101348A
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India
Phone: (91-11) 692-4789
Fax: (91-11) 692-4712
Korea
Phone: (82-2) 565-2880
Fax: (82-2) 565-1440
Korea (Satellite)
Phone: (82-53) 745-2880
Fax: (82-53) 745-1440
Singapore
Phone: (65) 737 7355
Fax: (65) 737 9077
Japan
Phone: (81-3) 5371 1520
Fax: (81-3) 5371 1501
www.conexant.com
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