[AP1017] AP1017 12V 1ch H-Bridge Motor driver 1. Genaral Description The AP1017AEN is a 1 channel H-bridge Motor Driver corresponding to an operating voltage of 12V. It has a N-channel LDMOS FET for both high and low sides of output circuit, it is available in a small package. Additionally, the AP1017 has under voltage lock out and thermal shutdown circuits. It is suitable for driving various small motors. 2. Features Control Supply Voltage 2.7V ~ 3.6V Available for the input level of 1.8V Wide Motor Driver Operating Voltage 1.8V ~ 12V Maximum Output Current (DC) 1.56A@ Ta=25C Maximum Output Current (Peak) 3.3A(Ta=25C, within 5ms in each 200ms) H-Bridge On Resistance RON(TOP+BOT)=0.47 Built-in Under Voltage Lock Out circuit (UVLO) Built-in Thermal Shut Down circuit (TSD) Small Package 8-pin SON 015000991-E-00 -1- 2015/03 [AP1017] 3. Table of Contents 1. 2. 3. 4. 5. 6. Genaral Description ....................................................................................................................................1 Features .......................................................................................................................................................1 Table of Contents ........................................................................................................................................2 Block Diagram ............................................................................................................................................3 Ordering Guide ...........................................................................................................................................3 Pin Configurations and Functions ...............................................................................................................4 Pin Configurations .....................................................................................................................................4 Functions ...................................................................................................................................................4 7. Absolute Maximum Ratings .......................................................................................................................5 8. Recommended Operating Conditions .........................................................................................................5 9. Electrical Characteristics ............................................................................................................................6 10. Control Logic...........................................................................................................................................8 11. Recommended External Circuits ...........................................................................................................10 12. Package ..................................................................................................................................................11 Outline Dimensions .................................................................................................................................11 Marking ...................................................................................................................................................11 13. Revise History .......................................................................................................................................12 IMPORTANT NOTICE ...................................................................................................................................13 015000991-E-00 -2- 2015/03 [AP1017AEN] 4. Block Diagram VC PS_bar PSAVEB EN INA INB VM TSD UVLO Control Logic CP OUTA H Bridge OUTB GND Exposed Pad(EP) (GND) Figure 1. Block Diagram 5. Ordering Guide AP1017AEN 015000991-E-00 -30C ~+ 85C 8-pin SON -3- 2015/03 [AP1017AEN] 6. Pin Configurations and Functions EN VC VM OUTA Pin Configurations 81 7 6 5 Exposed pad(GND) 3 4 OUTB 2 INB INA 1 PSAVEB Thermal Via (Top view) Functions Pin No. Pin Name I/O (Note 1) 1 INA I Control Signal Input Terminal Internally pull-down by 200k 2 INB I Control Signal Input Terminal Internally pull-down by 200k 3 PSAVEB I Power Save Input Terminal Internally pull-down by 200k 4 OUTB O Motor Driver Output Terminal 5 OUTA O Motor Driver Output Terminal 6 VM P Motor Driver Power Supply 7 VC P Control Power Supply 8 EN I Enable Signal Input Terminal Function Exposed GND P Ground Terminal Pad Note 1. I (Input terminal), O (Output terminal) and P (Power terminal) Note 2. Exposed pad must be connected to GND. 015000991-E-00 -4- Description Connect decoupling capacitor nearby. Connect decoupling capacitor nearby. Internally pull-down by 200k (Note 2) 2015/03 [AP1017AEN] 7. Absolute Maximum Ratings Parameter Control Supply Voltage Motor Driver Operating Voltage VC level terminal voltage (PSAVEB, EN, INA, and INB) VM level terminal voltage (OUTA, OUTB) Symbol VC VM min -0.5 -0.5 max 6 12 Unit V V Vterm1 -0.5 VC V Vterm2 -0.5 12 V -65 1.56 1.29 2.2 3.3 1786 1214 150 150 A A A A mW mW C C Maximum DC output current Iout1 Maximum peak output current Iout2 PD1 PD2 Tj Tstg Power Dissipation Condition Ta = 25C Ta = 65C within 10msec in 200msec within 5msec in 200msec (Note 4) Ta = 25C (Note 4) Ta = 65C Maximum Junction Temperature Storage Temperature Range Note 3. All voltages respect to GND. Note 4. When 4-layer board is used, this is calculated as JA=70C/W. Note 5. The each power supply of VM and VC is sequence-free. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Figure 2. Maximum Power Dissipation 8. Recommended Operating Conditions Parameter Control Supply Voltage Motor Driver Operating Voltage Input Frequency Range Operating Temperature Range 015000991-E-00 Symbol VC VM fPWM Ta min 2.7 1.8 -30 -5- typ 3.3 - max 3.6 12 200 85 Unit V V kHz C Description 2015/03 [AP1017AEN] 9. Electrical Characteristics Parameter UVLO VC under voltage lock out voltage Voltage hysteresis (Note 6) TSD Thermal shutdown temperature (Note 6) Temperature hysteresis (Note 6) Quiescent Current VM quiescent current at power save VC quiescent current at power save VM quiescent current at no power VM quiescent current at EN="L" VC quiescent current at EN="L" VC quiescent current at PWM operation Motor Driver On-resistance 1 (High side + Low side) (Ta = 25C, VM=7.2V and VC = 3.3V, unless otherwise specified.) Symbol Condition min typ max Unit VCUV VCUVHYS 1.8 0.005 2.1 0.1 2.4 0.25 V V TTSD 150 175 200 C TTSDHYS 20 30 40 C - 40 230 0.5 1 1 1 100 500 0.8 A A A A A mA - 0.47 0.54 - 0.55 0.60 - 0.64 0.73 - 0.8 0.45 0.20 0.33 0.50 1.2 1.0 1.0 1.0 2.0 V s s s s 0.6 0.9 - s 1.5 - VC V GND - 0.3 V - - 1 A 133 200 300 k IVMPS IVCPS IVMNP IVM IVC IVC PWM RON1 On-resistance 2 (High side + Low side) (Note 6) RON2 On-resistance 3 (High side + Low side) (Note 6) RON3 Body diode forward voltage Output delay time ("L""H") Output delay time ("H""L") Output delay time(Hi-Z"H")(Note 6) Output delay time("L"Hi-Z)(Note 6) VF tPDH tPDL tPDZH tPDHZ H-bridge output pulse width tPWO PSAVEB= "L" PSAVEB= "L" VC=0V EN="L", INA=INB= "L" EN="L", INA=INB= "L" fPWM=100kHz VC=3.3V, Iout=100mA, Ta=25C VC=3.3V, Iout=1.0A, Ta=25C (Equivalent to Tj=75C) VC=3.3V, Iout=1.29A, Ta=65C (Equivalent to Tj=150C) IF=100mA (Note 7, Figure 3) (Note 7, Figure 3) (Note 8, Figure 3) (Note 8, Figure 3) tPWI=1.0s tr=rf=10ns, fPWM=100kHz (Figure 3) Control Logic Input high level voltage VIH (INA, INB, EN, PSAVEB) Input low level voltage VIL (INA, INB, EN, PSAVEB) Input low level current IIL (INA, INB, EN, PSAVEB) Pull-down resistance RPD Note 6. Not tested in production. Note 7. Connect 1k between OUTA and OUTB. Note 8. Connect 1k between VM and OUTA/B, and OUTA/B and GND. 015000991-E-00 -6- 2015/03 [AP1017AEN] tf VC INA 50 90 INA % 50 tPDH tr 1u s 50 % 10 % tPDL VM VM 90 OUTB OUTB 50% tPWO 10 (a) Output Delay Time (INB="H") (b) Pulse Width (INB="H") VC VC 50 INA VC INA 50 tPDHZ tPDZH VM VM x 0.9 OUTB OUTB Hi-Z (c) Hi-Z "H" Delay Time (INB = "L") VM VM x 0.75(VM25%down) Hi-Z (d) "H" Hi-Z Delay Time (INB = "L") Figure 3. Time Chart (Output delay time, pulse width) 015000991-E-00 -7- 2015/03 [AP1017AEN] 10. Control Logic The AP1017 is suitable to drive DC motor and voice coil motor. If the input signals are fed to INA and INB, the output signals, OUTA and OUTB are decided as Table 1.The AP1017 includes Under Voltage Lock Out (UVLO) and Thermal Shut Down (TSD) circuits. The UVLO circuit monitors the control voltage (VC). If the VC is less than the specified voltage, the output of the H-bridge goes to high impedance. The TSD circuit monitors the chip temperature. If the temperature of the chip exceeds specified temperature, the output of the H-bridge goes to high impedance. UVLO circuit and TSD circuit have hysteresis levels. Table 1. Control logic truth table (X: don't care) Input Output Operation PSAVEB EN (Note 9) INA INB OUTA OUTB H H L L Hi-Z Hi-Z Standby(Coast) H H H L H L Forward (CW) H H L H L H Reverse (CCW) H H H H L L Brake H L X X L L Brake L X X X Hi-Z Hi-Z Power save (Note 10) Note 9. See Figure 4. Note 10. TSD, UVLO, Internal charge pump and VREF circuit stop operation. Forward (CW) Reverse (CCW) VM VM ON OFF OFF OUTB OUTA OUTB OUTA ON OFF ON OFF ON GND GND Brake Standby(Coast) VM OFF VM OFF OFF OUTB OUTA ON ON OFF OUTA OUTB OFF OFF GND GND Figure 4. Direction of current 015000991-E-00 -8- 2015/03 [AP1017AEN] VM VCUV+VCUVHYS VCUV+VCUVHYS VC VCUV VCUV EN UVLOB(internal signal) INA INB OUTA Hi-Z Hi-Z Hi-Z OUTB Hi-Z Hi-Z Hi-Z Coast Coast Break Break Coast Figure 5. Time Chart (UVLO) VM VCUV VCUV+VCUVHYS VC UVLOB TTSD TTSDTTSDHYS Temp TSD INA INB OUTA Hi-Z Hi-Z Hi-Z OUTB Hi-Z Hi-Z Hi-Z Coast Coast Coast Figure 6. Time Chart (TSD) 015000991-E-00 -9- 2015/03 [AP1017AEN] 11. Recommended External Circuits MCU INA INB PSAVEB OUTB 1 Exposed pad 8 2 7 3 6 4 5 EN VC VM CVC CVM VC VM OUTA M Figure 7. External circuit (Top view) Table 2. Recommended External Parts Parameter Symbol min typ max Unit Notes Motor driver power supply CVM 1.0 10 (Note 11) F (decoupling capacitor) Control power supply CVC 0.1 1.0 (Note 11) F (decoupling capacitor) Note 11. Decoupling capacitors of CVM and CVC should be placed close to the each IC terminal. And these capacitor values should be determined in consideration of the load current profile, the load capacitance, the wiring resistance and etc. of the actual system board. 015000991-E-00 - 10 - 2015/03 [AP1017AEN] 12. Package Outline Dimensions 8-pin SON (Unit: mm) Recommended foot pattern Top View 0.45 0.20 0.35 1.20 0.50 5 2.000.05 8 4 2.000.05 0.60 (max) 0.30 P=0.50 1.80 1.80 4 1.20 0.50 0.20 Note) Foot Pattern of Exposed pad must not surround the steam via hole. 8 5 0.30 P=0.50 Unit : mm Marking 1017 Market No. ABCD Date Code Pin #1 Indication ABCD: Date code (4 digit) A: Year code (last 1 digit) BC: Week code D: Management code 015000991-E-00 - 11 - 2015/03 [AP1017AEN] 13. Revise History Date (YY/MM/DD) 15/03/31 015000991-E-00 Revision Page 00 - Contents First Edition - 12 - 2015/03 [AP1017AEN] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation ("AKM") reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document ("Product"), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. 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