Description
The A4975 is designed to drive one winding of a bipolar
stepper motor in a microstepping mode. The outputs are
rated for continuous output currents to ±1.5 A and operating
voltages to 50 V. Internal pulse width modulated (PWM) current
control combined with an internal three-bit nonlinear digital-
to-analog converter allows the motor current to be controlled
in full-, half-, quarter-, or eighth-step (microstepping) modes.
Nonlinear increments minimize the number of control lines
necessary for microstepping. Microstepping provides increased
step resolution, and reduces torque variations and resonance
problems at low speed.
Internal circuitry determines whether the PWM current-control
circuitry operates in a slow (recirculating) current-decay
mode, fast (regenerative) current-decay mode, or in a mixed
current-decay mode in which the off-time is divided into a
period of fast current decay and with the remainder of the
fixed off-time spent in slow current decay. The combination of
user-selectable current-sensing resistor and reference voltage,
digitally selected output current ratio; and slow, fast, or mixed
current-decay modes provides users with a broad, variable
range of motor control.
4975-DS
Features and Benefits
▪ ±1.5 A continuous output current
▪ 50 V output voltage rating
▪ Internal PWM current control
▪ 3-bit nonlinear DAC
▪ Fast, mixed fast/slow, and slow current-decay modes
▪ Internal thermal shutdown circuitry
▪ Crossover-current and UVLO protection
Full-Bridge PWM Microstepping Motor Driver
Continued on the next page…
Functional Block Diagram
A4975
9
REF
D
D
D
28 14
D/A
2
1
0
V
V
CC
LOGIC
SUPPLY
6
PHASE
7
LOAD
SUPPLY
16
OUTA
OUTB
10 15
PFD 1+
–
BB
RC
GROUND
4
5
RS
SENSE
11
12
13
V
CC
BLANKING
UVLO
& TSD
Q
R
S
PWM LATCH
+ –
VTH
RT
CT
3
MIXED-DECAY
COMPARATOR
+
–
w5
DISABLE
CURRENT-SENSE
COMPARATOR
BLANKING
GATE
Not to scale
Package B, 16-pin DIP
with exposed tabs
Package LB, 16-pin SOIC
with internally fused pins
Packages:
Full-Bridge PWM Microstepping Motor Driver
A4975
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Description (continued)
Selection Guide
Part Number Packing Package
A4975SB-T 16-pin DIP with exposed thermal tabs 25 per tube
A4975SLBTR-T 16-pin SOICW with internally fused pins 1000 per reel
Internal circuit protection includes thermal shutdown with hysteresis,
an undervoltage monitor, and crossover-current protection. Special
power-up sequencing is not required.
The A4975 is supplied in a choice of two power packages; a 16-pin
dual-in-line plastic package with copper heat-sink tabs (suffix ‘B’),
and a 16-lead plastic SOIC with internally fused pins (suffix ‘LB’).
For both package styles, the thermally enhanced pins are at ground
potential and need no electrical isolation. Both packages are lead
(Pb) free, with leadframe plating 100% matte tin.
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Units
Load Supply Voltage VBB 50 V
Logic Supply Voltage VCC 6V
Logic/Reference Input Voltage Range VIN –0.3 to 6 V
Sense Voltage VS0.5 V
Output Current, Continuous IOUT
Output current rating may be limited by duty cycle, ambient
temperature, and heat sinking. Under any set of conditions, do
not exceed the specifi ed current rating or a junction tempera-
ture of 150°C.
±1.5 A
Package Power Dissipation PDSee graph W
Operating Ambient Temperature TARange S –20 to 85 ºC
Maximum Junction Temperature TJ(max)
Fault conditions that produce excessive junction temperature
will activate the device’s thermal shutdown circuitry. These
conditions can be tolerated but should be avoided.
150 ºC
Storage Temperature Tstg –55 to 150 ºC
Thermal Characteristics
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance, Junction
to Ambient RJA
B Package, single-layer PCB, 1 in.
2 2-oz. exposed copper 43 ºC/W
LB Package, 2-layer PCB, 0.3 in.
2 2-oz. exposed copper each
side 67 ºC/W
Package Thermal Resistance, Junction
to Tab RJT 6 ºC/W
*Additional thermal information available on Allegro website.
50 75 100 125 150
1
0
ALLOWABLE PACKAGE POWER DISSIPATION (W)
TEMPERATURE IN °C
4
3
2
25
R = 6.0°C/W
JT
SUFFIX 'B', R = 43°C/W
JA
SUFFIX 'LB', R = 67°C/W
JA
Full-Bridge PWM Microstepping Motor Driver
A4975
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Continued next page…
ELECTRICAL CHARACTERISTICS at TA = 25°C, VCC = 4.5 to 5.5 V (unless otherwise noted.)
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Power Outputs
Load Supply Voltage Range VBB Operating 5 — 50 V
Output Leakage Current ICEX
VOUT = VBB — <1.0 50 A
VOUT = 0 V — <-1.0 -50 A
Output Resistance RDS
Total Sink + Source, IOUT = 1.5 A ,
VBB > 8 V, TJ = 25°C — 1 1.4
Motor Supply Current (No Load) IBB(ON) D0 = D1 = D2 = VIN(1) — 500 700 A
IBB(OFF) D0 = D1 = D2 = VIN(0) — 250 500 A
Control Circuitry
Logic Supply Voltage Range VCC Operating 4.5 5.0 5.5 V
Reference Voltage Range VREF Operating 0.5 — 2.5 V
UVLO Enable Threshold VCC = 0 5 V 3.35 3.7 4.05 V
UVLO Hysteresis 0.3 0.45 0.6 V
Logic Supply Current ICC(ON) D0 = D1 = D2 = VIN(1) — 2.7 — mA
ICC(OFF) D0 = D1 = D2 = VIN(0) — 2.7 — mA
Logic Input Voltage
VIN(1)
VCC ×
0.55 —— V
VIN(0) ——
VCC ×
0.27 V
Logic Input Current IIN(1) VIN = VCC = 5 V — 0 –10 A
IIN(0) VIN = 0 V, VCC = 5 V — –106 –200 A
Mixed-Decay Comparator Trip
Points VPFD
Slow Current-Decay Mode 3.5 — — V
Mixed Current-Decay Mode 1.1 — 3.1 V
Fast Current-Decay Mode — — 0.8 V
Mixed-Decay Comparator Input
Offset Voltage VIO(PFD) — 0 ±50 mV
Mixed-Decay Comparator
Hysteresis VIO(PFD) 52555mV
Reference Input Current IREF VREF = 0.5 to 2.5 V — — ±5.0 A
Reference Divider Ratio VREF/VSAt trip, D0 = D1 = D2 = VIN(1) —5——
Digital-to-Analog Converter
Accuracy* —1.0 V < VREF 2.5 V — — ±3.0 %
0.5 V VREF 1.0 V — — ±4.0 %
Full-Bridge PWM Microstepping Motor Driver
A4975
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Control Circuitry (cont’d)
Current-Sense Comparator Input
Offset Voltage* VIO(S) VREF = 0 V — — ±5.0 mV
Step Reference Current Ratio SRCR
D0 = D1 = D2 = VIN(0) —0—%
D0 = VIN(1), D1 = D2 = VIN(0) — 19.5 — %
D0 = VIN(0), D1 = VIN(1), D2 = VIN(0) — 38.2 — %
D0 = D1 = VIN(1), D2 = VIN(0) — 55.5 — %
D0 = D1 = VIN(0), D2 = VIN(1) — 70.7 — %
D0 = VIN(1), D1 = VIN(0), D2 = VIN(1) — 83.1 — %
D0 = VIN(0), D1 = D2 = VIN(1) — 92.4 — %
D0 = D1 = D2 = VIN(1) — 100 — %
Thermal Shutdown Temp. TJ— 165 — °C
Thermal Shutdown Hysteresis TJ—15—°C
AC Timing
PWM RC Fixed Off-time tOFFRC CT = 470 pF, RT= 43 k18.2 20.2 22.3 s
PWM Minimum On Time tON(min)
VCC = 5.0 V, RT 43 k, CT = 470 pF,
IOUT = 100 mA 0.8 1.6 2.2 s
ELECTRICAL CHARACTERISTICS (continued) at TA = 25°C, VCC = 4.5 to 5.5 V (unless
otherwise noted.)
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
* The total error for the VREF/VS function is the sum of the D/A error and the current-sense comparator input offset voltage.
Table 3 — DAC Truth Table
DAC DATA Current
D
2 D
1 D
0 Ratio, % VREF/VS
H H H 100 5.00
H H L 92.4 5.41
H L H 83.1 6.02
H L L 70.7 7.07
L H H 55.5 9.01
L H L 38.2 13.09
L L H 19.5 25.64
L L L All Outputs Disabled
where VS = ITRIP×RS. See Applications section.
Table 1 — PHASE Truth Table
PHASE OUTA OUTB
H H L
L L H
Table 2 — PFD Truth Table
V
PFD Description
3.5 V Slow Current-Decay Mode
1.1 V to 3.1 V Mixed Current-Decay Mode
0.8 V Fast Current-Decay Mode
Full-Bridge PWM Microstepping Motor Driver
A4975
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Terminal Functions
Terminal Name Description
1 PFD (Percent Fast Decay) The analog input used to set the current-decay mode.
2 REF (VREF) The voltage at this input (along with the value of RS and the states of DAC inputs
D
0, D1, and D2) set the peak output current.
3 RC The parallel combination of external resistor RT and capacitor CT set the off time for the
PWM current regulator. CT also sets the blanking time.
4-5 GROUND Return for the logic supply (VCC) and load supply (VBB); the reference for all voltage
measurements.
6 LOGIC SUPPLY (VCC) Supply voltage for the logic circuitry. Typically = 5 V.
7 PHASE The PHASE input determines the direction of current in the load.
8 D2 (DATA2) One-of-three (MSB) control bits for the internal digital-to-analog converter.
9 D1 (DATA1) One-of-three control bits for the internal digital-to-analog converter.
10 OUTA One-of-two output load connections.
11 SENSE Connection to the sink-transistor emitters. Sense resistor RS is connected between this
point and ground.
12-13 GROUND Return for the logic supply (VCC) and load supply (VBB); the reference for all voltage
measurements.
14 D0 (DATA0) One-of-three (LSB) control bits for the internal digital-to-analog converter.
15 OUTB One-of-two output load connections.
16 LOAD SUPPLY (VBB) Supply voltage for the load.
Note the A4975SB (DIP) and the A4975SLB
(SOIC) are electrically identical and share a
common terminal number assignment.
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
GROUND
GROUND
LOGIC
SUPPLY
PHASE
GROUND
GROUND
RC
SENSE
D
REF
LOAD
SUPPLY
V
CC
OUTB
OUTA
V
BB
LOGIC
PFD
1
D0
D2
Full-Bridge PWM Microstepping Motor Driver
A4975
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Description
Two A4975 full-bridge PWM microstepping motor drivers are
needed to drive the windings of a bipolar stepper motor. Internal
pulse width modulated (PWM) control circuitry regulates each
motor winding current. The peak motor current is set by the
value of an external current-sense resistor (RS), a reference
voltage (VREF), and the digital-to-analog converter (DAC) data
inputs (D0, D1, and D2).
To improve motor performance, especially when using
sinusoidal current profi les necessary for microstepping, the
A4975 has three distinct current-decay modes: slow decay, fast
decay, and mixed decay.
PHASE Input. The PHASE input controls the direction of
current fl ow in the load (table 1). An internally generated dead
time of approximately 500 ns prevents crossover currents that
could occur when switching the PHASE input.
DAC Data Inputs (D0, D1, D2). A non-linear DAC is used
to digitally control the output current. The output of the DAC is
used to set the trip point of the current-sense comparator. Table 3
shows DAC output voltages for each input condition. When D0,
D1, and D2 are all logic low, all of the power output transistors
are turned off.
Internal PWM Current Control. Each motor driver
contains an internal fi xed off-time PWM current-control circuit
that limits the load current to a desired value (ITRIP). Initially,
a diagonal pair of source and sink transistors are enabled and
current fl ows through the motor winding and RS (fi gure 1). When
the voltage across the sense resistor equals the DAC output
voltage the current-sense comparator resets the PWM latch,
which turns off the source drivers (slow-decay mode) or the sink
and source drivers (fast- or mixed-decay mode).
With the DAC data input lines at VIN(1) voltage, the maximum
value of current limiting is set by the selection of RS and VREF
with a transconductance function approximated by:
ITRIP ≈ VREF / 5RS.
The actual peak load current (IPEAK) will be slightly higher than
ITRIP due to internal logic and switching delays. The driver(s)
remain off for a time period determined by a user-selected
external resistor-capacitor combination (RTCT). At the end of
the fi xed off-time, the driver(s) are re-enabled, allowing the load
current to increase to ITRIP again, maintaining an average load
current.
The DAC data input lines are used to provide up to eight levels
of output current. The internal 3-bit digital-to-analog converter
reduces the reference input to the current-sense comparator
in precise steps (the step reference current ratio or SRCR) to
provide half-step, quarter-step, or “microstepping” load-current
levels.
ITRIP ≈ SRCR x VREF / 5RS
Slow Current-Decay Mode. When VPFD ≥ 3.5 V, the
device is in slow current-decay mode (the source drivers are
disabled when the load current reaches ITRIP). During the fi xed
off-time, the load inductance causes the current to recirculate
through the motor winding and sink drivers (see fi gure 1).
Slow-decay mode produces low ripple current for a given fi xed
off-time (see fi gure 2). Low ripple current is desirable because
the average current in the motor winding is more nearly equal
to the desired reference value, resulting in increased motor
Figure 1 — Load-Current Paths
PFD
Dwg. WP-031-1
t
I
PEAK
OFF
SLOW (V ≥ 3.5 V)
PFD
MIXED (1.1 V ≤ V ≤ 3.1 V)
FAST (V ≤ 0.8 V)
PFD
PFD
Figure 2 — Current-Decay Waveforms
RS
VBB
Drive Current (Normal)
Recirculation (Fast Decay)
Recirculation (Slow Decay)
Full-Bridge PWM Microstepping Motor Driver
A4975
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 3 — Sinusoidal Drive Currents
performance in microstepping applications.
For a given level of ripple current, slow decay affords the lowest
PWM frequency, which reduces heating in the motor and driver
IC due to a corresponding decrease in hysteretic core losses and
switching losses respectively. Slow decay also has the advantage
that the PWM load current regulation can follow a more rapidly
increasing reference before the PWM frequency drops into the
audible range. For these reasons slow-decay mode is typically
used as long as good current regulation can be maintained.
Under some circumstances slow-decay mode PWM can fail to
maintain good current regulation:
1) The load current will fail to regulate in slow-decay mode
due to a suffi ciently negative back-EMF voltage in conjunction
with the low voltage drop across the load during slow decay
recirculation. The negative back-EMF voltage can cause the load
current to actually increase during the slow decay off time. A
negative back-EMF voltage condition commonly occurs when
driving stepping motors because the phase lead of the rotor
typically causes the back-EMF voltage to be negative towards
the end of each step (see fi gure 3A).
2) When the desired load current is decreased rapidly, the slow
rate of load current decay can prevent the current from following
the desired reference value.
3) When the desired load current is set to a very low value, the
current-control loop can fail to regulate due to its minimum duty
cycle, which is a function of the user-selected value of tOFF and
the minimum on-time pulse width ton(min) that occurs each time
the PWM latch is reset.
Fast Current-Decay Mode. When VPFD < 0.8 V, the
device is in fast current-decay mode (both the sink and source
drivers are disabled when the load current reaches ITRIP , and the
opposite pair is turned on). During the fi xed off-time, the load
inductance causes the current to fl ow from ground to the load
supply via the motor winding and the opposite pair of transistors
(see fi gure 1). Because the full motor supply voltage is across
the load during fast-decay recirculation, the rate of load current
decay is rapid, producing a high ripple current for a given fi xed
off-time (see fi gure 2). This rapid rate of decay allows good
current regulation to be maintained at the cost of decreased
average current accuracy or increased driver and motor losses.
A — Slow-Decay
B — Fast-Decay
C — Mixed-Decay
Full-Bridge PWM Microstepping Motor Driver
A4975
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Mixed Current-Decay Mode. If VPFD is between 1.1 V
and 3.1 V, the device will be in a mixed current-decay mode.
Mixed-decay mode allows the user to achieve good current
regulation with a minimum amount of ripple current and
motor/driver losses by selecting the minimum percentage of fast
decay required for their application (see also the Stepper Motor
Applications section).
As in fast current-decay mode, mixed-decay starts with the
sink and source drivers disabled and the opposite pair turned
on after the load current reaches ITRIP. When the voltage at the
RC terminal decays to a value below VPFD, the sink drivers are
re-enabled, placing the device in slow current-decay mode for
the remainder of the fi xed off-time (fi gure 2). The percentage
of fast decay (PFD) is user determined by VPFD or two external
resistors.
PFD = 100 ln (0.6[R1+R2]/R2)
where:
Dwg. EP-062-1
PFD
V
CC
R2
R1
Fixed Off-Time. The internal PWM current-control circuitry
uses a one shot to control the time the driver(s) remain(s) off.
The one-shot off-time, tOFF, is determined by the selection of
an external resistor (RT) and capacitor (CT) connected from the
RC timing terminal to ground. The off-time, over a range of
values of CT = 470 pF to 1500 pF and RT = 12 kΩ to 100 kΩ, is
approximated by:
tOFF ≈ RTCT.
When the load current is increasing, but has not yet reached the
sense-current comparator threshold (ITRIP), the voltage on the
RC terminal is approximately 0.6VCC. When ITRIP is reached,
the PWM latch is reset by the current-sense comparator and
the voltage on the RC terminal will decay until it reaches
approximately 0.22VCC. The PWM latch is then set, thereby
re-enabling the driver(s) and allowing load current to increase
again. The PWM cycle repeats, maintaining the peak load current
at the desired value.
With increasing values of tOFF, switching losses will decrease,
low-level load-current regulation will improve, EMI will be
reduced, the PWM frequency will decrease, and ripple current
will increase. A value of tOFF can be chosen for optimization
of these parameters. For applications where audible noise is a
concern, typical values of tOFF are chosen to be in the range of
15 to 35 μs.
RC Blanking. In addition to determining the fi xed off-time of
the PWM control circuit, the CT component sets the comparator
blanking time. This function blanks the output of the current-
sense comparator when the outputs are switched by the internal
current-control circuitry (or by the PHASE input, or when the
device is enabled with the DAC data inputs). The comparator
output is blanked to prevent false over-current detections due to
reverse recovery currents of the clamp diodes, and/or switching
transients related to distributed capacitance in the load.
During internal PWM operation, at the end of the tOFF time, the
comparator’s output is blanked and CT begins to be charged
from approximately 0.22VCC by an internal current source of
approximately 1 mA. The comparator output remains blanked
until the voltage on CT reaches approximately 0.6VCC. The
blanking time, tBLANK, can be calculated as:
tBLANK = RTCT ln (RT/[RT – 3 kΩ]).
When a transition of the PHASE input occurs, CT is discharged
to near ground during the crossover delay time (the crossover
delay time is present to prevent simultaneous conduction of
the source and sink drivers). After the crossover delay, CT is
charged by an internal current source of approximately 1 mA.
The comparator output remains blanked until the voltage on CT
reaches approximately 0.6VCC.
Similarly, when the device is disabled, via the DAC data inputs,
CT is discharged to near ground. When the device is re-enabled,
CT is charged by an internal current source of approximately 1
mA. The comparator output remains blanked until the voltage on
CT reaches approximately 0.6VCC. The blanking time, tBLANK,
can be calculated as:
tBLANK = RTCT ln ([RT - 1.1 kΩ]/RT - 3 kΩ).
The minimum recommended value for CT is 470 pF ± 5 %.
This value ensures that the blanking time is suffi cient to avoid
Full-Bridge PWM Microstepping Motor Driver
A4975
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
false trips of the comparator under normal operating conditions.
For optimal regulation of the load current, this value for CT is
recommended and the value of RT can be sized to determine tOFF.
Thermal Considerations. Thermal-protection circuitry
turns off all output transistors when the junction temperature
reaches approximately +165°C. This is intended only to protect
the device from failures due to excessive junction temperatures
and should not imply that output short circuits are permitted. The
output transistors are re-enabled when the junction temperature
cools to approximately +150°C.
Stepper Motor Applications. The A4975 is used to
optimize performance in microstepping/sinusoidal stepper-motor
drive applications (see fi gures 4 and 5). When the load current
is increasing, the slow current-decay mode is used to limit the
switching losses in the driver and iron losses in the motor. This
also improves the maximum rate at which the load current can
increase (as compared to fast decay) due to the slow rate of
decay during tOFF. When the load current is decreasing, the mixed
current-decay mode is used to regulate the load current to the
desired level. This prevents tailing of the current profi le caused
by the back-EMF voltage of the stepper motor (see fi gure 3A).
Figure 5 — Microstepping/Sinusoidal Drive Current
Dwg. WK-004-3
MIXED DECAY MIXED DECAYSLOW DECAY SLOW DECAY
Figure 4 — Typical Application
LOGIC LOGIC
Dwg. EP-047-3
D
1B
47 MF
+
30 k7
0.5 7
V
BB
PHASE
470 pF
+5 V
REF
PFD
D
2B
D
0B
BRIDGE B
D
1A
47 MF
+
11
30 k7
0.5 7
V
BB
PHASE
470 pF
+5 V
REF
PFD
D
2A
D
0A
BRIDGE A
A
B
V
V
V
V
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Full-Bridge PWM Microstepping Motor Driver
A4975
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Bridge A Bridge B
Full Half Quarter Eighth
Step Step Step Step PHASEA D
2A D
1A D
0A I
LOADA PHASEB D
2B D
1B D
0B I
LOADB
1 1 1 1 H H L L 70.7% H H L L 70.7%
2 H L H H 55.5% H H L H 83.1%
2 3 H L H L 38.2% H H H L 92.4%
4 H L L H 19.5% H H H H 100%
2 3 5 X L L L 0% H H H H 100%
6 L L L H -19.5% H H H H 100%
4 7 L L H L -38.2% H H H L 92.4%
8 L L H H -55.5% H H L H 83.1%
2 3 5 9 L H L L -70.7% H H L L 70.7%
10 L H L H -83.1% H L H H 55.5%
6 11 L H H L -92.4% H L H L 38.2%
12 L H H H -100% H L L H 19.5%
4 7 13 L H H H -100% X L L L 0%
14 L H H H -100% L L L H -19.5%
8 15 L H H L -92.4% L L H L -38.2%
16 L H L H -83.1% L L H H -55.5%
3 5 9 17 L H L L -70.7% L H L L -70.7%
18 L L H H -55.5% L H L H -83.1%
10 19 L L H L -38.2% L H H L -92.4%
20 L L L H -19.5% L H H H -100%
6 11 21 X L L L 0% L H H H -100%
22 H L L H 19.5% L H H H -100%
12 23 H L H L 38.2% L H H L -92.4%
24 H L H H 55.5% L H L H -83.1%
4 7 13 25 H H L L 70.7% L H L L -70.7%
26 H H L H 83.1% L L H H -55.5%
14 27 H H H L 92.4% L L H L -38.2%
28 H H H H 100% L L L H -19.5%
8 15 29 H H H H 100% X L L L 0%
30 H H H H 100% H L L H 19.5%
16 31 H H H L 92.4% H L H L 38.2%
32 H H L H 83.1% H L H H 55.5%
Table 4 — Step Sequencing
Full-Bridge PWM Microstepping Motor Driver
A4975
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 5 —
Current and Displacement Vectors
Dwg. GK-020-1
A
A
BB
100
92.4
83.1
70.7
55.5
38.2
19.5
10092.483.170.755.538.219.5
100% CONSTANT TORQUE
MAXIMUM FULL-STEP
TORQUE (141%)
CURRENT IN PER CENT
CURRENT IN PER CENT
7/8 STEP
3/4 STEP
5/8 STEP
1/2 STEP
3/8 STEP
1/4 STEP
1/8 STEP
FULL STEP
Full-Bridge PWM Microstepping Motor Driver
A4975
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
LB package 16-pin SOICW
9.50
0.65
2.25
1.27
C
SEATING
PLANE
C0.10
16X
1.27
0.25
0.20 ±0.10
0.41 ±0.10 2.65 MAX
10.30±0.33
7.50±0.10
4° ±4
0.27 +0.07
–0.06
0.84 +0.44
–0.43
10.30±0.20
21
16
GAUGE PLANE
SEATING PLANE For Reference Only
Pins 4 and 5, and 12 and 13 internally fused
Dimensions in millimeters
(reference JEDEC MS-013 AA)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
A
BReference pad layout (reference IPC SOIC127P1030X265-16M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
BPCB Layout Reference View
B package 16-pin DIP
2
19.05±0.25
5.33 MAX
0.46 ±0.12
1.27 MIN
1
16
A
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
6.35 +0.76
–0.25
3.30 +0.51
–0.38
10.92 +0.38
–0.25
1.52 +0.25
–0.38
0.38 +0.10
–0.05
7.62
2.54
For Reference Only
(reference JEDEC MS-001 BB)
Dimensions in millimeters
Full-Bridge PWM Microstepping Motor Driver
A4975
13
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Copyright ©2009-2011, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Revision History
Revision Revision Date Description of Revision
Final December 19, 2011 Update production availability
