CYPRESS SEMICONDUCTOR 4BE D) BE 2549bb2 0006248 O Eacyp T-U6-23-10 CY7C101 a PRELIMINARY CY7C102 CYPRESS SEMICONDUCTOR 262,144 x 4 Static R/(W RAM Features e High speed tsa = 25ns Transparent write (7C101) * @ CMOS for optimum speed/power Lowactive power 825 mW @ Lowstandby power 165 mW Automatic power-down when deselected e TTL-compatible inputs and outputs Functional Description TheCY7C101 andCY7C102arehigh-per- formance CMOS static RAMs organized as 262,144 x 4 bits with separate I/O, Easy memory expansion is provided by active LOW chip enable (CE) and three-state drivers. They have an automatic power- down feature, reducing the power con- sumption by more than 70% when dese- lected. Writing to the device is accomplished by taking both chip enable (CE) and write en- able (WE) inputs LOW. Data on the four input pins (Ip through Is) is written into the memory location specified on the address pins (Ag through A47). with Separate I/O Reading the device is accomplished by tak- ing chip enable (CE) LOW while write en- able (WE) remains HIGH. Under these conditions, the contents of the memory lo- cationspecifted on the address pinswill ap- pear on the four data output pins (Op through O3). The data output pins on the CY7C101 and the CY7C102 are placed in a high-impe- dance state when the device is deselected (CE HIGH). The CY7C102s outputs are also placed in a high-impedance state dur- ing a write operation (CE and WE LOW). Ina write operation on the CY7C101, the output pins will track the inputs after aspe- cified delay. The CY7C101 and 7C102 are available in 32-pin leadless chip carriers and standard 400-mil-wide DIPs and SOJs. Logic Block Diagram Pin Configurations ho hh LCC DIP/SOJ a Top View Top View ly NG D1 326 Voc NC Ate p 2 314 Ats Ate Ai p 3 309 Aa At INPUT BUFFER Agp4 299 Ay Ao Atos 286 As Ay 429 6 279 Aa Aa Ao ro Aio p 7 26g Az Ato Al a Ap 87 25q Ag An AS g g Aap 9 24q NC Aig ven 512 x512x4 2 o% A 239 4 Ata As a ARRAY ww Au 22g Ata Ag 3 i Op Ae 21g Oo Aa A; = 4 ly 20g h 2 e cE GND We GND COLUMN DECODER cto1-3 101-2 aor cE ECKERT Df eT WE beeee ast C1o1-1 Selection Guide 7C101-25 7010135 7C101-45 7C102-25 7C102-35 70102 45 Maximum Access Time (ns) 25 35 45 Maximum Operating Current (mA) Commercial 150 125 115 Military 150 125 . 115 Maximum Standby Current (mA) Commercial 30 25 25 Military 35 30 30 2-26SEMICONDUCTOR UbE D ES 258%bbe O00b269 2 EACYP eo CY7C101 S ppnss 7-Y6~R3-/O6____PRELIMINARY __CY7C102 Sess = =SEMICONDUCTOR ~ Maximum Ratings (Abovewhich the useful life may be impaired. Foruser guidelines, Static Discharge Voltage .-..+.+.+.ssseeeeeees see => 2001V not tested.) (per MIL-STD-883, Method 3015) Storage Temperature .......60005 veces 65Cta +150C _ Latch-Up Current ....-.ce-seererecererereenes >200mA Ambient Temperaturewith Operating Range PowerApplied ......seseeseeeeerecees 55C to +125C Ambient Supply Voltage on Vcc Relative to GNDIt 0.5V to +7.0V Range Temperaturel2l Vec DC Voltage Applied to Outputs ; o + 10% inEligh ZStatell-..sccscsesecsesseeses 0.5Vto-+7.0V Commercial OCto + 70C SV = 10% DC Input Voltage veeeeveueeeeeveeeves 08V to +7.0V Military 55C to + 125C SV + 10% Current into Outputs (Low) .......--. teneeeee veeee 20MA Electrical Characteristics Over the Operating Rangel 71C101~25 7C10135 7C101~35 7102-25 7C102-35 7C10235 Parameters Description Test Conditions Min. | Max. {Min.| Max. | Min. | Max. | Units Vou Output HIGH Vec = Min. 2.4 2.4 2.4 Vv Voltage Joy = 4.0mA Voi Output LOW Voltage | Vcc = Min., lor = 8.0mA 0.4 0.4 0.4 Vv Vin Input HIGH Voltage 2.2 1Vcec+0.3) 22 | Vcco+O3| 2.2 | Vcct 0.3] V Vit Input LOW Voltage! -03 08 |-03| 08 ~0.3 0.8 Vv Tx Input LoadCurrent | GND < Vi< Vcc -10 +10 -10 +10 10 +10 pA loz Output Leakage GND < Vi< Veo 10 +10 -10 +10 -10 +10 pA Current Output Disabled Tos Output Short Vcc = Max., Vour = GND 300 300 300 [| mA CircuitCurrent lec VccOperatingSupply | Vcc = Max., Com'l 150 425 115 mA Current Tour = OmA, - f=fyax=Wtpc | Mil 150 125 115 Ispi Automatic CE Power- | Max. Vcc, Com'l 30 25 25 mA DownCurrent CE > Vin, TTLInputs Vin > Virzor 7 VIN< Vite fi Mil 35 30 30 Isp2 Automatic CE Power- } Max. Vcc, Com'l 10 10 10 mA Down Current CE > Vcc 03V, ~- CMOS Inputs Vin = Voc ~ 0.3V ; or Vin < 03V,f=0 Mil 10 10 10 Capacitancel] _ . Parameters Description Test Conditions Max, Units Cw InputCapacitance Ta = 25C, f= 1 MHz, 10 pF Cour OutputCapacitance Vec = 5.0V 12 pF Notes: 1. Vin qin) = ~2.0V for pulse durations of less than 20 ns. 2. Taisthe instant on case temperature. 3, Seethe last page of this specification for Group A subgroup testing in- formation. 4. Notmore than l outputshouldbeshorted atone time. Duration of the short circuit should not exceed 30 seconds, 5. Tested initially and after any design or processchanges that may affect these parameters. 2-27 SRAMs mie54%9bbe2 0006290 9 Emcyp 4bBE ) =~ CY7C101 SSS F or. PRELIMINARY CY7C102 SSS & SEMICONDUCTOR = as AC Test Loads and Waveforms / SE - & 3 40 . Ri 480.0, Al 4800, BY Oe SV O14 ALL INPUT PULSES OUTPUT ~T ] ome , 90 PF 1 265.0. SOF 1 265.0. MIGAND Sr NCWGAND > oe SCOPE = SCOPE = = Cto1-5 . (a) : (b) Cto1~4 Equivalent to: THEVENIN EQUIVALENT , OUTPUT 0-0 1.73V Switching Characteristics Over the Operating Rangel 4 7C101~25 7C101-35 7C10145 7C10225 7102-35 7C102~45 Parameters Description Min, | Max. | Min. | Max. | Min. [ Max. | Units READ CYCLE tre Read Cycle Time 25 35 45 ns taa Address to Data Valid 25 35 45 ns toHa Data Hold from AddressChange 5 5 5 ns tace CE LOW to Data Valid 25 35 45 ns tLzcE CELOW to Low ZI] 5 5 5 ns tHzcE CEHIGH to High ZI? 81 10 15 20 ns tpu CELOW to Power-Up 0 0 0 ns tpp CE HIGH to Power-Down. 25 35 45 ns WRITE CYCLE! twe Write Cycle Time 25 35 45 ns tscE CELOW to Write End 20 25 30 ns taw Address Set-Up to Write End 20 25 30 ns tHa Address Hold from Write End 0 0 0 ns tsa Address Set-Up to Write Start 0 0 0 ns tpwe WE Pulse Width 20 25 30 ns tsp Data Set-Up to Write End 15 20 25 ns typ Data Hold from Write End 0 0 0 ns tLZwe WE HIGH to Low Zl7] 5 5 5 ns tyzweE WE LOW to High ZI? 8] 15 20 25 ns tpwe WE LOW to Data Valid(7C101) 20 25 30 ns tpce CE LOW to Data Valid(7C101) 25 35 45 ns tapv Data Valid to Output Valid (7C101) 20 25 30 ns Notes: : 6. Testconditions assume signal transition time of 5 ns orless, timing ref- erence levelsof 1,5V, input pulse levels of 0 to 3.0V, and output loading of the specified Io, lop and 30-pF load capacitance, At any given temperature and voltage condition, tyzcg is less than tizcg and tyzwe is less than tuzwe for any given device. tuzcr, and tyzwe are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured +500 mV from steady state voltage. qh 8 2-28 The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.cy uv gy =e SEMICONDUCTOR 7-98 o> 37/9 Switching Waveforms Read Cycle No. 1{10: 11] ! tre ADDRESS x x SRAMs nT taa >| k< ton, > DATA OUT PREVIOUS DATA VALID x*K DATA VALID C101--6 Read Cycle No. 2{11, 12) ADDRESS x sk cE tac __ NX. JS t pf thzce HIGH HIGH IMPEDANCE IMPEDANCE DATA OUT ee K DATA VALID me tice pee [wo SUPPLY 50% CURRENT soe Sk C101-7 Write Cycle No. 1 (CE Controlled)! 13] ADDRESS CE WE tsn DATA IN DATA VALID HIGH IMPEDANCE DATA OUT (7G102) ne Son) DATA VALID hizce crol-8 toce Notes: 10. Device is continuously selected. CE = Vit. 13. ECE goes HIGH simultaneously with WE going HIGH, the output 11. WEis HIGH for read cycle. remains in a high-impedance state (7C102 only). 12, Address valid prior to or coincident with CE transition LOW. 2-29 RESS SEMICONDUCTOR UbE D ES 258%bbe O00be4) o emcyP moe CY7C101 PRELIMINARY CY7C102CYPRESS SEMICONDUCTOR a, 1 ant PRESS == SEMICONDUCTOR HEE D MM 254%9bbe OO0be Ie 2 ECYP PRELIMINARY Switching Waveforms (continued) Write Cycle No. 2 (WE Controftea)(9 ADDRESS T=46-230 CE tpwe WE tsp tuo DATA IN DATA VALID tuzwe =| tiawe DATA OUT HIGH IMPEDANCE (7G102) towe tyzce paolo DATA VALID tanv Truth Table CE | WE Oo 03 Mode Power H | X | Highz Power-Down Standby (Isp) L | H } DataOut Read Active (Icc) L | L | Highz 7C102: Standard Write Active (Icc) L | L | Input Tracking | 7C101: Transparent Writel!4] | Active (Icc) Notes: 14, Outputs track inputs after specified delay. 2-30CYPRESS SEMICONDUCTOR eo PRESS SEMICONDUCTOR Ordering Information 4WbE D Ea 258%bb2 0006293 4 EACYP PRELIMINARY ~ CY7C101 CY7C102 7-96-2310 Speed Package | Operating Speed Package | Operating (ns) Ordering Code Type Range (ns) Ordering Code Type Range 25 CY7C10125DC D46 Commercial 25 CY7C10225DC D46 Commercial CY7C101-25LC L75 , CY7C102-25LC L75 CY7C10125PC P43 CY7C10225PC P43 CY7C101-25VC V33 CY7C10225VC V33 CY7C101-25DMB D46 |: Military CY7Ci0225DMB D416} Military CY7C101-25LMB L75 CY7C102--25LMB LI5 35 CY7C101-35DC D46 Commercial 35 CYX7C10235DC D46 Commercial CY7Ci01--35LC Lis CY7C10235LC L75 CY7C10135PC P43 CY7C10235PC P43. CY7C101-35VC V33 CY7C10235VC V33 CY7C101~35DMB D46 |: Military CY7C10235DMB D46 {| Military CY7C101-35LMB L75 CY7C102~35LMB L75 45 CY7C10145DC D46__| Commercial 45 CY7C10245DC D46 CY7C10145LC L75 CY7C10245LC LI5 CY7C101~45PC P43 CY7C10245PC P43 CY7C10145VC V33 CY7C10245VC V33 CY7C101-45DMB D46 | Military CY7C10245DMB D46 Military CY7C10145LMB L75 CY7C102--45LMB L75 MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameters Subgroups Vou 1,2,3 VoL 1,2,3 Vint 1,2,3 Vy Max. 1,2,3 Ix 1,2,3 loz 12,3 Icc 1,2,3 Ispi - 1,2,3 Isp 1,2,3 Document #: 3800148-B Switching Characteristics Parameters | Subgroups READ CYCLE tre 7,8, 9, 10, 1 taa 7, 8,9, 10, i1 foHA 7,8, 9, 10, 11 tacE 7,8, 9, 10, 11 WRITE CYCLE twe 7, 8,9, 10, 11 sce 7,8, 9, 10, 11 taw 7, 8, 9, 10, 11 ta 7, 8,9, 10, 11 tsa, 7,8, 9, 10, 1f tpwE 7,8, 9, 10, 11 tsp 7,8, 9, 10, 11 typ 7, 8,9, 10, 11 tpwell5l 7, 8, 9, 10, 11 tapvilil 7,8, 9, 10, 11 Note: __.15, 7C101 only. 2-31 ah SRAMs