MR4A08BYS35R - Everspin Technologies

MR4A08B

2M x 8 MRAM Memory

INTRODUCTION

The MR4A08B is a 16,777,216-bit magnetoresistive random access

memory (MRAM) device organized as 2,097,152 words of 8 bits.

The MR4A08B oers SRAM compatible 35ns read/write timing with

unlimited endurance. Data is always non-volatile for greater than

20-years. Data is automatically protected on power loss by low-

voltage inhibit circuitry to prevent writes with voltage out of specication. The

MR4A08B is the ideal memory solution for applications that must permanently store and retrieve critical

data and programs quickly.

The MR4A08B is available in small footprint 400-mil, 44-lead plastic small-outline TSOP type-II package or

10 mm x 10 mm, 48-pin ball grid array (BGA) package with 0.75 mm ball centers. These packages are com-

patible with similar low-power SRAM products and other non-volatile RAM products.

The MR4A08B provides highly reliable data storage over a wide range of temperatures. The product is

oered with commercial (0 to +70 °C), industrial (-40 to +85 °C), and AEC-Q100 Grade 1 (-40 to +125 °C)

operating temperature range options.

Document Number: MR4A08B Rev. 5, 9/20111

RoHS

CONTENTS

1. DEVICE PIN ASSIGNMENT......................................................................... 2

2. ELECTRICAL SPECIFICATIONS................................................................. 4

3. TIMING SPECIFICATIONS.......................................................................... 7

4. ORDERING INFORMATION....................................................................... 11

5. MECHANICAL DRAWING.......................................................................... 12

6. REVISION HISTORY...................................................................................... 14

How to Reach Us.......................................................................................... 14

FEATURES

• +3.3 Volt power supply

• Fast 35 ns read/write cycle

• SRAM compatible timing

• Unlimited read & write endurance

• Data always non-volatile for >20-years at temperature

• RoHS-compliant small footprint BGA and TSOP2 packages

• AEC-Q100 Grade 1 option in TSOP2 package.

BENEFITS

• One memory replaces FLASH, SRAM, EEPROM and BBSRAM in systems

for simpler, more ecient designs

• Improves reliability by replacing battery-backed SRAM

Document Number: MR4A08B Rev. 5, 9/20112

CHIP

ENABLE

BUFFER

OUTPUT

ENABLE

BUFFER

ADDRESS

BUFFER

WRITE

ENABLE

BUFFER

OUTPUT ENABLE

2M x 8 BIT

MEMORY

ARRAY

ROW

DECODER

COLUMN

DECODER

SENSE

AMPS

OUTPUT

BUFFER

WRITE

DRIVER

FINAL

WRITE

DRIVERS

WRITE ENABLE

A[20:0]

DQ[7:0]

1. DEVICE PIN ASSIGNMENT

Figure 1.1 Block Diagram

Table 1.1 Pin Functions

Signal Name Function

A Address Input

E Chip Enable

W Write Enable

G Output Enable

DQ Data I/O

VDD Power Supply

VSS Ground

DC Do Not Connect

NC No Connection

MR4A08B

VDD

VSS

DC 22

44 DC

VSS

VDD

A20 19

123456

G A A A A

AAEB

DQ AA

DQ C

VSS

VDD D

VDD

VSS E

A A

DQ F

NCNC

DCDC

DQ3

Document Number: MR4A08B Rev. 5, 9/20113

Figure 1.2 Pin Diagrams for Available Packages (Top View)

44 Pin TSOP2 48 Pin FBGA

Table 1.2 Operating Modes

E1G1W1Mode VDD Current DQ[7:0]2

H X X Not selected ISB1, ISB2 Hi-Z

L H H Output disabled IDDR Hi-Z

L L H Byte Read IDDR DOut

L X L Byte Write IDDW Din

1 H = high, L = low, X = don’t care

2 Hi-Z = high impedance

DEVICE PIN ASSIGNMENT MR4A08B

2. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

This device contains circuitry to protect the inputs against damage caused by high static voltages or

electric elds; however, it is advised that normal precautions be taken to avoid application of any

voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.

The device also contains protection against external magnetic elds. Precautions should be taken

to avoid application of any magnetic eld more intense than the maximum eld intensity specied

in the maximum ratings.

Document Number: MR4A08B Rev. 5, 9/20114

Parameter Symbol Value Unit

Supply voltage2VDD -0.5 to 4.0 V

Voltage on an pin2VIN

-0.5 to VDD +

0.5 V

Output current per pin IOUT ±20 mA

Package power dissipation PD0.600 W

Temperature under bias

MR4A08B (Commercial)

MR4A08BC (Industrial)

MR4A08BM (AEC-Q100 Grade 1)

TBIAS

-10 to 85

-45 to 95

-45 to 130

°C

Storage Temperature Tstg -55 to 150 °C

Lead temperature during solder (3 minute max) TLead 260 °C

Maximum magnetic eld during write

MR4A08B (All Temperatures) Hmax_write 8000 A/m

Maximum magnetic eld during read or standby Hmax_read 8000 A/m

1 Permanent device damage may occur if absolute maximum ratings are exceeded. Functional opera-

tion should be restricted to recommended operating conditions. Exposure to excessive voltages or

magnetic elds could aect device reliability.

2 All voltages are referenced to VSS.

3 Power dissipation capability depends on package characteristics and use environment.

Table 2.1 Absolute Maximum Ratings1

MR4A08B

Document Number: MR4A08B Rev. 5, 9/20115

Parameter Symbol Min Typical Max Unit

Power supply voltage VDD 3.0 i3.3 3.6 V

Write inhibit voltage VWI 2.5 2.7 3.0 i V

Input high voltage VIH 2.2 - VDD + 0.3 ii V

Input low voltage VIL -0.5 iii - 0.8 V

Temperature under bias

MR4A08B (Commercial)

MR4A08BC (Industrial)

MR4A08BM (AEC-Q100 Grade 1)iv

-40

125

°C

i There is a 2 ms startup time once VDD exceeds VDD,(min). See Power Up and Power Down Sequencing below.

ii VIH(max) = VDD + 0.3 VDC ; VIH(max) = VDD + 2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA.

iii VIL(min) = -0.5 VDC ; VIL(min) = -2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA.

iv AEC-Q100 Grade 1 temperature profile assumes 10% duty cycle at maximum temperature (2-years out of 20-year life)

Table 2.2 Operating Conditions

Power Up and Power Down Sequencing

MRAM is protected from write operations whenever VDD is less than VWI. As soon as VDD exceeds VDD(min),

there is a startup time of 2 ms before read or write operations can start. This time allows memory power

supplies to stabilize.

The E and W control signals should track VDD on power up to VDD- 0.2 V or VIH (whichever is lower) and re-

main high for the startup time. In most systems, this means that these signals should be pulled up with a

resistor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and

W should hold the signals high with a power-on reset signal for longer than the startup time.

During power loss or brownout where VDD goes below VWI, writes are protected and a startup time must be

observed when power returns above VDD(min).

BROWNOUT or POWER LOSS

NORMAL

OPERATION

VDD

READ/WRITE

INHIBITED

VWIDD

2 ms

READ/WRITE

INHIBITED

VIH

STARTUP

NORMAL

OPERATION

2 ms

RECOVER

VIH

Figure 2.1 Power Up and Power Down Diagram

MR4A08B

Electrical Specications

Document Number: MR4A08B Rev. 5, 9/20116

Parameter Symbol Min Typical Max Unit

Input leakage current Ilkg(I) - - ±1 μA

Output leakage current Ilkg(O) - - ±1 μA

Output low voltage

(IOL = +4 mA)

(IOL = +100 μA)

VOL - - 0.4

VSS + 0.2

Output high voltage

(IOL = -4 mA)

(IOL = -100 μA)

VOH 2.4

VDD - 0.2

--V

Table 2.3 DC Characteristics

Table 2.4 Power Supply Characteristics

Parameter Symbol Typical Max Unit

AC active supply current - read modes1

(IOUT= 0 mA, VDD= max) IDDR 60 68 mA

AC active supply current - write modes1

(VDD= max) IDDW 152 180 mA

AC standby current

(VDD= max, E = VIH)

no other restrictions on other inputs

ISB1 9 14 mA

CMOS standby current

(E ≥ VDD - 0.2 V and VIn ≤ VSS + 0.2 V or ≥ VDD - 0.2 V)

(VDD = max, f = 0 MHz)

ISB2 5 9 mA

1 All active current measurements are measured with one address transition per cycle and at minimum cycle time.

MR4A08B

Electrical Specications

Document Number: MR4A08B Rev. 5, 9/20117

MR4A08B

3. TIMING SPECIFICATIONS

Table 3.1 Capacitance1

Parameter Symbol Typical Max Unit

Address input capacitance CIn - 6 pF

Control input capacitance CIn - 6 pF

Input/Output capacitance CI/O - 8 pF

1 f = 1.0 MHz, dV = 3.0 V, TA = 25 °C, periodically sampled rather than 100% tested.

Table 3.2 AC Measurement Conditions

Figure 3.1 Output Load Test Low and High

Figure 3.2 Output Load Test All Others

Parameter Value Unit

Logic input timing measurement reference level 1.5 V

Logic output timing measurement reference level 1.5 V

Logic input pulse levels 0 or 3.0 V

Input rise/fall time 2 ns

Output load for low and high impedance parameters See Figure 3.1

Output load for all other timing parameters See Figure 3.2

Output

L= 1.5 V

RL= 50 Ω

ZD= 50 Ω

Output

435 Ω

590 Ω

5 pF

3.3 V

MR4A08B

Timing Specications

Document Number: MR4A08B Rev. 5, 9/20118

Parameter Symbol Min Max Unit

Read cycle time tAVAV 35 - ns

Address access time tAVQV - 35 ns

Enable access time2tELQV - 35 ns

Output enable access time tGLQV - 15 ns

Output hold from address change tAXQX 3 - ns

Enable low to output active3tELQX 3 - ns

Output enable low to output active3tGLQX 0 - ns

Enable high to output Hi-Z3tEHQZ 0 15 ns

Output enable high to output Hi-Z3tGHQZ 0 10 ns

1 W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be

minimized or eliminated during read or write cycles.

2 Addresses valid before or at the same time E goes low.

3 This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage.

Table 3.3 Read Cycle Timing1

Read Mode

Figure 3.3A Read Cycle 1

Figure 3.3B Read Cycle 2

A (ADDRESS)

Q (DATA OUT)

tAVAV

tAXQX

tAVQV

Previous Data Valid

Note: Device is continuously selected (E≤VIL, G≤VIL).

Data Valid

A (ADDRESS)

E (CHIP ENABLE)

G (OUTPUT ENABLE)

Q (DATA OUT) Data Valid

tAVAV

tAVQV

tELQV

tELQX

tGHQZ

tEHQZ

tGLQV

tGLQX

MR4A08B

Timing Specications

Document Number: MR4A08B Rev. 5, 9/20119

Table 3.4 Write Cycle Timing 1 (W Controlled)1

Parameter Symbol Min Max Unit

Write cycle time2tAVAV 35 - ns

Address set-up time tAVWL 0 - ns

Address valid to end of write (G high) tAVWH 18 - ns

Address valid to end of write (G low) tAVWH 20 - ns

Write pulse width (G high) tWLWH

tWLEH

15 - ns

Write pulse width (G low) tWLWH

tWLEH

15 - ns

Data valid to end of write tDVWH 10 - ns

Data hold time tWHDX 0 - ns

Write low to data Hi-Z3tWLQZ 0 12 ns

Write high to output active3tWHQX 3 - ns

Write recovery time tWHAX 12 - ns

1 All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus

contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after

W goes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must

remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being

asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.

2 All write cycle timings are referenced from the last valid address to the rst transition address.

3 This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. At any given

voltage or temperature, tWLQZ(max) < tWHQX(min)

W (WRITE ENABLE)

A (ADDRESS)

E (CHIP ENABLE)

AVAV

AVWH

WHAX

AVWL

WLEH

WLWH

DATA VALID

DVWH

WHDX

Q (DATA OUT)

D (DATA IN)

WLQZ

WHQX

Hi -Z Hi -Z

Figure 3.4 Write Cycle Timing 1 (W Controlled)

MR4A08B

Timing Specications

Table 3.5 Write Cycle Timing 2 (E Controlled)1

Figure 3.5 Write Cycle Timing 2 (E Controlled)

Parameter Symbol Min Max Unit

Write cycle time2tAVAV 35 - ns

Address set-up time tAVEL 0 - ns

Address valid to end of write (G high) tAVEH 18 - ns

Address valid to end of write (G low) tAVEH 20 - ns

Enable to end of write (G high) tELEH

tELWH

15 - ns

Enable to end of write (G low)3tELEH

tELWH

15 - ns

Data valid to end of write tDVEH 10 - ns

Data hold time tEHDX 0 - ns

Write recovery time tEHAX 12 - ns

1 All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus

contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after

W goes low, the output will remain in a high impedance state. After W, E or UB/ LB has been brought high, the signal must

remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being

asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.

2 All write cycle timings are referenced from the last valid address to the rst transition address.

3 If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the

same time or before W goes high, the output will remain in a high-impedance state.

A (ADDRESS)

E (CHIP ENABLE)

W (WRITE ENABLE)

Q (DATA OUT)

D (DATA IN)

AVAV

AVEH

EHAX

ELEH

EHDX

DVEH

AVEL

Hi-Z

ELWH

Data Valid

Document Number: MR4A08B Rev. 5, 9/201111

MR4A08B

4. ORDERING INFORMATION

Figure 4.1 Part Numbering System

Carrier (Blank = Tray, R = Tape & Reel)

Speed (35 ns)

Package (YS = TSOP2, MA = FBGA)

Temperature Range

(Blank= Commercial (0 to +70°C),

C= Industrial (-40 to +85°C), M= AEC-

Q100 Grade 1 (-40 to +125°C)

Revision

Data Width (08 = 8-Bit)

Type (A = Asynchronous)

Density (4 =16Mb)

Magnetoresistive RAM

(MR)

MR 4 A 08 B C YS 35 R

Part Number Description Temperature

MR4A08BYS35 13.3 V 2Mx8 MRAM 44-TSOP2 Commercial 0 to +70°C

MR4A08BCYS35 13.3 V 2Mx8 MRAM 44-TSOP2 Industrial 40 to +85°C

MR4A08BMYS3513.3 V 2Mx8 MRAM 44-TSOP2 AEC-Q100 Grade 1 -40 to +125°C

MR4A08BYS35R 13.3 V 2Mx8 MRAM 44-TSOP2 T&R Commercial 0 to +70°C

MR4A08BCYS35R 1 3.3 V 2Mx8 MRAM 44-TSOP2 T&R Industrial 40 to +85°C

MR4A08BMYS35R 13.3 V 2Mx8 MRAM 44-TSOP2 T&R AEC-Q100

Grade 1 -40 to +125°C

MR4A08BMA3513.3 V 2Mx8 MRAM 48-BGA Commercial 0 to +70°C

MR4A08BCMA3513.3 V 2Mx8 MRAM 48-BGA Industrial 40 to +85°C

MR4A08BMA35R13.3 V 2Mx8 MRAM 48-BGA T&R Commercial 0 to +70°C

MR4A08BCMA35R13.3 V 2Mx8 MRAM 48-BGA T&R Industrial 40 to +85°C

1 Preliminary Products: These products are classied as Preliminary until the completion of all qualication tests.

The specications in this data sheet are intended to be nal but are subject to change. Please check the Ever-

spin web site www.everspin.com for the latest information on product status.

Table 4.1 Available Parts

Document Number: MR4A08B Rev. 5, 9/201112

Figure 5.1 TSOP2

MR4A08B

5. MECHANICAL DRAWING

Print Version Not To Scale

1. Dimensions and tolerances per ASME Y14.5M - 1994.

2. Dimensions in Millimeters.

3. Dimensions do not include mold protrusion.

4. Dimension does not include DAM bar protrusions.

DAM Bar protrusion shall not cause the lead width to exceed 0.58.

Document Number: MR4A08B Rev. 5, 9/201113

123456

(DATUM A)

(DATUM B)

SEATING PLANE

PIN A1

INDEX

PIN A1

INDEX

BOTTOM VIEW TOP VIEW

SOLDER BALL DIAMETER REFERS

TO POST REFLOW CONDITION.

THE PRE-REFLOW DIAMETER IS

0.35mm

Figure 5.2 FBGA

MR4A08B

Mechanical Drawings

Print Version Not To Scale

1. Dimensions in Millimeters.

2. The ‘e’ represents the basic solder ball grid pitch.

3. ‘b’ is measurable at the maximum solder ball diameter

in a plane parallel to datum C.

4. Dimension ‘ccc’ is measured parallel to primary datum

5. Primary datum C (seating plane) is dened by the

crowns

of the solder balls.

6. Package dimensions refer to JEDEC MO-205 Rev. G.

Ref Min Nominal Max

A 1.19 1.27 1.35

A1 0.22 0.27 0.32

b0.31 0.36 0.41

D10.00 BSC

E10.00 BSC

D1 5.25 BSC

E1 3.75 BSC

DE 0.375 BSC

SE 0.375 BSC

e0.75 BSC

Ref Tolerance of, from and position

aaa 0.10

bbb 0.10

ddd 0.12

eee 0.15

f 0.08

MR4A08B

Document Number: MR4A08B Rev. 5, 9/201114

Revision Date Description of Change

1 May 29, 2009 Establish Speed and Power Specications

2 July 27, 2009 Increase BGA Package to 11 mm x 11 mm

3 May 5, 2010 Changed speed marking and timing specs to 35 ns part. Changed BGA package to

10 mm x 10mm

4 Aug 10, 2011 Max. magnetic eld during write (Hmax_write ) increased to 8000 A/m.

5 Sep 14, 2011 Added AEC-Q100- Grade 1 qualication.

6. REVISION HISTORY

Information in this document is provided solely to enable system and software implementers to

use Everspin Technologies products. There are no express or implied licenses granted hereunder

to design or fabricate any integrated circuit or circuits based on the information in this document.

Everspin Technologies reserves the right to make changes without further notice to any products

herein. Everspin makes no warranty, representation or guarantee regarding the suitability of its

products for any particular purpose, nor does Everspin Technologies assume any liability arising

out of the application or use of any product or circuit, and specically disclaims any and all

liability, including without limitation consequential or incidental damages. “Typical” param-

eters, which may be provided in Everspin Technologies data sheets and/or specications can

and do vary in dierent applications and actual performance may vary over time. All operating

parameters including “Typicals” must be validated for each customer application by customer’s

technical experts. Everspin Technologies does not convey any license under its patent rights nor

the rights of others. Everspin Technologies products are not designed, intended, or authorized for

use as components in systems intended for surgical implant into the body, or other applica-

tions intended to support or sustain life, or for any other application in which the failure of

the Everspin Technologies product could create a situation where personal injury or death may

occur. Should Buyer purchase or use Everspin Technologies products for any such unintended or

unauthorized application, Buyer shall indemnify and hold Everspin Technologies and its ocers,

employees, subsidiaries, aliates, and distributors harmless against all claims, costs, damages,

and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of

personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that Everspin Technologies was negligent regarding the design or manufacture of

the part. Everspin™ and the Everspin logo are trademarks of Everspin Technologies, Inc. All other

product or service names are the property of their respective owners.

How to Reach Us:

Home Page:

www.everspin.com

E-Mail:

support@everspin.com

orders@everspin.com

sales@everspin.com

USA/Canada/South and Central America

Everspin Technologies

1347 N. Alma School Road, Suite 220

Chandler, Arizona 85224

+1-877-347-MRAM (6726)

+1-480-347-1111

Europe, Middle East and Africa

support.europe@everspin.com

Japan

support.japan@everspin.com

Asia Pacic

support.asia@everspin.com

MR4A08B, Revision 4, 9/2011

Document Control Number:

MR4A08B_Datasheet_EST356_Rev4