M48Z2M1Y70PL1 - STMICROELECTRONICS

Not recommended for new design

This is information on a product still in production but not recommended for new designs.

June 2011 Doc ID 5135 Rev 6 1/20

M48Z2M1Y

M48Z2M1V

5 V or 3.3 V, 16 Mbit (2 Mb x 8) ZEROPOWER® SRAM

Features

■Integrated, ultra low power SRAM, power-fail

control circuit, and batteries

■Conventional SRAM operation; unlimited

WRITE cycles

■10 years of data retention in the absence of

power

■Automatic power-fail chip deselect and WRITE

protection

■WRITE protect voltages

(VPFD = power-fail deselect voltage):

–M48Z2M1Y: V

CC = 4.5 to 5.5 V;

4.2 V ≤ VPFD ≤ 4.5 V

–M48Z2M1V: V

CC = 3.0 to 3.6 V;

2.8 V ≤ VPFD ≤ 3.0 V

■Batteries are internally isolated until power is

applied

■Pin and function compatible with JEDEC

standard 2 Mb x 8 SRAMs

■RoHS compliant

– Lead-free second level interconnect

PLDIP36 module

www.st.com

Contents M48Z2M1Y, M48Z2M1V

2/20 Doc ID 5135 Rev 6

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

M48Z2M1Y, M48Z2M1V List of tables
Doc ID 5135 Rev 6 3/20
List of tables
Table 1. Signal names  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Operating modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. WRITE mode AC characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Capacitance  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 10. Power down/up trip points DC characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 11. PLDIP36 – 36-pin plastic DIP long module, package mechanical data  . . . . . . . . . . . . . . . 16
Table 12. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 13. Document revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

List of figures M48Z2M1Y, M48Z2M1V

4/20 Doc ID 5135 Rev 6

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. Address controlled, READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. Chip enable or output enable controlled, READ mode AC waveforms. . . . . . . . . . . . . . . . . 8

Figure 6. WRITE enable controlled, WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 7. Chip enable controlled, WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 8. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 9. AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 10. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 11. PLDIP36 – 36-pin plastic DIP long module, package outline . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 12. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

M48Z2M1Y, M48Z2M1V Description

Doc ID 5135 Rev 6 5/20

1 Description

The M48Z2M1Y/V ZEROPOWER® RAM is a non-volatile 16,777,216-bit, static RAM

organized as 2,097,152 words by 8 bits. The device combines two internal lithium batteries,

CMOS SRAMs and a control circuit in a plastic 36-pin DIP, long module.

The ZEROPOWER RAM replaces industry standard SRAMs. It provides the non-volatility of

PROMs without any requirement for special WRITE timing or limitations on the number of

WRITEs that can be performed.

Figure 1. Logic diagram

Table 1. Signal names

A0-A20 Address inputs

DQ0-DQ7 Data inputs / outputs

EChip enable

GOutput enable

WWRITE enable

VCC Supply voltage

VSS Ground

NC Not connected internally

AI02048

A0-A20

DQ0-DQ7

VCC

M48Z2M1Y

M48Z2M1V

VSS

Description M48Z2M1Y, M48Z2M1V

6/20 Doc ID 5135 Rev 6

Figure 2. DIP connections

Figure 3. Block diagram

VSS

VCC

AI02049

M48Z2M1Y

M48Z2M1V

DQ0

A13

A10

DQ7

A15

A11

DQ5DQ1

DQ2

DQ3

DQ4

DQ6

A16

A18

A12

A14

A17

A20

A19

AI02050

INTERNAL

BATTERIES

VCC

VSS

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

2048K x 8

SRAM ARRAY

A0-A20

DQ0-DQ7

POWER

M48Z2M1Y, M48Z2M1V Operation modes

Doc ID 5135 Rev 6 7/20

2 Operation modes

The M48Z2M1Y/V has its own power-fail detect circuit. The control circuitry constantly

monitors the single 5 V supply for an out of tolerance condition. When VCC is out of

tolerance, the circuit write protects the SRAM, providing a high degree of data security in the

midst of unpredictable system operations brought on by low VCC. As VCC falls below

approximately 3 V, the control circuitry connects the batteries which sustain data until valid

power returns.

Table 2. Operating modes

Note: X = VIH or VIL; VSO = battery backup switchover voltage.

2.1 READ mode

The M48Z2M1Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip

enable) is low. The device architecture allows ripple-through access of data from eight of

16,777,216 locations in the static storage array. Thus, the unique address specified by the

21 address inputs defines which one of the 2,097,152 bytes of data is to be accessed. Valid

data will be available at the data I/O pins within address access time (tAVQV) after the last

address input signal is stable, providing that the E (chip enable) and G (output enable)

access times are also satisfied. If the E and G access times are not met, valid data will be

available after the later of chip enable access time (tELQV) or output enable access time

(tGLQV). The state of the eight three-state data I/O signals is controlled by E and G. If the

outputs are activated before tAVQV, the data lines will be driven to an indeterminate state

until tAVQV. If the address inputs are changed while E and G remain low, output data will

remain valid for output data hold time (tAXQX) but will go indeterminate until the next address

access.

Figure 4. Address controlled, READ mode AC waveforms

Note: Chip enable (E) and output enable (G) = low, WRITE enable (W) = high.

Mode VCC E G W DQ0-

DQ7 Power

Deselect

3.0 to 3.6 V

4.5 to 5.5 V

VIH X X High Z Standby

WRITE VIL XV

IL DIN Active

READ VIL VIL VIH DOUT Active

READ VIL VIH VIH High Z Active

Deselect VSO to VPFD (min)(1)

1. See Table 10 on page 15 for details.

X X X High Z CMOS standby

Deselect ≤ VSO(1) X X X High Z Battery backup mode

AI02051

tAXQX

DATA VALID

A0-A20

DQ0-DQ7

tAVAV

tAVQV

Operation modes M48Z2M1Y, M48Z2M1V

8/20 Doc ID 5135 Rev 6

Figure 5. Chip enable or output enable controlled, READ mode AC waveforms

Note: WRITE enable (W) = high.

Table 3. READ mode AC characteristics

AI02052

tAVAV

tAVQV tAXQX

tELQV

tELQX

tEHQZ

tGLQV

tGLQX

tGHQZ

DATA OUT

A0-A20

DQ0-DQ7

VALID

Symbol Parameter(1)

1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where

noted).

M48Z2M1Y M48Z2M1V

Unit–70 –85

Min Max Min Max

tAVAV READ cycle time 70 85 ns

tAVQV(2)

2. CL = 100 pF or 50 pF (see Figure 9 on page 13).

Address valid to output valid 70 85 ns

tAXQX(2) Address transition to output transition 5 5 ns

tEHQZ(3)

3. CL = 5 pF (see Figure 9 on page 13).

Chip enable high to output Hi-Z 30 35 ns

tELQV(2) Chip enable low to output valid 70 85 ns

tELQX(3) Chip enable low to output transition 5 5 ns

tGHQZ(3) Output enable high to output Hi-Z 25 35 ns

tGLQV(2) Output enable low to output valid 35 45 ns

tGLQX(3) Output enable low to output transition 5 5 ns

M48Z2M1Y, M48Z2M1V Operation modes

Doc ID 5135 Rev 6 9/20

2.2 WRITE mode

The M48Z2M1Y/V is in the WRITE mode whenever W and E are active. The start of a

WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated

by the earlier rising edge of W or E.

The addresses must be held valid throughout the cycle. E or W must return high for

minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE

cycle. Data-in must be valid tDVEH or tDVWH prior to the end of WRITE and remain valid for

tEHDX or tWHDX afterward. G should be kept high during WRITE cycles to avoid bus

contention; although, if the output bus has been activated by a low on E and G, a low on W

will disable the outputs tWLQZ after W falls.

Figure 6. WRITE enable controlled, WRITE mode AC waveforms

Note: Output enable (G) = high.

Figure 7. Chip enable controlled, WRITE mode AC waveforms

Note: Output enable (G) = high.

AI02053

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A20

DQ0-DQ7

VALID

tAVWH

tAVEL

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

AI02054

tAVAV

tEHAX

tDVEH

A0-A20

DQ0-DQ7

VALID

tAVEH

tAVEL

tAVWL

tELEH

tEHDX

DATA INPUT

Operation modes M48Z2M1Y, M48Z2M1V

10/20 Doc ID 5135 Rev 6

Table 4. WRITE mode AC characteristics

2.3 Data retention mode

With valid VCC applied, the M48Z2M1Y/V operates as a conventional BYTEWIDE™ static

RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write

protecting itself tWP after VCC falls below VPFD. All outputs become high impedance, and all

inputs are treated as “Don't care.”

If power fail detection occurs during a valid access, the memory cycle continues to

completion. If the memory cycle fails to terminate within the time tWP

, write protection takes

place. When VCC drops below VSO, the control circuit switches power to the internal energy

source which preserves data.

The internal coin cells will maintain data in the M48Z2M1Y/V after the initial application of

VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system

power returns and VCC rises above VSO, the batteries are disconnected, and the power

supply is switched to external VCC. Write protection continues for tER after VCC reaches

VPFD to allow for processor stabilization. After tER, normal RAM operation can resume.

For more information on battery storage life refer to the application note AN1012.

Symbol Parameter(1)

1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6V (except where

noted).

M48Z2M1Y M48Z2M1V

Unit–70 –85

Min Max Min Max

tAVAV WRITE cycle time 70 85 ns

tAVEH Address valid to chip enable high 65 75 ns

tAVEL Address valid to chip enable low 0 0 ns

tAVWH Address valid to WRITE enable high 65 75 ns

tAVWL Address valid to WRITE enable low 0 0 ns

tDVEH Input valid to chip enable high 30 35 ns

tDVWH Input valid to WRITE enable high 30 35 ns

tEHAX Chip enable high to address transition 15 15 ns

tEHDX Chip enable high to input transition 10 15 ns

tELEH Chip enable low to chip enable high 55 75 ns

tWHAX WRITE enable high to address transition 5 5 ns

tWHDX WRITE enable high to input transition 0 0 ns

tWHQX(2)(3)

2. CL = 5 pF (see Figure 9 on page 13).

3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

WRITE enable high to output transition 5 5 ns

tWLQZ(2)(3) WRITE enable low to output Hi-Z 25 30 ns

tWLWH WRITE enable pulse width 55 65 ns

M48Z2M1Y, M48Z2M1V Operation modes

Doc ID 5135 Rev 6 11/20

2.4 VCC noise and negative going transients

ICC transients, including those produced by output switching, can produce voltage

fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if

capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the

bypass capacitors will be released as low going spikes are generated or energy will be

absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in

Figure 8) is recommended in order to provide the needed filtering.

In addition to transients that are caused by normal SRAM operation, power cycling can

generate negative voltage spikes on VCC that drive it to values below VSS by as much as

one volt. These negative spikes can cause data corruption in the SRAM while in battery

backup mode. To protect from these voltage spikes, it is recommended to connect a

schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode

1N5817 is recommended for through hole and MBRS120T3 is recommended for surface

mount.

Figure 8. Supply voltage protection

AI02169

VCC

0.1µF DEVICE

VCC

VSS

Maximum ratings M48Z2M1Y, M48Z2M1V

12/20 Doc ID 5135 Rev 6

3 Maximum ratings

Stressing the device above the rating listed in the absolute maximum ratings table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the operating sections of

this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

Table 5. Absolute maximum ratings

Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup

mode.

Symbol Parameter Value Unit

TAAmbient operating temperature 0 to 70 °C

TSTG Storage temperature (VCC off) –40 to 85 °C

TBIAS Temperature under bias –40 to 85 °C

TSLD(1)

1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. Furthermore, the devices

shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST

recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries.

Lead solder temperature for 10 seconds 260 °C

VIO Input or output voltages M48Z2M1Y –0.3 to 7 V

M48Z2M1V –0.3 to 4.6 V

VCC Supply voltage M48Z2M1Y –0.3 to 7 V

M48Z2M1V –0.3 to 4.6 V

IOOutput current 20 mA

PDPower dissipation 1 W

M48Z2M1Y, M48Z2M1V DC and AC parameters

Doc ID 5135 Rev 6 13/20

4 DC and AC parameters

This section summarizes the operating and measurement conditions, as well as the DC and

AC characteristics of the device. The parameters in the following DC and AC characteristic

tables are derived from tests performed under the measurement conditions listed in the

relevant tables. Designers should check that the operating conditions in their projects match

the measurement conditions when using the quoted parameters.

Table 6. Operating and AC measurement conditions

Note: Output Hi-Z is defined as the point where data is no longer driven.

Figure 9. AC testing load circuit

Parameter M48Z2M1Y M48Z2M1V Unit

Supply voltage (VCC) 4.5 to 5.5 3.0 to 3.6 V

Ambient operating temperature (TA) 0 to 70 0 to 70 °C

Load capacitance (CL) 100 50 pF

Input rise and fall times ≤ 5 ≤ 5ns

Input pulse voltages 0 to 3 0 to 3 V

Input and output timing ref. voltages 1.5 1.5 V

AI07816

OUT

CL = 100pF or 5pF (Y)

50pF or 5pF (V)

CL includes JIG capacitance

1.9kΩ

DEVICE

UNDER

TEST

1kΩ

DC and AC parameters M48Z2M1Y, M48Z2M1V

14/20 Doc ID 5135 Rev 6

Table 7. Capacitance

Table 8. DC characteristics

Symbol Parameter(1)(2)

1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.

2. Outputs deselected.

Min Max Unit

CIN Input capacitance - 40 pF

CIO(3)

3. At 25 °C.

Input / output capacitance - 40 pF

Sym Parameter Test condition(1)

1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).

M48Z2M1Y M48Z2M1V

Unit

Min Max Min Max

ILI(2)

2. Outputs deselected.

Input leakage current 0 V ≤ VIN ≤ VCC ±4 ±4 µA

ILO(2) Output leakage current 0 V ≤ VOUT ≤ VCC ±4 ±4 µA

ICC Supply current E = VIL,

Outputs open 140 70 mA

ICC1 Supply current (standby) TTL E = VIH 10 2 mA

ICC2 Supply current (standby) CMOS E ≥ VCC – 0.2 V 8 1 mA

VIL Input low voltage –0.3 0.8 –0.3 0.6 V

VIH Input high voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 V

VOL Output low voltage IOL = 2.1 mA 0.4 0.4 V

VOH Output high voltage IOH = –1 mA 2.4 2.2 V

M48Z2M1Y, M48Z2M1V DC and AC parameters

Doc ID 5135 Rev 6 15/20

Figure 10. Power down/up mode AC waveforms

Table 9. Power down/up AC characteristics

Table 10. Power down/up trip points DC characteristics

Symbol Parameter(1)

1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where

noted).

Min Max Unit

tER E recovery time 40 120 ms

tF(2)

2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring

until 200 µs after VCC passes VPFD (min).

VPFD (max) to VPFD (min) VCC fall time 300 µs

tFB(3)

3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.

VPFD (min) to VSO VCC fall time M48Z2M1Y 10 µs

M48Z2M1V 150 µs

tRVPFD (min) to VPFD (max) VCC rise time 10 µs

tWP Write protect time from VCC = VPFD

M48Z2M1Y 40 150 µs

M48Z2M1V 40 250 µs

Symbol Parameter(1)(2)

1. All voltages referenced to VSS.

2. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where

noted).

Min Typ Max Unit

VPFD Power-fail deselect voltage M48Z2M1Y 4.2 4.3 4.5 V

M48Z2M1V 2.8 2.9 3.0 V

VSO Battery backup switchover voltage M48Z2M1Y 3.0 V

M48Z2M1V 2.45 V

tDR(3)

3. At 25 °C; VCC = 0 V.

Expected data retention time 10 YEARS

AI01031

VCC

(PER CONTROL INPUT)

OUTPUTS

DON'T CARE

HIGH-Z

tFB

tRB

tWP

tDR

VALID VALID

(PER CONTROL INPUT)

RECOGNIZEDRECOGNIZED

VPFD (max)

VPFD (min)

VSO

tER

Package mechanical data M48Z2M1Y, M48Z2M1V

16/20 Doc ID 5135 Rev 6

5 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

Figure 11. PLDIP36 – 36-pin plastic DIP long module, package outline

Note: Drawing is not to scale.

Table 11. PLDIP36 – 36-pin plastic DIP long module, package mechanical data

PMDIP

Be1

Symb

mm inches

Typ Min Max Typ Min Max

A 9.27 9.52 0.3650 0.3748

A1 0.38 0.0150

B 0.43 0.59 0.0169 0.0232

C 0.20 0.33 0.0079 0.0130

D 52.58 53.34 2.0701 2.1000

E 18.03 18.80 0.7098 0.7402

e1 2.30 2.81 0.0906 0.1106

e3 43.18 1.7

eA 14.99 16.00 0.5902 0.6299

L 3.05 3.81 0.1201 0.1500

S 4.45 5.33 0.1752 0.2098

N36 36

M48Z2M1Y, M48Z2M1V Part numbering

Doc ID 5135 Rev 6 17/20

6 Part numbering

Table 12. Ordering information scheme

For other options, or for more information on any aspect of this device, please contact the

ST sales office nearest you.

Example: M48Z 2M1Y –70 PL 1

Device type

M48Z

Supply voltage and write protect voltage

2M1Y(1) = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V

1. Not recommended for new design. Contact ST sales office for availability.

2M1V(1) = VCC = 3.0 to 3.6 V; VPFD = 2.8 to 3.0 V

Speed

–70 = 70 ns (Y)

–85 = 85 ns (V)

Package

PL = PLDIP36

Temperature range

1 = 0 to 70°C

9 = extended temperature

Shipping method

blank = ECOPACK® package, tubes

Environmental information M48Z2M1Y, M48Z2M1V

18/20 Doc ID 5135 Rev 6

7 Environmental information

Figure 12. Recycling symbols

This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)

button cell battery fully encapsulated in the final product.

Recycle or dispose of batteries in accordance with the battery manufacturer's instructions

and local/national disposal and recycling regulations.

M48Z2M1Y, M48Z2M1V Revision history
Doc ID 5135 Rev 6 19/20
8 Revision history
Table 13. Document revision history
         
Date Revision Changes
Jul-1999 1 First issue
31-Aug-2000 2 From preliminary data to datasheet
20-Mar-2002 3 Reformatted; temperature information added to tables (Ta bl e 7 , 8, 3, 4, 
9, 10)
29-May-2002 3.1 Modified “VCC noise and negative going transients” text
28-Mar-2003 3.2 Remove 5 V/5%, add 3 V part (Figure 1, 2, 9; Ta bl e 5 , 6, 8, 2, 3, 4, 9, 
10, 12)
02-Jul-2003 3.3 Changed characteristic (Ta b l e 8 )
18-Feb-2005 4 Reformatted; IR reflow update (Ta b l e 5 )
02-Aug-2010 5 Updated Features, Section 3, Ta bl e 1 2 ; added ECOPACK® text to 
Section 5; added Section 7: Environmental information.
24-Jun-2011 6
Devices are not recommended for new design (updated cover page, 
Ta bl e 1 2 ); updated footnote of Table 5: Absolute maximum ratings; 
updated Section 7: Environmental information.

M48Z2M1Y, M48Z2M1V

20/20 Doc ID 5135 Rev 6

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no

liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this

document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products

or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such

third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS

OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT

RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING

APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,

DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE

GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void

any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any

liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America