Revision 2.3
April 2002
1
BSI Very Low Power/Voltage CMOS SRAM
256K x 16 or 512K x 8 bit switchable
The BS616LV4020 is a high performance, very low power CMOS Static
Random Access Memory organized as 262,144 words by 16 bits or
524,288 bytes by 8 bits selectable by CIO pin and operates from a wide
range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.5uA and maximum access time of 70/100ns in 3V operation.
Easy memory expansion is provided by active HIGH chip
enable2(CE2), active LOW chip enable1(CE1), active LOW output
enable(OE) and three-state output drivers.
The BS616LV4020 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV4020 is available in DICE form and 48-pin BGA type.
• Very low operation voltage : 2.7 ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I-grade : 25mA (Max.) operating current
0.5uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc=3.0V
-10 100ns (Max.) at Vcc=3.0V
•Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin
DESCRIPTION
FEATURES
BLOCK DIAGRAM
PRODUCT FAMILY
Brilliance Semiconductor Inc.reserves the right to modify document contents without notice.
BS616LV4020
Row
Decoder
Memory Array
2048 x 2048
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
A1 A2 A3
Data
Input
Buffer
Control
Vss
Vdd
OE
WE
D0
A8
A12
16(8)
16(8)
16(8)
16(8)
CE1
D15
A11
A7
A17
A13
14(16)
128(256)
2048
2048
22
A10
A9
A0
A6
A4
A16
A14
Address
Input
Buffer
A5
Address Input Buffer
.
.
.
.
UB
.
.
.
.
LB
A15
CIO
CE2
(SAE)
PIN CONFIGURATION
R0201-BS616LV4020
POWER DISSIPATION
STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
PRODUCT FAMILY OPERATING
TEMPERATURE Vcc RANGE
Vcc=3.0V Vcc=3.0V Vcc=3.0V
PKG TYPE
BS616LV4020DC DICE
BS616LV4020AC BGA-48-0608
BS616LV4020BC
+0 OC to +70 OC 2.7V ~ 3.6V 70 / 100 8uA 20mA
BGA-48-0810
BS616LV4020DI DICE
BS616LV4020AI BGA-48-0608
BS616LV4020BI
-40 OC to +85 OC 2.7V ~ 3.6V 70 / 100 12uA 25mA
BGA-48-0810
SPEED
(ns)
Revision 2.3
April 2002
2
Name Function
A0-A17 Address Input These 18 address inputs select one of the 262,144 x 16-bit words in the RAM.
SAE Address Input This address input incorporates with the above 18 address input select one of the
524,288 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH.
CIO x8/x16 select input This input selects the organization of the SRAM. 262,144 x 16-bit words configuration
is selected if CIO is HIGH. 524,288 x 8-bit bytes configuration is selected if CIO is
LOW.
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input Lower byte and upper byte data input/output control pins. The chip is deselected when
both LB and UB pins are HIGH.
DQ0 - DQ15 Data Input/Output These 16 bi-directional ports are used to read data from or write data into the RAM.
Ports
Vcc Power Supply
Gnd Ground
PIN DESCRIPTIONS
BSI BS616LV4020
R0201-BS616LV4020
Revision 2.3
April 2002
3
MODE CE1 CE2 OE WE CIO LB UB SAE D0~7 D8~15 VCC Current
HX XX
Fully Standby
XL
XX X
XX
X High-Z High-Z ICCSB, ICCSB1
Output Disable L H H H X X X X High-Z High-Z ICC
L H Dout High-Z
H L High-Z Dout
Read from SRAM
( WORD mode )
LHLH H
LL
X
Dout Dout
ICC
LH Din X
HL X Din
Write to SRAM
( WORD mode )
LHXL H
LL
X
Din Din
ICC
Read from SRAM
( BYTE Mode )
L H L H L X X A-1 Dout High-Z ICC
Write to SRAM
( BYTE Mode )
LHXL L XXA-1 Din X I
CC
TRUTH TABLE
BSI BS616LV4020
CIN Input
Capacitance
VIN=0V 6 pF
CDQ Input/Output
Capacitance
VI/O=0V 8 pF
RANGE AMBIENT
TEMPERATURE Vcc
Commercial 0 O C to +70 O C2.7V ~ 3.6V
Industrial -40 O C to +85 O C2.7V ~ 3.6V
ABSOLUTE MAXIMUM RATINGS(1) OPERATING RANGE
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not tested.
SYMBOL PARAMETER RATING UNITS
V
TERM Term inal Vo lta g e w ith
Respect to GND
-0.5 to
Vcc+0.5 V
T
BIAS Temperature Under Bias -40 to +125 OC
T
STG Storage Temperature -60 to +150 OC
P
TPower Dissipation 1.0 W
I
OUT DC Output Current 20 mA
R0201-BS616LV4020
SYMBOL PARAMETER CONDITIONS MAX. UNIT
Revision 2.3
April 2002
4
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC .
DC ELECTRICAL CHARACTERISTICS (TA = 0oC to +70oC)
BSI BS616LV4020
R0201-BS616LV4020
PARAMETER
NAME PARAMETER TEST CONDITIONS MIN. TYP.
(1) MAX. UNITS
VIL Guaranteed Input Low
Voltage(2) Vcc=3V -0.5 -- 0.8 V
VIH Guaranteed Input High
Voltage(2) Vcc=3V 2.0 -- Vcc+0.2 V
IIL Input Leakage Current = 0V to VccVcc = Max, VIN -- -- 1 uA
IOL Output Leakage Current Vcc = Max, CE1 = V
IH or CE2=VIL or OE = V
IH,
VI/O = 0V to
Vcc -- -- 1 uA
VOL Output Low Voltage = 2mAVcc = Max, IOL Vcc=3V -- -- 0.4 V
VOH Output High Voltage Vcc = Min, IOH = -1mA Vcc=3V 2.4 -- -- V
ICC Operating Power Supply
Current
IL, CE2=V IH
= 0mA, F = Vcc=3V
Vcc = Max, CE1= V
IDQ Fmax(3) -- -- 20 mA
ICCSB Standby Current -TTL Vcc = Max, CE1 = V
I= 0mA
IH or CE2=VIL
DQ
Vcc=3V -- -- 1 mA
ICCSB1 Standby Current
ЊVcc-0.2V or
IN ЊVcc - 0.2V or
0.2V
Vcc=3V
-CMOS CE2Љ0.2V ;V
Vcc = Max, CE1
VINЉ
-- 0.5 8 uA
Revision 2.3
April 2002
5
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS
VDR Vcc for Data Retention CE1 ЊVcc - 0.2V or CE2 Љ0.2V ;
VIN ЊVcc - 0.2V or VIN Љ0.2V 1.5 -- -- V
ICCDR Data Retention Current CE1 ЊVcc - 0.2V or CE2 Љ0.2V
VIN ЊVcc - 0.2V or VIN Љ0.2V -- 0.3 2 uA
tCDR
Chip Deselect to Data
Retention Time 0---- ns
tROperation Recovery Time
See Retention Waveform
TRC (2) -- -- ns
DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )
1. Vcc = 1.5V, TA= + 25OC
2. tRC = Read Cycle Time
BSI BS616LV4020
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
CE1
Data Retention Mode
Vcc
tCDR
Vcc
tR
VIHVIH
Vcc VDR Њ1.5V
CE1 ЊVcc - 0.2V
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
CE2
Data Retention Mode
Vcc
tCDR
Vcc
tR
VIL
VIL
Vcc VDR Њ1.5V
CE2 Љ0.2V
R0201-BS616LV4020
Revision 2.3
April 2002
6
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
AC ELECTRICAL CHARACTERISTICS (TA = 0oC to +70oC , Vcc=3.0V)
READ CYCLE
AC TEST CONDITIONS
AC TEST LOADS AND WAVEFORMS
Ω667
THEVENIN EQUIVALENT
ALL INPUT PULSES
→
10% 90%
←
Vcc
GND
→←5ns
90% 10%
1.73V
OUTPUT
FIGURE 2
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
Ω
1269
Ω
1404
5PF
FIGURE 1B
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
Ω
1269
Ω
100PF
FIGURE 1A
1404
BSI BS616LV4020
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION BS616LV4020-70
MIN. TYP. MAX.
UNIT
Data Byte Control to Output High Z
Read Cycle Time
tAVAX
tAVQV
tE1LQV
tGLQV
tBE
tE1HQZ
tGHQZ
tBDO
tGLQX
tE1LQX
tBA
tRC
tAA
tACS1
tBA
tOE
tCLZ
tBE
tOLZ
tCHZ
tBDO
tOHZ
tOH
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
Output Disable to Output Address Change
Data Byte Control to Output Low Z
70
10
10
10
0
0
0
10
tAXQX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output Enable to Output Valid
(CE1)
(CE2,CE1)
70
70
70
35
35
35
35
30
BS616LV4020-10
MIN. TYP. MAX.
100
15
15
15
0
0
0
15
100
100
100
50
50
40
40
35
(CE2,CE1)
ns
tE2LQV tACS2 (CE2)
Chip Select Access Time
(LB,UB)
(LB,UB)
(LB,UB)
R0201-BS616LV4020
(1)
1. tBA is 35ns/50ns (@speed=70ns/100ns) with address toggle .
tBA is 70ns/100ns (@speed=70ns/100ns) without address toggle .
NOTE :
Revision 2.3
April 2002
7
READ CYCLE3 (1,4)
READ CYCLE2 (1,3,4)
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.
4. OE = VIL .
5. Transition is measured 500mV from steady state with CL = 30pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
±
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
tRC
tOH
tAA
DOUT
ADDRESS
tOH
tCLZ tCHZ
(5)
DOUT
CE1
(5)
tACS1
CE2
tOH
tRC
tOE
DOUT
LB,UB
CE1
OE
ADDRESS
tCLZ
(5)
tACS1
tCHZ
(1,5)
tOHZ (5)
tOLZ
tAA
tBDO
tBA
tBE
CE2
tACS2
tACS2
BSI BS616LV4020
R0201-BS616LV4020
Revision 2.3
April 2002
8
tWR
AC ELECTRICAL CHARACTERISTICS (TA = 0oC to +70oC , Vcc=3.0V)
WRITE CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION BS616LV4020-70
MIN. TYP. MAX.
UNIT
Data Hold from Write Time
Write Cycle Time
tAVAX
tE1LWH
tAVWL
tWLWH
tBW
tDVWH
tGHQZ
tWHQX
tWHDX
tWLQZ
tWHAX
tAVWH
tWC
tCW
tAS
tAW
tWP
tWR
tBW
tWHZ
tDW
tDH
tOHZ
tOW
Chip Select to End of Write
Address Set up Time
Address Valid to End of Write
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Output Disable to Output in High Z
End of Write to Output Active
Data Byte Control to End of Write
70
70
0
70
35
0
30
0
30
0
0
5
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1) tWC
(3)
tCW
(11)
tBW
(2)
tWP
tAW
tOHZ
(4,10)
tAS
(3)
tDH
tDW
DIN
DOUT
WE
CE1
OE
ADDRESS
(CE2, CE1, WE)
Write Pulse Width
(5)
BS616LV4020-10
MIN. TYP. MAX.
100
100
0
100
50
0
40
0
40
0
0
10
40
40
CE2 (5)
BSI BS616LV4020
(LB,UB)
(5)
LB,UB
R0201-BS616LV4020
(1)
1. tBW is 30ns/40ns (@speed=70ns/100ns) with address toggle .
tBW is 70ns/100ns (@speed=70ns/100ns) without address toggle .
NOTE :
Revision 2.3
April 2002
9
WRITE CYCLE2 (1,6)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low.
All signals must be active to initiate a write and any one signal can terminate
a write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.
3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition or LB,UB low transition occurs simultaneously with the WE low transitions
or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 30pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write.
±
tWC
tCW
(11)
(2)
tWP
tAW
tWHZ
(4,10)
tAS
tWR (3)
tDH
tDW
DIN
DOUT
WE
CE1
ADDRESS
tDH
(7) (8)
(8,9)
CE2
BSI BS616LV4020
LB,UB
tBW
(5)
(5)
R0201-BS616LV4020
Revision 2.3
April 2002
10
BSI BS616LV4020
R0201-BS616LV4020
PACKAGE DIMENSIONS
D1
VIEW A
1.4 Max.
e
E1
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
8.0 6.0
EN
48 3.755.25
E1D1
NOTES:
48 mini-BGA (6 x 8mm)
PACKAGE
A :BGA - 48 PIN(6x8mm)
B :BGA - 48 PIN(8x10mm)
D :DICE
ORDERING INFORMATION
BS616LV4020 X X -- Y Y
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
SPEED
70: 70ns
10: 100ns
Revision 2.3
April 2002
11
BSI BS616LV4020
R0201-BS616LV4020
E0.1
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
N ED
NOTES:
48 10.0 8.0
E1D1 e
3.755.25 0.75
SIDE VIEW
D0.1
D1
1.4 Max.
e
E1
0.25
0.05
SOLDER BALL 0.350.05
VIEW A
48 mini-BGA (8 x 10mm)
PACKAGE DIMENSIONS (continued)
Revision 2.3
April 2002
12
BSI
R0201-BS616LV4020
REVISION HISTORY
Revision Description Date Note
2.2 2001 Data Sheet release Apr. 15, 2001
2.3 Modify some AC parameters April,11,2002
BS616LV4020
