The following document contains information on Cypress products. Although the document is marked with the name "Broadcom", the company that originally developed the specification, Cypress will continue to offer these products to new and existing customers. There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made are the result of normal document improvements and are noted in the document history page, where supported. Future revisions will occur when appropriate, and changes will be noted in a document history page. Cypress continues to support existing part numbers. To order these products, please use only the Cypress Ordering Part Number listed in the table. Broadcom Ordering Part Number BCM4343WKUBGT BCM4343W1KUBG BCM4343W1KUBGT BCM4343WKUBG Cypress Ordering Part Number CYW4343WKUBGT CYW4343W1KUBG CYW4343W1KUBGT CYW4343WKUBG Please visit our website at www.cypress.com or contact your local sales office for additional information about Cypress products and services. Cypress is for true innovators - in companies both large and small. Our customers are smart, aggressive, out-of-the-box thinkers who design and develop game-changing products that revolutionize their industries or create new industries with products and solutions that nobody ever thought of before. Founded in 1982, Cypress is the leader in advanced embedded system solutions for the world's most innovative automotive, industrial, home automation and appliances, consumer electronics and medical products. Cypress's programmable systems-on-chip, general-purpose microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and engineering resources on the planet enabling innovators and out-of-the-box thinkers to disrupt markets and create new product categories in record time. To learn more, go to www.cypress.com. Cypress Semiconductor Corporation Document Number: 002-14797 Rev. *G 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Revised October 18, 2016 Data Sheet BCM4343W Single-Chip IEEE 802.11 b/g/n MAC/Baseband/ Radio with Bluetooth 4.1, an FM Receiver, and Wireless Charging GENERAL DESCRIPTION The Broadcom(R) BCM4343W is a highly integrated single-chip solution and offers the lowest RBOM in the industry for wearables, tablets, and a wide range of other portable devices. The chip includes a 2.4 GHz WLAN IEEE 802.11 b/g/n MAC/baseband/radio, Bluetooth 4.1 support, and an FM receiver. In addition, it integrates a power amplifier (PA) that meets the output power requirements of most handheld systems, a low-noise amplifier (LNA) for best-in-class receiver sensitivity, and an internal transmit/receive (iTR) RF switch, further reducing the overall solution cost and printed circuit board area. The WLAN host interface supports gSPI and SDIO v2.0 modes, providing a raw data transfer rate up to 200 Mbps when operating in 4-bit mode at a 50 MHz bus frequency. An independent, high-speed UART is provided for the Bluetooth/FM host interface. Using advanced design techniques and process technology to reduce active and idle power, the BCM4343W is designed to address the needs of highly mobile devices that require minimal power consumption and compact size. It includes a power management unit that simplifies the system power topology and allows for operation directly from a rechargeable mobile platform battery while maximizing battery life. The BCM4343W implements the world's most advanced Enhanced Collaborative Coexistence algorithms and hardware mechanisms, allowing for an extremely collaborative WLAN and Bluetooth coexistence. Figure 1: BCM4343W System Block Diagram VDDIO VBAT WL_REG_ON WLAN Host I/F WL_IRQ SDIO*/SPI CLK_REQ BT_REG_ON BCM4343W 2.4 GHz WLAN + Bluetooth TX/RX BPF PCM Bluetooth Host I/F BT_DEV_WAKE BT_HOST_WAKE UART FM RX Host I/F FM RX I2S Stereo Analog Out 4343W-DS107-R 5300 California Avenue * Irvine, CA 92617 * Phone: 949-926-5000 * Fax: 949-926-5203 August 24, 2015 Broadcom Corporation 5300 California Avenue Irvine, CA 92617 (c) 2015 by Broadcom Corporation All rights reserved Printed in the U.S.A. Broadcom(R), the pulse logo, Connecting everything(R), the Connecting everything logo, OneDriverTM, SmartAudio(R), and TurboQAM(R) are among the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their respective owners. This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high-risk application. BROADCOM PROVIDES THIS DATA SHEET "AS-IS," WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES, EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. BCM4343W Data Sheet Revision History FEATURES FEATURES IEEE 802.11x Key Features * Single-band 2.4 GHz IEEE 802.11b/g/n. * Support for 2.4 GHz Broadcom TurboQAM(R) data rates (256-QAM) and 20 MHz channel bandwidth. * Integrated iTR switch supports a single 2.4 GHz antenna shared between WLAN and Bluetooth. * Supports explicit IEEE 802.11n transmit beamforming. * Tx and Rx Low-density Parity Check (LDPC) support for improved range and power efficiency. * Supports standard SDIO v2.0 and gSPI host interfaces. * Supports Space-Time Block Coding (STBC) in the receiver. * Integrated ARM Cortex-M3 processor and onchip memory for complete WLAN subsystem functionality, minimizing the need to wake up the applications processor for standard WLAN functions. This allows for further minimization of power consumption, while maintaining the ability to field-upgrade with future features. On-chip memory includes 512 KB SRAM and 640 KB ROM. * OneDriverTM software architecture for easy migration from existing embedded WLAN and Bluetooth devices as well as to future devices. Bluetooth and FM Key Features (Continued) * FM receiver unit supports HCI for communication. * Low-power consumption improves battery life of handheld devices. * FM receiver: 65 MHz to 108 MHz FM bands; supports the European Radio Data Systems (RDS) and the North American Radio Broadcast Data System (RBDS) standards. * Supports multiple simultaneous Advanced Audio Distribution Profiles (A2DP) for stereo sound. * Automatic frequency detection for standard crystal and TCXO values. Bluetooth and FM Key Features * Complies with Bluetooth Core Specification Version 4.1 with provisions for supporting future specifications. * Bluetooth Class 1 or Class 2 transmitter operation. * Supports extended Synchronous Connections (eSCO), for enhanced voice quality by allowing for retransmission of dropped packets. * Adaptive Frequency Hopping (AFH) for reducing radio frequency interference. * Interface support -- Host Controller Interface (HCI) using a high-speed UART interface and PCM for audio data. Broadcom(R) August 24, 2015 * 4343W-DS107-R General Features * Supports a battery voltage range from 3.0V to 4.8V with an internal switching regulator. * Programmable dynamic power management. * 4 Kbit One-Time Programmable (OTP) memory for storing board parameters. * Can be routed on low-cost 1 x 1 PCB stack-ups. * 74-ball WLBGA package (4.87 mm x 2.87 mm, 0.4 mm pitch). * 153-bump WLCSP package (115 m bump diameter, 180 m bump pitch). * Security: - WPA and WPA2 (Personal) support for powerful encryption and authentication. - AES in WLAN hardware for faster data encryption and IEEE 802.11i compatibility. - Reference WLAN subsystem provides Cisco Compatible Extensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, CCX 5.0). - Reference WLAN subsystem provides Wi-Fi Protected Setup (WPS). * Worldwide regulatory support: Global products supported with worldwide homologated design. * Multimode wireless charging support that complies with the Alliance for Wireless Power (A4WP), the Wireless Power Consortium (WPC), and the Power Matters Alliance (PMA). Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 3 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Revision History Revision History Revision Date Change Description 4343W-DS107-R 08/24/15 4343W-DS106-R 07/01/15 Updated: * Figure 3: "Typical Power Topology (1 of 2)," on page 21 and Figure 4: "Typical Power Topology (2 of 2)," on page 22 . * Table 2: "Crystal Oscillator and External Clock Requirements and Performance," on page 30. * Table 23: "I/O States," on page 110. Updated: * Table 23: "I/O States," on page 110. * Table 26: "ESD Specifications," on page 114. * Table 29: "WLAN 2.4 GHz Receiver Performance Specifications," on page 118. * Table 30: "WLAN 2.4 GHz Transmitter Performance Specifications," on page 121. * Table 38: "FM Receiver Specifications," on page 130. * Table 43: "2.4 GHz Mode WLAN Power Consumption," on page 140. * Table 50: "Part Ordering Information," on page 155. 4343W-DS105-R 4343W-DS104-R 4343W-DS103-R 4343W-DS102-R 4343W-DS101-R 4343W-DS100-R 01/12/15 10/03/14 09/05/14 6/09/14 4/18/14 4/07/14 Broadcom(R) August 24, 2015 * 4343W-DS107-R Refer to the earlier release for detailed revision history. Refer to the earlier release for detailed revision history. Refer to the earlier release for detailed revision history. Refer to the earlier release for detailed revision history. Refer to the earlier release for detailed revision history. Initial release. Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 4 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Table of Contents Table of Contents About This Document ................................................................................................................................ 14 Purpose and Audience .......................................................................................................................... 14 Acronyms and Abbreviations................................................................................................................. 14 Document Conventions ......................................................................................................................... 14 Technical Support ...................................................................................................................................... 14 Section 1: Overview .......................................................................................................... 15 Overview...................................................................................................................................................... 15 Features....................................................................................................................................................... 17 Standards Compliance............................................................................................................................... 18 Section 2: Power Supplies and Power Management ..................................................... 19 Power Supply Topology............................................................................................................................. 19 BCM4343W PMU Features ......................................................................................................................... 20 WLAN Power Management ........................................................................................................................ 23 PMU Sequencing ........................................................................................................................................ 24 Power-Off Shutdown .................................................................................................................................. 25 Power-Up/Power-Down/Reset Circuits..................................................................................................... 25 Wireless Charging ...................................................................................................................................... 26 Section 3: Frequency References.................................................................................... 29 Crystal Interface and Clock Generation ................................................................................................... 29 TCXO............................................................................................................................................................ 30 External 32.768 kHz Low-Power Oscillator .............................................................................................. 31 Section 4: WLAN System Interfaces................................................................................ 33 SDIO v2.0..................................................................................................................................................... 33 SDIO Pin Descriptions........................................................................................................................... 33 Generic SPI Mode ....................................................................................................................................... 35 SPI Protocol .......................................................................................................................................... 36 Command Structure ....................................................................................................................... 38 Write............................................................................................................................................... 38 Write/Read ..................................................................................................................................... 38 Read............................................................................................................................................... 38 Status ............................................................................................................................................. 39 gSPI Host-Device Handshake............................................................................................................... 41 Boot-Up Sequence ................................................................................................................................ 41 Section 5: Wireless LAN MAC and PHY .......................................................................... 44 MAC Features ............................................................................................................................................. 44 MAC Description ................................................................................................................................... 44 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 5 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Table of Contents PSM ............................................................................................................................................... 45 WEP ............................................................................................................................................... 46 TXE ................................................................................................................................................ 46 RXE................................................................................................................................................ 46 IFS.................................................................................................................................................. 47 TSF ................................................................................................................................................ 47 NAV................................................................................................................................................ 47 MAC-PHY Interface........................................................................................................................ 47 PHY Description ......................................................................................................................................... 48 PHY Features........................................................................................................................................ 48 Section 6: WLAN Radio Subsystem ................................................................................ 50 Receive Path ............................................................................................................................................... 51 Transmit Path.............................................................................................................................................. 51 Calibration................................................................................................................................................... 51 Section 7: Bluetooth + FM Subsystem Overview ........................................................... 52 Features....................................................................................................................................................... 52 Bluetooth Radio.......................................................................................................................................... 54 Transmit ................................................................................................................................................ 54 Digital Modulator ................................................................................................................................... 54 Digital Demodulator and Bit Synchronizer............................................................................................. 54 Power Amplifier ..................................................................................................................................... 54 Receiver ................................................................................................................................................ 55 Digital Demodulator and Bit Synchronizer............................................................................................. 55 Receiver Signal Strength Indicator........................................................................................................ 55 Local Oscillator Generation ................................................................................................................... 55 Calibration ............................................................................................................................................. 55 Section 8: Bluetooth Baseband Core .............................................................................. 56 Bluetooth 4.1 Features............................................................................................................................... 56 Link Control Layer...................................................................................................................................... 57 Test Mode Support ..................................................................................................................................... 57 Bluetooth Power Management Unit .......................................................................................................... 58 RF Power Management ........................................................................................................................ 58 Host Controller Power Management ..................................................................................................... 58 BBC Power Management...................................................................................................................... 60 FM Power Management ........................................................................................................................ 60 Wideband Speech ................................................................................................................................. 60 Packet Loss Concealment..................................................................................................................... 61 Codec Encoding .................................................................................................................................... 61 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 6 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Table of Contents Multiple Simultaneous A2DP Audio Streams ........................................................................................ 61 FM Over Bluetooth ................................................................................................................................ 62 Adaptive Frequency Hopping.................................................................................................................... 62 Advanced Bluetooth/WLAN Coexistence................................................................................................. 62 Fast Connection (Interlaced Page and Inquiry Scans) ........................................................................... 62 Section 9: Microprocessor and Memory Unit for Bluetooth.......................................... 63 RAM, ROM, and Patch Memory ................................................................................................................. 63 Reset............................................................................................................................................................ 63 Section 10: Bluetooth Peripheral Transport Unit ........................................................... 64 PCM Interface.............................................................................................................................................. 64 Slot Mapping ......................................................................................................................................... 64 Frame Synchronization ......................................................................................................................... 64 Data Formatting..................................................................................................................................... 64 Wideband Speech Support ................................................................................................................... 65 Multiplexed Bluetooth and FM over PCM.............................................................................................. 65 PCM Interface Timing............................................................................................................................ 66 Short Frame Sync, Master Mode ................................................................................................... 66 Short Frame Sync, Slave Mode ..................................................................................................... 67 Long Frame Sync, Master Mode.................................................................................................... 68 Long Frame Sync, Slave Mode...................................................................................................... 69 UART Interface............................................................................................................................................ 70 I2S Interface................................................................................................................................................. 72 I2S Timing.............................................................................................................................................. 72 Section 11: FM Receiver Subsystem ............................................................................... 75 FM Radio ..................................................................................................................................................... 75 Digital FM Audio Interfaces ....................................................................................................................... 75 Analog FM Audio Interfaces ...................................................................................................................... 75 FM Over Bluetooth ..................................................................................................................................... 75 eSCO............................................................................................................................................................ 75 Wideband Speech Link .............................................................................................................................. 76 A2DP ............................................................................................................................................................ 76 Autotune and Search Algorithms ............................................................................................................. 76 Audio Features ........................................................................................................................................... 77 RDS/RBDS................................................................................................................................................... 79 Section 12: CPU and Global Functions ........................................................................... 80 WLAN CPU and Memory Subsystem........................................................................................................ 80 One-Time Programmable Memory ............................................................................................................ 80 GPIO Interface............................................................................................................................................. 81 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 7 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Table of Contents External Coexistence Interface ................................................................................................................. 81 2-Wire Coexistence ............................................................................................................................... 81 3-Wire and 4-Wire Coexistence Interfaces............................................................................................ 82 JTAG Interface ........................................................................................................................................... 83 UART Interface ........................................................................................................................................... 83 Section 13: WLAN Software Architecture ....................................................................... 84 Host Software Architecture ....................................................................................................................... 84 Device Software Architecture.................................................................................................................... 84 Remote Downloader.............................................................................................................................. 85 Wireless Configuration Utility ................................................................................................................... 85 Section 14: Pinout and Signal Descriptions ................................................................... 86 Ball Map....................................................................................................................................................... 86 WLBGA Ball List in Ball Number Order with X-Y Coordinates .............................................................. 88 WLCSP Bump List in Bump Order with X-Y Coordinates....................................................................... 91 WLBGA Ball List Ordered By Ball Name .................................................................................................. 96 WLCSP Bump List Ordered By Name....................................................................................................... 97 Signal Descriptions .................................................................................................................................... 99 WLAN GPIO Signals and Strapping Options ......................................................................................... 108 Chip Debug Options................................................................................................................................. 109 I/O States ................................................................................................................................................... 109 Section 15: DC Characteristics ...................................................................................... 113 Absolute Maximum Ratings .................................................................................................................... 113 Environmental Ratings ............................................................................................................................ 114 Electrostatic Discharge Specifications .................................................................................................. 114 Recommended Operating Conditions and DC Characteristics ........................................................... 115 Section 16: WLAN RF Specifications ............................................................................ 117 2.4 GHz Band General RF Specifications............................................................................................... 117 WLAN 2.4 GHz Receiver Performance Specifications .......................................................................... 118 WLAN 2.4 GHz Transmitter Performance Specifications ..................................................................... 121 General Spurious Emissions Specifications ......................................................................................... 123 Section 17: Bluetooth RF Specifications ...................................................................... 124 Section 18: FM Receiver Specifications........................................................................ 130 Section 19: Internal Regulator Electrical Specifications ............................................. 135 Core Buck Switching Regulator.............................................................................................................. 135 3.3V LDO (LDO3P3) .................................................................................................................................. 137 CLDO ......................................................................................................................................................... 138 LNLDO ....................................................................................................................................................... 139 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 8 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Table of Contents Section 20: System Power Consumption...................................................................... 140 WLAN Current Consumption................................................................................................................... 140 2.4 GHz Mode ..................................................................................................................................... 140 Bluetooth and FM Current Consumption ............................................................................................... 141 Section 21: Interface Timing and AC Characteristics .................................................. 142 SDIO Default Mode Timing ...................................................................................................................... 142 SDIO High-Speed Mode Timing............................................................................................................... 144 gSPI Signal Timing ................................................................................................................................... 145 JTAG Timing ............................................................................................................................................. 146 Section 22: Power-Up Sequence and Timing ............................................................... 147 Sequencing of Reset and Regulator Control Signals ........................................................................... 147 Description of Control Signals ............................................................................................................. 147 Control Signal Timing Diagrams.......................................................................................................... 148 Section 23: Package Information ................................................................................... 150 Package Thermal Characteristics ........................................................................................................... 150 Junction Temperature Estimation and PSI Versus Thetajc ................................................................. 150 Section 24: Mechanical Information .............................................................................. 151 Section 25: Ordering Information .................................................................................. 155 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 9 BROADCOM CONFIDENTIAL BCM4343W Data Sheet List of Figures List of Figures Figure 1: BCM4343W System Block Diagram ................................................................................................... 1 Figure 2: BCM4343W Block Diagram .............................................................................................................. 16 Figure 3: Typical Power Topology (1 of 2) ....................................................................................................... 21 Figure 4: Typical Power Topology (2 of 2) ....................................................................................................... 22 Figure 5: A4WP System Block Diagram .......................................................................................................... 26 Figure 6: Magnetic Coupling for Wireless Charging ........................................................................................ 27 Figure 7: An Example Multimode Wireless Charging Implementation ............................................................. 27 Figure 8: BCM4343W Interface to a BCM59350 ............................................................................................. 28 Figure 9: Recommended Oscillator Configuration ........................................................................................... 29 Figure 10: Recommended Circuit to Use with an External Dedicated TCXO .................................................. 30 Figure 11: Signal Connections to SDIO Host (SD 4-Bit Mode) ........................................................................ 33 Figure 12: Signal Connections to SDIO Host (SD 1-Bit Mode) ........................................................................ 34 Figure 13: Signal Connections to SDIO Host (gSPI Mode) ............................................................................. 35 Figure 14: gSPI Write Protocol ........................................................................................................................ 36 Figure 15: gSPI Read Protocol ........................................................................................................................ 37 Figure 16: gSPI Command Structure ............................................................................................................... 38 Figure 17: gSPI Signal Timing Without Status ................................................................................................. 39 Figure 18: gSPI Signal Timing with Status (Response Delay = 0)................................................................... 40 Figure 19: WLAN Boot-Up Sequence .............................................................................................................. 43 Figure 20: WLAN MAC Architecture ................................................................................................................ 45 Figure 21: WLAN PHY Block Diagram............................................................................................................. 49 Figure 22: Radio Functional Block Diagram .................................................................................................... 50 Figure 23: Startup Signaling Sequence ........................................................................................................... 59 Figure 24: CVSD Decoder Output Waveform Without PLC ............................................................................. 61 Figure 25: CVSD Decoder Output Waveform After Applying PLC................................................................... 61 Figure 26: Functional Multiplex Data Diagram ................................................................................................. 65 Figure 27: PCM Timing Diagram (Short Frame Sync, Master Mode) .............................................................. 66 Figure 28: PCM Timing Diagram (Short Frame Sync, Slave Mode) ................................................................ 67 Figure 29: PCM Timing Diagram (Long Frame Sync, Master Mode)............................................................... 68 Figure 30: PCM Timing Diagram (Long Frame Sync, Slave Mode)................................................................. 69 Figure 31: UART Timing .................................................................................................................................. 71 Figure 32: I2S Transmitter Timing .................................................................................................................... 74 Figure 33: I2S Receiver Timing ........................................................................................................................ 74 Figure 34: Blending and Switching Usage ....................................................................................................... 77 Figure 35: Blending and Switching Separation ................................................................................................ 78 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 10 BROADCOM CONFIDENTIAL BCM4343W Data Sheet List of Figures Figure 36: Soft Muting Characteristic............................................................................................................... 78 Figure 37: 2-Wire Coexistence Interface to an LTE IC .................................................................................... 81 Figure 38: 3-Wire Coexistence Interface to an LTE IC .................................................................................... 82 Figure 39: 4-Wire Coexistence Interface to an LTE IC .................................................................................... 83 Figure 40: WLAN Software Architecture .......................................................................................................... 85 Figure 41: 74-Ball WLBGA Ball Map (Bottom View) ........................................................................................ 86 Figure 42: 153-Bump WLCSP (Top View) ....................................................................................................... 87 Figure 43: RF Port Location ........................................................................................................................... 117 Figure 44: SDIO Bus Timing (Default Mode) ................................................................................................. 142 Figure 45: SDIO Bus Timing (High-Speed Mode).......................................................................................... 144 Figure 46: gSPI Timing .................................................................................................................................. 145 Figure 47: WLAN = ON, Bluetooth = ON ....................................................................................................... 148 Figure 48: WLAN = OFF, Bluetooth = OFF.................................................................................................... 148 Figure 49: WLAN = ON, Bluetooth = OFF ..................................................................................................... 148 Figure 50: WLAN = OFF, Bluetooth = ON ..................................................................................................... 149 Figure 51: 74-Ball WLBGA Mechanical Information ...................................................................................... 151 Figure 52: 153-Bump WLCSP Mechanical Information ................................................................................. 152 Figure 53: WLCSP Package Keep-Out Areas--Top View with the Bumps Facing Down ............................ 153 Figure 54: WLBGA Package Keep-Out Areas--Top View with the Bumps Facing Down ............................ 154 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 11 BROADCOM CONFIDENTIAL BCM4343W Data Sheet List of Tables List of Tables Table 1: Power-Up/Power-Down/Reset Control Signals.................................................................................. 25 Table 2: Crystal Oscillator and External Clock Requirements and Performance............................................. 30 Table 3: External 32.768 kHz Sleep-Clock Specifications ............................................................................... 31 Table 4: SDIO Pin Descriptions ....................................................................................................................... 33 Table 5: gSPI Status Field Details ................................................................................................................... 40 Table 6: gSPI Registers ................................................................................................................................... 41 Table 7: Power Control Pin Description ........................................................................................................... 58 Table 8: PCM Interface Timing Specifications (Short Frame Sync, Master Mode).......................................... 66 Table 9: PCM Interface Timing Specifications (Short Frame Sync, Slave Mode)............................................ 67 Table 10: PCM Interface Timing Specifications (Long Frame Sync, Master Mode) ........................................ 68 Table 11: PCM Interface Timing Specifications (Long Frame Sync, Slave Mode) .......................................... 69 Table 12: Example of Common Baud Rates.................................................................................................... 70 Table 13: UART Timing Specifications ............................................................................................................ 71 Table 14: Timing for I2S Transmitters and Receivers ...................................................................................... 73 Table 15: BCM4343W WLBGA Ball List -- Ordered By Ball Number ............................................................. 88 Table 16: BCM4343W WLCSP Bump List -- Ordered By Bump Number....................................................... 91 Table 17: BCM4343W WLBGA Ball List -- Ordered By Ball Name ................................................................ 96 Table 18: BCM4343W WLCSP Bump List -- Ordered By Bump Name .......................................................... 97 Table 19: WLBGA Signal Descriptions ............................................................................................................ 99 Table 20: WLCSP Signal Descriptions .......................................................................................................... 103 Table 21: GPIO Functions and Strapping Options......................................................................................... 108 Table 22: Chip Debug Options....................................................................................................................... 109 Table 23: I/O States ....................................................................................................................................... 110 Table 24: Absolute Maximum Ratings ........................................................................................................... 113 Table 25: Environmental Ratings................................................................................................................... 114 Table 26: ESD Specifications ........................................................................................................................ 114 Table 27: Recommended Operating Conditions and DC Characteristics ...................................................... 115 Table 28: 2.4 GHz Band General RF Specifications...................................................................................... 117 Table 29: WLAN 2.4 GHz Receiver Performance Specifications .................................................................. 118 Table 30: WLAN 2.4 GHz Transmitter Performance Specifications .............................................................. 121 Table 31: General Spurious Emissions Specifications .................................................................................. 123 Table 32: Bluetooth Receiver RF Specifications............................................................................................ 124 Table 33: LTE Specifications for Spurious Emissions ................................................................................... 127 Table 34: Bluetooth Transmitter RF Specifications........................................................................................ 128 Table 35: LTE Specifications for Out-of-Band Noise Floor ............................................................................ 129 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 12 BROADCOM CONFIDENTIAL BCM4343W Data Sheet List of Tables Table 36: Local Oscillator Performance ......................................................................................................... 129 Table 37: BLE RF Specifications ................................................................................................................... 129 Table 38: FM Receiver Specifications ........................................................................................................... 130 Table 39: Core Buck Switching Regulator (CBUCK) Specifications .............................................................. 135 Table 40: LDO3P3 Specifications .................................................................................................................. 137 Table 41: CLDO Specifications...................................................................................................................... 138 Table 42: LNLDO Specifications.................................................................................................................... 139 Table 43: 2.4 GHz Mode WLAN Power Consumption ................................................................................... 140 Table 44: Bluetooth BLE and FM Current Consumption................................................................................ 141 Table 45: SDIO Bus Timing Parameters (Default Mode) .............................................................................. 143 Table 46: SDIO Bus Timing Parameters (High-Speed Mode) ...................................................................... 144 Table 47: gSPI Timing Parameters................................................................................................................ 145 Table 48: JTAG Timing Characteristics ......................................................................................................... 146 Table 49: Package Thermal Characteristics .................................................................................................. 150 Table 50: Part Ordering Information .............................................................................................................. 155 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 13 BROADCOM CONFIDENTIAL About This Document BCM4343W Data Sheet About This Document Purpose and Audience This document provides details of the functional, operational, and electrical characteristics of the Broadcom(R) BCM4343W. It is intended for hardware design, application, and OEM engineers. Acronyms and Abbreviations In most cases, acronyms and abbreviations are defined on first use. For a comprehensive list of acronyms and other terms used in Broadcom documents, go to: http://www.broadcom.com/press/glossary.php. Document Conventions The following conventions may be used in this document: Convention Description Bold User input and actions: for example, type exit, click OK, press Alt+C Monospace Code: #include <iostream> HTML: <td rowspan = 3> Command line commands and parameters: wl [l] <command> <> Placeholders for required elements: enter your <username> or wl <command> [] Indicates optional command-line parameters: wl [l] Indicates bit and byte ranges (inclusive): [0:3] or [7:0] Technical Support Broadcom provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates through its customer support portal (https://support.broadcom.com). For a CSP account, contact your Sales or Engineering support representative. In addition, Broadcom provides other product support through its Downloads and Support site (http://www.broadcom.com/support/). Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 14 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Overview Section 1: Overview Overview The Broadcom(R) BCM4343W provides the highest level of integration for a mobile or handheld wireless system, with integrated IEEE 802.11 b/g/n. It provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. The BCM4343W is designed to address the needs of highly mobile devices that require minimal power consumption and reliable operation. Figure 2 on page 16 shows the interconnection of all the major physical blocks in the BCM4343W and their associated external interfaces, which are described in greater detail in subsequent sections. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 15 BROADCOM CONFIDENTIAL Overview BCM4343W Data Sheet FM RX SDP FM Digital FM I/F FM Demod. MDX RDS Decode LNA ADC AHB to APB Bridge AHB Bus Matrix ADC RSSI Debug AHB FM RF FM_RX ETM Cortex M3 JTAG* Figure 2: BCM4343W Block Diagram Patch WD Timer InterCtrl SW Timer Control LO Gen. RAM ROM APB DPLL DMA Bus Arb ARM IP GPIO Ctrl JTAG supported over SDIO or BT PCM SDIO or gSPI ARM CM3 LCU RAM RX/TX GPIO ROM Buffer IF PLL BT PHY Wake/ WiMax Ctrl Coex Sleep WiMax Coex. BTWLAN ECI BTFM Clock Control Sleep time Keeping LPO Clock Management PMU XO Buffer PMU Ctrl OTP GPIO GPIO UART Supported over SDIO or BT PCM UART JTAG* 2.4 GHz PA Shared LNA BPF POR WLAN BT_REG_ON VREGs VBAT PTU XTAL Power Supply Sleep CLK XTAL WL_REG_ON WDT Radio Digital Mod. 2.4 GHz PA MAC I S/PCM gSPI LNPPHY I/O Port Control 2 BlueRF Interface SDIO IEEE 802.11a/b/g/n Digital I/O APU BT Clock/ Hopper RF SWREG LDOx2 LPO XTAL OSC. POR PMU Control Backplane Debug UART Modem Digital Demod. & Bit Sync JTAG* Buffer Common and Radio Digital BPL UART * Via GPIO configuration, JTAG is supported over SDIO or BT PCM Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 16 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Features Features The BCM4343W supports the following WLAN, Bluetooth, and FM features: * IEEE 802.11b/g/n single-band radio with an internal power amplifier, LNA, and T/R switch * Bluetooth v4.1 with integrated Class 1 PA * Concurrent Bluetooth, FM (RX) RDS/RBDS, and WLAN operation * On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality * Simultaneous BT/WLAN reception with a single antenna * WLAN host interface options: - SDIO v2.0, including default and high-speed timing. - gSPI--up to a 50 MHz clock rate * BT UART (up to 4 Mbps) host digital interface that can be used concurrently with the above WLAN host interfaces. * ECI--enhanced coexistence support, which coordinates BT SCO transmissions around WLAN receptions. * I2S/PCM for FM/BT audio, HCI for FM block control * HCI high-speed UART (H4 and H5) transport support * Wideband speech support (16 bits, 16 kHz sampling PCM, through I2S and PCM interfaces) * Bluetooth SmartAudio(R) technology improves voice and music quality to headsets. * Bluetooth low power inquiry and page scan * Bluetooth Low Energy (BLE) support * Bluetooth Packet Loss Concealment (PLC) * FM advanced internal antenna support * FM auto searching/tuning functions * FM multiple audio routing options: I2S, PCM, eSCO, and A2DP * FM mono-stereo blending and switching, and soft mute support * FM audio pause detection support * Multiple simultaneous A2DP audio streams * FM over Bluetooth operation and on-chip stereo headset emulation Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 17 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Standards Compliance Standards Compliance The BCM4343W supports the following standards: * Bluetooth 2.1 + EDR * Bluetooth 3.0 * Bluetooth 4.1 (Bluetooth Low Energy) * 65 MHz to 108 MHz FM bands (US, Europe, and Japan) * IEEE 802.11n--Handheld Device Class (Section 11) * IEEE 802.11b * IEEE 802.11g * IEEE 802.11d * IEEE 802.11h * IEEE 802.11i The BCM4343W will support the following future drafts/standards: * IEEE 802.11r -- Fast Roaming (between APs) * IEEE 802.11k -- Resource Management * IEEE 802.11w -- Secure Management Frames * IEEE 802.11 Extensions: * IEEE 802.11e QoS Enhancements (as per the WMM(R) specification is already supported) * IEEE 802.11i MAC Enhancements * IEEE 802.11r Fast Roaming Support * IEEE 802.11k Radio Resource Measurement The BCM4343W supports the following security features and proprietary protocols: * Security: - WEP - WPATM Personal - WPA2TM Personal - WMM - WMM-PS (U-APSD) - WMM-SA - WAPI - AES (Hardware Accelerator) - TKIP (host-computed) - CKIP (SW Support) * Proprietary Protocols: - CCXv2 - CCXv3 - CCXv4 - CCXv5 * IEEE 802.15.2 Coexistence Compliance -- on silicon solution compliant with IEEE 3-wire requirements. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 18 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Power Supplies and Power Management Section 2: Power Supplies and Power Management Power Supply Topology One Buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the BCM4343W. All regulators are programmable via the PMU. These blocks simplify power supply design for Bluetooth, WLAN, and FM functions in embedded designs. A single VBAT (3.0V to 4.8V DC maximum) and VDDIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided by the regulators in the BCM4343W. Two control signals, BT_REG_ON and WL_REG_ON, are used to power up the regulators and take the respective circuit blocks out of reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down only when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO can be turned on and off based on the dynamic demands of the digital baseband. The BCM4343W allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO regulators. When in this state, LPLDO1 provides the BCM4343W with all required voltage, further reducing leakage currents. Note: VBAT should be connected to the LDO_VDDBAT5V and SR_VDDBAT5V pins of the device. Note: VDDIO should be connected to the SYS_VDDIO and WCC_VDDIO pins of the device. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 19 BROADCOM CONFIDENTIAL BCM4343W Data Sheet BCM4343W PMU Features BCM4343W PMU Features The PMU supports the following: * VBAT to 1.35Vout (170 mA nominal, 370 mA maximum) Core-Buck (CBUCK) switching regulator * VBAT to 3.3Vout (250 mA nominal, 450 mA maximum 800 mA peak maximum) LDO3P3 * 1.35V to 1.2Vout (100 mA nominal, 150 mA maximum) LNLDO * 1.35V to 1.2Vout (80 mA nominal, 200 mA maximum) CLDO with bypass mode for deep sleep * Additional internal LDOs (not externally accessible) * PMU internal timer auto-calibration by the crystal clock for precise wake-up timing from extremely low power-consumption mode. * PMU input supplies automatic sensing and fast switching to support A4WP operations. Figure 3 on page 21 and Figure 4 on page 22 show the typical power topology of the BCM4343W. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 20 BROADCOM CONFIDENTIAL BCM4343W PMU Features BCM4343W Data Sheet Figure 3: Typical Power Topology (1 of 2) SR_VDDBAT5V VBAT BCM4343W WL RF--TX Mixer and PA (not all versions) Mini PMU 1.2V VBAT: Operational: 2.4--4.8V Performance: 3.0--4.8V Absolute Maximum: 5.5V VDDIO Operational: 1.8--3.3V VDD1P35 Internal VCOLDO 80 mA (NMOS) 1.2V WL RF--LOGEN Internal RXLDO 10 mA (NMOS) 1.2V WL RF--RX LNA Internal ADCLDO 10 mA (NMOS) 1.2V WL RF--ADC REF Internal TXLDO 80 mA (PMOS) 1.2V WL RF--TX Internal AFELDO 80 mA (NMOS) 1.2V 1.35V Core Buck Int_SR_VBAT Regulator Peak: 370 mA Avg: 170 mA (320 mA) SR_VLX Mini PMU is placed in WL radio 2.2 uH 0603 SW1 LDO_VDD_1P5 SR_VBAT5V VBAT SR_PVSS GND WCC_VDDIO WL RF--AFE and TIA 4.7 uF 0402 LNLDO (100 mA) 1.2V 600 @ 100 MHz WL RF--XTAL FM_RFVDD VOUT_LNLDO 2.2 uF 0402 PMU_VSS WLRF_XTAL_ VDD1P2 FM LNA, Mixer 0.1 uF 0201 FM_RFPLL WPT_1P8 WCC_VDDIO (40 mA) (40 mA) LPLDO1 (5 mA) 1.1V WLAN/BT/CLB/Top, Always On VSEL1 (40 mA) WPT_1P8 o_wpt_resetb WL_REG_ON BT_REG_ON 4.6 mA FM PLL, LOGEN, Audio DAC SYS_VDDIO SYS_VDDIO 10 mA average, > 10 mA at startup WL RF--RFPLL PFD and MMD VDDC1 1.3V, 1.2V, WPTLDO (40 mA) 1.3V CL LDO or 0.95V Peak: 200 mA (AVS) Avg: 80 mA (Bypass in deep VOUT_CLDO sleep) WL OTP VDDC2 2.2 uF 0402 o_wl_resetb o_bt_resetb Supply ball WL Digital and PHY WL VDDM (SROMs & AOS) Supply bump/pad Power switch BT VDDM Ground ball Ground bump/pad No power switch BT/WLAN reset balls External to chip No dedicated power switch, but internal power down modes and blockspecific power switches Broadcom(R) August 24, 2015 * 4343W-DS107-R BT Digital Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 21 BROADCOM CONFIDENTIAL BCM4343W PMU Features BCM4343W Data Sheet Figure 4: Typical Power Topology (2 of 2) BCM4343W 6.4 mA 1.8V, 2.5V, and 3.3V VBAT LDO_ VDDBAT5V WL BBPLL/DFLL WL OTP 3.3V LDO3P3 with BackPower VOUT_3P3 Protection 4.7 uF (Peak 450800 mA 200 mA Average) 3.3V 0402 WPT_3P3 SW2 Peak: 92 mA Average: 75 mA Resistance: 1 ohm WLRF_PA_VDD 480 to 800 mA WL RF--PA (2.4 GHz) 1 uF 0201 6.4 mA 2.5V Capless LNLDO (10 mA) 22 ohm WL RF--ADC, AFE, LOGEN, LNA, NMOS MiniPMU LDOs Placed inside WL Radio BT_PAVDD Peak: 70 mA Average: 15 mA BT Class 1 PA 1 uF 0201 Power switch External to chip No power switch Supply ball No dedicated power switch, but internal power down modes and blockspecific power switches Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 22 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLAN Power Management WLAN Power Management The BCM4343W has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. Additionally, the BCM4343W integrated RAM is a high volatile memory with dynamic clock control. The dominant supply current consumed by the RAM is leakage current only. Additionally, the BCM4343W includes an advanced WLAN power management unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the BCM4343W into various power management states appropriate to the operating environment and the activities that are being performed. The power management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. Power-up sequences are fully programmable. Configurable, free-running counters (running at the 32.768 kHz LPO clock) in the PMU sequencer are used to turn on/turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for the current mode. Slower clock speeds are used wherever possible. The BCM4343W WLAN power states are described as follows: * Active mode-- All WLAN blocks in the BCM4343W are powered up and fully functional with active carrier sensing and frame transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock speeds are dynamically adjusted by the PMU sequencer. * Doze mode--The radio, analog domains, and most of the linear regulators are powered down. The rest of the BCM4343W remains powered up in an IDLE state. All main clocks (PLL, crystal oscillator) are shut down to reduce active power to the minimum. The 32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leakage current. * Deep-sleep mode--Most of the chip, including analog and digital domains, and most of the regulators are powered off. Logic states in the digital core are saved and preserved to retention memory in the always-on domain before the digital core is powered off. To avoid lengthy hardware reinitialization, the logic states in the digital core are restored to their pre-deep-sleep settings when a wake-up event is triggered by an external interrupt, a host resume through the SDIO bus, or by the PMU timers. * Power-down mode--The BCM4343W is effectively powered off by shutting down all internal regulators. The chip is brought out of this mode by external logic re-enabling the internal regulators. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 23 BROADCOM CONFIDENTIAL BCM4343W Data Sheet PMU Sequencing PMU Sequencing The PMU sequencer is used to minimize system power consumption. It enables and disables various system resources based on a computation of required resources and a table that describes the relationship between resources and the time required to enable and disable them. Resource requests can derive from several sources: clock requests from cores, the minimum resources defined in the ResourceMin register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of resources required to produce the requested clocks. Each resource is in one of the following four states: * enabled * disabled * transition_on * transition_off The timer value is 0 when the resource is enabled or disabled and nonzero during state transition. The timer is loaded with the time_on or time_off value of the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If the time_on value is 0, the resource can transition immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that the resource can transition immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either the immediate transition or the timer load-decrement sequence. During each clock cycle, the PMU sequencer performs the following actions: * Computes the required resource set based on requests and the resource dependency table. * Decrements all timers whose values are nonzero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource and inverts the ResourceState bit. * Compares the request with the current resource status and determines which resources must be enabled or disabled. * Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered-up dependents. * Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 24 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Power-Off Shutdown Power-Off Shutdown The BCM4343W provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices in the system, remain operational. When the BCM4343W is not needed in the system, VDDIO_RF and VDDC are shut down while VDDIO remains powered. This allows the BCM4343W to be effectively off while keeping the I/O pins powered so that they do not draw extra current from any other devices connected to the I/O. During a low-power shutdown state, provided VDDIO remains applied to the BCM4343W, all outputs are tristated, and most input signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths or create loading on any digital signals in the system, and enables the BCM4343W to be fully integrated in an embedded device and to take full advantage of the lowest power-savings modes. When the BCM4343W is powered on from this state, it is the same as a normal power-up, and the device does not retain any information about its state from before it was powered down. Power-Up/Power-Down/Reset Circuits The BCM4343W has two signals (see Table 1) that enable or disable the Bluetooth and WLAN circuits and the internal regulator blocks, allowing the host to control power consumption. For timing diagrams of these signals and the required power-up sequences, see Section 22: "Power-Up Sequence and Timing," on page 147. Table 1: Power-Up/Power-Down/Reset Control Signals Signal Description WL_REG_ON This signal is used by the PMU (with BT_REG_ON) to power-up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the internal BCM4343W regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. If BT_REG_ON and WL_REG_ON are both low, the regulators are disabled. This pin has an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming. BT_REG_ON This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the internal BCM4343W regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be disabled. This pin has an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 25 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Wireless Charging Wireless Charging The BCM4343W, when paired with a Broadcom BCM5935X wireless power transfer (WPT) front-end device, complies with the following three wireless charging standards: * Alliance for Wireless Power (A4WP) * Wireless Power Consortium (WPC) * Power Matters Alliance (PMA) To support the WPC and PMA standards, control-plane signaling is accomplished using in-band signaling between the BCM5935X WPT front-end device (located in the power receiving entity) and the power transmitting wireless charger. To support the A4WP standard, energy is transferred from a Power Transmitting Unit (PTU) to a Power Receiving Unit (PRU). The energy transferred charges the PRU battery. Bidirectional communication between the PTU and PRU is accomplished using Bluetooth Low Energy (BLE), where the PTU is a BLE client and the PRU is a BLE server. Using a BLE link, the PRU sends performance data to the PTU so that it can adapt its power output to meet the needs of the PRU. The most common use for wireless charging is to charge a mobile device battery. Figure 5 shows a simple block diagram of a system that supports the A4WP standard. Figure 5: A4WP System Block Diagram BT Power Receiving Unit (PRU) Bluetooth lowenergy (BLE) bidirectional communication enables the transmitter to adapt to mobile device system needs. A4WPCompatible Mobile Device BLE Server Wireless Power Transfer at 6.78 MHz Power Transmitting Unit (PTU) BT aka Power Plate BLE Client Note: A single PTU can be used to charge multiple devices. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 26 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Wireless Charging Figure 6 shows an example of the magnetic coupling between a single PTU and one or more PRUs. Figure 6: Magnetic Coupling for Wireless Charging Power Transmitting Unit Power Receiving Unit(s) RX1 TX RX2 RX3 Figure 7 shows an example A4WP-compliant wireless charging implementation. Figure 7: An Example Multimode Wireless Charging Implementation Motherboard BSC BSC WPC/PMA Coil USB NTC WPT Front End (Power IC) Load Control A4WP Coil Bridge Rectifier BSC IF Slave Voltage Regulator Power 3.3V LDO 1.8V LDO External Charger Battery Charging VDDIO Host (AP) VBAT V1P8SYS VBAT VBAT SPDT WPT_3V3 (VBAT) 1V8 SPDT WPT_1V8 (VDDIO) Monitoring/ Control WPT_IRQ PMU BT_REG_ON LDO_VDDBAT5V, SR_VDDBAT5V SYS_VDDIO, WCC_VDDIO BCM5935X WL_REG_ON PMU WakeUp POR Internal Power WPT_IRQ BSC_CLK BSC_SDA NFC IC NFC_GPIO BT_VDDIO Domain Broadcom(R) August 24, 2015 * 4343W-DS107-R OTP for A4WPT Parameters BCM4343W Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 27 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Wireless Charging Figure 8 shows the signal interface between a BCM4343W and a BCM59350. Figure 8: BCM4343W Interface to a BCM59350 BT_GPIO_3 (WPT_INTb) BCM4343W BT_GPIO_4 (BSC_SDA) BCM59350 Wireless Charging PMU BT_GPIO_5 (BSC_SCL) Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 28 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Frequency References Section 3: Frequency References An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency reference driven by a temperature-compensated crystal oscillator (TCXO) signal may be used. No software settings are required to differentiate between the two. In addition, a low-power oscillator (LPO) is provided for lower power mode timing. Crystal Interface and Clock Generation The BCM4343W can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator, including all external components, is shown in Figure 9. Consult the reference schematics for the latest configuration. Figure 9: Recommended Oscillator Configuration C WLRF_XTAL_XOP 12 - 27 pF C WLRF_XTAL_XON 12 - 27 pF R Note: Resistor value determined by crystal drive level. See reference schematics for details. The BCM4343W uses a fractional-N synthesizer to generate the radio frequencies, clocks, and data/packet timing so that it can operate using numerous frequency references. The frequency reference can be an external source such as a TCXO or a crystal interfaced directly to the BCM4343W. The default frequency reference setting is a 37.4 MHz crystal or TCXO. The signal requirements and characteristics for the crystal interface are shown in Table 2 on page 30. Note: Although the fractional-N synthesizer can support many reference frequencies, frequencies other than the default require support to be added in the driver, plus additional extensive system testing. Contact Broadcom for further details. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 29 BROADCOM CONFIDENTIAL BCM4343W Data Sheet TCXO TCXO As an alternative to a crystal, an external precision TCXO can be used as the frequency reference, provided that it meets the phase noise requirements listed in Table 2 on page 30. If the TCXO is dedicated to driving the BCM4343W, it should be connected to the WLRF_XTAL_XOP pin through an external capacitor with value ranges from 200 pF to 1000 pF as shown in Figure 10. Figure 10: Recommended Circuit to Use with an External Dedicated TCXO 200 pF - 1000 pF TCXO WLRF_XTAL_XOP NC WLRF_XTAL_XON Table 2: Crystal Oscillator and External Clock Requirements and Performance External Frequency Reference Crystal Parameter Conditions/Notes Min. Typ. Frequency - - Crystal load capacitance - ESR - Drive level Min. Typ. Max. Units 37.4a - - - - MHz - 12 - - - - pF - - 60 - - - External crystal must be able to 200 tolerate this drive level. - - - - - W Input Impedance (WLRF_XTAL_XOP) Resistive - - - 10k 100k - Capacitive - - - - - 7 pF WLRF_XTAL_XOP input voltage AC-coupled analog signal - - - 400b - 1260 mVp-p WLRF_XTAL_XOP input low level DC-coupled digital signal - - - 0 - 0.2 V WLRF_XTAL_XOP input high level DC-coupled digital signal - - - 1.0 - 1.26 V Frequency tolerance Initial + over temperature - -20 - 20 -20 - 20 ppm Duty cycle 37.4 MHz clock c, d, e Phase Noise (IEEE 802.11 b/g) Max. - - - 40 50 60 % 37.4 MHz clock at 10 kHz offset - - - - - -129 dBc/Hz 37.4 MHz clock at 100 kHz offset - - - - - -136 dBc/Hz Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 30 BROADCOM CONFIDENTIAL BCM4343W Data Sheet External 32.768 kHz Low-Power Oscillator Table 2: Crystal Oscillator and External Clock Requirements and Performance (Cont.) External Frequency Reference Crystal Parameter Conditions/Notes Min. Typ. Max. Min. Typ. Max. Units Phase Noisec, d, e (IEEE 802.11n, 2.4 GHz) 37.4 MHz clock at 10 kHz offset - - - - - -134 dBc/Hz 37.4 MHz clock at 100 kHz offset - - - - - -141 dBc/Hz Phase Noisec, d, e (256-QAM) 37.4 MHz clock at 10 kHz offset - - - - - -140 dBc/Hz 37.4 MHz clock at 100 kHz offset - - - - - -147 dBc/Hz a. The frequency step size is approximately 80 Hz. The BCM4343W does not auto-detect the reference clock frequency; the frequency is specified in the software and/or NVRAM file. b. To use 256-QAM, a 800 mV minimum voltage is required. c. For a clock reference other than 37.4 MHz, 20 x log10(f/37.4) dB should be added to the limits, where f = the reference clock frequency in MHz. d. Phase noise is assumed flat above 100 kHz. e. The BCM4343W supports a 26 MHz reference clock sharing option. See the phase noise requirement in the table. External 32.768 kHz Low-Power Oscillator The BCM4343W uses a secondary low-frequency sleep clock for low-power mode timing. Either the internal low-precision LPO or an external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz 30% over process, voltage, and temperature, which is adequate for some applications. However, one trade-off caused by this wide LPO tolerance is a small current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing beacons. Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed in Table 3 on page 31. Note: The BCM4343W will auto-detect the LPO clock. If it senses a clock on the EXT_SLEEP_CLK pin, it will use that clock. If it doesn't sense a clock, it will use its own internal LPO. * To use the internal LPO: Tie EXT_SLEEP_CLK to ground. Do not leave this pin floating. * To use an external LPO: Connect the external 32.768 kHz clock to EXT_SLEEP_CLK. Table 3: External 32.768 kHz Sleep-Clock Specifications Parameter LPO Clock Units Nominal input frequency Frequency accuracy Duty cycle Input signal amplitude Signal type 32.768 200 30-70 200-3300 Square wave or sine wave kHz ppm % mV, p-p - Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 31 BROADCOM CONFIDENTIAL BCM4343W Data Sheet External 32.768 kHz Low-Power Oscillator Table 3: External 32.768 kHz Sleep-Clock Specifications (Cont.) Parameter a Input impedance Clock jitter LPO Clock Units >100 <5 <10,000 k pF ppm a. When power is applied or switched off. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 32 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLAN System Interfaces Section 4: WLAN System Interfaces SDIO v2.0 The BCM4343W WLAN section supports SDIO version 2.0. for both 1-bit (25 Mbps) and 4-bit modes (100 Mbps), as well as high speed 4-bit mode (50 MHz clocks--200 Mbps). It has the ability to map the interrupt signal on a GPIO pin. This out-of-band interrupt signal notifies the host when the WLAN device wants to turn on the SDIO interface. The ability to force control of the gated clocks from within the WLAN chip is also provided. SDIO mode is enabled using the strapping option pins. See Table 21 on page 108 for details. Three functions are supported: * Function 0 standard SDIO function. The maximum block size is 32 bytes. * Function 1 backplane function to access the internal System-on-a-Chip (SoC) address space. The maximum block size is 64 bytes. * Function 2 WLAN function for efficient WLAN packet transfer through DMA. The maximum block size is 512 bytes. SDIO Pin Descriptions Table 4: SDIO Pin Descriptions SD 4-Bit Mode DATA0 Data line 0 DATA1 DATA2 SD 1-Bit Mode DATA gSPI Mode Data line DO Data output Data line 1 or Interrupt IRQ Interrupt IRQ Interrupt Data line 2 NC Not used NC Not used DATA3 Data line 3 NC Not used CS Card select CLK Clock CLK Clock SCLK Clock CMD Command line CMD Command line DI Data input Figure 11: Signal Connections to SDIO Host (SD 4-Bit Mode) CLK CMD SD Host BCM4343W DAT[3:0] Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 33 BROADCOM CONFIDENTIAL BCM4343W Data Sheet SDIO v2.0 Figure 12: Signal Connections to SDIO Host (SD 1-Bit Mode) CLK CMD BCM4343W SD Host DATA IRQ Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 34 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Generic SPI Mode Generic SPI Mode In addition to the full SDIO mode, the BCM4343W includes the option of using the simplified generic SPI (gSPI) interface/protocol. Characteristics of the gSPI mode include: * Up to 50 MHz operation * Fixed delays for responses and data from the device * Alignment to host gSPI frames (16 or 32 bits) * Up to 2 KB frame size per transfer * Little-endian and big-endian configurations * A configurable active edge for shifting * Packet transfer through DMA for WLAN gSPI mode is enabled using the strapping option pins. See Table 21 on page 108 for details. Figure 13: Signal Connections to SDIO Host (gSPI Mode) SCLK DI DO SD Host BCM4343W IRQ CS Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 35 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Generic SPI Mode SPI Protocol The SPI protocol supports both 16-bit and 32-bit word operation. Byte endianess is supported in both modes. Figure 14 and Figure 15 on page 37 show the basic write and write/read commands. Figure 14: gSPI Write Protocol Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 36 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Generic SPI Mode Figure 15: gSPI Read Protocol Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 37 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Generic SPI Mode Command Structure The gSPI command structure is 32 bits. The bit positions and definitions are shown in Figure 16. Figure 16: gSPI Command Structure BCM_SPID Command Structure 31 30 29 28 27 C A 11 10 F1 F0 Address - 17 bits 0 Packet length - 11bits * * 11'h0 = 2048 bytes Function No: 00 - Func 0: 0 All SPI-specific registers 01 - Func 1: 1 Registers and memories belonging to other blocks in the chip (64 bytes max) 10 - Func 2: 2 DMA channel 1. WLAN packets up to 2048 bytes. 11 - Func 3: 3 DMA channel 2 (optional). Packets up to 2048 bytes. Access : 0 - Fixed address 1 - Incremental address Command : 0 - Read 1 - Write Write The host puts the first bit of the data onto the bus half a clock-cycle before the first active edge following the CS going low. The following bits are clocked out on the falling edge of the gSPI clock. The device samples the data on the active edge. Write/Read The host reads on the rising edge of the clock requiring data from the device to be made available before the first rising-clock edge of the data. The last clock edge of the fixed delay word can be used to represent the first bit of the following data word. This allows data to be ready for the first clock edge without relying on asynchronous delays. Read The read command always follows a separate write to set up the WLAN device for a read. This command differs from the write/read command in the following respects: a) chip selects go high between the command/address and the data, and b) the time interval between the command/address is not fixed. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 38 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Generic SPI Mode Status The gSPI interface supports status notification to the host after a read/write transaction. This status notification provides information about packet errors, protocol errors, available packets in the RX queue, etc. The status information helps reduce the number of interrupts to the host. The status-reporting feature can be switched off using a register bit, without any timing overhead. The gSPI bus timing for read/write transactions with and without status notification are as shown in Figure 17 below and Figure 18 on page 40. See Table 5 on page 40 for information on status-field details. Figure 17: gSPI Signal Timing Without Status Write CS SCLK MOSI C31 C31 C30 C30 C1 C1 C0 C0 D31 D31 D30 D30 Command 32 bits Write-Read D1 D1 D0 D0 Write Data 16*n bits CS SCLK MOSI C31 C31 C30 C30 C0 C0 MISO D31 D31 D30 D30 Response Delay Command 32 bits Read D1 D1 D0 D0 Read Data 16*n bits CS SCLK MOSI C31 C31 C30 C30 C0 C0 D31 D31 D30 D30 MISO Command 32 bits Broadcom(R) August 24, 2015 * 4343W-DS107-R Response Delay D0 D0 Read Data 16*n bits Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 39 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Generic SPI Mode Figure 18: gSPI Signal Timing with Status (Response Delay = 0) CS Write SCLK MOSI C31 C31 C1 C1 C0 C0 D31 D31 D1 D1 D0 D0 S31 S31 MISO Command 32 bits Write-Read Write Data 16*n bits S1 S1 S0 S0 Status 32 bits CS SCLK MOSI C31 C31 C0 C0 MISO D31 D31 D0 D0 Read Data 16*n bits Command 32 bits Read D1 D1 S31 S31 S0 S0 Status 32 bits CS SCLK MOSI C31 C31 C0 C0 MISO D31 D31 Command 32 bits D1 D1 D0 D0 Read Data 16*n bits S31 S31 S0 S0 Status 32 bits Table 5: gSPI Status Field Details Bit Name Description 0 Data not available The requested read data is not available. 1 Underflow FIFO underflow occurred due to current (F2, F3) read command. 2 Overflow FIFO overflow occurred due to current (F1, F2, F3) write command. 3 F2 interrupt F2 channel interrupt. 5 F2 RX ready F2 FIFO is ready to receive data (FIFO empty). 7 Reserved - 8 F2 packet available Packet is available/ready in F2 TX FIFO. 9:19 F2 packet length Length of packet available in F2 FIFO Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 40 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Generic SPI Mode gSPI Host-Device Handshake To initiate communication through the gSPI after power-up, the host needs to bring up the WLAN chip by writing to the wake-up WLAN register bit. Writing a 1 to this bit will start up the necessary crystals and PLLs so that the BCM4343W is ready for data transfer. The device can signal an interrupt to the host indicating that the device is awake and ready. This procedure also needs to be followed for waking up the device in sleep mode. The device can interrupt the host using the WLAN IRQ line whenever it has any information to pass to the host. On getting an interrupt, the host needs to read the interrupt and/or status register to determine the cause of the interrupt and then take necessary actions. Boot-Up Sequence After power-up, the gSPI host needs to wait 50 ms for the device to be out of reset. For this, the host needs to poll with a read command to F0 address 0x14. Address 0x14 contains a predefined bit pattern. As soon as the host gets a response back with the correct register content, it implies that the device has powered up and is out of reset. After that, the host needs to set the wake-up WLAN bit (F0 reg 0x00 bit 7). Wake-up WLAN turns the PLL on; however, the PLL doesn't lock until the host programs the PLL registers to set the crystal frequency. For the first time after power-up, the host needs to wait for the availability of the low-power clock inside the device. Once it is available, the host needs to write to a PMU register to set the crystal frequency. This will turn on the PLL. After the PLL is locked, the chipActive interrupt is issued to the host. This indicates device awake/ ready status. See Table 6 for information on gSPI registers. In Table 6, the following notation is used for register access: * R: Readable from host and CPU * W: Writable from host * U: Writable from CPU Table 6: gSPI Registers Address Register Bit Access Default Description x0000 Word length 0 R/W/U 0 0: 16-bit word length 1: 32-bit word length Endianess 1 R/W/U 0 0: Little endian 1: Big endian High-speed mode 4 R/W/U 1 0: Normal mode. Sample on SPICLK rising edge, output on falling edge. 1: High-speed mode. Sample and output on rising edge of SPICLK (default). Interrupt polarity 5 R/W/U 1 0: Interrupt active polarity is low. 1: Interrupt active polarity is high (default). Wake-up 7 R/W 0 A write of 1 denotes a wake-up command from host to device. This will be followed by an F2 interrupt from the gSPI device to host, indicating device awake status. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 41 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Generic SPI Mode Table 6: gSPI Registers (Cont.) Address Register Bit Access Default Description x0002 Status enable 0 R/W 1 0: No status sent to host after a read/write. 1: Status sent to host after a read/write. Interrupt with status 1 R/W 0 0: Do not interrupt if status is sent. 1: Interrupt host even if status is sent. x0003 Reserved - - - - x0004 Interrupt register 0 R/W 0 Requested data not available. Cleared by writing a 1 to this location. 1 R 0 F2/F3 FIFO underflow from the last read. 2 R 0 F2/F3 FIFO overflow from the last write. 5 R 0 F2 packet available 6 R 0 F3 packet available 7 R 0 F1 overflow from the last write. 5 R 0 F1 Interrupt 6 R 0 F2 Interrupt 7 R 0 F3 Interrupt x0005 Interrupt register x0006, x0007 Interrupt enable register 15:0 R/W/U 16'hE0E7 Particular interrupt is enabled if a corresponding bit is set. x0008 to x000B Status register 31:0 R 32'h0000 Same as status bit definitions x000C, x000D F1 info. register x000E, x000F F2 info. register 0 R 1 F1 enabled 1 R 0 F1 ready for data transfer 13:2 R/U 12'h40 F1 maximum packet size 0 R/U 1 F2 enabled 1 R 0 F2 ready for data transfer 15:2 R/U 14'h800 F2 maximum packet size 31:0 R 32'hFEEDB This register contains a predefined pattern, which EAD the host can read to determine if the gSPI interface is working properly. R/W/U 32'h000000 This is a dummy register where the host can write 00 some pattern and read it back to determine if the gSPI interface is working properly. R/W 0x1D = 4, other registers = 0 x0014 to x0017 Test-Read only register x0018 to x001B Test-R/W register 31:0 x001C to Response delay x001F registers 7:0 Individual response delays for F0, F1, F2, and F3. The value of the registers is the number of byte delays that are introduced before data is shifted out of the gSPI interface during host reads. Figure 19 on page 43 shows the WLAN boot-up sequence from power-up to firmware download, including the initial device power-on reset (POR) evoked by the WL_REG_ON signal. After initial power-up, the WL_REG_ON signal can be held low to disable the BCM4343W or pulsed low to induce a subsequent reset. Note: The BCM4343W has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 3 ms after VDDC and VDDIO have both passed the 0.6V threshold. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 42 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Generic SPI Mode Figure 19: WLAN Boot-Up Sequence Ramp time from 0V to 4.3V > 40 s 0.6V VBAT VDDIO > 2 Sleep Clock cycles WL_REG_ON < 1.5 ms VDDC (from internal PMU) < 3 ms Internal POR < 50 ms After a fixed delay following internal POR going high, the device responds to host F0 (address 0x14) reads. Device requests a reference clock. 1 15 ms SPI Host Interaction: 1 After 15 ms the reference clock is assumed to be up. Access to PLL registers is possible. Host polls F0 (address 0x14) until it reads a predefined pattern. Host sets wakeupwlan bit 1 and waits 15 ms , the maximum time for reference clock availability. 1 After 15 ms, the host programs the PLL registers to set the crystal frequency. Chipactive interrupt is asserted after the PLL locks. WL_IRQ Host downloads code. 1 This wait time is programmable in sleepclock increments from 1 to 255 (30 us to 15 ms). Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 43 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Wireless LAN MAC and PHY S e c t i o n 5 : Wi r e l e s s L A N M A C a n d P H Y MAC Features The BCM4343W WLAN MAC supports features specified in the IEEE 802.11 base standard, and amended by IEEE 802.11n. The salient features are listed below: * Transmission and reception of aggregated MPDUs (A-MPDU). * Support for power management schemes, including WMM power-save, power-save multipoll (PSMP) and multiphase PSMP operation. * Support for immediate ACK and Block-ACK policies. * Interframe space timing support, including RIFS. * Support for RTS/CTS and CTS-to-self frame sequences for protecting frame exchanges. * Back-off counters in hardware for supporting multiple priorities as specified in the WMM specification. * Timing synchronization function (TSF), network allocation vector (NAV) maintenance, and target beacon transmission time (TBTT) generation in hardware. * Hardware off-load for AES-CCMP, legacy WPA TKIP, legacy WEP ciphers, WAPI, and support for key management. * Support for coexistence with Bluetooth and other external radios. * Programmable independent basic service set (IBSS) or infrastructure basic service set functionality * Statistics counters for MIB support. MAC Description The BCM4343W WLAN MAC is designed to support high throughput operation with low-power consumption. It does so without compromising on Bluetooth coexistence policies, thereby enabling optimal performance over both networks. In addition, several power-saving modes that have been implemented allow the MAC to consume very little power while maintaining network-wide timing synchronization. The architecture diagram of the MAC is shown in Figure 20 on page 45. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 44 BROADCOM CONFIDENTIAL BCM4343W Data Sheet MAC Features Figure 20: WLAN MAC Architecture Embedded CPU Interface Host Registers, DMA Engines TXFIFO 32 KB PMQ RXFIFO 10 KB PSM PSM UCODE Memory IFS Backoff, BTCX WEP WEP, TKIP, AES TSF SHM BUS IHR NAV BUS RXE RX AMPDU TXE TX AMPDU EXT IHR MAC Shared Memory 6 KB PHY Interface The following sections provide an overview of the important modules in the MAC. PSM The programmable state machine (PSM) is a microcoded engine that provides most of the low-level control to the hardware to implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized for flowcontrol operations, which are predominant in implementations of communication protocols. The instruction set and fundamental operations are simple and general, which allows algorithms to be optimized until very late in the design process. It also allows for changes to the algorithms to track evolving IEEE 802.11 specifications. The PSM fetches instructions from the microcode memory. It uses the shared memory to obtain operands for instructions, as a data store, and to exchange data between both the host and the MAC data pipeline (via the SHM bus). The PSM also uses a scratch-pad memory (similar to a register bank) to store frequently accessed and temporary variables. The PSM exercises fine-grained control over the hardware engines by programming internal hardware registers (IHR). These IHRs are collocated with the hardware functions they control and are accessed by the PSM via the IHR bus. The PSM fetches instructions from the microcode memory using an address determined by the program counter, an instruction literal, or a program stack. For ALU operations, the operands are obtained from shared memory, scratch-pad memory, IHRs, or instruction literals, and the results are written into the shared memory, scratch-pad memory, or IHRs. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 45 BROADCOM CONFIDENTIAL BCM4343W Data Sheet MAC Features There are two basic branch instructions: conditional branches and ALU-based branches. To better support the many decision points in the IEEE 802.11 algorithms, branches can depend on either readily available signals from the hardware modules (branch condition signals are available to the PSM without polling the IHRs) or on the results of ALU operations. WEP The wired equivalent privacy (WEP) engine encapsulates all the hardware accelerators to perform the encryption and decryption, as well as the MIC computation and verification. The accelerators implement the following cipher algorithms: legacy WEP, WPA TKIP, and WPA2 AES-CCMP. Based on the frame type and association information, the PSM determines the appropriate cipher algorithm to be used. It supplies the keys to the hardware engines from an on-chip key table. The WEP interfaces with the transmit engine (TXE) to encrypt and compute the MIC on transmit frames and the receive engine (RXE) to decrypt and verify the MIC on receive frames. WAPI is also supported. TXE The transmit engine (TXE) constitutes the transmit data path of the MAC. It coordinates the DMA engines to store the transmit frames in the TXFIFO. It interfaces with WEP module to encrypt frames and transfers the frames across the MAC-PHY interface at the appropriate time determined by the channel access mechanisms. The data received from the DMA engines are stored in transmit FIFOs. The MAC supports multiple logical queues to support traffic streams that have different QoS priority requirements. The PSM uses the channel access information from the IFS module to schedule a queue from which the next frame is transmitted. Once the frame is scheduled, the TXE hardware transmits the frame based on a precise timing trigger received from the IFS module. The TXE module also contains the hardware that allows the rapid assembly of MPDUs into an A-MPDU for transmission. The hardware module aggregates the encrypted MPDUs by adding appropriate headers and pad delimiters as needed. RXE The receive engine (RXE) constitutes the receive data path of the MAC. It interfaces with the DMA engine to drain the received frames from the RX FIFO. It transfers bytes across the MAC-PHY interface and interfaces with the WEP module to decrypt frames. The decrypted data is stored in the RX FIFO. The RXE module contains programmable filters that are programmed by the PSM to accept or filter frames based on several criteria such as receiver address, BSSID, and certain frame types. The RXE module also contains the hardware required to detect A-MPDUs, parse the headers of the containers, and disaggregate them into component MPDUS. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 46 BROADCOM CONFIDENTIAL BCM4343W Data Sheet MAC Features IFS The IFS module contains the timers required to determine interframe space timing including RIFS timing. It also contains multiple back-off engines required to support prioritized access to the medium as specified by WMM. The interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the PHY. These timers provide precise timing to the TXE to begin frame transmission. The TXE uses this information to send response frames or perform transmit frame-bursting (RIFS or SIFS separated, as within a TXOP). The back-off engines (for each access category) monitor channel activity, in each slot duration, to determine whether to continue or pause the back-off counters. When the back-off counters reach 0, the TXE gets notified so that it may commence frame transmission. In the event of multiple back-off counters decrementing to 0 at the same time, the hardware resolves the conflict based on policies provided by the PSM. The IFS module also incorporates hardware that allows the MAC to enter a low-power state when operating under the IEEE power-saving mode. In this mode, the MAC is in a suspended state with its clock turned off. A sleep timer, whose count value is initialized by the PSM, runs on a slow clock and determines the duration over which the MAC remains in this suspended state. Once the timer expires, the MAC is restored to its functional state. The PSM updates the TSF timer based on the sleep duration, ensuring that the TSF is synchronized to the network. The IFS module also contains the PTA hardware that assists the PSM in Bluetooth coexistence functions. TSF The timing synchronization function (TSF) module maintains the TSF timer of the MAC. It also maintains the target beacon transmission time (TBTT). The TSF timer hardware, under the control of the PSM, is capable of adopting timestamps received from beacon and probe response frames in order to maintain synchronization with the network. The TSF module also generates trigger signals for events that are specified as offsets from the TSF timer, such as uplink and downlink transmission times used in PSMP. NAV The network allocation vector (NAV) timer module is responsible for maintaining the NAV information conveyed through the duration field of MAC frames. This ensures that the MAC complies with the protection mechanisms specified in the standard. The hardware, under the control of the PSM, maintains the NAV timer and updates the timer appropriately based on received frames. This timing information is provided to the IFS module, which uses it as a virtual carriersense indication. MAC-PHY Interface The MAC-PHY interface consists of a data path interface to exchange RX/TX data from/to the PHY. In addition, there is a programming interface, which can be controlled either by the host or the PSM to configure and control the PHY. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 47 BROADCOM CONFIDENTIAL BCM4343W Data Sheet PHY Description PHY Description The BCM4343W WLAN digital PHY is designed to comply with IEEE 802.11b/g/n single stream to provide wireless LAN connectivity supporting data rates from 1 Mbps to 96 Mbps for low-power, high-performance handheld applications. The PHY has been designed to meet specification requirements in the presence of interference, radio nonlinearity, and impairments. It incorporates efficient implementations of the filters, FFT, and Viterbi decoder algorithms. Efficient algorithms have been designed to achieve maximum throughput and reliability, including algorithms for carrier sense/rejection, frequency/phase/timing acquisition and tracking, and channel estimation and tracking. The PHY receiver also contains a robust IEEE 802.11b demodulator. The PHY carrier sense has been tuned to provide high throughput for IEEE 802.11g/IEEE 802.11b hybrid networks with Bluetooth coexistence. PHY Features * Supports the IEEE 802.11b/g/n single-stream standards. * Explicit IEEE 802.11n transmit beamforming. * Supports optional Greenfield mode in TX and RX. * Tx and Rx LDPC for improved range and power efficiency. * Supports IEEE 802.11h/d for worldwide operation. * Algorithms achieving low power, enhanced sensitivity, range, and reliability. * Algorithms to maximize throughput performance in the presence of Bluetooth signals. * Automatic gain control scheme for blocking and nonblocking application scenarios for cellular applications. * Closed-loop transmit power control. * Designed to meet FCC and other regulatory requirements. * Support for 2.4 GHz Broadcom TurboQAM data rates and 20 MHz channel bandwidth. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 48 BROADCOM CONFIDENTIAL BCM4343W Data Sheet PHY Description Figure 21: WLAN PHY Block Diagram Filters and Radio Comp AFE and Radio Radio Control Block CCK/DSSS Demodulate Frequency and Timing Synch OFDM Demodulate Carrier Sense, AGC, and Rx FSM Buffers Viterbi Decoder Descramble and Deframe MAC Interface FFT/IFFT Modulation and Coding Tx FSM Frame and Scramble Filters and Radio Comp PA Comp Modulate/ Spread COEX The PHY is capable of fully calibrating the RF front-end to extract the highest performance. On power-up, the PHY performs a full calibration suite to correct for IQ mismatch and local oscillator leakage. The PHY also performs periodic calibration to compensate for any temperature related drift, thus maintaining highperformance over time. A closed-loop transmit control algorithm maintains the output power at its required level and can control TX power on a per-packet basis. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 49 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLAN Radio Subsystem Section 6: WLAN Radio Subsystem The BCM4343W includes an integrated WLAN RF transceiver that has been optimized for use in 2.4 GHz Wireless LAN systems. It is designed to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM band. The transmit and receive sections include all on-chip filtering, mixing, and gain control functions. Improvements to the radio design include shared TX/RX baseband filters and high immunity to supply noise. Figure 22 shows the radio functional block diagram. Figure 22: Radio Functional Block Diagram WL DAC WL TXLPF WL PA WL DAC WL PGA WL TX GMixer WL TXLPF Voltage Regulators WLAN BB 4 ~ 6 nH Recommend Q = 40 WLRF_2G_RF WL ADC 10 pF WL RXLPF WLRF_2G_eLG SLNA WL ADC WL GLNA12 WL RX GMixer WL RXLPF WL ATX WL ARX WL GTX WL GRX Gm BT LNA GM CLB WL LOGEN WL PLL Shared XO BT RX BT TX BT LOGEN BT PLL LPO/Ext LPO/RCAL BT ADC BT RXLPF BT ADC BT LNA Load BT PA BT RX Mixer BT RXLPF BT BB BT FM BT DAC BT DAC BT TX Mixer Broadcom(R) August 24, 2015 * 4343W-DS107-R BT TXLPF Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 50 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Receive Path Receive Path The BCM4343W has a wide dynamic range, direct conversion receiver. It employs high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. Transmit Path Baseband data is modulated and upconverted to the 2.4 GHz ISM band. A linear on-chip power amplifier is included, which is capable of delivering high output powers while meeting IEEE 802.11b/g/n specifications without the need for an external PA. This PA is supplied by an internal LDO that is directly supplied by VBAT, thereby eliminating the need for a separate PALDO. Closed-loop output power control is integrated. Calibration The BCM4343W features dynamic on-chip calibration, eliminating process variation across components. This enables the BCM4343W to be used in high-volume applications because calibration routines are not required during manufacturing testing. These calibration routines are performed periodically during normal radio operation. Automatic calibration examples include baseband filter calibration for optimum transmit and receive performance and LOFT calibration for leakage reduction. In addition, I/Q calibration, R calibration, and VCO calibration are performed on-chip. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 51 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Bluetooth + FM Subsystem Overview Section 7: Bluetooth + FM Subsystem Overview The Broadcom BCM4343W is a Bluetooth 4.1-compliant, baseband processor and 2.4 GHz transceiver with an integrated FM/RDS/RBDS receiver. It features the highest level of integration and eliminates all critical external components, thus minimizing the footprint, power consumption, and system cost of a Bluetooth plus FM radio solution. The BCM4343W is the optimal solution for any Bluetooth voice and/or data application that also requires an FM radio receiver. The Bluetooth subsystem presents a standard Host Controller Interface (HCI) via a high speed UART and PCM interface for audio. The FM subsystem supports the HCI control interface as well as I2S, PCM, and stereo analog interfaces. The BCM4343W incorporates all Bluetooth 4.1 features including secure simple pairing, sniff subrating, and encryption pause and resume. The BCM4343W Bluetooth radio transceiver provides enhanced radio performance to meet the most stringent mobile phone temperature applications and the tightest integration into mobile handsets and portable devices. It is fully compatible with any of the standard TCXO frequencies and provides full radio compatibility to operate simultaneously with GPS, WLAN, NFC, and cellular radios. The Bluetooth transmitter also features a Class 1 power amplifier with Class 2 capability. Features Major Bluetooth features of the BCM4343W include: * Supports key features of upcoming Bluetooth standards * Fully supports Bluetooth Core Specification version 4.1 plus enhanced data rate (EDR) features: - Adaptive Frequency Hopping (AFH) - Quality of Service (QoS) - Extended Synchronous Connections (eSCO)--voice connections - Fast connect (interlaced page and inquiry scans) - Secure Simple Pairing (SSP) - Sniff Subrating (SSR) - Encryption Pause Resume (EPR) - Extended Inquiry Response (EIR) - Link Supervision Timeout (LST) * UART baud rates up to 4 Mbps * Supports all Bluetooth 4.1 packet types * Supports maximum Bluetooth data rates over HCI UART Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 52 BROADCOM CONFIDENTIAL BCM4343W Data Sheet * Features Multipoint operation with up to seven active slaves - Maximum of seven simultaneous active ACL links - Maximum of three simultaneous active SCO and eSCO connections with scatternet support * Trigger Beacon fast connect (TBFC) * Narrowband and wideband packet loss concealment * Scatternet operation with up to four active piconets with background scan and support for scatter mode * High-speed HCI UART transport support with low-power out-of-band BT_DEV_WAKE and BT_HOST_WAKE signaling (see "Host Controller Power Management" on page 58) * Channel-quality driven data rate and packet type selection * Standard Bluetooth test modes * Extended radio and production test mode features * Full support for power savings modes - Bluetooth clock request - Bluetooth standard sniff - Deep-sleep modes and software regulator shutdown * TCXO input and auto-detection of all standard handset clock frequencies. Also supports a low-power crystal, which can be used during power save mode for better timing accuracy. Major FM Radio features include: * 65 MHz to 108 MHz FM bands supported (US, Europe, and Japan) * FM subsystem control using the Bluetooth HCI interface * FM subsystem operates from reference clock inputs. * Improved audio interface capabilities with full-featured bidirectional PCM, I2S, and stereo analog output. * I2S can be master or slave. FM Receiver-Specific Features Include: * Excellent FM radio performance with 1 V sensitivity for 26 dB (S+N)/N * Signal-dependent stereo/mono blending * Signal dependent soft mute * Auto search and tuning modes * Audio silence detection * RSSI and IF frequency status indicators * RDS and RBDS demodulator and decoder with filter and buffering functions * Automatic frequency jump Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 53 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Bluetooth Radio Bluetooth Radio The BCM4343W has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM band. It is fully compliant with the Bluetooth Radio Specification and EDR specification and meets or exceeds the requirements to provide the highest communication link quality of service. Transmit The BCM4343W features a fully integrated zero-IF transmitter. The baseband transmit data is GFSK-modulated in the modem block and upconverted to the 2.4 GHz ISM band in the transmitter path. The transmitter path has signal filters, an I/Q upconverter, an output power amplifier, and RF filters. The transmitter path also incorporates /4-DQPSK for 2 Mbps and 8-DPSK for 3 Mbps to support EDR. The transmitter section is compatible with the Bluetooth Low Energy specification. The transmitter PA bias can also be adjusted to provide Bluetooth Class 1 or Class 2 operation. Digital Modulator The digital modulator performs the data modulation and filtering required for the GFSK, /4-DQPSK, and 8- DPSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal and is much more stable than direct VCO modulation schemes. Digital Demodulator and Bit Synchronizer The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit-synchronization algorithm. Power Amplifier The fully integrated PA supports Class 1 or Class 2 output using a highly linearized, temperature-compensated design. This provides greater flexibility in front-end matching and filtering. Due to the linear nature of the PA combined with some integrated filtering, external filtering is required to meet the Bluetooth and regulatory harmonic and spurious requirements. For integrated mobile handset applications in which Bluetooth is integrated next to the cellular radio, external filtering can be applied to achieve near-thermal noise levels for spurious and radiated noise emissions. The transmitter features a sophisticated on-chip transmit signal strength indicator (TSSI) block to keep the absolute output power variation within a tight range across process, voltage, and temperature. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 54 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Bluetooth Radio Receiver The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology with built-in out-of-band attenuation enables the BCM4343W to be used in most applications with minimal off-chip filtering. For integrated handset operation, in which the Bluetooth function is integrated close to the cellular transmitter, external filtering is required to eliminate the desensitization of the receiver by the cellular transmit signal. Digital Demodulator and Bit Synchronizer The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit synchronization algorithm. Receiver Signal Strength Indicator The radio portion of the BCM4343W provides a Receiver Signal Strength Indicator (RSSI) signal to the baseband so that the controller can take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter should increase or decrease its output power. Local Oscillator Generation Local Oscillator (LO) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The LO generation subblock employs an architecture for high immunity to LO pulling during PA operation. The BCM4343W uses an internal RF and IF loop filter. Calibration The BCM4343W radio transceiver features an automated calibration scheme that is self contained in the radio. No user interaction is required during normal operation or during manufacturing to optimize performance. Calibration optimizes the performance of all the major blocks within the radio to within 2% of optimal conditions, including filter gain and phase characteristics, matching between key components, and key gain blocks. This takes into account process variation and temperature variation. Calibration occurs transparently during normal operation during the settling time of the hops and calibrates for temperature variations as the device cools and heats during normal operation in its environment. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 55 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Bluetooth Baseband Core Section 8: Bluetooth Baseband Core The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high-performance Bluetooth operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it, handles data flow control, schedules SCO/ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these functions, it independently handles HCI event types and HCI command types. The following transmit and receive functions are also implemented in the BBC hardware to increase the reliability and security of data before sending and receiving it over the air: * Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), data decryption, and data dewhitening in the receiver. * Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the transmitter. Bluetooth 4.1 Features The BBC supports all Bluetooth 4.1 features, with the following benefits: * Dual-mode classic Bluetooth and classic Low Energy (BT and BLE) operation. * Low energy physical layer * Low energy link layer * Enhancements to HCI for low energy * Low energy direct test mode * 128 AES-CCM secure connection for both BT and BLE Note: The BCM4343W is compatible with the Bluetooth Low Energy operating mode, which provides a dramatic reduction in the power consumption of the Bluetooth radio and baseband. The primary application for this mode is to provide support for low data rate devices, such as sensors and remote controls. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 56 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Link Control Layer Link Control Layer The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU). This layer contains the command controller that takes commands from the software, and other controllers that are activated or configured by the command controller, to perform the link control tasks. Each task performs a different state in the Bluetooth link controller. * Major states: - Standby - Connection * Substates: - Page - Page Scan - Inquiry - Inquiry Scan - Sniff - BLE Adv - BLE Scan/Initiation Test Mode Support The BCM4343W fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version 3.0. This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence. In addition to the standard Bluetooth Test Mode, the BCM4343W also supports enhanced testing features to simplify RF debugging and qualification as well as type-approval testing. These features include: * Fixed frequency carrier-wave (unmodulated) transmission - Simplifies some type-approval measurements (Japan) - Aids in transmitter performance analysis * Fixed frequency constant receiver mode - Receiver output directed to an I/O pin - Allows for direct BER measurements using standard RF test equipment - Facilitates spurious emissions testing for receive mode * Fixed frequency constant transmission - Eight-bit fixed pattern or PRBS-9 - Enables modulated signal measurements with standard RF test equipment Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 57 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Bluetooth Power Management Unit Bluetooth Power Management Unit The Bluetooth Power Management Unit (PMU) provides power management features that can be invoked by either software through power management registers or packet handling in the baseband core. The power management functions provided by the BCM4343W are: * RF Power Management * Host Controller Power Management * BBC Power Management * FM Power Management RF Power Management The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz transceiver. The transceiver then processes the power-down functions accordingly. Host Controller Power Management When running in UART mode, the BCM4343W can be configured so that dedicated signals are used for power management handshaking between the BCM4343W and the host. The basic power saving functions supported by those handshaking signals include the standard Bluetooth defined power savings modes and standby modes of operation. Table 7 describes the power-control handshake signals used with the UART interface. Table 7: Power Control Pin Description Signal Type Description BT_DEV_WAKE I Bluetooth device wake-up signal: Signal from the host to the BCM4343W indicating that the host requires attention. * Asserted: The Bluetooth device must wake up or remain awake. * Deasserted: The Bluetooth device may sleep when sleep criteria are met. The polarity of this signal is software configurable and can be asserted high or low. BT_HOST_WAKE O Host wake-up signal. Signal from the BCM4343W to the host indicating that the BCM4343W requires attention. * Asserted: Host device must wake up or remain awake. * Deasserted: Host device may sleep when sleep criteria are met. The polarity of this signal is software configurable and can be asserted high or low. CLK_REQ O The BCM4343W asserts CLK_REQ when Bluetooth or WLAN directs the host to turn on the reference clock. The CLK_REQ polarity is active-high. Add an external 100 k pull-down resistor to ensure the signal is deasserted when the BCM4343W powers up or resets when VDDIO is present. Note: Pad function Control Register is set to 0 for these pins. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 58 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Bluetooth Power Management Unit Figure 23: Startup Signaling Sequence LPO VDDIO Host IOs unconfigured Host IOs configured HostResetX T1 BT_GPIO_0 (BT_DEV_WAKE) T2 BTH IOs unconfigured BTH IOs configured BT_REG_ON BT_GPIO_1 (BT_HOST_WAKE) T3 Host side drives this line low BT_UART_CTS_N T4 BT_UART_RTS_N CLK_REQ_OUT T5 BTH device drives this line low indicating transport is ready Driven Pulled Notes : T1 is the time for host to settle it's IOs after a reset. T2 is the time for host to drive BT_REG_ON high after the Host IOs are configured. T3 is the time for BTH (Bluetooth) device to settle its IOs after a reset and reference clock settling time has elapsed. T4 is the time for BTH device to drive BT_UART_RTS_N low after the host drives BT_UART_CTS_N low. This assumes the BTH device has already completed initialization. T5 is the time for BTH device to drive CLK_REQ_OUT high after BT_REG_ON goes high. Note this pin is used for designs that use an external reference clock source from the Host. This pin is irrelevant for Crystal reference clock based designs where the BTH device generates it's own reference clock from an external crystal connected to it's oscillator circuit. Timing diagram assumes VBAT is present. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 59 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Bluetooth Power Management Unit BBC Power Management The following are low-power operations for the BBC: * Physical layer packet-handling turns the RF on and off dynamically within transmit/receive packets. * Bluetooth-specified low-power connection modes: sniff and hold. While in these modes, the BCM4343W runs on the low-power oscillator and wakes up after a predefined time period. * A low-power shutdown feature allows the device to be turned off while the host and any other devices in the system remain operational. When the BCM4343W is not needed in the system, the RF and core supplies are shut down while the I/O remains powered. This allows the BCM4343W to effectively be off while keeping the I/O pins powered, so they do not draw extra current from any other I/O-connected devices. During the low-power shut-down state, provided VDDIO remains applied to the BCM4343W, all outputs are tristated, and most input signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths or create loading on digital signals in the system and enables the BCM4343W to be fully integrated in an embedded device to take full advantage of the lowest powersaving modes. Two BCM4343W input signals are designed to be high-impedance inputs that do not load the driving signal even if the chip does not have VDDIO power supplied to it: the frequency reference input (WRF_TCXO_IN) and the 32.768 kHz input (LPO). When the BCM4343W is powered on from this state, it is the same as a normal power-up, and the device does not contain any information about its state from the time before it was powered down. FM Power Management The BCM4343W FM subsystem can operate independently of, or in tandem with, the Bluetooth RF and BBC subsystems. The FM subsystem power management scheme operates in conjunction with the Bluetooth RF and BBC subsystems. The FM block does not have a low power state, it is either on or off. Wideband Speech The BCM4343W provides support for wideband speech (WBS) technology. The BCM4343W can perform subband-codec (SBC), as well as mSBC, encoding and decoding of linear 16 bits at 16 kHz (256 kbps rate) transferred over the PCM bus. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 60 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Bluetooth Power Management Unit Packet Loss Concealment Packet Loss Concealment (PLC) improves the apparent audio quality for systems with marginal link performance. Bluetooth messages are sent in packets. When a packet is lost, it creates a gap in the received audio bit-stream. Packet loss can be mitigated in several ways: * Fill in zeros. * Ramp down the output audio signal toward zero (this is the method used in current Bluetooth headsets). * Repeat the last frame (or packet) of the received bit-stream and decode it as usual (frame repeat). These techniques cause distortion and popping in the audio stream. The BCM4343W uses a proprietary waveform extension algorithm to provide dramatic improvement in the audio quality. Figure 24 and Figure 25 show audio waveforms with and without Packet Loss Concealment. Broadcom PLC/BEC algorithms also support wideband speech. Figure 24: CVSD Decoder Output Waveform Without PLC Packet losses causes ramp-down Figure 25: CVSD Decoder Output Waveform After Applying PLC Codec Encoding The BCM4343W can support SBC and mSBC encoding and decoding for wideband speech. Multiple Simultaneous A2DP Audio Streams The BCM4343W has the ability to take a single audio stream and output it to multiple Bluetooth devices simultaneously. This allows a user to share his or her music (or any audio stream) with a friend. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 61 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Adaptive Frequency Hopping FM Over Bluetooth FM Over Bluetooth enables the BCM4343W to stream data from FM over Bluetooth without requiring the host to be awake. This can significantly extend battery life for usage cases where someone is listening to FM radio on a Bluetooth headset. Adaptive Frequency Hopping The BCM4343W gathers link quality statistics on a channel by channel basis to facilitate channel assessment and channel map selection. The link quality is determined using both RF and baseband signal processing to provide a more accurate frequency-hop map. Advanced Bluetooth/WLAN Coexistence The BCM4343W includes advanced coexistence technologies that are only possible with a Bluetooth/WLAN integrated die solution. These coexistence technologies are targeted at small form-factor platforms, such as cell phones and media players, including applications such as VoWLAN + SCO and Video-over-WLAN + High Fidelity BT Stereo. Support is provided for platforms that share a single antenna between Bluetooth and WLAN. Dual-antenna applications are also supported. The BCM4343W radio architecture allows for lossless simultaneous Bluetooth and WLAN reception for shared antenna applications. This is possible only via an integrated solution (shared LNA and joint AGC algorithm). It has superior performance versus implementations that need to arbitrate between Bluetooth and WLAN reception. The BCM4343W integrated solution enables MAC-layer signaling (firmware) and a greater degree of sharing via an enhanced coexistence interface. Information is exchanged between the Bluetooth and WLAN cores without host processor involvement. The BCM4343W also supports Transmit Power Control (TPC) on the STA together with standard Bluetooth TPC to limit mutual interference and receiver desensitization. Preemption mechanisms are utilized to prevent AP transmissions from colliding with Bluetooth frames. Improved channel classification techniques have been implemented in Bluetooth for faster and more accurate detection and elimination of interferers (including nonWLAN 2.4 GHz interference). The Bluetooth AFH classification is also enhanced by the WLAN core's channel information. Fast Connection (Interlaced Page and Inquiry Scans) The BCM4343W supports page scan and inquiry scan modes that significantly reduce the average inquiry response and connection times. These scanning modes are compatible with the Bluetooth version 2.1 page and inquiry procedures. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 62 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Microprocessor and Memory Unit for Bluetooth Section 9: Microprocessor and Memory Unit for Bluetooth The Bluetooth microprocessor core is based on the ARM Cortex-M3 32-bit RISC processor with embedded ICERT debug and JTAG interface units. It runs software from the link control (LC) layer up to the host controller interface (HCI). The ARM core is paired with a memory unit that contains 576 KB of ROM for program storage and boot ROM, and 160 KB of RAM for data scratch-pad and patch RAM code. The internal ROM allows for flexibility during power-on reset (POR) to enable the same device to be used in various configurations. At power-up, the lowerlayer protocol stack is executed from the internal ROM memory. External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes or feature additions. These patches may be downloaded from the host to the BCM4343W through the UART transports. RAM, ROM, and Patch Memory The BCM4343W Bluetooth core has 160 KB of internal RAM which is mapped between general purpose scratch-pad memory and patch memory, and 576 KB of ROM used for the lower-layer protocol stack, test mode software, and boot ROM. The patch memory is used for bug fixes and feature additions to ROM memory code. Reset The BCM4343W has an integrated power-on reset circuit that resets all circuits to a known power-on state. The BT POR circuit is out of reset after BT_REG_ON goes high. If BT_REG_ON is low, then the POR circuit is held in reset. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 63 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Bluetooth Peripheral Transport Unit S e c t i o n 1 0 : B l u e t o o t h P e r i p h e r a l Tr a n s p o r t Unit PCM Interface The BCM4343W supports two independent PCM interfaces that share pins with the I2S interfaces. The PCM interface on the BCM4343W can connect to linear PCM codec devices in master or slave mode. In master mode, the BCM4343W generates the PCM_CLK and PCM_SYNC signals, and in slave mode, these signals are provided by another master on the PCM interface and are inputs to the BCM4343W. The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI commands. Slot Mapping The BCM4343W supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate of 128 kHz, 512 kHz, or 1024 kHz. The corresponding number of slots for these interface rates is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot. Frame Synchronization The BCM4343W supports both short- and long-frame synchronization in both master and slave modes. In shortframe synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident with the first bit of the first slot. Data Formatting The BCM4343W may be configured to generate and accept several different data formats. For conventional narrowband speech mode, the BCM4343W uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0's, 1's, a sign bit, or a programmed value on the output. The default format is 13-bit 2's complement data, left justified, and clocked MSB first. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 64 BROADCOM CONFIDENTIAL BCM4343W Data Sheet PCM Interface Wideband Speech Support When the host encodes Wideband Speech (WBS) packets in transparent mode, the encoded packets are transferred over the PCM bus for an eSCO voice connection. In this mode, the PCM bus is typically configured in master mode for a 4 kHz sync rate with 16-bit samples, resulting in a 64 kbps bit rate. The BCM4343W also supports slave transparent mode using a proprietary rate-matching scheme. In SBC-code mode, linear 16-bit data at 16 kHz (256 kbps rate) is transferred over the PCM bus. Multiplexed Bluetooth and FM over PCM In this mode of operation, the BCM4343W multiplexes both FM and Bluetooth audio PCM channels over the same interface, reducing the number of required I/Os. This mode of operation is initiated through an HCI command from the host. The data stream format contains three channels: a Bluetooth channel followed by two FM channels (audio left and right). In this mode of operation, the bus data rate only supports 48 kHz operation per channel with 16 bits sent for each channel. This is done to allow the low data rate Bluetooth data to coexist in the same interface as the higher speed I2S data. To accomplish this, the Bluetooth data is repeated six times for 8 kHz data and three times for 16 kHz data. An initial sync pulse on the PCM_SYNC line is used to indicate the beginning of the frame. To support multiple Bluetooth audio streams within the Bluetooth channel, both 16 kHz and 8 kHz streams can be multiplexed. This mode of operation is only supported when the Bluetooth host is the master. Figure 26 shows the operation of the multiplexed transport with three simultaneous SCO connections. To accommodate additional SCO channels, the transport clock speed is increased. To change between modes of operation, the transport must be halted and restarted in the new configuration. Figure 26: Functional Multiplex Data Diagram 1 Frame BT SCO 1 RX BT SCO 2 RX BT SCO 3 RX PCM_OUT BT SCO 1 TX BT SCO 2 TX FM right FM left FM right FM left 16 bits per frame 16 bits per frame BT SCO 3 TX PCM_IN PCM_SYNC CLK PCM_CLK 16 bits per SCO frame Each SCO channel duplicates the data 6 times. Each WBS frame duplicates the data 3 times per frame. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 65 BROADCOM CONFIDENTIAL BCM4343W Data Sheet PCM Interface PCM Interface Timing Short Frame Sync, Master Mode Figure 27: PCM Timing Diagram (Short Frame Sync, Master Mode) 1 2 3 PCM_BCLK 4 PCM_SYNC 8 PCM_OUT High Impedance 5 7 6 PCM_IN Table 8: PCM Interface Timing Specifications (Short Frame Sync, Master Mode) Ref No. Characteristics Minimum Typical Maximum Unit 1 PCM bit clock frequency - - 12 MHz 2 PCM bit clock low 41 - - ns 3 PCM bit clock high 41 - - ns 4 PCM_SYNC delay 0 - 25 ns 5 PCM_OUT delay 0 - 25 ns 6 PCM_IN setup 8 - - ns 7 PCM_IN hold 8 - - ns 8 Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance 0 - 25 ns Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 66 BROADCOM CONFIDENTIAL BCM4343W Data Sheet PCM Interface Short Frame Sync, Slave Mode Figure 28: PCM Timing Diagram (Short Frame Sync, Slave Mode) 1 2 3 PCM_BCLK 4 5 PCM_SYNC 9 PCM_OUT High Impedance 6 8 7 PCM_IN Table 9: PCM Interface Timing Specifications (Short Frame Sync, Slave Mode) Ref No. Characteristics Minimum Typical Maximum Unit 1 PCM bit clock frequency - - 12 MHz 2 PCM bit clock low 41 - - ns 3 PCM bit clock high 41 - - ns 4 PCM_SYNC setup 8 - - ns 5 PCM_SYNC hold 8 - - ns 6 PCM_OUT delay 0 - 25 ns 7 PCM_IN setup 8 - - ns 8 PCM_IN hold 8 - - ns 9 Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance 0 - 25 ns Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 67 BROADCOM CONFIDENTIAL BCM4343W Data Sheet PCM Interface Long Frame Sync, Master Mode Figure 29: PCM Timing Diagram (Long Frame Sync, Master Mode) 1 2 3 PCM_BCLK 4 PCM_SYNC 8 PCM_OUT Bit 0 Bit 1 Bit 0 Bit 1 High Impedance 5 7 6 PCM_IN Table 10: PCM Interface Timing Specifications (Long Frame Sync, Master Mode) Ref No. Characteristics Minimum Typical Maximum Unit 1 PCM bit clock frequency - - 12 MHz 2 PCM bit clock low 41 - - ns 3 PCM bit clock high 41 - - ns 4 PCM_SYNC delay 0 - 25 ns 5 PCM_OUT delay 0 - 25 ns 6 PCM_IN setup 8 - - ns 7 PCM_IN hold 8 - - ns 8 Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance 0 - 25 ns Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 68 BROADCOM CONFIDENTIAL BCM4343W Data Sheet PCM Interface Long Frame Sync, Slave Mode Figure 30: PCM Timing Diagram (Long Frame Sync, Slave Mode) 1 2 3 PCM_BCLK 4 5 PCM_SYNC 9 PCM_OUT Bit 0 HIGH IMPEDANCE Bit 1 6 8 7 PCM_IN Bit 0 Bit 1 Table 11: PCM Interface Timing Specifications (Long Frame Sync, Slave Mode) Ref No. Characteristics Minimum Typical Maximum Unit 1 PCM bit clock frequency - - 12 MHz 2 PCM bit clock low 41 - - ns 3 PCM bit clock high 41 - - ns 4 PCM_SYNC setup 8 - - ns 5 PCM_SYNC hold 8 - - ns 6 PCM_OUT delay 0 - 25 ns 7 PCM_IN setup 8 - - ns 8 PCM_IN hold 8 - - ns 9 Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance 0 - 25 ns Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 69 BROADCOM CONFIDENTIAL BCM4343W Data Sheet UART Interface UART Interface The BCM4343W shares a single UART for Bluetooth and FM. The UART is a standard 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 9600 bps to 4.0 Mbps. The interface features an automatic baud rate detection capability that returns a baud rate selection. Alternatively, the baud rate may be selected through a vendor-specific UART HCI command. The UART has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support EDR. Access to the FIFOs is conducted through the Advanced High Performance Bus (AHB) interface through either DMA or the CPU. The UART supports the Bluetooth 4.1 UART HCI specification: H4 and H5. The default baud rate is 115.2 Kbaud. The UART supports the 3-wire H5 UART transport as described in the Bluetooth specification (Three-wire UART Transport Layer). Compared to H4, the H5 UART transport reduces the number of signal lines required by eliminating the CTS and RTS signals. The BCM4343W UART can perform XON/XOFF flow control and includes hardware support for the Serial Line Input Protocol (SLIP). It can also perform a wake-on activity function. For example, activity on the RX or CTS inputs can wake the chip from a sleep state. Normally, the UART baud rate is set by a configuration record downloaded after device reset or by automatic baud rate detection, and the host does not need to adjust the baud rate. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. The BCM4343W UARTs operate correctly with the host UART as long as the combined baud rate error of the two devices is within 2% (see Table 12). Table 12: Example of Common Baud Rates Desired Rate Actual Rate Error (%) 4000000 4000000 0.00 3692000 3692308 0.01 3000000 3000000 0.00 2000000 2000000 0.00 1500000 1500000 0.00 1444444 1454544 0.70 921600 923077 0.16 460800 461538 0.16 230400 230796 0.17 115200 115385 0.16 57600 57692 0.16 38400 38400 0.00 28800 28846 0.16 19200 19200 0.00 14400 14423 0.16 9600 9600 0.00 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 70 BROADCOM CONFIDENTIAL BCM4343W Data Sheet UART Interface UART timing is defined in Figure 31 and Table 13. Figure 31: UART Timing UART_CTS_N 1 2 UART_TXD Midpoint of STOP bit Midpoint of STOP bit UART_RXD 3 UART_RTS_N Table 13: UART Timing Specifications Ref No. Characteristics Minimum Typical Maximum Unit 1 Delay time, UART_CTS_N low to UART_TXD valid - - 1.5 Bit periods 2 Setup time, UART_CTS_N high before midpoint of stop bit - - 0.5 Bit periods 3 Delay time, midpoint of stop bit to UART_RTS_N - high - 0.5 Bit periods Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 71 BROADCOM CONFIDENTIAL I2S Interface BCM4343W Data Sheet I2S Interface The BCM4343W supports an independent I2S digital audio port for high-fidelity FM audio or Bluetooth audio. The I2S interface supports both master and slave modes. The I2S signals are: * I2S Clock: I2S SCK * I2S Word Select: I2S WS * I2S Data Out: I2S SDO * I2S Data In: I2S SDI I2S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S SDO is always an output. The channel word length is 16 bits and the data is justified so that the MSB of the left-channel data is aligned with the MSB of the I2S bus, per the I2S specification. The MSB of each data word is transmitted one bit-clock cycle after the I2S WS transition, synchronous with the falling edge of the bit clock. Left-channel data is transmitted when I2S WS is low, and right-channel data is transmitted when I2S WS is high. Data bits sent by the BCM4343W are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the rising edge of I2S_SSCK. The clock rate in master mode is either of the following: 48 kHz x 32 bits per frame = 1.536 MHz 48 kHz x 50 bits per frame = 2.400 MHz The master clock is generated from the input reference clock using an N/M clock divider. In slave mode, clock rates up to 3.072 MHz are supported. I2S Timing Note: Timing values specified in Table 14 are relative to high and low threshold levels. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 72 BROADCOM CONFIDENTIAL I2S Interface BCM4343W Data Sheet Table 14: Timing for I2S Transmitters and Receivers Transmitter Clock period T Receiver Lower LImit Upper Limit Lower Limit Upper Limit Min. Max. Min. Max. Min. Max. Min. Max. Notes Ttr - - - Tr - - - 1 Master mode: Clock generated by transmitter or receiver. High tHC 0.35Ttr - - - 0.35Ttr - - - 2 Low tLC 0.35Ttr - - - 0.35Ttr - - - 2 Slave mode: Clock accepted by transmitter or receiver. High tHC - 0.35Ttr - - - 0.35Ttr - - 3 Low tLC - 0.35Ttr - - - 0.35Ttr - - 3 Rise time tRC - - 0.15Ttr - - - - - 4 Delay tdtr - - - 0.8T - - - - 5 Hold time thtr 0 - - - - - - - 4 Setup time tsr - - - - - 0.2Tr - - 6 Hold time thr - - - - - 0 - - 6 Transmitter Receiver Note: * * * * * * The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the data transfer rate. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, tHC and tLC are specified with respect to T. In slave mode, the transmitter and receiver need a clock signal with minimum high and low periods so that they can detect the signal. As long as the minimum periods are greater than 0.35Tr, any clock that meets the requirements can be used. Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can result in tdtr not exceeding tRC, which means thtr becomes zero or negative. Therefore, the transmitter has to guarantee that thtr is greater than or equal to zero, as long as the clock rise-time, tRC, does not exceed tRCmax, where tRCmax is not less than 0.15Ttr. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient setup time. The data setup and hold time must not be less than the specified receiver setup and hold time. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 73 BROADCOM CONFIDENTIAL I2S Interface BCM4343W Data Sheet Note: The time periods specified in Figure 32 and Figure 33 are defined by the transmitter speed. The receiver specifications must match transmitter performance. Figure 32: I2S Transmitter Timing T tRC* tLC > 0.35T tHC > 0.35T VH = 2.0V SCK VL = 0.8V thtr > 0 tdtr < 0.8T SD and WS T = Clock period Ttr = Minimum allowed clock period for transmitter T = Ttr * tRC is only relevant for transmitters in slave mode. Figure 33: I2S Receiver Timing T tLC > 0.35T tHC > 0.35 VH = 2.0V SCK VL = 0.8V tsr > 0.2T thr > 0 SD and WS T = Clock period Tr = Minimum allowed clock period for transmitter T > Tr Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 74 BROADCOM CONFIDENTIAL BCM4343W Data Sheet FM Receiver Subsystem S e c t i o n 11: F M R e c e i v e r S u b s y s t e m FM Radio The BCM4343W includes a completely integrated FM radio receiver with RDS/RBDS covering all FM bands from 65 MHz to 108 MHz. The receiver is controlled through commands on the HCI. FM received audio is available as a stereo analog output or in digital form through I2S or PCM. The FM radio operates from the external clock reference. Digital FM Audio Interfaces The FM audio can be transmitted via the shared PCM and I2S pins, and the sampling rate is programmable. The BCM4343W supports a three-wire PCM or I2S audio interface in either a master or slave configuration. The master or slave configuration is selected using vendor specific commands over the HCI interface. In addition, multiple sampling rates are supported, derived from either the FM or Bluetooth clocks. In master mode, the clock rate is either of the following: * 48 kHz x 32 bits per frame = 1.536 MHz * 48 kHz x 50 bits per frame = 2.400 MHz In slave mode, clock rates up to 3.072 MHz are supported. Analog FM Audio Interfaces The demodulated FM audio signal is available as line-level analog stereo output, generated by twin internal high SNR audio DACs. FM Over Bluetooth The BCM4343W can output received FM audio onto Bluetooth using one of following three links: eSCO, WBS, or A2DP. For all link types, after a link has been established, the host processor can enter sleep mode while the BCM4343W streams FM audio to the remote Bluetooth device, thus minimizing system current consumption. eSCO In this use case, the stereo FM audio is downsampled to 8 kHz and a mono or stereo stream is sent through the Bluetooth eSCO link to a remote Bluetooth device, typically a headset. Two Bluetooth voice connections must be used to transport stereo. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 75 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Wideband Speech Link Wideband Speech Link In this case, the stereo FM audio is downsampled to 16 kHz and a mono or stereo stream is sent through the Bluetooth wideband speech link to a remote Bluetooth device, typically a headset. Two Bluetooth voice connections must be used to transport stereo. A2DP In this case, the stereo FM audio is encoded by the on-chip SBC encoder and transported as an A2DP link to a remote Bluetooth device. Sampling rates of 48 kHz, 44.1 kHz, and 32 kHz joint stereo are supported. An A2DP lite stack is implemented in the BCM4343W to support this use case, which eliminates the need to route the SBC-encoded audio back to the host to create the A2DP packets. Autotune and Search Algorithms The BCM4343W supports a number of FM search and tune functions, allowing the host to implement many convenient user functions by accessing the Broadcom FM stack. * Tune to Play--Allows the FM receiver to be programmed to a specific frequency. * Search for SNR > Threshold--Checks the power level of the available channel and the estimated SNR of the channel to help achieve precise control of the expected sound quality for the selected FM channel. Specifically, the host can adjust its SNR requirements to retrieve a signal with a specific sound quality, or adjust this to return the weakest channels. * Alternate Frequency Jump--Allows the FM receiver to automatically jump to an alternate FM channel that carries the same information, but has a better SNR. For example, when traveling, a user may pass through a region where a number of channels carry the same station. When the user passes from one area to the next, the FM receiver can automatically switch to another channel with a stronger signal to spare the user from having to manually change the channel to continue listening to the same station. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 76 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Audio Features Audio Features A number of features are implemented in the BCM4343W to provide the best possible audio experience for the user. * Mono/Stereo Blend or Switch--The BCM4343W provides automatic control of the stereo or mono settings based on the FM signal carrier-to-noise ratio (C/N). This feature is used to maintain the best possible audio SNR based on the FM channel condition. Two modes of operation are supported: - Blend: In this mode, fine control of stereo separation is used to achieve optimal audio quality over a wide range of input C/N. The amount of separation is fully programmable. In Figure 34, the separation is programmed to maintain a minimum 50 dB SNR across the blend range. - Switch: In this mode, the audio switches from full stereo to full mono at a predetermined level to maintain optimal audio quality. The stereo-to-mono switch point and the mono-to-stereo switch points are fully programmable to provide the desired amount of audio SNR. In Figure 35, the switch point is programmed to switch to mono to maintain a 40 dB SNR. Audio SNR (dB) Figure 34: Blending and Switching Usage Input C/N (dB) Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 77 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Audio Features Channel Separation (dB) Figure 35: Blending and Switching Separation Input C/N (dB) * Soft Mute--Improves the user experience by dynamically muting the output audio proportionate to the FM signal C/N. This prevents a blast of static to the user. The mute characteristic is fully programmable to accommodate fine tuning of the output signal level. An example mute characteristic is shown in Figure 36. Audio Gain (dB) Figure 36: Soft Muting Characteristic Input C/N (dB) Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 78 BROADCOM CONFIDENTIAL BCM4343W Data Sheet RDS/RBDS * High Cut--A programmable high-cut filter is provided to reduce the amount of high-frequency noise caused by static in the output audio signal. Like the soft mute circuit, it is fully programmable to provide any amount of high cut based on the FM signal C/N. * Audio Pause Detect--The FM receiver monitors the magnitude of the audio signal and notifies the host through an interrupt when the magnitude of the signal has fallen below the threshold set for a programmable period. This feature can be used to provide alternate frequency jumps during periods of silence to minimize disturbances to the listener. Filtering techniques are used within the audio pause detection block to provide more robust presence-to-silence detection and silence-to-presence detection. * Automatic Antenna Tuning--The BCM4343W has an on-chip automatic antenna tuning network. When used with a single off-chip inductor, the on-chip circuitry automatically chooses an optimal on-chip matching component to obtain the highest signal strength for the desired frequency. The high-Q nature of this matching network simultaneously provides out-of-band blocking protection as well as a reduction of radiated spurious emissions from the FM antenna. It is designed to accommodate a wide range of external wire antennas. RDS/RBDS The BCM4343W integrates a RDS/RBDS modem, the decoder includes programmable filtering and buffering functions. The RDS/RBDS data can be read out through the HCI interface. In addition, the RDS/RBDS receive functionality supports the following: * Block decoding, error correction, and synchronization * A flywheel synchronization feature, allowing the host to set parameters for acquisition, maintenance, and loss of sync. (It is possible to set up the BCM4343W such that synchronization is achieved when a minimum of two good blocks (error free) are decoded in sequence. The number of good blocks required for sync is programmable.) * Storage capability up to 126 blocks of RDS data * Full or partial block-B match detection with host interruption * Audio pause detection with programmable parameters * Program Identification (PI) code detection with host interruption * Automatic frequency jumping * Block-E filtering * Soft muting * Signal dependent mono/stereo blending Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 79 BROADCOM CONFIDENTIAL BCM4343W Data Sheet CPU and Global Functions Section 12: CPU and Global Functions WLAN CPU and Memory Subsystem The BCM4343W includes an integrated ARM Cortex-M3 processor with internal RAM and ROM. The ARM Cortex-M3 processor is a low-power processor that features low gate count, low interrupt latency, and low-cost debugging. It is intended for deeply embedded applications that require fast interrupt response features. The processor implements the ARM architecture v7-M with support for the Thumb-2 instruction set. ARM Cortex-M3 provides a 30% performance gain over ARM7TDMI. At 0.19 W/MHz, the Cortex-M3 is the most power efficient general purpose microprocessor available, outperforming 8- and 16-bit devices on MIPS/W. It supports integrated sleep modes. ARM Cortex-M3 uses multiple technologies to reduce cost through improved memory utilization, reduced pin overhead, and reduced silicon area. ARM Cortex-M3 supports independent buses for code and data access (ICode/DCode and system buses). ARM Cortex-M3 supports extensive debug features including real-time tracing of program execution. On-chip memory for the CPU includes 512 KB SRAM and 640 KB ROM. One-Time Programmable Memory Various hardware configuration parameters may be stored in an internal 4096-bit One-Time Programmable (OTP) memory, which is read by system software after a device reset. In addition, customer-specific parameters, including the system vendor ID and the MAC address, can be stored, depending on the specific board design. The initial state of all bits in an unprogrammed OTP device is 0. After any bit is programmed to a 1, it cannot be reprogrammed to 0. The entire OTP array can be programmed in a single write cycle using a utility provided with the Broadcom WLAN manufacturing test tools. Alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state can be altered during each programming cycle. Prior to OTP memory programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with the reference board design package. Documentation on the OTP development process is available on the Broadcom customer support portal (http://www.broadcom.com/support). Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 80 BROADCOM CONFIDENTIAL BCM4343W Data Sheet GPIO Interface GPIO Interface Five general purpose I/O (GPIO) pins are available on the BCM4343W that can be used to connect to various external devices. GPIOs are tristated by default. Subsequently, they can be programmed to be either input or output pins via the GPIO control register. They can also be programmed to have internal pull-up or pull-down resistors. GPIO_0 is normally used as a WL_HOST_WAKE signal. The BCM4343W supports 2-wire, 3-wire, and 4-wire coexistence configurations using GPIO_1 through GPIO_4. The signal functions of GPIO_1 through GPIO_4 are programmable to support the three coexistence configurations. External Coexistence Interface The BCM4343W supports 2-wire, 3-wire, and 4-wire coexistence interfaces to enable signaling between the device and an external colocated wireless device in order to manage wireless medium sharing for optimal performance. The external colocated device can be any of the following ICs: GPS, WiMAX, LTE, or UWB. An LTE IC is used in this section for illustration. 2-Wire Coexistence Figure 37 shows a 2-wire LTE coexistence example. The following definitions apply to the GPIOs in the figure: * GPIO_1: WLAN_SECI_TX output to an LTE IC. * GPIO_2: WLAN_SECI_RX input from an LTE IC. Figure 37: 2-Wire Coexistence Interface to an LTE IC WLAN GPIO_1 WLAN_SECI_TX GPIO_2 WLAN_SECI_RX Coexistence Interface UART_IN UART_OUT BT/FM BCM4343W LTE/IC Notes: OR'ing to generate ISM_RX_PRIORITY for ERCX_TXCONF or BT_RX_PRIORITY is achieved by setting the GPIO mask registers appropriately. WLAN_SECI_OUT and WLAN_SECI_IN are multiplexed on the GPIOs. See Figure 31 on page 71 and Table 13: "UART Timing Specifications," on page 71 for UART timing. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 81 BROADCOM CONFIDENTIAL BCM4343W Data Sheet External Coexistence Interface 3-Wire and 4-Wire Coexistence Interfaces Figure 38 and Figure 39 show 3-wire and 4-wire LTE coexistence examples, respectively. The following definitions apply to the GPIOs in the figures: * For the 3-wire coexistence interface: * GPIO_2: WLAN priority output to an LTE IC. * GPIO_3: LTE_RX input from an LTE IC. * GPIO_4: LTE_TX input from an LTE IC. For the 4-wire coexistence interface: * GPIO_1: WLAN priority output to an LTE IC. * GPIO_2: LTE frame sync input from an LTE IC. This GPIO applies only to the 4-wire coexistence interface. * GPIO_3: LTE_RX input from an LTE IC. * GPIO_4: LTE_TX input from an LTE IC. Figure 38: 3-Wire Coexistence Interface to an LTE IC GPIO_2 WLAN Coexistence Interface WLAN Priority GPIO_3 LTE_RX GPIO_4 LTE_TX BT/FM BCM4343W LTE/IC Note: OR'ing to generate WCN_PRIORITY for ERCX_TXCONF or BT_RX_PRIORITY is achieved by setting the GPIO mask registers appropriately. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 82 BROADCOM CONFIDENTIAL BCM4343W Data Sheet JTAG Interface Figure 39: 4-Wire Coexistence Interface to an LTE IC GPIO_1 WLAN WLAN Priority GPIO_2 Coexistence Interface LTE_Frame_Sync GPIO_3 LTE_RX GPIO_4 LTE_TX BT/FM BCM4343W LTE/IC Note: OR'ing to generate WCN_PRIORITY for ERCX_TXCONF or BT_RX_PRIORITY is achieved by setting the GPIO mask registers appropriately. JTAG Interface The BCM4343W supports the IEEE 1149.1 JTAG boundary scan standard over SDIO for performing device package and PCB assembly testing during manufacturing. In addition, the JTAG interface allows Broadcom to assist customers by using proprietary debug and characterization test tools during board bring-up. Therefore, it is highly recommended to provide access to the JTAG pins by means of test points or a header on all PCB designs. UART Interface One UART interface can be enabled by software as an alternate function on the JTAG pins. UART_RX is available on the JTAG_TDI pin, and UART_TX is available on the JTAG_TDO pin. The UART is primarily for debugging during development. By adding an external RS-232 transceiver, this UART enables the BCM4343W to operate as RS-232 data termination equipment (DTE) for exchanging and managing data with other serial devices. It is compatible with the industry standard 16550 UART, and it provides a FIFO size of 64 x 8 in each direction. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 83 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLAN Software Architecture S e c t i o n 1 3 : W L A N S o ft w a r e A r c h i t e c t u r e Host Software Architecture The host driver (DHD) provides a transparent connection between the host operating system and the BCM4343W media (for example, WLAN) by presenting a network driver interface to the host operating system and communicating with the BCM4343W over an interface-specific bus (SPI, SDIO, and so on) to: * Forward transmit and receive frames between the host network stack and the BCM4343W device. * Pass control requests from the host to the BCM4343W device, returning the BCM4343W device responses. The driver communicates with the BCM4343W over the bus using a control channel and a data channel to pass control messages and data messages. The actual message format is based on the BDC protocol. Device Software Architecture The wireless device, protocol, and bus drivers are run on the embedded ARM processor using a Broadcomdefined operating system called HNDRTE, which transfers data over a propriety Broadcom format over the SDIO/SPI interface between the host and device (BDC/LMAC). The data portion of the format consists of IEEE 802.11 frames wrapped in a Broadcom encapsulation. The host architecture provides all missing functionality between a network device and the Broadcom device interface. The host can also be customized to provide functionality between the Broadcom device interface and a full network device interface. This transfer requires a message-oriented (framed) interconnect between the host and device. The SDIO bus is an addressed bus--each host-initiated bus operation contains an explicit device target address--and does not natively support a higher-level data frame concept. Broadcom has implemented a hardware/software message encapsulation scheme that ignores the bus operation code address and prefixes each frame with a 4byte length tag for framing. The device presents a packet-level interface over which data, control, and asynchronous event (from the device) packets are supported. The data and control packets received from the bus are initially processed by the bus driver and then passed on to the protocol driver. If the packets are data packets, they are transferred to the wireless device driver (and out through its medium), and a data packet received from the device medium follows the same path in the reverse direction. If the packets are control packets, the protocol header is decoded by the protocol driver. If the packets are wireless IOCTL packets, the IOCTL API of the wireless driver is called to configure the wireless device. The microcode running in the D11 core processes all time-critical tasks. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 84 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Wireless Configuration Utility Remote Downloader When the BCM4343W powers up, the DHD initializes and downloads the firmware to run in the device. Figure 40: WLAN Software Architecture DHD Host Driver SPI/SDIO BDC/LMAC Protocol Wireless Device Driver D11 Core Wireless Configuration Utility The device driver that supports the Broadcom IEEE 802.11 family of wireless solutions provides an input/output control (IOCTL) interface for making advanced configuration settings. The IOCTL interface makes it possible to make settings that are normally not possible when using just the native operating system-specific IEEE 802.11 configuration mechanisms. The utility uses IOCTLs to query or set a number of different driver/chip operating properties. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 85 BROADCOM CONFIDENTIAL Pinout and Signal Descriptions BCM4343W Data Sheet Section 14: Pinout and Signal Descriptions Ball Map Figure 41 shows the 74-ball WLBGA ball map. Figure 42 on page 87 shows the 153-bump WLCSP. Figure 41: 74-Ball WLBGA Ball Map (Bottom View) A B C 1 BT_UART_R BT_DEV_W BT_HOST_ XD AKE WAKE 2 BT_UART_T BT_UART_C FM_OUT1 XD TS_N FM_OUT2 VDDC 4 BT_I2S_CL BT_PCM_O BT_PCM_IN K UT VSSC 5 BT_PCM_C BT_PCM_S SYS_VDDI LK YNC O WPT_1P8 6 SR_VLX 7 SR_PVSS BT_I2S_DO PMU_AVSS B F G C D H J K L M BT_VCO_V WLRF_2G_ WLRF_2G_ BT_IF_VDD BT_PAVDD DD eLG RF WLRF_PA_ 1 VDD FM_RF_VD BTFM_PLL_ BTFM_PLL_ WLRF_LNA WLRF_GEN WLRF_PA_ BT_IF_VSS D VDD VSS _GND ERAL_GND GND WLRF_VDD _ 2 1P35 FM_RF_VS S WLRF_XTA L_ 3 VDD1P2 BT_VCO_V WLRF_GPI SS O BT_GPIO_3 WPT_3P3 LPO_IN VDDC VOUT_3P3 LDO_VDDB AT5V E F WLRF_AFE _GND BT_GPIO_4 BT_GPIO_5 VOUT_CLD VOUT_LNL BT_REG_O WCC_VDDI WL_REG_O O DO N O N SR_VDDBA LDO_VDD1 T5V P5 A E FM_RF_IN BT_UART_R TS_N 3 BT_I2S_ WS D GPIO_1 WLRF_VCO _GND GPIO_3 VSSC GPIO_0 GPIO_4 H Broadcom(R) August 24, 2015 * 4343W-DS107-R J GPIO_2 WLRF_XTA 5 L_XON SDIO_DATA SDIO_CMD CLK_REQ _0 SDIO_DATA SDIO_DATA _1 _3 G WLRF_XTA WLRF_XTA 4 L_GND L_XOP 6 SDIO_DATA SDIO_CLK 7 _2 K L M Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 86 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Ball Map Figure 42: 153-Bump WLCSP (Top View) Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 87 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLBGA Ball List in Ball Number Order with X-Y Coordinates WLBGA Ball List in Ball Number Order with X-Y Coordinates Table 15 provides ball numbers and names in ball number order. The table includes the X and Y coordinates for a top view with a (0,0) center. Table 15: BCM4343W WLBGA Ball List -- Ordered By Ball Number Ball Number Ball Name X Coordinate Y Coordinate A1 BT_UART_RXD -1200.006 2199.996 A2 BT_UART_TXD -799.992 2199.996 A3 BT_I2S_WS or BT_PCM_SYNC -399.996 2199.996 A4 BT_I2S_CLK or BT_PCM_CLK 0 2199.996 A5 BT_PCM_CLK or BT_I2S_CLK 399.996 2199.996 A6 SR_VLX 799.992 2199.978 A7 SR_PVSS 1199.988 2199.978 B1 BT_DEV_WAKE -1200.006 1800 B2 BT_UART_CTS_N -799.992 1800 B3 BT_I2S_DO or BT_PCM_OUT -399.996 1800 B4 BT_PCM_OUT or BT_I2S_DO 0 1800 B5 BT_PCM_SYNC or BT_I2S_WS 399.996 1800 B6 PMU_AVSS 799.992 1799.982 B7 SR_VBAT5V 1199.988 1799.982 C1 BT_HOST_WAKE -1200.006 1399.995 C2 FM_OUT1 -799.992 1399.986 C3 BT_UART_RTS_N -399.996 1399.995 C4 BT_PCM_IN or BT_I2S_DI 0 1399.995 C5 SYS_VDDIO 399.996 1399.986 C6 VOUT_CLDO 799.992 1399.986 C7 LDO_VDD15V 1199.988 1399.986 D2 FM_OUT2 -799.992 999.99 D3 VDDC -399.996 999.999 D4 VSSC 0 999.999 D5 WPT_1P8 399.996 999.99 D6 VOUT_LNLDO 799.992 999.99 E1 FM_RF_IN -1199.988 599.994 E2 FM_RF_VDD -799.992 599.994 E3 FM_RF_VSS -399.996 599.994 E5 WPT_3P3 399.996 599.994 E6 BT_REG_ON 799.992 599.994 E7 VOUT_3P3 1199.988 599.994 F1 BT_VCO_VDD -1199.988 199.998 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 88 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLBGA Ball List in Ball Number Order with X-Y Coordinates Table 15: BCM4343W WLBGA Ball List -- Ordered By Ball Number (Cont.) Ball Number Ball Name X Coordinate Y Coordinate F2 BTFM_PLL_VDD -799.992 199.998 F4 BT_GPIO_3 0 199.998 F5 LPO_IN 399.996 199.998 F6 WCC_VDDIO 800.001 199.998 F7 LDO_VBAT5V 1199.988 199.998 G1 BT_IF_VDD -1199.988 -199.998 G2 BTFM_PLL_VSS -799.992 -199.998 G4 VDDC 0 -199.998 G5 BT_GPIO_4 399.996 -199.998 G6 WL_REG_ON 800.001 -199.998 H1 BT_PAVDD -1199.988 -599.994 H2 BT_IF_VSS -799.992 -599.994 H3 BT_VCO_VSS -399.996 -599.994 H4 WLRF_AFE_GND 0 -599.994 H5 BT_GPIO_5 399.996 -599.994 H6 GPIO_1 800.001 -599.994 H7 SDIO_DATA_1 1200.006 -599.994 J1 WLRF_2G_eLG -1199.988 -999.99 J2 WLRF_LNA_GND -799.992 -999.99 J3 WLRF_GPIO -399.996 -999.99 J5 VSSC 399.996 -999.999 J6 GPIO_0 800.001 -999.999 J7 SDIO_DATA_3 1200.006 -999.999 K1 WLRF_2G_RF -1199.988 -1399.986 K2 WLRF_GENERAL_GND -799.992 -1399.986 K4 GPIO_3 0 -1399.995 K5 GPIO_4 399.996 -1399.995 K6 SDIO_DATA_0 800.001 -1399.995 L2 WLRF_PA_GND -799.992 -1799.982 L3 WLRF_VCO_GND -399.996 -1799.982 L4 WLRF_XTAL_GND 0 -1799.982 L5 GPIO_2 399.996 -1799.991 L6 SDIO_CMD 800.001 -1799.991 L7 SDIO_DATA_2 1200.006 -1799.991 M1 WLRF_PA_VDD -1199.988 -2199.978 M2 WLRF_VDD_1P35 -799.992 -2199.978 M3 WLRF_XTAL_VDD1P2 -399.996 -2199.978 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 89 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLBGA Ball List in Ball Number Order with X-Y Coordinates Table 15: BCM4343W WLBGA Ball List -- Ordered By Ball Number (Cont.) Ball Number Ball Name X Coordinate Y Coordinate M4 WLRF_XTAL_XOP 0 -2199.978 M5 WLRF_XTAL_XON 399.996 -2199.978 M6 CLK_REQ 800.001 -2199.996 M7 SDIO_CLK 1200.006 -2199.996 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 90 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLCSP Bump List in Bump Order with X-Y Coordinates WLCSP Bump List in Bump Order with X-Y Coordinates Table 16: BCM4343W WLCSP Bump List -- Ordered By Bump Number Bump View (0,0 Center of Die) Top View (0,0 Center of Die) Bump Number Bump Name X Coordinate Y Coordinate X Coordinate Y Coordinate 1 BT_UART_RXD 1228.248 2133.594 -1228.248 2133.594 2 BT_VDDC_ISO_2 944.082 2195.919 -944.082 2195.919 3 BT_PCM_CLK or BT_I2S_CLK 238.266 2275.020 -238.266 2275.020 4 BT_TM1 -327.438 2275.020 327.438 2275.020 5 BT_GPIO_3 662.544 2133.594 -662.544 2133.594 6 BT_DEV_WAKE 379.692 2133.594 -379.692 2133.594 7 BT_UART_RTS_N 1086.822 1992.168 -1086.822 1992.168 8 BT_GPIO_4 521.118 1992.168 -521.118 1992.168 9 BT_VDDC_ISO_1 -44.586 1992.168 44.586 1992.168 10 BT_GPIO_5 -327.438 1992.168 327.438 1992.168 11 BT_HOST_WAKE 1228.248 1850.742 -1228.248 1850.742 12 BT_UART_TXD 945.396 1850.742 -945.396 1850.742 13 BT_GPIO_2 662.544 1850.742 -662.544 1850.742 14 BT_VDDC 379.692 1850.742 -379.692 1850.742 15 BT_I2S_CLK or BT_PCM_CLK -186.012 1850.742 186.012 1850.742 16 BT_VDDC 516.501 1717.578 -516.501 1717.578 17 BT_PCM_SYNC or BT_I2S_WS 1086.822 1709.316 -1086.822 1709.316 18 BT_I2S_WS or BT_PCM_SYNC 238.266 1709.316 -238.266 1709.316 19 BT_PCM_OUT or BT_I2S_DO -327.438 1709.316 327.438 1709.316 20 BT_PCM_IN or BT_I2S_DI 662.544 1567.890 -662.544 1567.890 21 VSSC 96.840 1567.890 -96.840 1567.890 22 BT_UART_CTS_N -186.012 1567.890 186.012 1567.890 23 BT_I2S_DI or BT_PCM_IN 238.266 1426.464 -238.266 1426.464 24 BT_I2S_DO or BT_PCM_OUT -327.438 1426.464 327.438 1426.464 25 VSSC 96.840 1285.038 -96.840 1285.038 26 BT_VDDC 518.391 1189.863 -518.391 1189.863 27 VSSC 238.266 860.760 -238.266 860.760 28 BT_VDDC -44.586 719.334 44.586 719.334 29 VSSC 110.286 561.303 -110.286 561.303 30 VSSC -327.438 436.482 327.438 436.482 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 91 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLCSP Bump List in Bump Order with X-Y Coordinates Table 16: BCM4343W WLCSP Bump List -- Ordered By Bump Number (Cont.) Bump View (0,0 Center of Die) Top View (0,0 Center of Die) Bump Number Bump Name X Coordinate Y Coordinate X Coordinate Y Coordinate 31 BT_VDDC 521.118 436.473 -521.118 436.473 32 VSSC 238.266 153.630 -238.266 153.630 33 VSSC -44.586 153.630 44.586 153.630 34 BT_VDDC 229.986 -185.976 -229.986 -185.976 35 BT_PAVSS 1185.471 -455.270 -1185.471 -455.270 36 VSSC -875.142 -836.352 875.142 -836.352 37 FM_DAC_VOUT1 1243.031 1443.096 -1243.031 1443.096 38 FM_DAC_AVSS 1043.033 1443.096 -1043.033 1443.096 39 FM_PLLAVSS 820.485 1275.098 -820.485 1275.098 40 FM_DAC_VOUT2 1243.031 1243.098 -1243.031 1243.098 41 FM_DAC_AVDD 1043.033 1243.098 -1043.033 1243.098 42 FM_VCOVSS 1252.220 1043.100 -1252.220 1043.100 43 FM_PLLDVDD1P2 820.485 960.593 -820.485 960.593 44 FM_VCOVDD1P2 1120.383 892.373 -1120.383 892.373 45 FM_RFVDD1P2 1274.787 764.213 -1274.787 764.213 46 FM_RFVSS 1172.988 563.990 -1172.988 563.990 47 FM_IFVSS 972.990 563.990 -972.990 563.990 48 FM_IFDVDD1P2 772.304 563.990 -772.304 563.990 49 FM_RFINMAIN 1276.551 383.225 -1276.551 383.225 50 BT_DVSS 686.628 160.911 -686.628 160.911 51 BT_IFVDD1P2 886.626 148.775 -886.626 148.775 52 BT_AGPIO 1185.471 -55.274 -1185.471 -55.274 53 BT_PAVDD2P5 1185.462 -255.272 -1185.462 -255.272 54 BT_LNAVDD1P2 781.893 -263.768 -781.893 -263.768 55 BT_LNAVSS 781.893 -463.766 -781.893 -463.766 56 BT_PLLVSS 429.885 -499.995 -429.885 -499.995 57 BT_VCOVDD1P2 1185.471 -655.268 -1185.471 -655.268 58 BT_VCOVSS 786.393 -663.764 -786.393 -663.764 59 BT_PLLVDD1P2 429.885 -699.993 -429.885 -699.993 60 WRF_AFE_GND 583.250 -999.990 -583.250 -999.990 61 WRF_RFIN_ELG_2G 1262.642 -1006.290 -1262.642 -1006.290 62 WRF_RX2G_GND 1082.642 -1006.290 -1082.642 -1006.290 63 WRF_RFIO_2G 1206.990 -1458.198 -1206.990 -1458.198 64 WRF_GENERAL_GND 628.713 -1590.210 -628.713 -1590.210 65 WRF_PA_GND3P3 986.531 -1649.615 -986.531 -1649.615 66 WRF_VCO_GND 451.188 -1682.370 -451.188 -1682.370 67 WRF_GPAIO_OUT 799.992 -1729.224 -799.992 -1729.224 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 92 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLCSP Bump List in Bump Order with X-Y Coordinates Table 16: BCM4343W WLCSP Bump List -- Ordered By Bump Number (Cont.) Bump View (0,0 Center of Die) Top View (0,0 Center of Die) Bump Number Bump Name X Coordinate Y Coordinate X Coordinate Y Coordinate 68 WRF_PMU_VDD1P35 612.878 -1800.135 -612.878 -1800.135 69 WRF_PA_GND3P3 986.531 -1829.615 -986.531 -1829.615 70 WRF_PA_VDD3P3 1249.686 -2016.945 -1249.686 -2016.945 71 WRF_PA_VDD3P3 1069.686 -2016.945 -1069.686 -2016.945 72 WRF_XTAL_GND1P2 274.613 -2086.677 -274.613 -2086.677 73 WRF_XTAL_VDD1P2 75.519 -2106.621 -75.519 -2106.621 74 WRF_XTAL_XOP 311.126 -2298.978 -311.126 -2298.978 75 WRF_XTAL_XON 131.126 -2298.978 -131.126 -2298.978 76 LPO_IN 96.840 2133.594 -96.840 2133.594 77 WCC_VDDIO -186.012 2133.594 186.012 2133.594 78 VSSC 96.813 1850.742 -96.813 1850.742 79 WCC_VDDIO -44.586 1002.186 44.586 1002.186 80 GPIO_12 -1299.420 436.482 1299.420 436.482 81 GPIO_11 -1157.994 295.056 1157.994 295.056 82 GPIO_9 -1016.568 153.630 1016.568 153.630 83 GPIO_10 -1299.420 153.630 1299.420 153.630 84 GPIO_8 -1157.994 12.204 1157.994 12.204 85 VSSC -186.012 -129.222 186.012 -129.222 86 VDDC -468.864 -129.222 468.864 -129.222 87 GPIO_7 -1299.420 -129.222 1299.420 -129.222 88 VSSC -610.290 -270.648 610.290 -270.648 89 GPIO_6 -1157.994 -270.648 1157.994 -270.648 90 VSSC -44.586 -412.074 44.586 -412.074 91 GPIO_4 -1299.420 -412.074 1299.420 -412.074 92 VSSC 96.840 -553.500 -96.840 -553.500 93 VDDC -186.012 -553.500 186.012 -553.500 94 GPIO_5 -1157.994 -553.500 1157.994 -553.500 95 VDDC -44.586 -694.926 44.586 -694.926 96 WL_VDDP_ISO -733.716 -694.926 733.716 -694.926 97 GPIO_2 -1299.420 -694.926 1299.420 -694.926 98 GPIO_3 -1157.994 -836.352 1157.994 -836.352 99 WCC_VDDIO -1016.568 -977.778 1016.568 -977.778 100 GPIO_0 -1299.420 -977.778 1299.420 -977.778 101 GPIO_1 -1157.994 -1119.204 1157.994 -1119.204 102 VSSC -720.954 -1120.266 720.954 -1120.266 103 WCC_VDDIO -1016.568 -1260.630 1016.568 -1260.630 104 SDIO_CMD -1299.420 -1260.630 1299.420 -1260.630 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 93 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLCSP Bump List in Bump Order with X-Y Coordinates Table 16: BCM4343W WLCSP Bump List -- Ordered By Bump Number (Cont.) Bump View (0,0 Center of Die) Top View (0,0 Center of Die) Bump Number Bump Name X Coordinate Y Coordinate X Coordinate Y Coordinate 105 GPIO_14 -137.700 -1268.568 137.700 -1268.568 106 VSSC -841.113 -1402.056 841.113 -1402.056 107 VDDC -1016.568 -1543.482 1016.568 -1543.482 108 SDIO_CLK -1299.420 -1543.482 1299.420 -1543.482 109 GPIO_15 109.152 -1551.420 -109.152 -1551.420 110 PACKAGEOPTION_0 -173.700 -1551.420 173.700 -1551.420 111 VSSC -843.237 -1682.775 843.237 -1682.775 112 SDIO_DATA_0 -1157.994 -1684.908 1157.994 -1684.908 113 PACKAGEOPTION_1 -32.274 -1692.846 32.274 -1692.846 114 VDDC -1016.568 -1826.334 1016.568 -1826.334 115 SDIO_DATA_1 -1299.420 -1826.334 1299.420 -1826.334 116 PACKAGEOPTION_2 109.152 -1834.272 -109.152 -1834.272 117 JTAG_SEL -173.700 -1834.272 173.700 -1834.272 118 SDIO_DATA_2 -1157.994 -1967.760 1157.994 -1967.760 119 GPIO_13 -232.227 -2056.131 232.227 -2056.131 120 WCC_VDDIO -1016.568 -2109.186 1016.568 -2109.186 121 VSSC -1299.420 -2109.186 1299.420 -2109.186 122 SDIO_DATA_3 -1157.994 -2250.612 1157.994 -2250.612 123 SR_PVSS -739.130 2274.984 739.130 2274.984 124 SR_PVSS -1021.973 2274.984 1021.973 2274.984 125 VSSC -597.708 2133.563 597.708 2133.563 126 SR_VLX -880.551 2133.563 880.551 2133.563 127 SR_VLX -1163.394 2133.563 1163.394 2133.563 128 SR_VLX -739.130 1992.141 739.130 1992.141 129 SR_VDDBAT5V -1021.973 1992.141 1021.973 1992.141 130 SR_VDDBAT5V -1304.816 1992.141 1304.816 1992.141 131 PMU_AVSS -597.708 1850.720 597.708 1850.720 132 SR_VDDBAT5V -880.551 1850.720 880.551 1850.720 133 LDO_VDD1P5 -1021.973 1709.298 1021.973 1709.298 134 VOUT_CLDO -880.551 1567.877 880.551 1567.877 135 LDO_VDD1P5 -1163.394 1567.877 1163.394 1567.877 136 VOUT_CLDO -739.130 1426.455 739.130 1426.455 137 WCC_VDDIO -597.708 1285.034 597.708 1285.034 138 VOUT_LNLDO -880.551 1285.034 880.551 1285.034 139 VOUT_3P3 -1163.394 1285.034 1163.394 1285.034 140 SYS_VDDIO -739.130 1143.612 739.130 1143.612 141 LDO_VDDBAT5V -1304.816 1143.612 1304.816 1143.612 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 94 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLCSP Bump List in Bump Order with X-Y Coordinates Table 16: BCM4343W WLCSP Bump List -- Ordered By Bump Number (Cont.) Bump View (0,0 Center of Die) Top View (0,0 Center of Die) Bump Number Bump Name X Coordinate Y Coordinate X Coordinate Y Coordinate 142 VSSC -597.708 1002.191 597.708 1002.191 143 VOUT_3P3_SENSE -880.551 1002.191 880.551 1002.191 144 VOUT_3P3 -1163.394 1002.191 1163.394 1002.191 145 WPT_1P8 -739.130 860.769 739.130 860.769 146 WPT_3P3 -1021.973 860.769 1021.973 860.769 147 LDO_VDDBAT5V -1304.816 860.769 1304.816 860.769 148 WL_REG_ON -597.708 719.348 597.708 719.348 149 BT_REG_ON -880.551 719.348 880.551 719.348 150 WL_VDDM_ISO -875.142 12.204 875.142 12.204 151 PLL_VSSC -116.586 -985.716 116.586 -985.716 152 PLL_VDDC 29.286 -1130.076 -29.286 -1130.076 153 CLK_REQ 238.266 1992.168 -238.266 1992.168 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 95 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLBGA Ball List Ordered By Ball Name WLBGA Ball List Ordered By Ball Name Table 17 provides the ball numbers and names in ball name order. Table 17: BCM4343W WLBGA Ball List -- Ordered By Ball Name Ball Name Ball Number Ball Name Ball Number BT_DEV_WAKE BT_GPIO_3 BT_GPIO_4 BT_GPIO_5 BT_HOST_WAKE BT_I2S_CLK or BT_PCM_CLK BT_I2S_DO or BT_PCM_OUT BT_I2S_WS or BT_PCM_SYNC BT_IF_VDD BT_IF_VSS BT_PAVDD BT_PCM_CLK or BT_I2S_CLK BT_PCM_IN or BT_I2S_DI BT_PCM_OUT or BT_I2S_DO BT_PCM_SYNC or BT_I2S_WS BT_REG_ON BT_UART_CTS_N BT_UART_RTS_N BT_UART_RXD BT_UART_TXD BT_VCO_VDD BT_VCO_VSS BTFM_PLL_VDD BTFM_PLL_VSS CLK_REQ FM_OUT1 FM_OUT2 FM_RF_IN FM_RF_VDD FM_RF_VSS GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 LDO_VDD1P5 LDO_VDDBAT5V B1 F4 G5 H5 C1 A4 B3 A3 G1 H2 H1 A5 C4 B4 B5 E6 B2 C3 A1 A2 F1 H3 F2 G2 M6 C2 D2 E1 E2 E3 J6 H6 L5 K4 K5 C7 F7 LPO_IN PMU_AVSS SDIO_CLK SDIO_CMD SDIO_DATA_0 SDIO_DATA_1 SDIO_DATA_2 SDIO_DATA_3 SR_PVSS SR_VDDBAT5V SR_VLX SYS_VDDIO VDDC VDDC VOUT_3P3 VOUT_CLDO VOUT_LNLDO VSSC VSSC WCC_VDDIO WL_REG_ON WLRF_2G_eLG WLRF_2G_RF WLRF_AFE_GND WLRF_GENERAL_GND WLRF_GPIO WLRF_LNA_GND WLRF_PA_GND WLRF_PA_VDD WLRF_VCO_GND WLRF_VDD_1P35 WLRF_XTAL_GND WLRF_XTAL_VDD1P2 WLRF_XTAL_XON WLRF_XTAL_XOP WPT_1P8 WPT_3P3 F5 B6 M7 L6 K6 H7 L7 J7 A7 B7 A6 C5 D3 G4 E7 C6 D6 D4 J5 F6 G6 J1 K1 H4 K2 J3 J2 L2 M1 L3 M2 L4 M3 M5 M4 D5 E5 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 96 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLCSP Bump List Ordered By Name WLCSP Bump List Ordered By Name Table 18 provides the bump numbers and names in bump name order. Table 18: BCM4343W WLCSP Bump List -- Ordered By Bump Name Bump Name Bump Number(s) Bump Name Bump Number(s) BT_AGPIO 52 CLK_REQ 153 BT_DEV_WAKE 6 FM_DAC_AVDD 41 BT_DVSS 50 FM_DAC_AVSS 38 BT_GPIO_2 13 FM_DAC_VOUT1 37 BT_GPIO_3 5 FM_DAC_VOUT2 40 BT_GPIO_4 8 FM_IFDVDD1P2 48 BT_GPIO_5 10 FM_IFVSS 47 BT_HOST_WAKE 11 FM_PLLAVSS 39 BT_I2S_CLK or BT_PCM_CLK 15 FM_PLLDVDD1P2 43 BT_I2S_DI or BT_PCM_IN 23 FM_RFINMAIN 49 BT_I2S_DO or BT_PCM_OUT 24 FM_RFVDD1P2 45 BT_I2S_WS or BT_PCM_SYNC 18 FM_RFVSS 46 BT_IFVDD1P2 51 FM_VCOVDD1P2 44 BT_LNAVDD1P2 54 FM_VCOVSS 42 BT_LNAVSS 55 GPIO_0 100 BT_PAVDD2P5 53 GPIO_1 101 BT_PAVSS 35 GPIO_2 97 BT_PCM_CLK or BT_I2S_CLK 3 GPIO_3 98 BT_PCM_IN or BT_I2S_DI 20 GPIO_4 91 BT_PCM_OUT or BT_I2S_DO 19 GPIO_5 94 BT_PCM_SYNC or BT_I2S_WS 17 GPIO_6 89 BT_PLLVDD1P2 59 GPIO_7 87 BT_PLLVSS 56 GPIO_8 84 BT_REG_ON 149 GPIO_9 82 BT_TM1 4 GPIO_10 83 BT_UART_CTS_N 22 GPIO_11 81 BT_UART_RTS_N 7 GPIO_12 80 BT_UART_RXD 1 GPIO_13 119 BT_UART_TXD 12 GPIO_14 105 BT_VCOVDD1P2 57 GPIO_15 109 BT_VCOVSS 58 JTAG_SEL 117 BT_VDDC 14, 16, 26, 28, 31, 34 LDO_VDD1P5 133, 135 LDO_VDDBAT5V 141, 147 BT_VDDC_ISO_1 9 LPO_IN 76 BT_VDDC_ISO_2 2 PACKAGEOPTION_0 110 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 97 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLCSP Bump List Ordered By Name Bump Name Bump Number(s) Bump Name Bump Number(s) PACKAGEOPTION_1 113 WRF_XTAL_GND1P2 72 PACKAGEOPTION_2 116 WRF_XTAL_VDD1P2 73 PLL_VDDC 152 WRF_XTAL_XON 75 PLL_VSSC 151 WRF_XTAL_XOP 74 PMU_AVSS 131 SDIO_CLK 108 SDIO_CMD 104 SDIO_DATA_0 112 SDIO_DATA_1 115 SDIO_DATA_2 118 SDIO_DATA_3 122 SR_PVSS 123, 124 SR_VDDBAT5V 129, 130, 132 SR_VLX 126, 127, 128 SYS_VDDIO 140 VDDC 86, 93, 95, 107, 114 VOUT_3P3 139, 144 VOUT_3P3_SENSE 143 VOUT_CLDO 134, 136 VOUT_LNLDO 138 VSSC 21, 25, 27, 29, 30, 32, 33, 36, 78, 85, 88, 90, 92, 102, 106, 111, 121, 125, 142 WCC_VDDIO 77, 79, 99, 103, 120, 137 WL_REG_ON 148 WL_VDDM_ISO 150 WL_VDDP_ISO 96 WPT_1P8 145 WPT_3P3 146 WRF_AFE_GND 60 WRF_GENERAL_GND 64 WRF_GPAIO_OUT 67 WRF_PA_GND3P3 65, 69, 70, 71 WRF_PMU_VDD1P35 68 WRF_RFIN_ELG_2G 61 WRF_RFIO_2G 63 WRF_RX2G_GND 62 WRF_VCO_GND 66 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 98 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Signal Descriptions Signal Descriptions Table 19 provides the WLBGA package signal descriptions. Table 19: WLBGA Signal Descriptions Signal Name WLBGA Ball Type Description K1 O 2.4 GHz BT and WLAN RF output port SDIO_CLK SDIO_CMD SDIO_DATA_0 SDIO_DATA_1 SDIO_DATA_2 M7 L6 K6 H7 L7 I I/O I/O I/O I/O SDIO_DATA_3 J7 I/O SDIO clock input SDIO command line SDIO data line 0 SDIO data line 1. SDIO data line 2. Also used as a strapping option (see Table 23 on page 110). SDIO data line 3 RF Signal Interface WLRF_2G_RF SDIO Bus Interface Note: Per Section 6 of the SDIO specification, 10 to 100 k pull-ups are required on the four DATA lines and the CMD line. This requirement must be met during all operating states by using external pull-up resistors or properly programming internal SDIO host pull-ups. WLAN GPIO Interface WLRF_GPIO J3 I/O Test pin. Not connected in normal operation. WLRF_XTAL_XON WLRF_XTAL_XOP CLK_REQ M5 M4 M6 O I O LPO_IN F5 I XTAL oscillator output XTAL oscillator input External system clock request--Used when the system clock is not provided by a dedicated crystal (for example, when a shared TCXO is used). Asserted to indicate to the host that the clock is required. Shared by BT, and WLAN. External sleep clock input (32.768 kHz). If an external 32.768 kHz clock cannot be provided, pull this pin low. However, BLE will be always on and cannot go to deep sleep. C2 D2 E1 E2 O O I I Clocks FM Receiver FM_OUT1 FM_OUT2 FM_RF_IN FM_RF_VDD Broadcom(R) August 24, 2015 * 4343W-DS107-R FM analog output 1 FM analog output 2 FM radio antenna port FM power supply Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 99 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Signal Descriptions Table 19: WLBGA Signal Descriptions (Cont.) Signal Name WLBGA Ball Type Description BT_PCM_CLK or BT_I2S_CLK A5 I/O PCM or I2S clock; can be master (output) or slave (input) BT_PCM_IN or BT_I2S_DI C4 I PCM or I2S data input sensing BT_PCM_OUT or BT_I2S_DO B4 O BT_PCM_SYNC or BT_I2S_WS B5 I/O PCM or I2S data output PCM SYNC or I2S_WS; can be master (output) or slave (input) F4 G5 H5 I/O I/O I/O WPT_INTb to wireless charging PMU. BSC_SDA to/from wireless charging PMU. BSC_SCL from wireless charging PMU. B2 I BT_I2S_CLK or BT_PCM_CLK A4 I/O I2S or PCM clock; can be master (output) or slave (input) BT_I2S_DO or BT_PCM_OUT B3 I/O I2S or PCM data output BT_I2S_WS or BT_PCM_SYNC A3 I/O I2S WS or PCM sync; can be master (output) or slave (input) Bluetooth PCM Bluetooth GPIO BT_GPIO_3 BT_GPIO_4 BT_GPIO_5 Bluetooth UART and Wake BT_UART_CTS_N UART clear-to-send. Active-low clear-to-send signal for the HCI UART interface. BT_UART_RTS_N C3 O UART request-to-send. Active-low requestto-send signal for the HCI UART interface. BT_UART_RXD A1 I UART serial input. Serial data input for the HCI UART interface. BT_UART_TXD A2 O UART serial output. Serial data output for the HCI UART interface. BT_DEV_WAKE B1 I/O DEV_WAKE or general-purpose I/O signal. BT_HOST_WAKE C1 I/O HOST_WAKE or general-purpose I/O signal. Note: By default, the Bluetooth BT WAKE signals provide GPIO/WAKE functionality, and the UART pins provide UART functionality. Through software configuration, the PCM interface can also be routed over the BT_WAKE/UART signals as follows: * PCM_CLK on the UART_RTS_N pin * PCM_OUT on the UART_CTS_N pin * PCM_SYNC on the BT_HOST_WAKE pin * PCM_IN on the BT_DEV_WAKE pin In this case, the BT HCI transport included sleep signaling will operate using UART_RXD and UART_TXD; that is, using a 3-Wire UART Transport. Bluetooth/FM I2S Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 100 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Signal Descriptions Table 19: WLBGA Signal Descriptions (Cont.) Signal Name WLBGA Ball Type Description WL_REG_ON G6 I BT_REG_ON E6 I WPT_3P3 WPT_1P8 GPIO_0 E5 D5 J6 N/A N/A I/O GPIO_1 GPIO_2 GPIO_3 GPIO_4 WLRF_2G_eLG H6 L5 K4 K5 J1 I/O I/O I/O I/O I Used by PMU to power up or power down the internal regulators used by the WLAN section. Also, when deasserted, this pin holds the WLAN section in reset. This pin has an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming. Used by PMU to power up or power down the internal regulators used by the Bluetooth/FM section. Also, when deasserted, this pin holds the Bluetooth/FM section in reset. This pin has an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming. Not used. Do not connect to this pin. Not used. Do not connect to this pin. Programmable GPIO pins. This pin becomes an output pin when it is used as WLAN_HOST_WAKE/out-of-band signal. Programmable GPIO pins Programmable GPIO pins Programmable GPIO pins Programmable GPIO pins Connect to an external inductor. See the reference schematic for details. SR_VDDBAT5V SR_VLX B7 A6 I O LDO_VDDBAT5V LDO_VDD1P5 VOUT_LNLDO VOUT_CLDO F7 C7 D6 C6 I I O O SR VBAT input power supply CBUCK switching regulator output. See Table 39 on page 135 for details of the inductor and capacitor required on this output. LDO VBAT LNLDO input Output of low-noise LNLDO Output of core LDO H1 G1 F2 F1 I I I I Bluetooth PA power supply Bluetooth IF block power supply Bluetooth RF PLL power supply Bluetooth RF power supply Miscellaneous Integrated Voltage Regulators Bluetooth Power Supplies BT_PAVDD BT_IF_VDD BTFM_PLL_VDD BT_VCO_VDD Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 101 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Signal Descriptions Table 19: WLBGA Signal Descriptions (Cont.) Signal Name WLBGA Ball Type Description M3 M1 F6 C5 M2 D3, G4 E7 I I I I I I O XTAL oscillator supply Power amplifier supply VDDIO input supply. Connect to VDDIO. VDDIO input supply. Connect to VDDIO. LNLDO input supply Core supply for WLAN and BT. 3.3V output supply. See the reference schematic for details. H2 G2 H3 E3 B6 A7 D4, J5 H4 J2 K2 L2 L3 L4 I I I I I I I I I I I I I 1.2V Bluetooth IF block ground Bluetooth/FM RF PLL ground 1.2V Bluetooth RF ground FM RF ground Quiet ground Switcher-power ground Core ground for WLAN and BT AFE ground 2.4 GHz internal LNA ground Miscellaneous RF ground 2.4 GHz PA ground VCO/LO generator ground XTAL ground Power Supplies WLRF_XTAL_VDD1P2 WLRF_PA_VDD WCC_VDDIO SYS_VDDIO WLRF_VDD_1P35 VDDC VOUT_3P3 Ground BT_IF_VSS BTFM_PLL_VSS BT_VCO_VSS FM_RF_VSS PMU_AVSS SR_PVSS VSSC WLRF_AFE_GND WLRF_LNA_GND WLRF_GENERAL_GND WLRF_PA_GND WLRF_VCO_GND WLRF_XTAL_GND Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 102 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Signal Descriptions Table 20 provides the WLCSP package signal descriptions. Table 20: WLCSP Signal Descriptions Signal Name WLCSP Bump Type Description or Instruction WRF_RFIN_ELG_2G 61 I WRF_RFIO_2G 63 I/O Connect to an external inductor. See the reference schematic for details. 2.4 GHz BT and WLAN RF input/output port SDIO_CLK SDIO_CMD SDIO_DATA_0 SDIO_DATA_1 SDIO_DATA_2 108 104 112 115 118 I I/O I/O I/O I/O SDIO_DATA_3 122 I/O RF Signal Interface SDIO Bus Interface SDIO clock input SDIO command line SDIO data line 0 SDIO data line 1. SDIO data line 2. Also used as a strapping option (see Table 23 on page 110). SDIO data line 3 Note: Per Section 6 of the SDIO specification, 10 to 100 k pull-ups are required on the four DATA lines and the CMD line. This requirement must be met during all operating states by using external pull-up resistors or properly programming internal SDIO host pull-ups. WLAN GPIO Interface WRF_GPAIO_OUT 67 O Test pin. Not connected in normal operation. WRF_XTAL_XON WRF_XTAL_XOP CLK_REQ 75 74 153 O I O LPO_IN 76 I XTAL oscillator output XTAL oscillator input External system clock request--Used when the system clock is not provided by a dedicated crystal (for example, when a shared TCXO is used). Asserted to indicate to the host that the clock is required. Shared by BT, and WLAN. External sleep clock input (32.768 kHz). If an external 32.768 kHz clock cannot be provided, pull this pin low. However, BLE will be always on and cannot go to deep sleep. 37 40 49 O O I Clocks FM FM_DAC_VOUT1 FM_DAC_VOUT2 FM_RFINMAIN Broadcom(R) August 24, 2015 * 4343W-DS107-R FM DAC output 1 FM DAC output 2 FM RF input Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 103 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Signal Descriptions Table 20: WLCSP Signal Descriptions (Cont.) Signal Name WLCSP Bump Type Description or Instruction BT_PCM_CLK or BT_I2S_CLK 3 I/O PCM or I2S clock; can be master (output) or slave (input) BT_PCM_IN or BT_I2S_DI 20 I PCM or I2S data input sensing BT_PCM_OUT or BT_I2S_DO 19 O BT_PCMM_SYNC or BT_I2S_WS 17 I/O PCM or I2S data output PCM SYNC or I2S WS; can be master (output) or slave (input) 52 13 5 8 10 4 I/O I/O I/O I/O I/O I/O Bluetooth analog GPIO Bluetooth general purpose I/O WPT_INTb to wireless charging PMU. BSC_SDA to/from wireless charging PMU. BSC_SCL from wireless charging PMU ARM JTAG mode 22 I BT_I2S_CLK or BT_PCM_CLK 15 I/O I2S or PCM clock; can be master (output) or slave (input) BT_I2S_DI or BT_PCM_IN 23 I I2S or PCM data input Bluetooth PCM Bluetooth GPIO BT_AGPIO BT_GPIO_2 BT_GPIO_3 BT_GPIO_4 BT_GPIO_5 BT_TM1 Bluetooth UART and Wake BT_UART_CTS_N UART clear-to-send. Active-low clear-to-send signal for the HCI UART interface. BT_UART_RTS_N 7 O UART request-to-send. Active-low request-tosend signal for the HCI UART interface. BT_UART_RXD 1 I UART serial input. Serial data input for the HCI UART interface. BT_UART_TXD 12 O UART serial output. Serial data output for the HCI UART interface. BT_DEV_WAKE 6 I/O DEV_WAKE or general-purpose I/O signal BT_HOST_WAKE 11 I/O HOST_WAKE or general-purpose I/O signal Note: By default, the Bluetooth BT WAKE signals provide GPIO/WAKE functionality, and the UART pins provide UART functionality. Through software configuration, the PCM interface can also be routed over the BT_WAKE/UART signals as follows: * PCM_CLK on the UART_RTS_N pin * PCM_OUT on the UART_CTS_N pin * PCM_SYNC on the BT_HOST_WAKE pin * PCM_IN on the BT_DEV_WAKE pin In this case, the BT HCI transport included sleep signaling will operate using UART_RXD and UART_TXD; that is, using a 3-Wire UART Transport. Bluetooth/FM I2S Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 104 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Signal Descriptions Table 20: WLCSP Signal Descriptions (Cont.) Signal Name WLCSP Bump Type Description or Instruction BT_I2S_DO or BT_PCM_OUT 24 O I2S or PCM data output BT_I2S_WS or BT_PCM_SYNC 18 I/O I2S WS or PCM SYNC; can be master (output) or slave (input) WL_REG_ON 148 I BT_REG_ON 149 I WPT_3P3 WPT_1P8 GPIO_0 146 145 100 N/A N/A I/O GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 PACKAGEOPTION_0 PACKAGEOPTION_1 PACKAGEOPTION_2 JTAG_SEL 101 97 98 91 94 89 87 84 82 83 81 80 119 105 109 110 113 116 117 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I Used by PMU to power up or power down the internal regulators used by the WLAN section. Also, when deasserted, this pin holds the WLAN section in reset. This pin has an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming. Used by PMU to power up or power down the internal regulators used by the Bluetooth/FM section. Also, when deasserted, this pin holds the Bluetooth/FM section in reset. This pin has an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming. Not used. Do not connect to this pin. Not used. Do not connect to this pin. Programmable GPIO pin. This pin becomes an output pin when it is used as WLAN_HOST_WAKE/out-of-band signal. Programmable GPIO pin Programmable GPIO pin Programmable GPIO pin Programmable GPIO pin Programmable GPIO pin Programmable GPIO pin Programmable GPIO pin Programmable GPIO pin Programmable GPIO pin Programmable GPIO pin Programmable GPIO pin Programmable GPIO pin Programmable GPIO pin Programmable GPIO pin Programmable GPIO pin VDDIO Ground Ground JTAG select. Connect to ground. Miscellaneous Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 105 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Signal Descriptions Table 20: WLCSP Signal Descriptions (Cont.) Signal Name WLCSP Bump Type Description or Instruction SR_VDDBAT5V SR_VLX 129, 130, 132 126, 127, 128 I O LDO_VDDBAT5V LDO_VDD1P5 VOUT_LNLDO VOUT_CLDO 141, 147 133, 135 138 134, 136 I I O O SR VBAT input power supply CBUCK switching regulator output. See Table 39 on page 135 for details of the inductor and capacitor required on this output. LDO VBAT LNLDO input Output of low-noise LDO (LNLDO) Output of core LDO 51 54 53 59 57 14, 16, 26, 28, 31, 34 9 2 PWR PWR PWR PWR PWR PWR Bluetooth IF-block power supply Bluetooth RF LNA power supply Bluetooth RF PA power supply Bluetooth RF PLL power supply Bluetooth RF power supply Bluetooth core power supply PWR PWR Bluetooth core power supply Bluetooth core power supply 41 48 43 45 44 152 140 86, 93, 95, 107, 114 139, 144 PWR PWR PWR PWR PWR PWR I I FM DAC power supply FM IF power supply FM PLL power supply FM RF power supply FM VCO power supply Core PLL power supply VDDIO input supply. Connect to VDDIO. Core supply for WLAN and BT O 143 77, 79, 99, 103, 120, 137 150 96 73 70, 71 68 O I 3.3V output supply. See the reference schematic for details. Voltage sense pin for LDO 3.3V output VDDIO input supply. Connect to VDDIO. - - I I I Test pin. Not connected in normal operation. Test pin. Not connected in normal operation. XTAL oscillator supply Power amplifier supply LNLDO input supply Integrated Voltage Regulators Bluetooth Power Supplies BT_IFVDD1P2 BT_LNAVDD1P2 BT_PAVDD2P5 BT_PLLVDD1P2 BT_VCOVDD1P2 BT_VDDC BT_VDDC_ISO_1 BT_VDDC_ISO_2 Power Supplies FM_DAC_AVDD FM_IFDVDD1P2 FM_PLLDVDD1P2 FM_RFVDD1P2 FM_VCOVDD1P2 PLL_VDDC SYS_VDDIO VDDC VOUT_3P3 VOUT_3P3_SENSE WCC_VDDIO WL_VDDM_ISO WL_VDDP_ISO WRF_XTAL_VDD1P2 WRF_PA_VDD3P3 WRF_PMU_VDD1P35 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 106 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Signal Descriptions Table 20: WLCSP Signal Descriptions (Cont.) Signal Name WLCSP Bump Type Description or Instruction 50 55 35 56 58 38 47 39 46 42 151 131 123, 124 21, 25, 27, 29, 30, 32, 33, 36, 78, 85, 88, 90, 92, 102, 106, 111, 121, 125, 142 60 62 64 65, 69 66 72 GND GND GND GND GND GND GND GND GND GND GND I I I Bluetooth digital ground Bluetooth LNA ground Bluetooth PA ground Bluetooth PLL ground Bluetooth VCO ground FM DAC analog ground FM IF-block ground FM PLL analog ground FM RF ground FM VCO ground PLL core ground Quiet ground Switcher-power ground Core ground for WLAN and BT I I I I I I AFE ground 2.4 GHz internal LNA ground Miscellaneous RF ground 2.4 GHz PA ground VCO/LO generator ground XTAL ground Ground BT_DVSS BT_LNAVSS BT_PAVSS BT_PLLVSS BT_VCOVSS FM_DAC_AVSS FM_IFVSS FM_PLLAVSS FM_RFVSS FM_VCOVSS PLL_VSSC PMU_AVSS SR_PVSS VSSC WRF_AFE_GND WRF_RX2G_GND WRF_GENERAL_GND WRF_PA_GND3P3 WRF_VCO_GND WRF_XTAL_GND1P2 Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 107 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLAN GPIO Signals and Strapping Options WLAN GPIO Signals and Strapping Options The pins listed in Table 21 are sampled at power-on reset (POR) to determine the various operating modes. Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative function specified in the signal descriptions table. Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to ground using a 10 k resistor or less. Note: Refer to the reference board schematics for more information. Table 21: GPIO Functions and Strapping Options Pin Name WLBGA Pin # Default Function Description SDIO_DATA_2 L7 This pin selects the WLAN host interface mode. The default is SDIO. For gSPI, pull this pin low. 1 Broadcom(R) August 24, 2015 * 4343W-DS107-R WLAN host interface select Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 108 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Chip Debug Options Chip Debug Options The chip can be accessed for debugging via the JTAG interface, multiplexed on the SDIO_DATA_0 through SDIO_DATA_3 (and SDIO_CLK) I/O or the Bluetooth PCM I/O depending on the bootstrap state of GPIO_1 and GPIO_2. Table 22 shows the debug options of the device. Table 22: Chip Debug Options SDIO I/O Pad Function BT PCM I/O Pad Function JTAG_SEL GPIO_2 GPIO_1 Function 0 0 0 Normal mode SDIO BT PCM 0 0 1 JTAG over SDIO JTAG BT PCM 0 1 0 JTAG over BT PCM SDIO JTAG 0 1 1 SWD over GPIO_1/ GPIO_2 SDIO BT PCM I/O States The following notations are used in Table 23 on page 110: * I: Input signal * O: Output signal * I/O: Input/Output signal * PU = Pulled up * PD = Pulled down * NoPull = Neither pulled up nor pulled down Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 109 BROADCOM CONFIDENTIAL I/O States BCM4343W Data Sheet Table 23: I/O Statesa Name I/O Keeperb Active Mode Power-Downc Low Power State/Sleep WL_REG_ON = 0 BT_REG_ON = 0 (All Power Present) Out-of-Reset; (WL_REG_ON = 1; BT_REG_ON = Do Not Care) Out-of-Reset; (WL_REG_ON = 1 (WL_REG_ON = 0 BT_REG_ON = 0) BT_REG_ON = 1) VDDIOs Present VDDIOs Present Power Rail WL_REG_ON I N Input; PD (pull-down can Input; PD (pull-down can Input; PD (of 200K) be disabled) be disabled) Input; PD (200k) Input; PD (200k) - - BT_REG_ON I N Input; PD (pull down can Input; PD (pull down can Input; PD (of 200K) be disabled) be disabled) Input; PD (200k) Input; PD (200k) Input; PD (200k) - CLK_REQ I/O Y Open drain or push-pull Open drain or push-pull PD (programmable). Active (programmable). Active high. high Open drain, active high. Open drain, active high. Open drain, active high. WCC_VDDIO BT_HOST_ WAKE I/O Y I/O; PU, PD, NoPull (programmable) I/O; PU, PD, NoPull (programmable) High-Z, NoPull - Input, PD Output, Drive low WCC_VDDIO BT_DEV_WAKE I/O Y I/O; PU, PD, NoPull (programmable) Input; PU, PD, NoPull (programmable) High-Z, NoPull - Input, PD Input, PD WCC_VDDIO BT_UART_CTS I Y Input; NoPull Input; NoPull High-Z, NoPull - Input; PU Input, NoPull WCC_VDDIO BT_UART_RTS O Y Output; NoPull Output; NoPull High-Z, NoPull - Input; PU Output, NoPull WCC_VDDIO BT_UART_RXD I Y Input; PU Input; NoPull High-Z, NoPull - Input; PU Input, NoPull WCC_VDDIO - BT_UART_TXD O Y Output; NoPull Output; NoPull High-Z, NoPull Input; PU Output, NoPull WCC_VDDIO SDIO_DATA_0 I/O N SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> PU SDIO MODE -> NoPull Input; PU WCC_VDDIO SDIO_DATA_1 I/O N SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> PU SDIO MODE -> NoPull Input; PU WCC_VDDIO SDIO_DATA_2 I/O N SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> PU SDIO MODE -> NoPull Input; PU WCC_VDDIO SDIO_DATA_3 I/O N SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> PU SDIO MODE -> NoPull Input; PU WCC_VDDIO SDIO_CMD I/O N SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> PU SDIO MODE -> NoPull Input; PU WCC_VDDIO SDIO_CLK I N SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> NoPull Input WCC_VDDIO BT_PCM_CLK I/O Y Input; NoPulld Input; NoPulld High-Z, NoPull - Input, PD Input, PD WCC_VDDIO BT_PCM_IN I/O Y d d High-Z, NoPull - Input, PD Input, PD WCC_VDDIO BT_PCM_OUT I/O Y Input; NoPull Input; NoPulld High-Z, NoPull - Input, PD Input, PD WCC_VDDIO BT_PCM_SYNC I/O Y Input; NoPulld Input; NoPulld High-Z, NoPull - Input, PD Input, PD WCC_VDDIO BT_I2S_WS I/O Y Input; NoPulle Input; NoPulle High-Z, NoPull - Input, PD Input, PD WCC_VDDIO BT_I2S_CLK I/O Y e e High-Z, NoPull - Input, PD Output, Drive low WCC_VDDIO Input; NoPull d Input; NoPull Input; NoPull Input; NoPull Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 110 BROADCOM CONFIDENTIAL I/O States BCM4343W Data Sheet Table 23: I/O Statesa (Cont.) Name I/O Keeperb Active Mode Power-Downc Low Power State/Sleep WL_REG_ON = 0 BT_REG_ON = 0 (All Power Present) BT_I2S_DO I/O Y Input; NoPulle Input; NoPulle High-Z, NoPull JTAG_SEL Out-of-Reset; (WL_REG_ON = 1; BT_REG_ON = Do Not Care) Out-of-Reset; (WL_REG_ON = 1 (WL_REG_ON = 0 BT_REG_ON = 0) BT_REG_ON = 1) VDDIOs Present VDDIOs Present Power Rail - Input, PD Input, PD WCC_VDDIO I Y PD PD High-Z, NoPull Input, PD PD Input, PD WCC_VDDIO GPIO_0 I/O Y TBD Active mode High-Z, NoPullf Input, SDIO OOB Int, NoPull Active mode Input, NoPull WCC_VDDIO GPIO_1 I/O Y TBD Active mode High-Z, NoPullf Input, PD Active mode Input, Strap, PD WCC_VDDIO GPIO_2 I/O Y TBD Active mode High-Z, NoPullf Input, GCI GPIO[7], NoPull Active mode Input, Strap, NoPull WCC_VDDIO GPIO_3 I/O Y TBD Active mode High-Z, NoPullf Input, GCI GPIO[0], PU Active mode Input, PU WCC_VDDIO GPIO_4 I/O Y TBD Active mode High-Z, NoPullf Input, GCI GPIO[1], PU Active mode Input, PU WCC_VDDIO GPIO_5 I/O N TBD Active mode High-Z, NoPullf Input, GCI GPIO[2], PU Active mode Input, PU WCC_VDDIO GPIO_6 I/O Y TBD Active mode High-Z, NoPullf Input, GCI GPIO[3], NoPull Active mode Input, NoPull WCC_VDDIO GPIO_7 I/O Y TBD Active mode High-Z, NoPullf Output, WLAN UART RTS#, NoPull Active mode Output, NoPull, Low WCC_VDDIO GPIO_8 I/O Y TBD Active mode High-Z, NoPullf Input, WLAN UART CTS#, NoPull Active mode Input, NoPull WCC_VDDIO GPIO_9 I/O Y TBD Active mode High-Z, NoPullf Input, WLAN UART RX, NoPull Active mode Input, NoPull WCC_VDDIO GPIO_10 I/O Y TBD Active mode High-Z, NoPullf Output, WLAN UART TX, NoPull Active mode Output, NoPull, Low WCC_VDDIO GPIO_11 I/O Y TBD Active mode High-Z, NoPullf Input, Low, NoPull Active mode Input, NoPull WCC_VDDIO GPIO_12 I/O Y TBD Active mode High-Z, NoPull f Input, GCI GPIO[6], NoPull Active mode Input, NoPull WCC_VDDIO GPIO_13 I/O Y TBD Active mode High-Z, NoPullf Input, GCI GPIO[7], NoPull Active mode Input, NoPull WCC_VDDIO GPIO_14 I/O Y TBD Active mode High-Z, NoPullf Input, PD Active mode Input, PD WCC_VDDIO GPIO_15 I/O Y TBD Active mode High-Z, NoPullf Input, PD Active mode Input, PD WCC_VDDIO a. PU = pulled up, PD = pulled down. b. N = pad has no keeper. Y = pad has a keeper. Keeper is always active except in the power-down state. If there is no keeper, and it is an input and there is NoPull, then the pad should be driven to prevent leakage due to floating pad, for example, SDIO_CLK. c. In the Power-down state (xx_REG_ON = 0): High-Z; NoPull => The pad is disabled because power is not supplied. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 111 BROADCOM CONFIDENTIAL I/O States BCM4343W Data Sheet d. Depending on whether the PCM interface is enabled and the configuration is master or slave mode, it can be either an output or input. e. Depending on whether the I2S interface is enabled and the configuration is master or slave mode, it can be either an output or input. f. The GPIO pull states for the active and low-power states are hardware defaults. They can all be subsequently programmed as a pull-up or pull-down. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 112 BROADCOM CONFIDENTIAL BCM4343W Data Sheet DC Characteristics Section 15: DC Characteristics Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Absolute Maximum Ratings Caution! The absolute maximum ratings in Table 24 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Excluding VBAT, operation at the absolute maximum conditions for extended periods can adversely affect long-term reliability of the device. Table 24: Absolute Maximum Ratings Rating Symbol Value Unit DC supply for VBAT and PA driver supply VBAT -0.5 to +6.0a V DC supply voltage for digital I/O VDDIO -0.5 to 3.9 V DC supply voltage for RF switch I/Os VDDIO_RF -0.5 to 3.9 V DC input supply voltage for CLDO and LNLDO - -0.5 to 1.575 V DC supply voltage for RF analog VDDRF -0.5 to 1.32 V VDDC -0.5 to 1.32 V Maximum undershoot voltage for I/O Vundershoot -0.5 V Maximum overshoot voltage for I/Ob Vovershoot VDDIO + 0.5 V Maximum junction temperature Tj 125 C DC supply voltage for core b a. Continuous operation at 6.0V is supported. b. Duration not to exceed 25% of the duty cycle. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 113 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Environmental Ratings Environmental Ratings The environmental ratings are shown in Table 25. Table 25: Environmental Ratings Characteristic Value Units Conditions/Comments Ambient temperature (TA) -30 to +70C a C Operation Storage temperature -40 to +125C C - Relative humidity Less than 60 % Storage Less than 85 % Operation a. Functionality is guaranteed, but specifications require derating at extreme temperatures (see the specification tables for details). Electrostatic Discharge Specifications Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding straps to discharge static electricity is required when handling these devices. Always store unused material in its antistatic packaging. Table 26: ESD Specifications Pin Type Symbol Condition ESD Rating Unit ESD, Handling Reference: ESD_HAND_HBM NQY00083, Section 3.4, Group D9, Table B Human Body Model Contact Discharge per JEDEC EID/ JESD22-A114 1000 V Machine Model (MM) ESD_HAND_MM Machine Model Contact 30 V CDM ESD_HAND_CDM Charged Device Model Contact Discharge per JEDEC EIA/ JESD22-C101 300 V Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 114 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Recommended Operating Conditions and DC Characteristics Recommended Operating Conditions and DC Characteristics Functional operation is not guaranteed outside the limits shown in Table 27, and operation outside these limits for extended periods can adversely affect long-term reliability of the device. Table 27: Recommended Operating Conditions and DC Characteristics Value Element Symbol DC supply voltage for VBAT VBAT DC supply voltage for core DC supply voltage for RF blocks in chip DC supply voltage for digital I/O VDD VDDRF VDDIO, VDDIO_SD VDDIO_RF 3.13 TSSI 0.15 Vth_POR 0.4 VIH VIL VOH VOL 1.27 - 1.40 - VIH VIL 0.625 x VDDIO - - - VOH VOL 0.75 x VDDIO - - - VIH VIL 0.65 x VDDIO - - - VOH VOL VIH VIL VOH VOL DC supply voltage for RF switch I/Os External TSSI input Internal POR threshold Minimum a 3.0 1.14 1.14 1.71 Typical Maximum Unit - 1.2 1.2 - 4.8b 1.26 1.26 3.63 V V V 3.3 - - 3.46 0.95 0.7 V V V - - - - - 0.58 - 0.45 V V V V - 0.25 x VDDIO - 0.125 x VDDIO V V V SDIO Interface I/O Pins For VDDIO_SD = 1.8V: Input high voltage Input low voltage Output high voltage @ 2 mA Output low voltage @ 2 mA For VDDIO_SD = 3.3V: Input high voltage Input low voltage Output high voltage @ 2 mA Output low voltage @ 2 mA V V Other Digital I/O Pins For VDDIO = 1.8V: Input high voltage Input low voltage Output high voltage @ 2 mA Output low voltage @ 2 mA For VDDIO = 3.3V: Input high voltage Input low voltage Output high voltage @ 2 mA Output low Voltage @ 2 mA Broadcom(R) August 24, 2015 * 4343W-DS107-R VDDIO - 0.45 - - - - 0.35 x VDDIO - 0.45 V V 2.00 - VDDIO - 0.4 - - 0.80 - 0.40 V V V V - - - - V V Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 115 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Recommended Operating Conditions and DC Characteristics Table 27: Recommended Operating Conditions and DC Characteristics (Cont.) Value Element Symbol Minimum Typical Maximum Unit VOH VOL CIN VDDIO - 0.4 - - - - - - 0.40 5 RF Switch Control Output Pinsc For VDDIO_RF = 3.3V: Output high voltage @ 2 mA Output low voltage @ 2 mA Input capacitance V V pF a. The BCM4343W is functional across this range of voltages. However, optimal RF performance specified in the data sheet is guaranteed only for 3.2V < VBAT < 4.8V. b. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration over the lifetime of the device are allowed. c. Programmable 2 mA to 16 mA drive strength. Default is 10 mA. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 116 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLAN RF Specifications S e c t i o n 1 6 : W L A N R F Sp e c i f i c a t i o n s The BCM4343W includes an integrated direct conversion radio that supports the 2.4 GHz band. This section describes the RF characteristics of the 2.4 GHz radio. Note: Values in this data sheet are design goals and may change based on device characterization results. Unless otherwise stated, the specifications in this section apply when the operating conditions are within the limits specified in Table 25: "Environmental Ratings," on page 114 and Table 27: "Recommended Operating Conditions and DC Characteristics," on page 115. Functional operation outside these limits is not guaranteed. Typical values apply for the following conditions: * VBAT = 3.6V. * Ambient temperature +25C. Figure 43: RF Port Location Chip Port C2 TX Filter Antenna Port 10 pF BCM4343W C1 L1 RX 4.7 nH 10 pF Note: All specifications apply at the chip port unless otherwise specified. 2.4 GHz Band General RF Specifications Table 28: 2.4 GHz Band General RF Specifications Item Condition Minimum Typical Maximum Unit TX/RX switch time Including TX ramp down - - 5 s RX/TX switch time Including TX ramp up - - 2 s Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 117 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLAN 2.4 GHz Receiver Performance Specifications WLAN 2.4 GHz Receiver Performance Specifications Note: Unless otherwise specified, the specifications in Table 29 are measured at the chip port (for the location of the chip port, see Figure 43 on page 117). Table 29: WLAN 2.4 GHz Receiver Performance Specifications Parameter Frequency range Condition/Notes - Minimum Typical Maximum Unit 2400 - 2500 MHz -97.5 -99.5 - dBm -93.5 -95.5 - dBm 5.5 Mbps DSSS -91.5 -93.5 - dBm RX sensitivity (8% PER for 1 Mbps DSSS 1024 octet PSDU) a 2 Mbps DSSS 11 Mbps DSSS -88.5 -90.5 - dBm RX sensitivity (10% PER for 6 Mbps OFDM 1000 octet PSDU) at WLAN 9 Mbps OFDM RF port a 12 Mbps OFDM -91.5 -93.5 - dBm -90.5 -92.5 - dBm -87.5 -89.5 - dBm 18 Mbps OFDM -85.5 -87.5 - dBm 24 Mbps OFDM -82.5 -84.5 - dBm 36 Mbps OFDM -80.5 -82.5 - dBm 48 Mbps OFDM -76.5 -78.5 - dBm 54 Mbps OFDM -75.5 -77.5 - dBm RX sensitivity (10% PER for 4096 octet PSDU). Defined for default parameters: Mixed mode, 800 ns GI. 20 MHz channel spacing for all MCS rates (Mixed mode) 256-QAM, R = 5/6 -67.5 -69.5 - dBm 256-QAM, R = 3/4 -69.5 -71.5 - dBm MCS7 -71.5 -73.5 - dBm MCS6 -73.5 -75.5 - dBm MCS5 -74.5 -76.5 - dBm MCS4 -79.5 -81.5 - dBm MCS3 -82.5 -84.5 - dBm MCS2 -84.5 -86.5 - dBm MCS1 -86.5 -88.5 - dBm MCS0 -90.5 -92.5 - dBm Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 118 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLAN 2.4 GHz Receiver Performance Specifications Table 29: WLAN 2.4 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Blocking level for 3 dB RX 704-716 MHz sensitivity degradation 777-787 MHz (without external filtering).b 776-794 MHz LTE Maximum receive level @ 2.4 GHz Minimum Typical Maximum Unit - -13 - dBm LTE - -13 - dBm CDMA2000 - -13.5 - dBm 815-830 MHz LTE - -12.5 - dBm 816-824 MHz CDMA2000 - -13.5 - dBm 816-849 MHz LTE - -11.5 - dBm 824-849 MHz WCDMA - -11.5 - dBm 824-849 MHz CDMA2000 - -12.5 - dBm 824-849 MHz LTE - -11.5 - dBm 824-849 MHz GSM850 - -8 - dBm 830-845 MHz LTE - -11.5 - dBm 832-862 MHz LTE - -11.5 - dBm 880-915 MHz WCDMA - -10 - dBm 880-915 MHz LTE - -12 - dBm 880-915 MHz E-GSM - -9 - dBm 1710-1755 MHz WCDMA - -13 - dBm 1710-1755 MHz LTE - -14.5 - dBm 1710-1755 MHz CDMA2000 - -14.5 - dBm 1710-1785 MHz WCDMA - -13 - dBm 1710-1785 MHz LTE - -14.5 - dBm 1710-1785 MHz GSM1800 - -12.5 - dBm 1850-1910 MHz GSM1900 - -11.5 - dBm 1850-1910 MHz CDMA2000 - -16 - dBm 1850-1910 MHz WCDMA - -13.5 - dBm 1850-1910 MHz LTE - -16 - dBm 1850-1915 MHz LTE - -17 - dBm 1920-1980 MHz WCDMA - -17.5 - dBm 1920-1980 MHz CDMA2000 - -19.5 - dBm 1920-1980 MHz LTE - -19.5 - dBm 2300-2400 MHz LTE - -44 - dBm 2500-2570 MHz LTE - -43 - dBm 2570-2620 MHz LTE - -34 - dBm 5G - >-4 - dBm @ 1, 2 Mbps (8% PER, 1024 octets) -6 - - dBm @ 5.5, 11 Mbps (8% PER, 1024 octets) -12 - - dBm @ 6-54 Mbps (10% PER, 1000 octets) -15.5 - - dBm Broadcom(R) August 24, 2015 * 4343W-DS107-R WLAN Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 119 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLAN 2.4 GHz Receiver Performance Specifications Table 29: WLAN 2.4 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit Adjacent channel rejection- 11 Mbps DSSS DSSS. (Difference between interfering and desired signal [25 MHz apart] at 8% PER for 1024 octet PSDU with desired signal level as specified in Condition/ Notes.) -70 dBm 35 - - dB 6 Mbps OFDM -79 dBm 16 - - dB 9 Mbps OFDM -78 dBm 15 - - dB 12 Mbps OFDM -76 dBm 13 - - dB 18 Mbps OFDM -74 dBm 11 - - dB 24 Mbps OFDM -71 dBm 8 - - dB 36 Mbps OFDM -67 dBm 4 - - dB 48 Mbps OFDM -63 dBm 0 - - dB 54 Mbps OFDM -62 dBm -1 - - dB 65 Mbps OFDM -61 dBm -2 - - dB Range -98 dBm to -75 dBm -3 - 3 dB Range above -75 dBm -5 - 5 dB Zo = 50 across the dynamic range. 10 - - dB Adjacent channel rejectionOFDM. (Difference between interfering and desired signal (25 MHz apart) at 10% PER for 1000c octet PSDU with desired signal level as specified in Condition/Notes.) RCPI accuracyd Return loss a. Optimal RF performance, as specified in this data sheet, is guaranteed only for temperatures between -10C and 55C. b. The cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that band for the purpose of this test. It is not intended to indicate any specific usage of each band in any specific country. c. For 65 Mbps, the size is 4096. d. The minimum and maximum values shown have a 95% confidence level. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 120 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLAN 2.4 GHz Transmitter Performance Specifications WLAN 2.4 GHz Transmitter Performance Specifications Note: Unless otherwise specified, the specifications in Table 29 are measured at the chip port (for the location of the chip port, see Figure 43 on page 117). Table 30: WLAN 2.4 GHz Transmitter Performance Specifications Parameter Frequency range Condition/Notes Minimum Typical Maximum Unit - Transmitted power in 776-794 MHz cellular and WLAN 5G 869-960 MHz bands (at 21 dBm, 90% 1450-1495 MHz duty cycle, 1 Mbps CCK).a 1570-1580 MHz - - - MHz CDMA2000 - -167.5 - dBm/Hz CDMAOne, GSM850 - -163.5 - dBm/Hz DAB - -154.5 - dBm/Hz GPS - -152.5 - dBm/Hz 1592-1610 MHz GLONASS - -149.5 - dBm/Hz 1710-1800 MHz DSC-1800-Uplink - -145.5 - dBm/Hz 1805-1880 MHz GSM1800 - -143.5 - dBm/Hz 1850-1910 MHz GSM1900 - -140.5 - dBm/Hz 1910-1930 MHz TDSCDMA, LTE - -138.5 - dBm/Hz 1930-1990 MHz GSM1900, CDMAOne, WCDMA - -139 - dBm/Hz 2010-2075 MHz TDSCDMA - -127.5 - dBm/Hz 2110-2170 MHz WCDMA - -124.5 - dBm/Hz 2305-2370 MHz LTE Band 40 - -104.5 - dBm/Hz 2370-2400 MHz LTE Band 40 - -81.5 - dBm/Hz 2496-2530 MHz LTE Band 41 - -94.5 - dBm/Hz 2530-2560 MHz LTE Band 41 - -120.5 - dBm/Hz 2570-2690 MHz LTE Band 41 - -121.5 - dBm/Hz 5000-5900 MHz WLAN 5G - -109.5 - - Harmonic level (at 21 dBm 4.8-5.0 GHz with 90% duty cycle, 1 Mbps CCK) 7.2-7.5 GHz 2nd harmonic - -26.5 - dBm/ MHz 3rd harmonic - -23.5 - dBm/ MHz 9.6-10 GHz 4th harmonic - -32.5 - dBm/ MHz Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 121 BROADCOM CONFIDENTIAL BCM4343W Data Sheet WLAN 2.4 GHz Transmitter Performance Specifications Table 30: WLAN 2.4 GHz Transmitter Performance Specifications (Cont.) Parameter TX power at the chip port for the highest power level setting at 25C, VBA = 3.6V, and spectral mask and EVM complianceb, c Condition/Notes Minimum Typical Maximum Unit - EVM Does Not Exceed IEEE 802.11b (DSSS/CCK) -9 dB 21 - - dBm OFDM, BPSK -8 dB 20.5 - - dBm OFDM, QPSK -13 dB 20.5 - - dBm OFDM, 16-QAM -19 dB 20.5 - - dBm OFDM, 64-QAM -25 dB (R = 3/4) 18 - - dBm OFDM, 64-QAM -27 dB (R = 5/6) 17.5 - - dBm OFDM, 256-QAM -32 dB (R = 5/6) 15 - - dBm - 9 - - dB - Closed loop TX power Across full temperature and voltage variation at highest power range. Applies across 5 to 21 dBm output level setting power range. - 1.5 dB Carrier suppression - 15 - - dBc Gain control step - - 0.25 - dB Return loss Zo = 50 4 6 - dB Load pull variation for output power, EVM, and Adjacent Channel Power Ratio (ACPR) VSWR = 2:1. - 3.5 - dB TX power control dynamic range VSWR = 3:1. EVM degradation Output power variation - 2 - dB ACPR-compliant power level - 15 - dBm EVM degradation - 4 - dB Output power variation - 3 - dB ACPR-compliant power level 15 - dBm - a. The cellular standards listed indicate only typical usages of that band in some countries. Other standards may also be used within those bands. b. TX power for channel 1 and channel 11 is specified separately by nonvolatile memory parameters to ensure band-edge compliance. c. Optimal RF performance, as specified in this data sheet, is guaranteed only for temperatures between -10C and 55C. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 122 BROADCOM CONFIDENTIAL BCM4343W Data Sheet General Spurious Emissions Specifications General Spurious Emissions Specifications Table 31: General Spurious Emissions Specifications Parameter Frequency range Condition/Notes - Minimum Typical Maximum Unit 2400 - 2500 MHz General Spurious Emissions TX emissions RX/standby emissions 30 MHz < f < 1 GHz RBW = 100 kHz - -99 -96 dBm 1 GHz < f < 12.75 GHz RBW = 1 MHz - -44 -41 dBm 1.8 GHz < f < 1.9 GHz RBW = 1 MHz - -68 -65 dBm 5.15 GHz < f < 5.3 GHz RBW = 1 MHz - -88 -85 dBm 30 MHz < f < 1 GHz RBW = 100 kHz - -99 -96 dBm 1 GHz < f < 12.75 GHz RBW = 1 MHz - -54 -51 dBm 1.8 GHz < f < 1.9 GHz RBW = 1 MHz - -88 -85 dBm 5.15 GHz < f < 5.3 GHz RBW = 1 MHz - -88 -85 dBm Note: The specifications in this table apply at the chip port. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 123 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Bluetooth RF Specifications S e c t i o n 1 7 : B l u e t o o t h R F Sp e c i f i c a t i o n s Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Unless otherwise stated, limit values apply for the conditions specified in Table 25: "Environmental Ratings," on page 114 and Table 27: "Recommended Operating Conditions and DC Characteristics," on page 115. Typical values apply for the following conditions: * VBAT = 3.6V. * Ambient temperature +25C. Note: All Bluetooth specifications apply at the chip port. For the location of the chip port, see Figure 43: "RF Port Location," on page 117. Table 32: Bluetooth Receiver RF Specifications Parameter Conditions Minimum Typical Maximum Unit Note: The specifications in this table are measured at the chip output port unless otherwise specified. General Frequency range RX sensitivity - 2402 - 2480 MHz GFSK, 0.1% BER, 1 Mbps - -94 - dBm /4-DQPSK, 0.01% BER, 2 Mbps - -96 - dBm 8-DPSK, 0.01% BER, 3 Mbps - -90 - dBm Input IP3 - -16 - - dBm Maximum input at antenna - - - -20 dBm C/I co-channel GFSK, 0.1% BER - - 11 dB C/I 1 MHz adjacent channel GFSK, 0.1% BER - - 0.0 dB C/I 2 MHz adjacent channel GFSK, 0.1% BER - - -30 dB Interference Performancea C/I 3 MHz adjacent channel GFSK, 0.1% BER - - -40 dB C/I image channel GFSK, 0.1% BER - - -9 dB C/I 1 MHz adjacent to image channel GFSK, 0.1% BER - - -20 dB C/I co-channel /4-DQPSK, 0.1% BER - - 13 dB C/I 1 MHz adjacent channel /4-DQPSK, 0.1% BER - - 0.0 dB C/I 2 MHz adjacent channel /4-DQPSK, 0.1% BER - - -30 dB C/I 3 MHz adjacent channel /4-DQPSK, 0.1% BER - - -40 dB Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 124 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Bluetooth RF Specifications Table 32: Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit C/I image channel /4-DQPSK, 0.1% BER - - -7 dB C/I 1 MHz adjacent to image channel /4-DQPSK, 0.1% BER - - -20 dB C/I co-channel 8-DPSK, 0.1% BER - - 21 dB C/I 1 MHz adjacent channel 8-DPSK, 0.1% BER - - 5.0 dB C/I 2 MHz adjacent channel 8-DPSK, 0.1% BER - - -25 dB C/I 3 MHz adjacent channel 8-DPSK, 0.1% BER - - -33 dB C/I Image channel 8-DPSK, 0.1% BER - - 0.0 dB C/I 1 MHz adjacent to image channel 8-DPSK, 0.1% BER - - -13 dB Out-of-Band Blocking Performance (CW) 30-2000 MHz 0.1% BER - -10.0 - dBm 2000-2399 MHz 0.1% BER - -27 - dBm 2498-3000 MHz 0.1% BER - -27 - dBm 3000 MHz-12.75 GHz 0.1% BER - -10.0 - dBm Out-of-Band Blocking Performance, Modulated Interferer (LTE) GFSK (1 Mbps) 2310 MHz LTE band40 TDD 20M BW - -20 - dBm 2330 MHz LTE band40 TDD 20M BW - -19 - dBm 2350 MHz LTE band40 TDD 20M BW - -20 - dBm 2370 MHz LTE band40 TDD 20M BW - -24 - dBm 2510 MHz LTE band7 FDD 20M BW - -24 - dBm 2530 MHz LTE band7 FDD 20M BW - -21 - dBm 2550 MHz LTE band7 FDD 20M BW - -21 - dBm 2570 MHz LTE band7 FDD 20M BW - -20 - dBm /4 DPSK (2 Mbps) 2310 MHz LTE band40 TDD 20M BW - -20 - dBm 2330 MHz LTE band40 TDD 20M BW - -19 - dBm 2350 MHz LTE band40 TDD 20M BW - -20 - dBm 2370 MHz LTE band40 TDD 20M BW - -24 - dBm 2510 MHz LTE band7 FDD 20M BW - -24 - dBm 2530 MHz LTE band7 FDD 20M BW - -20 - dBm 2550 MHz LTE band7 FDD 20M BW - -20 - dBm 2570 MHz LTE band7 FDD 20M BW - -20 - dBm 8DPSK (3 Mbps) 2310 MHz LTE band40 TDD 20M BW - -20 - dBm 2330 MHz LTE band40 TDD 20M BW - -19 - dBm 2350 MHz LTE band40 TDD 20M BW - -20 - dBm Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 125 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Bluetooth RF Specifications Table 32: Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions 2370 MHz Minimum Typical Maximum Unit LTE band40 TDD 20M BW - -24 - dBm 2510 MHz LTE band7 FDD 20M BW - -24 - dBm 2530 MHz LTE band7 FDD 20M BW - -21 - dBm 2550 MHz LTE band7 FDD 20M BW - -20 - dBm 2570 MHz LTE band7 FDD 20M BW - -20 - dBm Out-of-Band Blocking Performance, Modulated Interferer (Non-LTE) GFSK (1 Mbps)a 698-716 MHz WCDMA - -12 - dBm 776-849 MHz WCDMA - -12 - dBm 824-849 MHz GSM850 - -12 - dBm 824-849 MHz WCDMA - -12 - dBm 880-915 MHz E-GSM - -11 - dBm 880-915 MHz WCDMA - -11 - dBm 1710-1785 MHz GSM1800 - -16 - dBm 1710-1785 MHz WCDMA - -15 - dBm 1850-1910 MHz GSM1900 - -18 - dBm 1850-1910 MHz WCDMA - -17 - dBm 1880-1920 MHz TD-SCDMA - -18 - dBm 1920-1980 MHz WCDMA - -18 - dBm 2010-2025 MHz TD-SCDMA - -18 - dBm 2500-2570 MHz WCDMA - -21 - dBm /4 DPSK (2 Mbps) a 698-716 MHz WCDMA - -8 - dBm 776-794 MHz WCDMA - -8 - dBm 824-849 MHz GSM850 - -9 - dBm 824-849 MHz WCDMA - -9 - dBm 880-915 MHz E-GSM - -8 - dBm 880-915 MHz WCDMA - -8 - dBm 1710-1785 MHz GSM1800 - -14 - dBm 1710-1785 MHz WCDMA - -14 - dBm 1850-1910 MHz GSM1900 - -15 - dBm 1850-1910 MHz WCDMA - -14 - dBm 1880-1920 MHz TD-SCDMA - -16 - dBm 1920-1980 MHz WCDMA - -15 - dBm Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 126 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Bluetooth RF Specifications Table 32: Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit 2010-2025 MHz TD-SCDMA - -17 - dBm 2500-2570 MHz WCDMA - -21 - dBm 8DPSK (3 Mbps)a 698-716 MHz WCDMA - -11 - dBm 776-794 MHz WCDMA - -11 - dBm 824-849 MHz GSM850 - -11 - dBm 824-849 MHz WCDMA - -12 - dBm 880-915 MHz E-GSM - -11 - dBm 880-915 MHz WCDMA - -11 - dBm 1710-1785 MHz GSM1800 - -16 - dBm 1710-1785 MHz WCDMA - -15 - dBm 1850-1910 MHz GSM1900 - -17 - dBm 1850-1910 MHz WCDMA - -17 - dBm 1880-1920 MHz TD-SCDMA - -17 - dBm 1920-1980 MHz WCDMA - -17 - dBm 2010-2025 MHz TD-SCDMA - -18 - dBm 2500-2570 MHz WCDMA - -21 - dBm - - -90.0 -80.0 dBm - -95 -62 dBm RX LO Leakage 2.4 GHz band Spurious Emissions 30 MHz-1 GHz 1-12.75 GHz - -70 -47 dBm 869-894 MHz - -147 - dBm/Hz 925-960 MHz - -147 - dBm/Hz 1805-1880 MHz - -147 - dBm/Hz 1930-1990 MHz - -147 - dBm/Hz 2110-2170 MHz - -147 - dBm/Hz a. The Bluetooth reference level for the required signal at the Bluetooth chip port is 3 dB higher than the typical sensitivity level. Table 33: LTE Specifications for Spurious Emissions Parameter Conditions Typical Unit 2500-2570 MHz Band 7 -147 dBm/Hz 2300-2400 MHz Band 40 -147 dBm/Hz 2570-2620 MHz Band 38 -147 dBm/Hz 2545-2575 MHz XGP Band -147 dBm/Hz Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 127 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Bluetooth RF Specifications Table 34: Bluetooth Transmitter RF Specificationsa Parameter Conditions Minimum Typical Maximum Unit General Frequency range Basic rate (GFSK) TX power at Bluetooth QPSK TX power at Bluetooth 8PSK TX power at Bluetooth Power control step - 2402 - - - 2 - 12.0 8.0 8.0 4 2480 - - - 8 MHz dBm dBm dBm dB - 0.93 1 MHz M - N = the frequency range for - which the spurious emission is - measured relative to the - transmit center frequency. -38 -31 -43 -26.0 -20.0 -40.0 dBc dBm dBm GFSK In-Band Spurious Emissions -20 dBc BW - EDR In-Band Spurious Emissions 1.0 MHz < |M - N| < 1.5 MHz 1.5 MHz < |M - N| < 2.5 MHz |M - N| 2.5 MHzb Out-of-Band Spurious Emissions 30 MHz to 1 GHz - - - -36.0 c,d dBm 1 GHz to 12.75 GHz - - - dBm 1.8 GHz to 1.9 GHz 5.15 GHz to 5.3 GHz - - - - - - -30.0 d,e,f -47.0 -47.0 dBm dBm - - -103 - dBm FM RX CDMA2000 cdmaOne, GSM850 E-GSM GPS GSM1800 GSM1900, cdmaOne, WCDMA WCDMA - - - - - - - - -147 -146 -146 -146 -146 -144 -143 -137 - - - - - - - - dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz GPS Band Spurious Emissions Spurious emissions Out-of-Band Noise Floorg 65-108 MHz 776-794 MHz 869-960 MHz 925-960 MHz 1570-1580 MHz 1805-1880 MHz 1930-1990 MHz 2110-2170 MHz a. Unless otherwise specified, the specifications in this table apply at the chip output port, and output power specifications are with the temperature correction algorithm and TSSI enabled. b. Typically measured at an offset of 3 MHz. c. The maximum value represents the value required for Bluetooth qualification as defined in the v4.1 specification. d. The spurious emissions during Idle mode are the same as specified in Table 34 on page 128. e. Specified at the Bluetooth antenna port. f. Meets this specification using a front-end band-pass filter. g. Transmitted power in cellular and FM bands at the Bluetooth antenna port. See Figure 43 on page 117 for location of the port. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 128 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Bluetooth RF Specifications Table 35: LTE Specifications for Out-of-Band Noise Floor Parameter Conditions Typical Unit 2500-2570 MHz Band 7 -130 dBm/Hz 2300-2400 MHz Band 40 -130 dBm/Hz 2570-2620 MHz Band 38 -130 dBm/Hz 2545-2575 MHz XGP Band -130 dBm/Hz Table 36: Local Oscillator Performance Parameter Minimum Typical Maximum Unit Lock time - 72 - s Initial carrier frequency tolerance - 25 75 kHz DH1 packet - 8 25 kHz DH3 packet - 8 40 kHz DH5 packet - 8 40 kHz Drift rate - 5 20 kHz/50 s 00001111 sequence in payloada 140 155 175 kHz 10101010 sequence in payloadb 115 140 - kHz Channel spacing - 1 - MHz LO Performance Frequency Drift Frequency Deviation a. b. This pattern represents an average deviation in payload. Pattern represents the maximum deviation in payload for 99.9% of all frequency deviations. Table 37: BLE RF Specifications Parameter Conditions Minimum Typical Maximum Unit Frequency range - 2402 - 2480 MHz GFSK, 0.1% BER, 1 Mbps - -97 - dBm TX powerb - - 8.5 - dBm Mod Char: delta f1 average - 225 255 275 kHz Mod Char: delta f2 maxc - 99.9 - - % Mod Char: ratio - 0.8 0.95 - % RX sense a a. The Bluetooth tester is set so that Dirty TX is on. b. BLE TX power can be increased to compensate for front-end losses such as BPF, diplexer, switch, etc.). The output is capped at 12 dBm. The BLE TX power at the antenna port cannot exceed the 10 dBm specification limit. c. At least 99.9% of all delta F2 max. frequency values recorded over 10 packets must be greater than 185 kHz. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 129 BROADCOM CONFIDENTIAL BCM4343W Data Sheet FM Receiver Specifications S e c t i o n 1 8 : F M R e c e i v e r Sp e c i f i c a t i o n s Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Unless otherwise stated, limit values apply for the conditions specified inTable 25: "Environmental Ratings," on page 114 and Table 27: "Recommended Operating Conditions and DC Characteristics," on page 115. Typical values apply for the following conditions: * VBAT = 3.6V. * Ambient temperature +25C. Table 38: FM Receiver Specifications Parameter Conditionsa Minimum Typical Maximum Units RF Parameters Operating frequencyb Frequencies inclusive Sensitivityc Receiver adjacent channel selectivityc,d FM only, SNR 26 dB 65 - 108 MHz - 1 - dBV EMF - 1.1 - V EMF - -5 - dBV Measured for 30 dB SNR at audio output. Signal of interest: 23 dBV EMF (14.1 V EMF). At 200 kHz. - 51 - dB At 400 kHz. - 62 - dB 45 53 - dB Intermediate signal- Vin = 20 dBV (10 V EMF). plus-noise to noise ratio (S + N)/N, stereoc Intermodulation performancec,d Blocker level increased until desired at - 30 dB SNR. Wanted signal: 33 dBV EMF (45 V EMF) Modulated interferer: At fWanted + 400 kHz and + 4 MHz. CW interferer: At fWanted + 800 kHz and + 8 MHz. 55 - dBc AM suppression, monoc 40 Vin = 23 dBV EMF (14.1 V EMF). AM at 400 Hz with m = 0.3. No A-weighted or any other filtering applied. - - dB Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 130 BROADCOM CONFIDENTIAL BCM4343W Data Sheet FM Receiver Specifications Table 38: FM Receiver Specifications (Cont.) Conditionsa Minimum Typical Maximum Units RDS deviation = 1.2 kHz. - 17 - dBV EMF - 7.1 - V EMF - 11 - dBV - 13 - dBV EMF - 4.4 - V EMF - 7 - dBV 200 kHz - 49 - dB 300 kHz - 52 - dB 400 kHz - 52 - dB RF input impedance - 1.5 - - k Antenna tuning cap - 2.5 - 30 pF Maximum input levelc SNR > 26 dB. - - 113 dBV EMF - - 446 mV EMF - - 107 dBV Local oscillator breakthrough measured on - the reference port. - -55 dBm 869-894 MHz, 925-960 MHz, 1805-1880 MHz, and 1930-1990 MHz. GPS. - -90 dBm Parameter RDS RDS sensitivitye,f RDS deviation = 2 kHz. RDS selectivityf Wanted Signal: 33 dBV EMF (45 V EMF), 2 kHz RDS deviation. Interferer: f = 40 kHz, fmod = 1 kHz. RF Input RF conducted emissions Broadcom(R) August 24, 2015 * 4343W-DS107-R - Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 131 BROADCOM CONFIDENTIAL BCM4343W Data Sheet FM Receiver Specifications Table 38: FM Receiver Specifications (Cont.) Parameter Conditionsa RF blocking levels at the FM antenna input with a 40 dB SNR (assumes a 50 input and excludes spurs) GSM850, E-GSM (standard); BW = 0.2 MHz. - 824-849 MHz, 880-915 MHz. 7 - dBm GSM 850, E-GSM (edge); BW = 0.2 MHz. 824-849 MHz, 880-915 MHz. - 0 - dBm GSM DCS 1800, PCS 1900 (standard, edge); BW = 0.2 MHz. 1710-1785 MHz, 1850-1910 MHz. - 12 - dBm WCDMA: II (I), III (IV,X); BW = 5 MHz. 1710-1785 MHz (1710-1755 MHz, 1710-1770 MHz), 1850-1980 MHz (1920-1980 MHz). - 12 - dBm WCDMA: V (VI), VIII, XII, XIII, XIV; BW = 5 MHz. 824-849 MHz (830-840 MHz), 880-915 MHz. - 5 - dBm CDMA2000, CDMA One; BW = 1.25 MHz. 776-794 MHz, 824-849 MHz, 887-925 MHz. - 0 - dBm CDMA2000, CDMA One; BW= 1.25 MHz. 1750-1780 MHz, 1850-1910 MHz, 1920-1980 MHz. - 12 - dBm Bluetooth; BW = 1 MHz. 2402-2480 MHz. - 11 - dBm LTE, Band 38, Band 40, XGP Band - 11 - dBm WLAN-g/b; BW = 20 MHz. 2400-2483.5 MHz. - 11 - dBm WLAN-a; BW = 20 MHz. 4915-5825 MHz. - 6 - dBm Frequency step - 10 - - kHz Settling time Single frequency switch in any direction - to a frequency within the 88-108 MHz or 76-90 MHz bands. Time measured to within 5 kHz of the final frequency. 150 - s Search time Total time for an automatic search to sweep from 88-108 MHz or 76-90 MHz (or in the reverse direction) assuming no channels are found. - 8 sec Minimum Typical Maximum Units Tuning Broadcom(R) August 24, 2015 * 4343W-DS107-R - Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 132 BROADCOM CONFIDENTIAL BCM4343W Data Sheet FM Receiver Specifications Table 38: FM Receiver Specifications (Cont.) Conditionsa Minimum Typical Maximum Units Audio output levelg - -14.5 - -12.5 dBFS Maximum audio output levelh - - - 0 dBFS DAC audio output level Conditions: Vin = 66 dBV EMF (2 mV EMF), f = 22.5 kHz, fmod = 1 kHz, f Pilot = 6.75 kHz 72 - 88 mV RMS - 333 - mV RMS -1 - 1 dB Left and right AC mute FM input signal fully muted with DAC enabled 60 - - dB Left and right hard mute 80 - - dB Parameter General Audio Maximum DAC audio - output levelh Audio DAC output level differencei - FM input signal fully muted with DAC disabled Soft mute attenuation Muting is performed dynamically, proportional to the desired FM input signal C/N. The and start level muting characteristic is fully programmable. See "Audio Features" on page 77. Maximum signal plus - noise-to-noise ratio (S + N)/N, monoi - 69 - dB Maximum signal plus - noise-to-noise ratio (S + N)/N, stereog - 64 - dB Total harmonic distortion, mono Vin = 66 dBV EMF(2 mV EMF): - - - - f = 75 kHz, fmod = 400 Hz. - - 0.8 % f = 75 kHz, fmod = 1 kHz. - - 0.8 % f = 75 kHz, fmod = 3 kHz. - - 0.8 % f = 100 kHz, fmod = 1 kHz. - - 1.0 % Total harmonic distortion, stereo Vin = 66 dBV EMF (2 mV EMF), f = 67.5 kHz, fmod = 1 kHz, f pilot = 6.75 kHz, L = R - - 1.5 % Audio spurious productsi Range from 300 Hz to 15 kHz with respect to a 1 kHz tone. - - -60 dBc Audio bandwidth, upper (-3 dB point) Vin = 66 dBV EMF (2 mV EMF) f = 8 kHz, for 50 s 15 - - kHz - - 20 Hz Audio bandwidth, lower (-3 dB point) Audio in-band ripple 100 Hz to 13 kHz, Vin = 66 dBV EMF (2 mV EMF), f = 8 kHz, for 50 s. -0.5 - 0.5 dB Deemphasis time constant tolerance With respect to 50 and 75 s. - - 5 % Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 133 BROADCOM CONFIDENTIAL BCM4343W Data Sheet FM Receiver Specifications Table 38: FM Receiver Specifications (Cont.) Parameter Conditionsa Minimum Typical Maximum Units RSSI range With 1 dB resolution and 5 dB accuracy at room temperature. 3 - 83 dBV EMF 1.41 - 1.41E+4 V EMF -3 - 77 dBV - 44 - dB Stereo Decoder Stereo channel separation Forced Stereo mode Vin = 66 dBV EMF (2 mV EMF), f = 67.5 kHz, fmod = 1 kHz, f Pilot = 6.75 kHz, R = 0, L = 1 Mono stereo blend and switching Dynamically proportional to the desired FM input signal C/N. The blending and switching characteristics are fully programmable. See "Audio Features" on page 77. Pilot suppression Vin = 66 dBV EMF (2 mV EMF), f = 75 kHz, fmod = 1 kHz. 46 - - dB Relative to 1-kHz tone, f = 22.5 kHz. - - - - 4 values in 3 dB steps -21 - -12 dB 4 values 20 - 40 ms Pause Detection Audio level at which a pause is detected Audio pause duration a. The following conditions are applied to all relevant tests unless otherwise indicated: Preemphasis and deemphasis of 50 s, R = L for mono, BAF = 300 Hz to 15 kHz, A-weighted filtering applied. b. Contact your Broadcom representative for applications operating between 65-76 MHz. c. Signal of interest: f = 22.5 kHz, fmod = 1 kHz. d. Interferer: f = 22.5 kHz, fmod = 1 kHz. e. RDS sensitivity numbers are for 87.5-108 MHz only. f. Vin = f = 32 kHz, fmod = 1 kHz, f pilot = 7.5 kHz, and with an interferer for 95% of blocks decoded with no errors after correction, over a sample of 5000 blocks. g. Vin = 66 dBV EMF (2 mV EMF), f = 22.5 kHz, fmod = 1 kHz, f pilot = 6.75 kHz. h. Vin = 66 dBV EMF (2 mV EMF), f = 100 kHz, fmod = 1 kHz, f pilot = 6.75 kHz. i. Vin = 66 dBV EMF (2 mV EMF), f = 22.5 kHz, fmod = 1 kHz. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 134 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Internal Regulator Electrical Specifications Section 19: Internal Regulator Electrical Sp ecifications Note: Values in this data sheet are design goals and are subject to change based on device characterization results. Functional operation is not guaranteed outside of the specification limits provided in this section. Core Buck Switching Regulator Table 39: Core Buck Switching Regulator (CBUCK) Specifications Specification Notes Min. Typ. Max. Units Input supply voltage (DC) DC voltage range inclusive of disturbances. 2.4 3.6 4.8a V PWM mode switching frequency CCM, load > 100 mA VBAT = 3.6V. - 4 - MHz PWM output current - - - 370 mA Output current limit - - 1400 - mA Output voltage range Programmable, 30 mV steps. Default = 1.35V. 1.2 1.35 1.5 V PWM output voltage DC accuracy Includes load and line regulation. Forced PWM mode. -4 - 4 % PWM ripple voltage, static Measure with 20 MHz bandwidth limit. - Static load, max. ripple based on VBAT = 3.6V, Vout = 1.35V, Fsw = 4 MHz, 2.2 H inductor L > 1.05 H, Cap + Board total-ESR < 20 m, Cout > 1.9 F, ESL<200 pH 7 20 mVpp PWM mode peak efficiency Peak efficiency at 200 mA load, inductor DCR = 200 m, VBAT = 3.6V, VOUT = 1.35V - 85 - % PFM mode efficiency 10 mA load current, inductor DCR = 200 m, VBAT = 3.6V, VOUT = 1.35V - 77 - % Start-up time from power down VDDIO already ON and steady. - Time from REG_ON rising edge to CLDO reaching 1.2V 400 500 s External inductor 0603 size, 2.2 H 20%, DCR = 0.2 25% 2.2 - H External output capacitor Ceramic, X5R, 0402, 2.0b ESR <30 m at 4 MHz, 4.7 F 20%, 10V 4.7 10c F Broadcom(R) August 24, 2015 * 4343W-DS107-R - Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 135 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Core Buck Switching Regulator Table 39: Core Buck Switching Regulator (CBUCK) Specifications (Cont.) Specification Notes Min. Typ. Max. Units External input capacitor For SR_VDDBATP5V pin, ceramic, X5R, 0603, ESR < 30 m at 4 MHz, 4.7 F 20%, 10V 0.67b 4.7 - F Input supply voltage ramp-up time 0 to 4.3V 40 - - s a. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging. c. Total capacitance includes those connected at the far end of the active load. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 136 BROADCOM CONFIDENTIAL BCM4343W Data Sheet 3.3V LDO (LDO3P3) 3.3V LDO (LDO3P3) Table 40: LDO3P3 Specifications Specification Notes Input supply voltage, Vin Output current Nominal output voltage, Vo Min. = Vo + 0.2V = 3.5V dropout voltage 3.1 requirement must be met under maximum load for performance specifications. - 0.001 Default = 3.3V. - Dropout voltage Output voltage DC accuracy Quiescent current Line regulation At max. load. Includes line/load regulation. No load Vin from (Vo + 0.2V) to 4.8V, max. load Load regulation PSRR load from 1 mA to 450 mA Vin Vo + 0.2V, Vo = 3.3V, Co = 4.7 F, Max. load, 100 Hz to 100 kHz Chip already powered up. Ceramic, X5R, 0402, (ESR: 5 m-240 m), 10%, 10V For SR_VDDBATA5V pin (shared with band gap) Ceramic, X5R, 0402, (ESR: 30m-200 m), 10%, 10V. Not needed if sharing VBAT capacitor 4.7 F with SR_VDDBATP5V. LDO turn-on time External output capacitor, Co External input capacitor Min. Typ. Max. Units 3.6 4.8a V - 3.3 450 - mA V - -5 - - - - 66 - 200 +5 85 3.5 mV % A mV/V - 20 - - 0.3 - mV/mA dB - 1.0b 160 4.7 250 5.64 s F - 4.7 - F a. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 137 BROADCOM CONFIDENTIAL BCM4343W Data Sheet CLDO CLDO Table 41: CLDO Specifications Specification Notes Min. Typ. Max. Units Input supply voltage, Vin Min. = 1.2 + 0.15V = 1.35V dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 V Output current - 0.2 - 200 mA Output voltage, Vo Programmable in 10 mV steps. Default = 1.2.V 0.95 1.2 1.26 V Dropout voltage At max. load - - 150 mV Output voltage DC accuracy Includes line/load regulation -4 - +4 % Quiescent current No load - 13 - A 200 mA load - 1.24 - mA Line regulation Vin from (Vo + 0.15V) to 1.5V, maximum load - - 5 mV/V Load regulation Load from 1 mA to 300 mA - 0.02 0.05 mV/mA Leakage current Power down - 5 20 A Bypass mode - 1 3 A PSRR @1 kHz, Vin 1.35V, Co = 4.7 F 20 - - dB Start-up time of PMU VDDIO up and steady. Time from the REG_ON rising edge to the CLDO reaching 1.2V. - - 700 s LDO turn-on time LDO turn-on time when rest of the chip is up. - 140 180 s External output capacitor, Co Total ESR: 5 m-240 m 1.1a 2.2 - F External input capacitor Only use an external input capacitor at the VDD_LDO pin if it is not supplied from CBUCK output. - 1 2.2 F a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 138 BROADCOM CONFIDENTIAL BCM4343W Data Sheet LNLDO LNLDO Table 42: LNLDO Specifications Specification Notes Min. Typ. Max. Units Input supply voltage, Vin Min. VIN = VO + 0.15V = 1.35V (where VO = 1.2V) dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 V Output current - 0.1 - 150 mA Output voltage, Vo Programmable in 25 mV steps. Default = 1.2V 1.1 1.2 1.275 V Dropout voltage At maximum load - - 150 mV Output voltage DC accuracy Includes line/load regulation -4 - +4 % Quiescent current No load - 10 12 A Max. load - 970 990 A Line regulation Vin from (Vo + 0.15V) to 1.5V, 200 mA load - - 5 mV/V Load regulation Load from 1 mA to 200 mA: Vin (Vo + 0.12V) - 0.025 0.045 mV/mA Leakage current Power-down, junction temp. = 85C - 5 20 A Output noise @30 kHz, 60-150 mA load Co = 2.2 F @100 kHz, 60-150 mA load Co = 2.2 F - - 60 35 -nV/ Hz PSRR @1 kHz, Vin (Vo + 0.15V), Co = 4.7 F 20 - - dB LDO turn-on time LDO turn-on time when rest of chip is up - 140 180 s 0.5a 2.2 4.7 F 1 2.2 F External output capacitor, Co Total ESR (trace/capacitor): 5 m-240 m External input capacitor Only use an external input capacitor at the - VDD_LDO pin if it is not supplied from CBUCK output. Total ESR (trace/capacitor): 30 m-200 m a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 139 BROADCOM CONFIDENTIAL BCM4343W Data Sheet System Power Consumption Section 20: System Power Consumption Note: The values in this data sheet are design goals and are subject to change based on device characterization.Unless otherwise stated, these values apply for the conditions specified in Table 27: "Recommended Operating Conditions and DC Characteristics," on page 115. WLAN Current Consumption Table 43 shows typical currents consumed by the BCM4343W's WLAN section. All values shown are with the Bluetooth core in Reset mode with Bluetooth and FM off. 2.4 GHz Mode Table 43: 2.4 GHz Mode WLAN Power Consumption VBAT = 3.6V, VDDIO = 1.8V, TA 25C Mode Rate VBAT (mA) Vio (A) N/A 0.0035 0.08 N/A 0.0058 80 Sleep (idle, associated, inter-beacons) b Rate 1 0.0058 80 IEEE Power Save PM1 DTIM1 (Avg.) c Rate 1 1.05 74 IEEE Power Save PM1 DTIM3 (Avg.) d Rate 1 0.35 86 IEEE Power Save PM2 DTIM1 (Avg.) c Rate 1 1.05 74 IEEE Power Save PM2 DTIM3 (Avg.) d Rate 1 0.35 86 Rx Listen Mode e N/A 37 12 Rx Active (at -50dBm RSSI) f Rate 1 39 12 Rate 11 40 12 Rate 54 40 12 Rate MCS7 41 12 Rate 1 @ 20 dBm 320 15 Rate 11 @ 18 dBm 290 15 Rate 54 @ 15 dBm 260 15 Rate MCS7 @ 15 dBm 260 15 Sleep Modes Leakage (OFF) Sleep (idle, unassociated) a Active Modes Tx f a. Device is initialized in Sleep mode, but not associated. b. Device is associated, and then enters Power Save mode (idle between beacons). c. Beacon interval = 100 ms; beacon duration = 1 ms @ 1 Mbps (Integrated Sleep + wakeup + beacon). Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 140 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Bluetooth and FM Current Consumption d. Beacon interval = 300 ms; beacon duration = 1 ms @ 1 Mbps (Integrated Sleep + wakeup + beacon). e. Carrier sense (CCA) when no carrier present. f. Tx output power is measured on the chip-out side; duty cycle =100%. Tx Active mode is measured in Packet Engine mode (pseudo-random data) Bluetooth and FM Current Consumption The Bluetooth, BLE, and FM current consumption measurements are shown in Table 44. Note: * * * The WLAN core is in reset (WLAN_REG_ON = low) for all measurements provided in Table 44. For FM measurements, the Bluetooth core is in Sleep mode. The BT current consumption numbers are measured based on GFSK TX output power = 10 dBm. Table 44: Bluetooth BLE and FM Current Consumption Operating Mode VBAT (VBAT = 3.6V) Typical VDDIO (VDDIO = 1.8V) Typical Units Sleep 6 150 A Standard 1.28s Inquiry Scan 193 162 A 500 ms Sniff Master 305 172 A DM1/DH1 Master 23.3 - mA DM3/DH3 Master 28.4 - mA DM5/DH5 Master 29.1 - mA 3DH5/3DH5 Master 25.1 - mA SCO HV3 Master 11.8 - mA 8.6 - mA FMRX I2S Audioa 8 - mA FMRX I2S Audio + RDSa 8 - mA FMRX Analog Audio + RDSa 8.6 - mA BLE Scanb 187 164 A FMRX Analog Audio onlya BLE Adv. - Unconnectable 1.00 sec 93 163 A BLE Connected 1 sec 71 163 A a. In Mono/Stereo blend mode. b. No devices present. A 1.28 second interval with a scan window of 11.25 ms. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 141 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Interface Timing and AC Characteristics S e c t i o n 2 1 : I n t e r f a c e Ti m i n g a n d A C Characteristics Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Unless otherwise stated, the specifications in this section apply when the operating conditions are within the limits specified in Table 25 on page 114 and Table 27 on page 115. Functional operation outside of these limits is not guaranteed. SDIO Default Mode Timing SDIO default mode timing is shown by the combination of Figure 44 and Table 45 on page 143. Figure 44: SDIO Bus Timing (Default Mode) fPP tWL tWH SDIO_CLK tTHL tTLH tISU tIH Input Output tODLY tODLY (max) Broadcom(R) August 24, 2015 * 4343W-DS107-R (min) Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 142 BROADCOM CONFIDENTIAL BCM4343W Data Sheet SDIO Default Mode Timing Table 45: SDIO Bus Timing a Parameters (Default Mode) Parameter Symbol Minimum Typical Maximum Unit SDIO CLK (All values are referred to minimum VIH and maximum VILb) Frequency--Data Transfer mode fPP 0 - 25 MHz Frequency--Identification mode fOD 0 - 400 kHz Clock low time tWL 10 - - ns Clock high time tWH 10 - - ns Clock rise time tTLH - - 10 ns Clock fall time tTHL - - 10 ns Inputs: CMD, DAT (referenced to CLK) Input setup time tISU 5 - - ns Input hold time tIH 5 - - ns Output delay time--Data Transfer mode tODLY 0 - 14 ns Output delay time--Identification mode tODLY 0 - 50 ns Outputs: CMD, DAT (referenced to CLK) a. Timing is based on CL 40 pF load on command and data. b. min(Vih) = 0.7 x VDDIO and max(Vil) = 0.2 x VDDIO. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 143 BROADCOM CONFIDENTIAL BCM4343W Data Sheet SDIO High-Speed Mode Timing SDIO High-Speed Mode Timing SDIO high-speed mode timing is shown by the combination of Figure 45 and Table 46. Figure 45: SDIO Bus Timing (High-Speed Mode) fPP tWL tWH 50% VDD SDIO_CLK tTHL tISU tTLH tIH Input Output tODLY tOH Table 46: SDIO Bus Timing a Parameters (High-Speed Mode) Parameter Symbol Minimum Typical Maximum Unit SDIO CLK (all values are referred to minimum VIH and maximum VILb) Frequency - Data Transfer Mode fPP 0 - 50 MHz Frequency - Identification Mode fOD 0 - 400 kHz Clock low time tWL 7 - - ns Clock high time tWH 7 - - ns Clock rise time tTLH - - 3 ns Clock fall time tTHL - - 3 ns Input setup time tISU 6 - - ns Input hold time tIH 2 - - ns Output delay time - Data Transfer Mode tODLY - - 14 ns Output hold time tOH 2.5 - - ns Total system capacitance (each line) CL - - 40 pF Inputs: CMD, DAT (referenced to CLK) Outputs: CMD, DAT (referenced to CLK) a. Timing is based on CL 40 pF load on command and data. b. min(Vih) = 0.7 x VDDIO and max(Vil) = 0.2 x VDDIO. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 144 BROADCOM CONFIDENTIAL BCM4343W Data Sheet gSPI Signal Timing gSPI Signal Timing The gSPI device always samples data on the rising edge of the clock. Figure 46: gSPI Timing T1 T4 T2 T5 T3 SPI_CLK T6 T7 SPI_DIN T8 T9 SPI_DOUT (falling edge) Table 47: gSPI Timing Parameters Parameter Symbol Minimum Maximum Units Note Clock period T1 20.8 - ns Fmax = 50 MHz Clock high/low T2/T3 (0.45 x T1) - T4 (0.55 x T1) - T4 ns - Clock rise/fall time T4/T5 - 2.5 ns - Input setup time T6 5.0 - ns Setup time, SIMO valid to SPI_CLK active edge Input hold time T7 5.0 - ns Hold time, SPI_CLK active edge to SIMO invalid Output setup time T8 5.0 - ns Setup time, SOMI valid before SPI_CLK rising Output hold time T9 5.0 - ns Hold time, SPI_CLK active edge to SOMI invalid CSX to clocka - 7.86 - ns CSX fall to 1st rising edge Clock to CSXc - - - ns Last falling edge to CSX high a. SPI_CSx remains active for entire duration of gSPI read/write/write_read transaction (that is, overall words for multiple word transaction) Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 145 BROADCOM CONFIDENTIAL BCM4343W Data Sheet JTAG Timing JTAG Timing Table 48: JTAG Timing Characteristics Signal Name Period Output Maximum Output Minimum Setup Hold TCK 125 ns - - - - TDI - - - 20 ns 0 ns TMS - - - 20 ns 0 ns TDO - 100 ns 0 ns - - JTAG_TRST 250 ns - - - - Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 146 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Power-Up Sequence and Timing Section 22: Power-Up Sequence and Ti mi n g Sequencing of Reset and Regulator Control Signals The BCM4343W has two signals that allow the host to control power consumption by enabling or disabling the Bluetooth, WLAN, and internal regulator blocks. These signals are described below. Additionally, diagrams are provided to indicate proper sequencing of the signals for various operational states (see Figure 47 on page 148 through Figure 50 on page 149). The timing values indicated are minimum required values; longer delays are also acceptable. Note: * * * * The WL_REG_ON and BT_REG_ON signals are OR'ed in the BCM4343W. The diagrams show both signals going high at the same time (as would be the case if both REG signals were controlled by a single host GPIO). If two independent host GPIOs are used (one for WL_REG_ON and one for BT_REG_ON), then only one of the two signals needs to be high to enable the BCM4343W regulators. The reset requirements for the Bluetooth core are also applicable for the FM core. In other words, if FM is to be used, then the Bluetooth core must be enabled. The BCM4343W has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after VDDC and VDDIO have both passed the POR threshold (see Table 27: "Recommended Operating Conditions and DC Characteristics," on page 115). Wait at least 150 ms after VDDC and VDDIO are available before initiating SDIO accesses. VBAT and VDDIO should not rise faster than 40 s. VBAT should be up before or at the same time as VDDIO. VDDIO should not be present first or be held high before VBAT is high. Description of Control Signals * WL_REG_ON: Used by the PMU to power up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the internal BCM4343W regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this pin is low the WLAN section is in reset. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. * BT_REG_ON: Used by the PMU (OR-gated with WL_REG_ON) to power up the internal BCM4343W regulators. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. When this pin is low and WL_REG_ON is high, the BT section is in reset. Note: For both the WL_REG_ON and BT_REG_ON pins, there should be at least a 10 ms time delay between consecutive toggles (where both signals have been driven low). This is to allow time for the CBUCK regulator to discharge. If this delay is not followed, then there may be a VDDIO in-rush current on the order of 36 mA during the next PMU cold start. Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 147 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Sequencing of Reset and Regulator Control Signals Control Signal Timing Diagrams Figure 47: WLAN = ON, Bluetooth = ON 32.678 kHz Sleep Clock VBAT 90% of VH VDDIO ~ 2 Sleep cycles WL_REG_ON BT_REG_ON Figure 48: WLAN = OFF, Bluetooth = OFF 32.678 kHz Sleep Clock VBAT VDDIO WL_REG_ON BT_REG_ON Figure 49: WLAN = ON, Bluetooth = OFF 32.678 kHz Sleep Clock VBAT 90% of VH VDDIO ~ 2 Sleep cycles WL_REG_ON BT_REG_ON Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 148 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Sequencing of Reset and Regulator Control Signals Figure 50: WLAN = OFF, Bluetooth = ON 32.678 kHz Sleep Clock VBAT 90% of VH VDDIO ~ 2 Sleep cycles WL_REG_ON BT_REG_ON Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 149 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Package Information Section 23: Package Information Package Thermal Characteristics Table 49: Package Thermal Characteristicsa Characteristic Value in Still Air JA (C/W) 53.11 JB (C/W) 13.14 JC (C/W) 6.36 JT (C/W) 0.04 JB (C/W) 14.21 Maximum Junction Temperature Tj (C)b 125 Maximum Power Dissipation (W) 1.2 a. No heat sink, TA = 70C. This is an estimate based on a 4-layer PCB that conforms to EIA/JESD51-7 (101.6 mm x 114.3 mm x 1.6 mm) and P = 1.2W continuous dissipation. b. Absolute junction temperature limits maintained through active thermal monitoring and dynamic TX duty cycle limiting. Junction Temperature Estimation and PSI Versus Thetajc Package thermal characterization parameter PSI-JT (JT) yields a better estimation of actual junction temperature (TJ) versus using the junction-to-case thermal resistance parameter Theta-JC (JC). The reason for this is JC assumes that all the power is dissipated through the top surface of the package case. In actual applications, some of the power is dissipated through the bottom and sides of the package. JT takes into account power dissipated through the top, bottom, and sides of the package. The equation for calculating the device junction temperature is as follows: TJ = TT + P JT Where: * TJ = junction temperature at steady-state condition, C * TT = package case top center temperature at steady-state condition, C * P = device power dissipation, Watts * JT = package thermal characteristics (no airflow), C/W Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 150 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Mechanical Information Section 24: Mechanical Information Figure 51 shows the mechanical drawing for the BCM4343W WLBGA package. Figure 51: 74-Ball WLBGA Mechanical Information Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 151 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Mechanical Information Figure 52 shows the mechanical drawing for the BCM4343W WLCSP package. Figure 53 shows the WLCSP keep-out areas. Figure 52: 153-Bump WLCSP Mechanical Information Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 152 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Mechanical Information Note: No top-layer metal is allowed in the keep-out areas. Note: A DXF file containing WLBGA keep-outs can be imported into a layout program. Contact your Broadcom FAE for more information. Figure 53: WLCSP Package Keep-Out Areas--Top View with the Bumps Facing Down Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 153 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Mechanical Information Figure 54: WLBGA Package Keep-Out Areas--Top View with the Bumps Facing Down Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 154 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Ordering Information Section 25: Ordering Information Table 50: Part Ordering Information Part Number a Package BCM4343WKUBG 74-ball WLBGA halogen-free package 2.4 GHz single-band WLAN IEEE 802.11n + BT 4.1 + (4.87 mm x 2.87 mm, 0.40 pitch) FMRX + Wireless Charging Description BCM4343WKWBG 153-bump WLCSP 2.4 GHz single-band WLAN IEEE 802.11n + BT 4.1 + FMRX + Wireless Charging Operating Ambient Temperature -30C to +70C -30C to +70C a. Add "T" to the end of the part number to specify "Tape and Reel." Broadcom(R) August 24, 2015 * 4343W-DS107-R Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio Page 155 BROADCOM CONFIDENTIAL BCM4343W Data Sheet Broadcom(R) Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom Corporation is believed to be accurate and reliable. However, Broadcom Corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. (R) Broadcom Corporation 5300 California Avenue Irvine, CA 92617 (c) 2015 by BROADCOM CORPORATION. All rights reserved. 4343W-DS107-R August 24, 2015 Phone: 949-926-5000 Fax: 949-926-5203 E-mail: info@broadcom.com Web: www.broadcom.com