DATASHEET
FREESCALE P10XX AND P20XX SYSTEM CLOCK
W/66.66M DDR CLOCK IDT6V49205A
IDT®
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 1
IDT6V49205A REV Q 112316
General Description
The IDT6V49205A is a main clock for Freescale P10xx and
P20xx-based systems. It has a selectable System CCB
clock and a 66.66MHz DDRCLK. The IDT6V49205A also
provides LP-HCSL PCIe outputs for low power and reduced
board space.
Output Features
•1 - Sys_CCB 3.3V LVCMOS output @ 100M/83.33M/
80M/66.66M
•1 - DDRCLK 3.3V LVCMOS output @ 66.66M
•1 - 125M 3.3V LVCMOS output
•6 - LP-HCSL PCIe pairs selectable @ 100M or 125M
•6 - 25MHz 3.3V LVCMOS outputs
•2 - 2.048M 3.3V LVCMOS outputs
•2 - USB 3.3V LVCMOS outputs @12M or 24M
Key Specifications
•PCIe Gen1-2-3 compliant
•<3p rms phase noise on REF outputs
Recommended Application
System Clock for Freescale P10xx and P20xx-based
designs
Features
•Replaces 11 crystals, 2 oscillators and 3 clock
generators; lowers cost, power and area
•Integrated terminations on LP-HCSL PCIe outputs;
eliminate 24 resistors, saving 41mm2 of board area
•Industrial temperature range operation; supports
demanding environmental conditions
•Advanced 3.3V CMOS process; high-performance,
low-power
•Supports independent spread spectrum on
Sys_CCB/DDRCLK and PCIe outputs
•Packaged as 48-pin TSSOP, Pb-free, RoHS compliant
Block Diagram
GND
Crystal
Oscillator
PLL1
(SS)
25MHz
Crystal
X1
X2
PLL3
(non-
SS)
REF(5:0)
66M_SS
Sys_CCB
PLL4
(SS) PCIe_LR(5:0)
Control
Logic
SCLK
2.048M(1:0)
USB_CLK(2:1)
^FS0
PLL2
(non-
SS)
125M
^FS1
^SELPCIE125#_100
SDATA
100MHz
IDT6V49205A
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK
IDT®
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 2
IDT6V49205A
REV Q 112316
Pin Assignment
X2_25 1 48 VDDREF
X1_25 2 47 SDATA
GNDREF 3 46 SCLK
REF5 4 45 GND66
REF4 5 44 66M_SS
REF3 6 43 VDD66
VDDREF 7 42 AVDDSYS
GNDREF 8 41 Sys_CCB
REF2 9 40 GNDSYS
REF1 10 39 GNDPCIe
REF0 11 38 PCIeT_LR5
AVDD12_24 12 37 PCIeC_LR5
^FS0/USB_CLK1 13 36 PCIeT_LR4
^FS1/USB_CLK2 14 35 PCIeC_LR4
GND12_24 15 34 GNDPCIe
GND2.048 16 33 AVDDPCIe
CK2.048_0 17 32 PCIeT_LR3
CK2.048_1 18 31 PCIeC_LR3
VDD2.048 19 30 PCIeT_LR2
AVDD125 20 29 PCIeC_LR2
125M 21 28 GNDPCIe
GND125M 22 27 VDDPCIe
PCIeT_LR0 23 26 PCIeT_LR1
PCIeC_LR0 24 25 PCIeC_LR1
48-Pin TSSOP
^ Indicates Internal 100kohm pull up resistor
6V49205A
IDT6V49205A
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK
IDT®
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 3
IDT6V49205A
REV Q 112316
Pin Descriptions
PIN # PIN NAME PIN TYPE DESCRIPTION
1 X2_25 OUT Crystal output, Nominally 25.00MHz.
2 X1_25 IN Crystal input, Nominally 25.00MHz.
3 GNDREF PWR Ground pin for the REF outputs.
4 REF5 OUT Copy of crystal input
5 REF4 OUT Copy of crystal input
6 REF3 OUT Copy of crystal input
7 VDDREF PWR Ref, XTAL power supply, nominal 3.3V
8 GNDREF PWR Ground pin for the REF outputs.
9 REF2 OUT Copy of crystal input
10 REF1 OUT Copy of crystal input
11 REF0 OUT Copy of crystal input
12 AVDD12_24 PWR Power for 12_24MHz PLL core, and outputs. Nominal 3.3V
13 ^FS0/USB_CLK
1I/O Frequency select latch for Sys_CCB / 12 or 24MHz USB clock output. 3.3V. This pin has an
internal pull up resistor.
14 ^FS1/USB_CLK
2I/O Frequency select latch for Sys_CCB / 12 or 24MHz USB clock output. 3.3V. This pin has an
internal pull up resistor.
15 GND12_24 PWR Ground pin for 12_24M outputs.
16 GND2.048 PWR Ground pin for 2.048M outputs.
17 CK2.048_0 OUT 2.048M output, nominal 3.3V.
18 CK2.048_1 OUT 2.048M output, nominal 3.3V.
19 VDD2.048 PWR Power supply for 2.048M outputs, nominal 3.3V.
20 AVDD125 PWR Power for 125MHz PLL core and output, nominal 3.3V
21 125M OUT 125M output, nominal 3.3V.
22 GND125M PWR Ground pin for 125M outputs.
23 PCIeT_LR0 OUT True clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor
24 PCIeC_LR0 OUT Complement clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series
resistor
25 PCIeC_LR1 OUT Complement clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series
resistor
26 PCIeT_LR1 OUT True clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor
27 VDDPCIe PWR Power supply for PCI Express outputs, nominal 3.3V
28 GNDPCIe PWR Ground pin for the PCIe outputs.
29 PCIeC_LR2 OUT Complement clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series
resistor
30 PCIeT_LR2 OUT True clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor
31 PCIeC_LR3 OUT Complement clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series
resistor
32 PCIeT_LR3 OUT True clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor
33 AVDDPCIe PWR Analog Power supply for PCI Express clocks, nominal 3.3V
34 GNDPCIe PWR Ground pin for the PCIe outputs.
35 PCIeC_LR4 OUT Complement clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series
resistor
36 PCIeT_LR4 OUT True clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor
37 PCIeC_LR5 OUT Complement clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series
resistor
38 PCIeT_LR5 OUT True clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor
39 GNDPCIe PWR Ground pin for the PCIe outputs.
40 GNDSYS PWR Ground pin for the Sys_CCB output
41 Sys_CCB OUT System CCB clock output
42 AVDDSYS PWR Analog Power supply for Sys_CCB clock and outputs, nominal 3.3V
43 VDD66 PWR Power supply for 66.66M output(s), nominal 3.3V.
44 66M_SS OUT 66.66M spread-spectrum capable output, nominal 3.3V
45 GND66 PWR Ground pin for 66.66M output(s).
46 SCLK IN Clock pin of SMBus circuitry.
47 SDATA I/O Data pin for SMbus circuitry.
48 VDDREF PWR Ref, XTAL power supply, nominal 3.3V
IDT6V49205A
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK
IDT®
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 4
IDT6V49205A REV Q 112316
Table 1: PCIEX Spread Table (selectable via SMBUS)
Table 2: Sys_CCB and DDR Spread Table (selectable via SMBUS)
Table 3: Sys_CCB Frequency Select Table (Latched and selectable via SMBUS)
Table 4: PCI Express Amplitude Control
FS1 /
B4b3
FS0 /
B4b2
Sys_CCB (MHz)
00 66.66
0 0 100
01 80
01 83.33
SELPCIE125#_100
B6b4
B0b4 B0b3 Spread %
0 (125MHz) x x No Spread
1 (100MHz) 0 0 No Spread (default)
1 (100MHz) 0 1 Down -0.5%
1 (100MHz) 1 0 Down -0.75%
1 (100MHz) 1 1 No Spread
*Once in spread mode, do not return to non spread without reset
B0b7 B0b6 B0b5 S
p
read %
0 0 0 No Spread (default)
0 0 1 Down -0.5%
0 1 0 Down -0.75%
0 1 1 Down -0.25%
100 Reserved
101 Reserved
110 Reserved
111 Reserved
B6b7 B6b6 PCIe Amplitude
0 0 700mV
0 1 800mV
1 0 900mV
1 1 1000mV
IDT6V49205A
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK
IDT®
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 5
IDT6V49205A
REV Q 112316
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT6V49205A. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
Electrical Characteristics - Input/Supply/Common Output DC Parameters
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
Maximum Supply Voltage VDDxxx Supply Voltage 4.6 V 1
Maximum Input Voltage VIH Referenced to GND VDD + 0.5 V 1
Minimum Input Voltage VIL Referenced to GND GND - 0.5 V 1
Storage Temperature Ts - -65 150 °C
JunctionTemperature Tj - 125 °C 1
Input ESD protection ESD prot Human Body Model 2000 V 1
1 Operation under these conditions is neither implied, nor guaranteed.
NOTES on Absolute Max P ara m ete rs
IDT6V49205A
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK
IDT®
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 6
IDT6V49205A REV Q 112316
AC Electrical Characteristics - Low Power HCSL-Compatible PCIe Outputs
Electrical Characteristics - Phase Jitter, PCIe Outputs at 100MHz
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
MHz 2,3
MHz 2,3
ppmSSof f PCIe 100MHz or 125MHz ppm 1,2
ppmSSon PCIe @ -0.5% spread, 100MHz only ppm 1,2
Rising/Falling Edge Slew Rate tSLEW Differential Measurement 2.2 4.1 5.7 V/ns 1,3,6
Slew Rate Variation tSLVAR Single-ended Measurement 1 20 % 1,6
Maximum Output Voltage VHIGH Includes overshoot 793 1150 mV 6,7
Minimum Output Voltage VLOW Includes undershoot -300 -22 mV 6,7
Differential Voltage Swing VSWING Differential Measurement 300 mV 1,6
Crossing Point Voltage VXABS Single-ended Measurement 300 419 550 mV 1,4,6
Crossing Point Variation VXABSVAR Single-ended Measurement 115 140 mV 1,4,5
Duty Cycle DCYC Differential Measurement 45 50.1 55 % 1
PCIe Jitter - Cycle to Cycle PCIeJC2C Differential Measurement 36 125 ps 1
PCIe[5:0] Skew TSKEwPCIe50 Differential Measurement 1172 1500 ps 1,6,8
Spread Spectrum Modulation
Frequency fSSMOD Triangular Modulation 30 31.5 33 kHz
Notes fo r P CIe Clo c ks:
1 Guaranteed by design and characterization, not 100% tested in production.
2 Clock Frequency specifications are guaranteed assuming that REF is at 25MHz
3 Slew rate measured through V_swing voltage range centered about differential zero
4 Vcross is defined at the voltage where Clock = Clock#.
5 Only applies to the differential rising edge (Clock rising, Clock# falling.)
6 At default SMBus settings.
7 The Freescale P-series CPU's have internal terminations on their SerDes Reference Clock inputs. The resulting amplitude at these inputs will be 1/2 of the
values listed, which are well within the 800mV Freescale specification for these inputs.
8 This value includes an intentional output-to-output skew of approximately 250ps.
Synthesis error 0
+/-100
Clock Frequency f Spread off 100.00
125.00
PARAMETER SYMBOL CONDITIONS MIN TYP
MAX
INDUSTRY
SPEC LIMIT
UNITS
NOTES
t
jp
hPCIe1
PCIe Gen 1 phase jitter 35 56 86 ps 1,2,3
tjphPCIe2Lo
PCIe Gen 2 phase jitter
Lo-band content
1.6 2.4 3 ps
(RMS)
1,2,3
tjphPCIe2Hi
PCIe Gen 2 phase jitter
Hi-band content
1.9 2.8 3.1 ps
(RMS)
1,2,3
tjphPCIe3 PCIe Gen 3 phase jitter 0.5 0.83 1 ps
(RMS)
1,2,3
Notes on Phase Jitter:
2
Sample size of at least 100K cycles. This fi
g
ures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1
-12
3
Applies to PCIe outputs @ default amplitude and 100MHz with spread off or at -0.5%.
1
See http://www.pcisi
g
.com for complete specs. Guaranteed by desi
g
n and characterization, not tested in production.
Jitter, Phase
IDT6V49205A
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK
IDT®
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 7
IDT6V49205A
REV Q 112316
Electrical Characteristics - DDR Clock
Electrical Characteristics - Sys_CCB
Electrical Characteristics - 125M
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
FS(1:0) = 00, VT = OVDD/2 V MHz 2,3,6
FS(1:0) = 01, VT = OVDD/2 V MHz 2,3,6
FS(1:0) = 10, VT = OVDD/2 V MHz 2,3,6
FS(1:0) = 11, VT = OVDD/2 V MHz 2,3,6
ppmSSof f Spread off ppm 1,2,5
ppmSSon Spread on ppm 1,2,5
Output High Voltage VOH VOH at the selected operating frequency 2.4 V 1
Output Low Voltage VOL VOL at the selected operating frequency 0.4 V 1
tSLEW00 '00' = Hi-Z V/ns
tSLEW01 '01' Slow Slew Rate (Averaging on) 0.8 1.4 2.1 V/ns 1,3,8
tSLEW10 '10' Fast Slew Rate (Averaging on) 0.9 1.6 2.5 V/ns 1,3,8
tSLEW11 '11' Fastest Slew Rate (Averaging on) 1.1 1.9 3.1 V/ns 1,3,8
Duty Cycle dt1 VT = OVDD/2 V 40 51.4 60 % 1,6
Jitter, Peak period jitter tjpeak VT = OVDD/2 V, SSC < 0.75% ±116 ±150 ps 1
Phase Noise tphasenoise -56dBc 10 500 kHz 1,7
AC Input Swing Limits @ 3.3V
OVDD
ΔVAC
This is the difference between VOL and
VOH at the selected operating frequency. 1.9 V 1
Spread Spectrum Modulation
Frequency fSSMOD Triangular Modulation 0 31.5 60 kHz
Hi-Z
Slew Rate
VDDO = 3.3V
83.333
Synthesis error 0
+/-150
Clock Frequency fSys_CCB
66.666
100.00
80.00
IDT6V49205A
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK
IDT®
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 8
IDT6V49205A
REV Q 112316
Electrical Characteristics - REF(5:0)
Electrical Characteristics - USB_CLK(2:1)
Electrical Characteristics - 2.048M(1:0)
VDDO 3 3V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
MHz 2,3
MHz 2,3
Synthesis error ppm ppm 1,2,5
Output High Voltage VOH VOH at the selected operating frequency 2.2 V 1
Output Low Voltage VOL VOL at the selected operating frequency 0.4 V 1
tSLEW00 '00' = Hi-Z V/ns
tSLEW01 '01' Slow Slew Rate (Averaging on) 1.0 1.4 1.8 V/ns 1,3,4
tSLEW10 '10' Fast Slew Rate (Averaging on) 1.5 2.0 2.7 V/ns 1,3,4
tSLEW11 '11' Fastest Slew Rate (Averaging on) 1.8 2.3 3.1 V/ns 1,3,4
Duty Cycle dt1 VT = OVDD/2 V 45 50.3 55 % 1
Jitter, RMS tjRMS 12kHz to Nyquist 23 120 ps 1
Jitter, Cycle to cycle tjcyc-cyc VT = OVDD/2 V 142 350 ps 1
Slew Rate
VDDO = 3.3V
Hi-Z
24.00
0
Clock Frequency fUSB_CLK VT = OVDD/2 V 12.00
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Clock Frequency fUSB_CLK VT = OVDD/2 V MHz 2,3,6
Synthesis error ppm ppm 1,2,5
Output High Voltage VOH VOH at the selected operating frequency 2.2 V 1
Output Low Voltage VOL VOL at the selected operating frequency 0.4 V 1
tSLEW00 '00' = Hi-Z V/ns
tSLEW01 '01' Slow Slew Rate (Averaging on) 1.1 1.7 2.5 V/ns 1,3,4
tSLEW10 '10' Fast Slew Rate (Averaging on) 1.6 2.3 3.2 V/ns 1,3,4
tSLEW11 '11' Fastest Slew Rate (Averaging on) 1.8 2.6 3.6 V/ns 1,3,4
Duty Cycle dt1 VT = OVDD/2 V 45 46.7 55 % 1
Pin to Pin Skew tskew VT = OVDD/2 V 108 250 ps 1
Jitter, RMS tjRMS 12kHz to Nyquist 47 70 ps 1
Jitter, Peak period jitter tjpeak VT = OVDD/2 V ±170 ±250 ps 1
Notes for si ngle-ended clocks:
1 Guaranteed by design and characterization, not 100% tested in production.
2 Clock Frequency specifications are guaranteed assuming that REF is at 25MHz
3 At default SMBus settings
4 Measured betweeen 20% and 80% of OVDD
5 This is the frequency error with respect to the crystal frequency.
6 Measured at the rising and/or falling edge at OVDD/2 V.
7 Phase noise is calculated as the FFT of the TIE jitter.
8 Slew rate is measured from ±0.3ΔVAC at the center of peak to peak voltage at the clock input.
Hi-Z
Slew Rate
VDDO = 3.3V
2.048
0
IDT6V49205A
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK
IDT®
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 9
IDT6V49205A
REV Q 112316
General SMBus Serial Interface Information for IDT6V49205A
How to Write
•Controller (host) sends a start bit
•Controller (host) sends the write address
•IDT clock will acknowledge
•Controller (host) sends the beginning byte location = N
•IDT clock will acknowledge
•Controller (host) sends the byte count = X
•IDT clock will acknowledge
•Controller (host) starts sending Byte N through Byte
N+X-1
•IDT clock will acknowledge each byte one at a time
•Controller (host) sends a Stop bit
Note: I2C compatible. Native mode is SMBus Block mode
protocol. To use I2C Byte mode set the 2^7 bit in the
command Byte. No Byte count is used.
How to Read
•Controller (host) will send a start bit
•Controller (host) sends the write address
•IDT clock will acknowledge
•Controller (host) sends the beginning byte location = N
•IDT clock will acknowledge
•Controller (host) will send a separate start bit
•Controller (host) sends the read address
•IDT clock will acknowledge
•IDT clock will send the data byte count = X
•IDT clock sends Byte N+X-1
•IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
•Controller (host) will need to acknowledge each byte
•Controller (host) will send a not acknowledge bit
•Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address D2(H)
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
OO
OO
O
Byte N + X - 1
ACK
PstoP bit
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address D2(H)
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address D3(H)
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
OO
OO
O
Byte N + X - 1
N Not acknowledge
PstoP bit
IDT6V49205A
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK
IDT®
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 10
IDT6V49205A REV Q 112316
Byte 0 Frequency and Spread Select Register
Bit Name Description Type Default
7 SS4 RW 0
6 SS3 RW 0
5 SS2 RW 0
4 SS1 RW 0
3 SS0 RW 0
2 REF_5_EN Output enable for REF_5 RW 1
1 REF_4_EN Output enable for REF_4 RW 1
0 REF_3_EN Output enable for REF_5 RW 1
Byte 1 Output Enable Register
Bit Name Description Type Default
7 REF_2_EN Output enable for REF_2 RW 1
6 REF_1_EN Output enable for REF_1 RW 1
5 REF_0_EN Output enable for REF_0 RW 1
4 USB_CLK1_EN Output enable for USB_CLK1 RW 1
3 USB_CLK2_EN Output enable for USB_CLK2 RW 1
2 CK2.048_0_EN Output enable for CK2.048_0 RW 1
1 CK2.048_1_EN Output enable for CK2.048_1 RW 1
0 DDRCLK_EN Output enable for DDRCLK RW 1
Byte 2 Output Enable Register
Bit Name Description Type Default
7 Sys_CCB_EN Output enable for Sys_CCB RW 1
6 PCIe5_EN Output enable for PCIe5 RW 1
5 PCIe4_EN Output enable for PCIe4 RW 1
4 PCIe3_EN Output enable for PCIe3 RW 1
3 PCIe2_EN Output enable for PCIe2 RW 1
2 PCIe1_EN Output enable for PCIe1 RW 1
1 PCIe0_EN Output enable for PCIe0 RW 1
0 125M_EN Output enable for 125M RW 1
Byte 3 Slew Rate Control Register
Bit Name Description Type Default
7 USB1_SLEW1 RW 0
6 USB1_SLEW0 RW 1
5 USB2_SLEW1 RW 0
4 USB2_SLEW0 RW 1
3 CK2.048_SLEW1 RW 1
2 CK2.048_SLEW0 RW 1
1 Sys_CCB_SLEW1 RW 0
0 Sys_CCB_SLEW0 RW 1
Byte 4 Slew Rate Control Register
Bit Name Description Type Default
7 66M_Slew1 RW 0
6 66M_Slew0 RW 1
5 0
4 1
3FS1 RW Latch
2FS0 RW Latch
1 USB1_fSel USB_CLK1 Clock Frequency Select RW 0
0 USB2_fSel USB_CLK2 Clock Frequency Select RW 1
Byte 5 is Reserved
PCIE Spread Selection Table See Table 1: PCIE Spread Table
Output Disabled Output Enabled
Output Disabled Output Enabled
Output Disabled Output Enabled
01
Output Disabled Output Enabled
Output Disabled Output Enabled
Output Disabled Output Enabled
Output Disabled Output Enabled
Output Disabled Output Enabled
01
Output Disabled Output Enabled
Output Disabled Output Enabled
Output Disabled Output Enabled
01
Output Disabled Output Enabled
Output Disabled Output Enabled
Output Disabled Output Enabled
Output Disabled Output Enabled
Output Disabled Output Enabled
Output Disabled Output Enabled
Output Disabled Output Enabled
Output Disabled Output Enabled
CK2.048_0 and CK2.048_1 Slew Rate
Control See CK2.048 Electrical Tables
Sys_CCB Slew Rate Control See Sys_CCB Electrical Tables
01
01
USB_CLK1 Slew Rate Control See USB Electrical Tables
USB_CLK2 Slew Rate Control See USB Electrical Tables
66MCLK Slew Rate Control See 66M Electrical Tables
Sys_CCB Frequency Select Latch See Table 3: Sys_CCB Frequency
Selection
12MHz 24MHz
12MHz 24MHz
Reserved
Reserved
Sys_CCB and DDRCLK Spread
Selection Table
See Table 2: Sys_CCB and DDRCLK
Spread Table
IDT6V49205A
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK
IDT®
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 11
IDT6V49205A
REV Q 112316
Recommended Crystal Characteristics
Byte 6 PCI Express Amplitude Control Register
Bit Name Description Type Default
7 PCIE_AMP1 RW 0
6 PCIE_AMP0 RW 1
5 Reserved Reserved R 1
4 SELPCIE125#_100 PCI Express latch select R latch
3 Reserved Reserved RW 0
2 Reserved Reserved RW 1
1 Reserved Reserved RW 0
0 Reserved Reserved RW 1
Byte 7 Revision and Vendor ID Register
Bit Name Description Type Default
7REV ID R 0
6REV ID R 0
5REV ID R 0
4REV ID R 0
3 Vendor ID R 0
2 Vendor ID R 0
1 Vendor ID R 0
0 Vendor ID R 1
Byte 8 Byte Count Register
Bit Name Description Type Default
7BC7 RW 0
6BC6 RW 0
5BC5 RW 0
4BC4 RW 0
3BC3 RW 0
2BC2 RW 1
1BC1 RW 0
0BC0 RW 1
Revision ID
Vendor ID
--
01
--
PCI Express Amplitude Control See Table 4 PCIe Amplitude Selection
Table
--
125MHz 100MHz
--
--
1
--
--
--
--
--
--
--
01
Writing to this register will configure how
many bytes will be read back.
Byte Count Programming b(7:0)
--
0
PARAMETER VALUE UNITS NOTES
Frequency 25 MHz 1
Resonance Mode Fundamental -1
Frequency Tolerance @ 25°C
±
20 PPM Max 1
Frequency Stability, ref @ 25°C Over
Operating Temperature Range ±20 PPM Max 1
Temperature Range (commerical) 0~70 °C1
Temperature Range (industrial) -40~85 °C1
Equivalent Series Resistance (ESR) 50 Ω Max 1
Shunt Capacitance (C
O
)7pF Max1
Load Capacitance (C
L
)8pF Max1
Drive Level 0.3 mW Max 1
Aging per year ±5 PPM Max 1
IDT6V49205A
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK
IDT®
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 12
IDT6V49205A REV Q 112316
Test Loads
Thermal Characteristics (48-TSSOP) PAG48
Marking Diagrams
Notes:
1. ‘$’ is the mark code.
2. YYWW is the last two digits of the year, and the week number that the part was assembled.
3. “G” after the two-letter package code denotes Pb free package.
4. “I” denotes industrial temperature range.
5. Bottom marking: country of origin if not USA.
2pF
L inches
Differential Zo
2pF
Low-Power push-pull HCSL Output test load
(standard PCIe test load)
Rs=39
Zo
Test Load
CL=4.7pF
except
66M_SS
outputs
where
CL=15pf
Single-ended
Output
Device
Differential Test Load, Zo = 100ohm, L = 5 inches
PARAMETER SYMBOL CONDITIONS PKG TYP
VALUE UNITS NOTES
θ
JC
Junction to Case 28 °C/W 1
θ
Jb
Junction to Base 42 °C/W 1
θ
JA0
Junction to Air, still air 62 °C/W 1
θ
JA1
Junction to Air, 1 m/s air flow 54 °C/W 1
θJA3 Junction to Air, 3 m/s air flow 51 °C/W 1
PAG48Thermal Resistance
124
25
48
IDT
6V49205APAGI
YYWW$
48TSSOP
124
25
48
IDT
6V49205APAG
YYWW$
48TSSOP
IDT6V49205A
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK
IDT®
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 13
IDT6V49205A
REV Q 112316
Package Outline and Package Dimensions (PAG48, 48-pin TSSOP, 6.10 mm Body, 0.50 Pitch)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant.
For an NLG I-temp device, see the 6V49205B.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT does not authorize or warrant any IDT product for use in life support devices or
critical medical instruments.
Part / Order Number Marking Shipping Packaging Package Temperature
6V49205APAGI see page 12 Tubes 48-pin TSSOP -40to +85C
6V49205APAGI8 Tape and Reel 48-pin TSSOP -40to +85C
6V49205APAG see page 12 Tubes 48-pin TSSOP 0to +70C
6V49205APAG8 Tape and Reel 48-pin TSSOP 0to +70C
INDEX
AREA
1 2
48
D
E1 E
SEATING
PLANE
A1
A
A2
e
- C -
b
aaa C
c
L
*For reference only. Controlling dimensions in mm.
Millimeters Inches*
Symbol Min Max Min Max
A--1.20--0.047
A1 0.05 0.15 0.002 0.006
A2 0.80 1.05 0.032 0.041
b 0.17 0.27 0.007 0.011
c 0.09 0.20 0.0035 0.008
D 12.40 12.60 0.488 0.496
E 8.10 BASIC 0.319 BASIC
E1 6.00 6.20 0.236 0.244
e 0.50 Basic 0.020 Basic
L 0.45 0.75 0.018 0.030
0808
aaa -- 0.10 -- 0.004
IDT6V49205A
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK
IDT®
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK 14
IDT6V49205A REV Q 112316
Revision History
Rev. Issue Date Issuer Description Page #
L 12/12/2013 R. Wade
1. Extensive overhaul of Electrical tables to more closely align
with Freescale published specifications.
2. Updated electrical tables with characterization data.
3. Clarified SMBus registers for Slew Rate Controls
4. Moved electrical tables in front of SMBus for consistency
with other data sheets.
5. Updated Thermal Data and added test loads for clarity.
6. Updated front page text
7. Minor updates to pin names (mainly power and ground) for
consistency and clarity
Various
L 1/9/2014 J. Tajnai Table 2: Sys_CCB and DDR Spread Table; 100~111 marked as
Reserved. 4
M 2/12/2014 D. Christenberry Added 48-pin VFQFPN package, diagrams, and references Various
N 3/24/2015 RDW Updated ordering information to remove I-temp NLG package,
and to add commercial PAG and NLG packages 14
P5/11/2016 RDW
1. Correct PCIeT_LRn and PCIeC_LRn to be PCIeT_Ln and
PCIeC_Ln to indicate that the Rs for the PCIe outputs is outside
the part and to correct the pin description accordingly. The test
loads for the device are correct.
2. Update block diagram PCIe pin names to be consistent.
1-3
Q11/22/2016 RDW
1. Undo Revision P
2. PCIe outputs have integrated terminations for 100ohm
differential Zo.
3. Update Test Loads
4. Update Features/Benefits
1-3, 12
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registered trademarks used to identify products or services of their respective owners.
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IDT6V49205A
FREESCALE P10XX AND P20XX SYSTEM CLOCK W/66.66M DDR CLOCK