Semiconductor
MSC2343657D-xxBS10/DS10
4,194,304-word x 36-b it DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO
This version: Mar. 8. 1999
DESCRIPTION
The MSC2343657D-xxBS10/DS10 is a fully decoded, 4,194,304-word x 36-bit CMOS dynamic random access
m emory modul e composed of ei ght 16Mb DRAMs (4Mx 4) in SOJ packages and two 8Mb DRAMs (4Mx2) in SOJ
packages mounted with ten decoupling capacitors on a 72-pin glass epoxy single in-line package. This module
supports any application where hi gh densi ty and large capacit y of stor age memory ar e r equired.
FEATURES
· 4, 194,304-word x 36- bit or ganization
· 72-pin Singl e In-Line Memory M odule
MSC2343657D-xxBS 10 : Gold tab
MSC2343657D-xxDS10 : Solder tab
· Single +5V suppl y ± 10% tol er anc e
· I nput : T TL compatible
· Output : TTL compatible, 3-state
· Refresh : 2048cycles/32m s
· / CA S before /RA S r efresh, hi dden r efresh, /RA S only r efr esh capability
· F ast page mode with EDO c apability
· Mult i-bit test m ode c apability
PRODUCT FAMILY
Access Time (Max.) Power Dissipat i on
Family tRAC tAA tCAC
Cycle
Time
(Min.) Operating (Max.) Standby (Max.)
MSC2343657D-60BS10/DS10 60ns 30ns 15ns 110ns 5720mW
MSC2343657D-70BS10/DS10 70ns 35ns 20ns 130ns 5225mW 55mW
Semiconductor MSC2343657D
MODULE OUTLINE
1
72
R1.57
6.35
1.04Typ.
1.27±0.1
95.25
2.03Typ.
6.35Typ.
Typ.
6.35
Typ.
10.16
φ3.18
25.4±0.2
101.19Typ.
107.95±0.2
*1
3.38Typ.
3.17Min.
5.28Max.
+0.1
-0.08
1.27
(Un i t : m m)
MSC2343657D-xxBS10/DS10
*1 The common size difference of the board width 12.5mm of its height is specified as ±0.2.
The value above 12.5mm is specified as ±0.5.
Semiconductor MSC2343657D
PIN CONFIG URATION
Pin No. Pin Na me Pin No. Pin Na me Pin No. Pin Na me Pin No. Pin Na me
1V
SS 19 A10 37DQ1755DQ12
2 DQ0 20 DQ4 38 DQ35 56 DQ30
3 DQ18 21 DQ22 39 VSS 57 DQ13
4 DQ1 22 DQ5 40 /CAS0 58 DQ31
5 DQ19 23 DQ23 41 /CAS2 59 VCC
6 DQ2 24 DQ6 42 /CAS3 60 DQ32
7 DQ20 25 DQ24 43 /CAS1 61 DQ14
8 DQ3 26 DQ7 44 /RAS0 62 DQ33
9 DQ21 27 DQ25 45 NC 63 DQ15
10 VCC 28 A7 46 NC 64 DQ34
11 NC 29 NC 47 /WE 65 DQ16
12 A0 30 VCC 48 NC 66 NC
13 A1 31 A8 49 DQ9 67 PD1
14 A2 32 A9 50 DQ27 68 PD2
15 A3 33 NC 51 DQ10 69 PD3
16 A4 34 /RAS2 52 DQ28 70 PD4
17 A5 35 DQ26 53 DQ11 71 NC
18 A6 36 DQ8 54 DQ29 72 VSS
Presence Det ect P ins
Pin No. Pin Na me MSC2343657D
-60BS10/DS10 MSC2343657D
-70BS10/DS10
67 PD1 VSS VSS
68 PD2 NC NC
69 PD3 NC VSS
70 PD4 NC NC
Semiconductor MSC2343657D
BLOCK DIAGRAM
/WE
/CAS0
/RAS0
A0-A10
/CAS1
DQ0
A0-A10
DQ
DQ
DQ
DQ
/OE
V
CC
/RAS
/CAS
/WE
V
SS
DQ1
DQ2
DQ3
DQ8
A0-A10
DQ1
DQ2
/OE
V
CC
/RAS
/CAS1
/WE
V
SS
DQ17
/CAS2
V
CC
V
SS
C1-C10
A0-A10
DQ
DQ
DQ
DQ
/OE
V
CC
/RAS
/CAS
/WE
V
SS
DQ4
DQ5
DQ6
DQ7
A0-A10
DQ
DQ
DQ
DQ
/OE
V
CC
/RAS
/CAS
/WE
V
SS
DQ9
DQ10
DQ11
DQ12
A0-A10
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
DQ13
DQ14
DQ15
DQ16
DQ18
A0-A10
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
DQ19
DQ20
DQ21
V
CC
V
SS
V
CC
V
SS
DQ22
A0-A10
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
DQ23
DQ24
DQ25
V
CC
V
SS
DQ26
A0-A10
DQ1
DQ2
/OE
V
CC
/RAS
/CAS1
/WE
V
SS
DQ35
/CAS2
DQ27
A0-A10
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
DQ28
DQ29
DQ30
V
CC
V
SS
DQ31
A0-A10
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
DQ32
DQ33
DQ34
V
CC
V
SS
/CAS2
/RAS2
/CAS3
Semiconductor MSC2343657D
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Volt age on Any Pin Relati ve to VSS VIN, VOUT -0.5 to +7.0 V
Volt age on VCC Supply Relat ive to VSS VCC -0.5 to +7.0 V
Short Ci r cuit O ut put Cur r ent IOS 50 mA
Power Dissipation PD *10W
Operating Temperature TOPR 0 to +70 °C
Storage Temperature TSTG - 40 to +125 °C
* Ta = 25°C
Recommen ded Operating Conditions ( Ta = 0°C to +70°C )
Parameter Symbol Min. Typ. Max. Unit
VCC 4.5 5.0 5.5 V
Power Suppl y Voltage VSS 000V
Input High Volt age VIH 2.4 - VCC + 0.5 V
Input Low Vol t age VIL -0.5 - 0.8 V
Capacitance ( VCC = 5V ± 10%, Ta = 25°C, f = 1 MHz )
Parameter Symbol Typ. Max. Unit
Input Capacitance (A0 - A10) CIN1 -70pF
Input Capaci t ance (/WE) CIN2 -80pF
Input Capaci t ance (/RAS0, /RAS2) CIN3 -43pF
Input Capaci t ance (/CAS0- /CAS3) CIN4 -28pF
I/O Capacitance (DQ0 - DQ35) CDQ -16pF
Semiconductor MSC2343657D
DC CHARACT ERIST ICS (VCC = 5V ± 10%, Ta = 0°C to +70°C )
MSC2343657D
-60BS10/DS10 MSC2343657D
-70BS10/DS10
Parameter Symbol Condition
Min. Max. Min. Max.
Unit Note
Input Leakage Current ILI
0V ≤ VIN ≤ 6.5V;
All ot her pins not
under test = 0V -100 100 -100 100 µA
Out put Leakage Current ILO DQ disable
0V ≤ VOUT ≤ 5.5V -10 10 -10 10 µA
Out put Hi gh Voltage VOH IOH = -5.0mA 2.4 VCC 2.4 VCC V
Out put Low Vol t age VOL IOL = 4.2mA 0 0.4 0 0.4 V
Average Power
Supply Current
(Operating) ICC1 /RAS, /CAS c y cli n g,
tRC = Min. - 1040 - 950 m A 1, 2
/RAS, /CAS = VIH -20-20mA1
Power suppl y cur r ent
(Standby) ICC2 /RAS, /CAS
≥ VCC -0.2V -10-10mA1
Average Power
Supply Current
(/RAS only r efresh) ICC3
/RAS cy c li ng ,
/CAS = VIH,
tRC = Min. - 1040 - 950 m A 1, 2
Average Power
Supply Current
(/CAS before /RAS refresh) ICC6 /RAS cy c lin g ,
/CAS before /RAS - 1040 - 950 mA 1, 2
Average Power
Supply Current
(Fast Page Mode) ICC7
/RAS = VIL,
/CAS cy c li ng ,
tHPC = Min. - 920 - 830 mA 1, 3
Notes: 1. ICC Max. is specified as ICC for output open c ondition.
2. Address can be changed once or less whil e /RAS = VIL.
3. Address can be changed once or less whil e /CAS = VIH.
Semiconductor MSC2343657D
AC CHARACTERISTICS (1/2) (VCC = 5V ± 10%, Ta = 0°C to +70°C ) Not e: 1, 2, 3, 10, 11
MSC2343657D
-60BS10/DS10 MSC2343657D
-70BS10/DS10
Parameter Symbol
Min. Max. Min. Max.
Unit Note
Random Read or Wr ite Cycle Time tRC 110 - 130 - ns
Fast Page Mode Cycle Tim e t HPC 25 - 30 - ns
Access Time from /RAS tRAC - 60 - 70 ns 4, 5, 6
Access Time from /CAS tCAC - 15 - 20 ns 4, 5
Access Time from Column Address tAA - 30 - 35 ns 4, 6
Access Time from / CAS Precharge tCPA - 35 - 40 ns 4
Out put Low Impedance Tim e from / CAS t CLZ 0-0-ns4
Data Output Hold After /CAS Low tDOH 5-5-ns
/CAS to Data Output Buffer Turn-off Delay Ti me tCEZ 0 15 0 15 ns 7, 8
/RAS to Data Output Buffer Turn-off Delay Ti me tREZ 0 15 0 15 ns 7, 8
/WE to Data Output Buffer Turn-off Delay Time tWEZ 0 15 0 15 ns 7
Transi tion Time tT2 50 2 50 ns 3
Refr esh Per iod tREF -32-32ms
/RAS Pr echarge Time tRP 40 - 50 - ns
/RAS Pulse Widt h tRAS 60 10K 70 10K ns
/RAS Pulse Widt h ( Fast Page Mode wit h EDO) tRASP 60 100K 70 100K ns
/RAS Hold Time tRSH 15 - 20 - ns
/CAS Precharge Time (Fast Page Mode wit h EDO) tCP 10 - 10 - ns
/CAS Pulse Widt h tCAS 10 10K 13 10K ns
/CAS Hold Time tCSH 40 - 45 - ns
/CAS t o /RAS Prechar g e Time tCRP 10 - 10 - ns
/RAS Hold Tim e from /CAS Precharge tRHCP 35 - 40 - ns
/RAS to /CAS Delay Time tRCD 20 45 20 50 ns 5
/RAS to Column Address Delay Time tRAD 15 30 15 35 ns 6
Row Address Set-up Tim e tASR 0-0-ns
Row Address Hold Time tRAH 10 - 13 - ns
Column Address Set-up Tim e tASC 0-0-ns
Col u mn Ad d r ess Hold Time tCAH 10 - 15 - ns
Column Address to /RAS Lead Time tRAL 30 - 35 - ns
Read Com mand Set-up Tim e tRCS 0-0-ns
Read Com mand Hol d Time tRCH 0-0-ns9
Read Com mand Hol d Time referenced to /RAS tRRH 0-0-ns9
Semiconductor MSC2343657D
AC Characteristics (2/ 2) (VCC = 5V ± 10%, Ta = 0°C to +70°C ) Not e: 1, 2, 3, 10, 11
MSC2343657D
-60BS10/DS10 MSC2343657D
-70BS10/DS10
Parameter Symbol
Min. Max. Min. Max.
Unit Note
W r ite Command Set-up Tim e tWCS 0-0-ns
W r ite Command Hold Time tWCH 10 - 15 - ns
W r ite Command Pul se Wi dt h t WP 10 - 10 - ns
/WE Pulse Widt h ( DQ Di sable) tWPE 10 - 10 - ns
W r ite Command t o / RAS Lead Ti me tRWL 15 - 20 - ns
W r ite Command t o / CAS Lead Ti me tCWL 15 - 20 - ns
Data-i n Set-up Time tDS 0-0-ns
Dat a-i n Hold Time tDH 15 - 15 - ns
/CAS Active Delay Tim e from /RAS Precharge tRPC 10 - 10 - ns
/RAS to /CAS Set-up Tim e
(/ CAS b efore /RAS) tCSR 10 - 10 - ns
/RAS to /CAS Hold Time
(/ CAS b efore /RAS) tCHR 20 - 20 - ns
/WE to /RAS Precharge Time
(/ CAS b efore /RAS) tWRP 10 - 10 - ns
/WE Hold Time from /RAS
(/ CAS b efore /RAS) tWRH 10 - 10 - ns
/RAS to /W E Set-up Tim e
(Test Mode) tWTS 10 - 10 - ns
/RAS to /W E Hold Tim e
(Test Mode) tWTH 20 - 20 - ns
Semiconductor MSC2343657D
Notes: 1. A start- up delay of 200µs is required after power-up, followed by a minimum of eight ini tiali z ation cycles
(/RA S only r efr esh or / CA S before /RA S r efresh) before proper device operat ion is achieved.
2. The AC c har ac teristic s assumes tT = 5ns.
3. VIH(Min. ) and VIL(Max .) are ref erence lev els f or m easuring i nput ti mi ng si gnals. Transit ion ti me (tT) are
m easured bet ween VIH and VIL.
4. This param eter i s measured wi th a l oad c ircuit equivalent to 2TTL loads and 100pF.
5. Operati on within the tRCD(M ax.) l imi t ensures that tRAC(Max . ) can be met.
tRCD(Max.) is specified as a reference point only . If tRCD is greater than the specified tRCD(Max.) limit, then
the acc ess ti me is controlled by tCAC.
6. Operati on within the tRAD(Max. ) lim it ensures that t RAC(Max . ) can be met.
tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then
the acc ess ti me is controlled by tAA.
7. tCEZ(Max.), tREZ(Max.) and tWEZ(Max.) define the time at which the output achieves the open circuit
condi ti on and ar e not referenc ed to output voltage levels.
8. tCEZ and tREZ must be satisfied for open circuit c ondition.
9. tRCH or tRRH must be satisfied for a read cycle.
10. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet
is an 8-bi t parall el test f unction. CA0, CA1 and CA10 are not used. In a read cycle, if all internal bi ts are
equal, the DQ pin will in dic at e a hig h level. If a ny inte rn a l bits a re n ot equal, the DQ pin w ill ind ica te a lo w
level. The test mode is cleared and the memory device returned to its normal operating state by a /RAS
only refresh or /CAS bef ore /RAS ref resh cycle.
11. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the s pecified value.
These parameters should be specified in test mode cycle by adding the abov e value to the specified
value i n thi s data sheet.
