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FEATURES
3
2
4
61
A C
Y
GND
B
DBV PACKAGE
(TOP VIEW) YEP OR YZP PACKAGE
(BOTTOM VIEW)
DCK PACKAGE
(TOP VIEW)
3
2
4
61
A C
Y
GND
B
A
B
C
Y
GND
See mechanical drawings for dimensions.
1
4
2
3
6
VCC
VCC 5VCC
5
5
DESCRIPTION/ORDERING INFORMATION
SN74LVC1G3208SINGLE 3-INPUT POSITIVE OR-AND GATE
SCES605A – SEPTEMBER 2004 – REVISED JUNE 2005
•Can Be Used in Three Combinations:•Available in the Texas Instruments – OR-AND GateNanoStar™ and NanoFree™ Packages
– OR Gate•Supports 5-V V
CC
Operation
– AND Gate•Inputs Accept Voltages to 5.5 V
•I
off
Supports Partial-Power-Down Mode•Max t
pd
of 5 ns at 3.3 V Operation•Low Power Consumption, 10- µA Max I
CC
•Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II• ± 24-mA Output Drive at 3.3 V
•ESD Protection Exceeds JESD 22•Input Hysteresis Allows Slow Input Transitionand Better Switching Noise Immunity at the – 2000-V Human-Body Model (A114-A)Input
– 200-V Machine Model (A115-A)(V
hys
= 250 mV Typ @ 3.3 V)
– 1000-V Charged-Device Model (C101)
This device is designed for 1.65-V to 5.5-V V
CC
operation.
The SN74LVC1G3208 is a single 3-input positive OR-AND gate. It performs the Boolean function Y = (A + B) ⋅Cin positive logic.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(2)
NanoStar™ – WCSP (DSBGA)
SN74LVC1G3208YEPR0.23-mm Large Bump – YEP
Reel of 3000 _ _ _ DD _NanoFree™ – WCSP (DSBGA)0.23-mm Large Bump – YZP SN74LVC1G3208YZPR(Pb-free)–40 °C to 85 °C
Reel of 3000 SN74LVC1G3208DBVRSOT (SOT-23) – DBV CDD_Reel of 250 SN74LVC1G3208DBVT
Reel of 3000 SN74LVC1G3208DCKRSOT (SC-70) – DCK DD_Reel of 250 SN74LVC1G3208DCKT
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one followingcharacter to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ⋅= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
1
3
4
A
B
Y
6
C
1
2
3
6
5
4YB
VCC
BY
CC1
2
3
6
5
4Y
A
VCC
AY
CC
SN74LVC1G3208
SINGLE 3-INPUT POSITIVE OR-AND GATE
SCES605A – SEPTEMBER 2004 – REVISED JUNE 2005
By tying one input to GND or V
CC
, the SN74LVC1G3208 offers two more functions. When C is tied to V
CC
, thisdevice performs as a 2-input OR gate (Y = A + B). When A is tied to GND, the device works as a 2-input ANDgate (Y = B ⋅C). This device also works as a 2-input AND gate when B is tied to GND (Y = A ⋅C).
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using thedie as the package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
(1)
INPUTS
OUTPUT
YABC
H X H HX H H HX X L LL L H L
(1) X = Valid H or L
LOGIC DIAGRAM (POSITIVE LOGIC)
FUNCTION SELECTION TABLE
LOGIC FUNCTION FIGURE
2-Input AND Gate 12-Input OR Gate 2Y = (A + B) ⋅C 3
LOGIC CONFIGURATIONS
Figure 1. 2-Input AND Gate
2
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AY
B1
2
3
6
5
4
A
Y
VCC
B
Y
C
1
2
3
6
5
4
C
A
VCC
Y
A
B
B
Absolute Maximum Ratings
(1)
SN74LVC1G3208SINGLE 3-INPUT POSITIVE OR-AND GATE
SCES605A – SEPTEMBER 2004 – REVISED JUNE 2005
Figure 2. 2-Input OR Gate
Figure 3. Y = (A + B) ⋅C
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 6.5 VV
I
Input voltage range
(2)
–0.5 6.5 VV
O
Voltage range applied to any output in the high-impedance or power-off state
(2)
–0.5 6.5 VV
O
Voltage range applied to any output in the high or low state
(2) (3)
–0.5 V
CC
+ 0.5 VI
IK
Input clamp current V
I
< 0 –50 mAI
OK
Output clamp current V
O
< 0 –50 mAI
O
Continuous output current ±50 mAContinuous current through V
CC
or GND ±100 mADBV package 165θ
JA
Package thermal impedance
(4)
DCK package 259 °C/WYEP/YZP package 123T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) The value of VCC is provided in the recommended operating conditions table.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
3
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Recommended Operating Conditions
(1)
SN74LVC1G3208
SINGLE 3-INPUT POSITIVE OR-AND GATE
SCES605A – SEPTEMBER 2004 – REVISED JUNE 2005
MIN MAX UNIT
Operating 1.65 5.5V
CC
Supply voltage VData retention only 1.5V
CC
= 1.65 V to 1.95 V 0.65 × V
CC
V
CC
= 2.3 V to 2.7 V 1.7V
IH
High-level input voltage VV
CC
= 3 V to 3.6 V 2V
CC
= 4.5 V to 5.5 V 0.7 × V
CC
V
CC
= 1.65 V to 1.95 V 0.35 × V
CC
V
CC
= 2.3 V to 2.7 V 0.7V
IL
Low-level input voltage VV
CC
= 3 V to 3.6 V 0.8V
CC
= 4.5 V to 5.5 V 0.3 × V
CC
V
I
Input voltage 0 5.5 VV
O
Output voltage 0 V
CC
VV
CC
= 1.65 V –4V
CC
= 2.3 V –8I
OH
High-level output current V
CC
= 3 V –16 mA–24V
CC
= 4.5 V –32V
CC
= 1.65 V 4V
CC
= 2.3 V 8I
OL
Low-level output current V
CC
= 3 V 16 mA24V
CC
= 4.5 V 32V
CC
= 1.8 V ±0.15 V, 2.5 V ±0.2 V 20∆t/ ∆v Input transition rise or fall rate V
CC
= 3.3 V ±0.3 V 10 ns/VV
CC
= 5 V ±0.5 V 5T
A
Operating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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Electrical Characteristics
Switching Characteristics
Switching Characteristics
Operating Characteristics
SN74LVC1G3208SINGLE 3-INPUT POSITIVE OR-AND GATE
SCES605A – SEPTEMBER 2004 – REVISED JUNE 2005
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
I
OH
= –100 µA 1.65 V to 5.5 V V
CC
– 0.1I
OH
= –4 mA 1.65 V 1.2I
OH
= –8 mA 2.3 V 1.9V
OH
VI
OH
= –16 mA 2.43 VI
OH
= –24 mA 2.3I
OH
= –32 mA 4.5 V 3.8I
OL
= 100 µA 1.65 V to 5.5 V 0.1I
OL
= 4 mA 1.65 V 0.45I
OL
= 8 mA 2.3 V 0.3V
OL
VI
OL
= 16 mA 0.43 VI
OL
= 24 mA 0.55I
OL
= 32 mA 4.5 V 0.55A, B, orI
I
V
I
= 5.5 V or GND 0 to 5.5 V ±5 µAC inputsI
off
V
I
or V
O
= 5.5 V 0 ±10 µAI
CC
V
I
= 5.5 V or GND I
O
= 0 1.65 V to 5.5 V 10 µA∆I
CC
One input at V
CC
– 0.6 V, Other inputs at V
CC
or GND 3 V to 5.5 V 500 µAC
i
V
I
= V
CC
or GND 3.3 V 3.5 pF
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25°C.
over recommended operating free-air temperature range, C
L
= 15 pF (unless otherwise noted) (see Figure 4 )
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 V V
CC
= 5 VFROM TO
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
t
pd
A, B, or C Y 3.7 14 2.5 7 1.7 5 1.3 3.4 ns
over recommended operating free-air temperature range, C
L
= 30 pF or 50 pF (unless otherwise noted) (see Figure 5 )
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 V V
CC
= 5 VFROM TO
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
t
pd
A, B, or C Y 2.5 17.5 1.8 7.6 1.8 5.9 1.3 4 ns
T
A
= 25°C
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 V V
CC
= 5 VTESTPARAMETER UNITCONDITIONS
TYP TYP TYP TYP
C
pd
Power dissipation capacitance f = 10 MHz 15 15 16 17 pF
5
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PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1 VLOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WA VEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V∆
VOH − V∆≈0 V
VI
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
1 MΩ
1 MΩ
1 MΩ
1 MΩ
VCC RL
2 × VCC
2 × VCC
6 V
2 × VCC
VLOAD CL
15 pF
15 pF
15 pF
15 pF
0.15 V
0.15 V
0.3 V
0.3 V
V∆
VCC
VCC
3 V
VCC
VI
VCC/2
VCC/2
1.5 V
VCC/2
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
SN74LVC1G3208
SINGLE 3-INPUT POSITIVE OR-AND GATE
SCES605A – SEPTEMBER 2004 – REVISED JUNE 2005
Figure 4. Load Circuit and Voltage Waveforms
6
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PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1 VLOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WA VEFORMS
SETUP AND HOLD TIMES
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WA VEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V∆
VOH − V∆≈0 V
VI
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
1 kΩ
500 Ω
500 Ω
500 Ω
VCC RL
2 × VCC
2 × VCC
6 V
2 × VCC
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V∆
VCC
VCC
3 V
VCC
VI
VCC/2
VCC/2
1.5 V
VCC/2
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
SN74LVC1G3208SINGLE 3-INPUT POSITIVE OR-AND GATE
SCES605A – SEPTEMBER 2004 – REVISED JUNE 2005
Figure 5. Load Circuit and Voltage Waveforms
7
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC1G3208DBVR SOT-23 DBV 6 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G3208DBVR SOT-23 DBV 6 3000 178.0 9.2 3.3 3.2 1.55 4.0 8.0 Q3
SN74LVC1G3208DBVT SOT-23 DBV 6 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G3208DBVT SOT-23 DBV 6 250 178.0 9.2 3.3 3.2 1.55 4.0 8.0 Q3
SN74LVC1G3208DCKR SC70 DCK 6 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G3208DCKR SC70 DCK 6 3000 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3
SN74LVC1G3208DCKT SC70 DCK 6 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G3208YZPR DSBGA YZP 6 3000 180.0 8.4 1.02 1.52 0.63 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G3208DBVR SOT-23 DBV 6 3000 202.0 201.0 28.0
SN74LVC1G3208DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0
SN74LVC1G3208DBVT SOT-23 DBV 6 250 202.0 201.0 28.0
SN74LVC1G3208DBVT SOT-23 DBV 6 250 180.0 180.0 18.0
SN74LVC1G3208DCKR SC70 DCK 6 3000 180.0 180.0 18.0
SN74LVC1G3208DCKR SC70 DCK 6 3000 205.0 200.0 33.0
SN74LVC1G3208DCKT SC70 DCK 6 250 180.0 180.0 18.0
SN74LVC1G3208YZPR DSBGA YZP 6 3000 220.0 220.0 34.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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