TDA8377A/N2 - Philips Semiconductors / NXP Semiconductors

DATA SH EET

Preliminary speciﬁcation

File under Integrated Circuits, IC02 1997 Jul 01

INTEGRATED CIRCUITS

TDA837x family

I2C-bus controlled economy

PAL/NTSC and NTSC

TV-processors

1997 Jul 01 2

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

FEATURES

Available in all ICs:

•Vision IF amplifier with high sensitivity and good figures

for differential phase and gain

•PLL demodulator for the IF signal

•Alignment-free sound demodulator

•Flexible source selection with a CVBS input for the

internal signal and Y/C or CVBS input for the external

signal

•Audio switch

•The output signal of the CVBS (Y/C) switch is externally

available

•Integrated chrominance trap and band-pass filters

(auto-calibrated)

•Luminance delay line integrated

•A symmetrical peaking circuit in the luminance channel

•Black stretching of non-standard CVBS or luminance

signals

•RGB control circuit with black current stabilization and

white point adjustment

•Linear RGB inputs and fast blanking

•Horizontal synchronization with two control loops and

alignment-free horizontal oscillator

•Slow start and slow stop of the horizontal drive pulses

•Vertical count-down circuit

•Vertical driver optimized for DC-coupled vertical output

stages

•I2C-bus control of various functions

•Low dissipation

•Small amount of peripheral components compared with

competition ICs.

GENERAL DESCRIPTION

The various versions of the TDA837x series are I2C-bus

controlled single-chip TV processors which are intended to

be applied in PAL/NTSC (TDA8374 and TDA8375) and

NTSC (TDA8373 and TDA8377) television receivers.

All ICs are available in an SDIP56 package and some

versions are also available in a QFP64 package. The ICs

are pin compatible so that with one application board

NTSC and PAL/NTSC (or multistandard together with the

SECAM decoder TDA8395) receivers can be built.

Functionally this IC series is split in to 2 categories:

•Versions intended to be used in economy TV receivers

with all basic functions

•Versions with additional functions such as E-W

geometry control, horizontal and vertical zoom function

and YUV interface which are intended for TV receivers

with 110° picture tubes.

The various type numbers are given in Table 1.

The detailed differences between the various ICs are

given in Table 2.

Table 1 TV receiver versions

TV RECEIVERS SDIP56 PACKAGE QFP64 PACKAGE

ECONOMY MID/HIGH END ECONOMY MID/HIGH END

PAL only TDA8374B −TDA8374BH −

PAL/NTSC (SECAM) TDA8374 and TDA8374A TDA8375 and TDA8375A TDA8374AH TDA8375AH

NTSC TDA8373 TDA8377 and TDA8377A −−

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I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

Table 2 Differences between the various ICs

QUICK REFERENCE DATA

CIRCUITS IC VERSION (TDA)

8373 8374 8374A(H) 8374B(H) 8375 8375A(H) 8377 8377A

Multistandard IF −X−−XX −−

Automatic Volume Levelling

(AVL) XX − −−− −−

PAL decoder −X X XXX −−

SECAM interface −X X XXX −−

NTSC decoder X X X X X X X X

Colour matrix PAL/NTSC (Japan) −X X XXX −−

Colour matrix NTSC (USA/Japan) X − − −−−XX

YUV interface −− − −XX XX

Horizontal geometry −− − −XX XX

Horizontal and vertical zoom −− − −XX XX

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VPsupply voltage −8.0 −V

IPsupply current −110 −mA

Input voltages

V48,49(rms) video IF ampliﬁers sensitivity

(RMS value) −70 −µV

1(rms) sound IF ampliﬁers sensitivity

(RMS value) −1.0 −mV

V2(rms) external audio input voltage

(RMS value) −500 −mV

V11(p-p) external CVBS/Y input voltage

(peak-to-peak value) −1.0 −V

V10(p-p) external chrominance input voltage

(burst amplitude) (peak-to-peak value) −0.3 −V

V23-25(p-p) RGB input voltage

(peak-to-peak value) −0.7 −V

Output signals

V6(p-p) IF video output voltage

(peak-to-peak value) −2.5 −V

I54 tuner AGC output current range 0 −5mA

oVSW output signal level of video switch

(peak-to-peak value) −1.0 −V

V30(p-p) −(R −Y) output voltage

(peak-to-peak value) −525 −mV

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I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

ORDERING INFORMATION

V29(p-p) −(B −Y) output voltage

(peak-to-peak value) −675 −mV

V28(p-p) luminance output voltage

(peak-to-peak value) −1.4 −V

V19-21(p-p) RGB output signal amplitudes

(peak-to-peak value) −2.0 −V

I40 horizontal output current −10 −mA

I46,47(p-p) vertical output current

(peak-to-peak value) −1−mA

I45(peak) E-W output current (peak value) TDA8375A,

TDA8377A,

TDA8375 and

TDA8377

−1.2 −mA

TYPE

NUMBER PACKAGE

NAME DESCRIPTION VERSION

TDA837xA SDIP56 plastic shrink dual in-line package; 56 leads (600 mil) SOT400-1

TDA837xH QFP64 plastic quad ﬂat package; 64 leads (lead length 1.95 mm);

body 14 ×20 ×2.7 mm; high stand-off height SOT319-1

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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and NTSC TV-processors TDA837x family

BLOCK DIAGRAM

ok, full pagewidth

MGK286

RGB MATRIX

RGB INPUT

AND SWITCH

G - Y MATRIX

AND

SAT CONTROL

NTSC

DECODER

RGB CONTROL

AND

OUTPUT

DELAY

AND

PEAKING

BLACK

STRETCHER

VERTICAL

SYNC

SEPARATOR

TRAP BLACK

CURRENT

STABILIZER

VERTICAL

GEOMETRY

HORIZONTAL/

VERTICAL

DIVIDER

SYNC

SEPARATOR

AND 1st LOOP

VCO

AND

CONTROL

2nd LOOP AND

HORIZONTAL

OUTPUT

CONTROL DACs

1 × 8 BITS

14 × 6 BITS

1 × 4 BITS

2331

322930

43 14 44 12 37

REF

8753 9 42 4154

3436336161110381713 39

3.6

MHz

white

point BRI

TDA8373

SAT

REF

B−Y

R−Y

HUE

CONTR

24 25 26

FILTER

TUNING

BAND-PASS

MUTE

VOL SW

CVBS Y/C

SWITCH

PRE-AMPLIFIER

AND MUTE

MUTE

IDENT

ADJ tuner

take-over

point

+8 V

AFC

VIDEO

AMPLIFIER

AND MUTE

VIDEO

IDENTIFICATION

AGC FOR IF

AND TUNER I2C-BUS

TRANSCEIVER

VIF AMPLIFIER

AND PLL

DEMODULATOR

VCO

ADJUSTMENT

CVBS

SWITCH

A VL AND

SWITCH AND

VOLUME CONTROL

AFC

PLL

DEMODULATOR

SOUND

TRAP

SOUND

BAND-PASS

LIMITER

Fig.1 Block diagram of bus-controlled economy NTSC TV-processor TDA8373.

The TDA8373 is only supplied in an SDIP package.

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and NTSC TV-processors TDA837x family

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MGK287

RGB MATRIX

RGB INPUT

AND SWITCH

G - Y MATRIX

AND

SAT CONTROL

PAL/NTSC

DECODER

RGB CONTROL

AND

OUTPUT

DELAY

AND

PEAKING

BLACK

STRETCHER

VERTICAL

SYNC

SEPARATOR

TRAP BLACK

CURRENT

STABILIZER

VERTICAL

GEOMETRY

HORIZONTAL/

VERTICAL

DIVIDER

SYNC

SEPARATOR

AND 1st LOOP

VCO

AND

CONTROL

2nd LOOP AND

HORIZONTAL

OUTPUT

CONTROL DACs

1 × 8 BITS

14 × 6 BITS

1 × 4 BITS

322930

43 14 44 12 37

REF

53 9 42 41

(51)

36336161110381713 39

3.6

MHz

white

point BRI

TDA8374

SAT

REF

B−Y

R−Y

HUE

CONTR

24 25 26

4.4

MHz

FILTER

TUNING

BAND-PASS

MUTE

VOL SW

CVBS Y/C

SWITCH

PRE-AMPLIFIER

AND MUTE

MUTE

IDENT

ADJ tuner

take-over

point

POL

+8 V

AFC

POL

VIDEO

AMPLIFIER

AND MUTE

VIDEO

IDENTIFICATION

AGC FOR IF

AND TUNER I2C-BUS

TRANSCEIVER

VIF AMPLIFIER

AND PLL

DEMODULATOR

VCO

ADJUSTMENT

CVBS

SWITCH

A VL AND

SWITCH AND

VOLUME CONTROL

AFC

PLL

DEMODULATOR

SOUND

TRAP TDA4665

SOUND

BAND-PASS

LIMITER

Fig.2 Block diagram of bus-controlled economy PAL/NTSC TV processor TDA8374.

For most pins the QFP64 pinning is not indicated.

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I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

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MGK288

RGB MATRIX

RGB INPUT

AND SWITCH

G - Y MATRIX

AND

SAT CONTROL

PAL/NTSC

DECODER

RGB CONTROL

AND

OUTPUT

DELAY PLUS

PEAKING PLUS

CORING

BLACK

STRETCHER

VERTICAL

SYNC

SEPARATOR

TRAP BLACK

CURRENT

STABILIZER

VERTICAL

GEOMETRY

HORIZONTAL/

VERTICAL

DIVIDER

SYNC

SEPARATOR

AND 1st LOOP

VCO

AND

CONTROL

2nd LOOP AND

HORIZONTAL

OUTPUT

CONTROL DACs

1 × 8 BITS

18 × 6 BITS

1 × 4 BITS

(35)

(47)

31 (40)

28 (39)

(48)

(45)

(46)

(59) 14

(25,26) 44

(60,61) 12

(22,23) 37

(53)

REF

(18)

(17)

(6) 9

(19) 42

(58) 41

(57) 40

(56)

(7)

(50)

(51)

(52)

(49)

(16)

6(28)

(21)

(20)

(54)

(29)

(24)

13 (55)

3.6

MHz

(33) 21

(30) 18

(5) 52

(4) 51

(34) 22

(32) 20

(63) 46

(3) 50

E-W

GEOMETRY (62) 45

(64) 47

(31) 19

white

point BRI

TDA8375

SAT

REF

B−Y

R−Y

HUE

CONTR

(36)

24 (37)

25 (38)

4.4

MHz

FILTER

TUNING

BAND-PASS

56 (9)

1 (10)

55 (8)

2 (11)

15 (27)

49 (2)

5 (15)

MUTE

VOL SW

CVBS Y/C

SWITCH

PRE-AMPLIFIER

AND MUTE

MUTE

IDENT

ADJ tuner

take-over

point

POL

+8 V

AFC

POL

VIDEO

AMPLIFIER

AND MUTE

VIDEO

IDENTIFICATION

AGC FOR IF

AND TUNER I2C-BUS

TRANSCEIVER

48 (1)

4 (14)

3 (13)

VIF AMPLIFIER

AND PLL

DEMODULATOR

VCO

ADJUSTMENT

CVBS

SWITCH

SWITCH AND

VOLUME CONTROL

AFC

PLL

DEMODULATOR

SOUND

TRAP TDA4665

SOUND

BAND-PASS

LIMITER

Fig.3 Block diagram of bus-controlled economy PAL/NTSC TV processor TDA8375.

1997 Jul 01 8

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I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

ull pagewidth

MGK289

RGB MATRIX

RGB INPUT

AND SWITCH

G - Y MATRIX

AND

SAT CONTROL

NTSC

DECODER

RGB CONTROL

AND

OUTPUT

DELAY PLUS

PEAKING PLUS

CORING

BLACK

STRETCHER

VERTICAL

SYNC

SEPARATOR

TRAP BLACK

CURRENT

STABILIZER

VERTICAL

GEOMETRY

HORIZONTAL/

VERTICAL

DIVIDER

SYNC

SEPARATOR

AND 1st LOOP

VCO

AND

CONTROL

2nd LOOP AND

HORIZONTAL

OUTPUT

CONTROL DACs

1 × 8 BITS

18 × 6 BITS

1 × 4 BITS

31 28 27

322930

43 14 44 12 37

REF

53 9 42 41 40

3436336161110381713 39

3.6

MHz

E-W

GEOMETRY 45

white

point BRI

TDA8377

SAT

REF

B−Y

R−Y

HUE

CONTR

24 25 26

FILTER

TUNING

BAND-PASS

MUTE

VOL SW

CVBS Y/C

SWITCH

PRE-AMPLIFIER

AND MUTE

MUTE

IDENT

ADJ tuner

take-over

point

+8 V

AFC

VIDEO

AMPLIFIER

AND MUTE

VIDEO

IDENTIFICATION

AGC FOR IF

AND TUNER I2C-BUS

TRANSCEIVER

VIF AMPLIFIER

AND PLL

DEMODULATOR

VCO

ADJUSTMENT

CVBS

SWITCH

SWITCH AND

VOLUME CONTROL

AFC

PLL

DEMODULATOR

SOUND

TRAP

SOUND

BAND-PASS

LIMITER

Fig.4 Block diagram of bus-controlled economy NTSC TV processor TDA8377.

The TDA8377 is only supplied in an SDIP package.

1997 Jul 01 9

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

PINNING

SYMBOL PIN DESCRIPTION

SDIP56 QFP64

SIF 1 10 sound IF input

AUDI 2 11 external audio input

VCO1 3 13 IF VCO 1 tuned circuit

VCO2 4 14 IF VCO 2 tuned circuit

PLL 5 15 PLL loop ﬁlter

IFVO 6 16 IF video output

SCL 7 17 serial clock input (I2C-bus)

SDA 8 18 serial data input/output (I2C-bus)

DECBG 9 19 band gap decoupling

CHROMA 10 20 chrominance input

CVBS/Y 11 21 CVBS/Y input

VP1 12 22 and 23 main supply voltage (+8 V)

CVBSint 13 24 internal CVBS input

GND1 14 25 and 26 ground

AUDO 15 27 audio output

DECFT 16 28 decoupling ﬁlter tuning

CVBSext 17 29 external CVBS input

BLKIN 18 30 black current input

BO 19 31 blue output

GO 20 32 green output

RO 21 33 red output

BCLIN 22 34 beam current input

RI 23 35 red input

GI 24 36 green input

BI 25 37 blue input

RGBIN 26 38 RGB insertion input

YIN 27(2) 39 luminance input

YOUT 28 40 luminance output

BYO 29 45 (B −Y) output

RYO 30 46 (R −Y) output

RYI 31 47 (R −Y) input

BYI 32 48 (B −Y) input

SECref 33(1) 49 SECAM reference output

XTAL1 34 50 3.58 MHz crystal connection

XTAL2 35(1) 51 4.43 MHz crystal connection

LFBP 36 52 loop ﬁlter burst phase detector

VP2 37 53 horizontal oscillator supply voltage (+8 V)

CVBSO 38 54 CVBS output

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I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

Notes

1. In the TDA8373 and TDA8377 pin 35 (4.43 MHz crystal) is internally connected and pin 33 is just a subcarrier output

which can be used as a reference signal for comb filter ICs.

2. In the TDA8373 and TDA8374 the following pins are different (SDIP56): Pin 27: not connected; Pin 45: AVL

capacitor.

BLPH 39 55 black peak hold capacitor

HOUT 40 56 horizontal drive output

FBI/SCO 41 57 ﬂyback input and sandcastle output

PH2 42 58 phase 2 ﬁlter/protection

PH1 43 59 phase 1 ﬁlter

GND2 44 60 and 61 ground 2

EWD 45(2) 62 east-west drive output

VDOB 46 63 vertical drive output B

VDOA 47 64 vertical drive output A

IFIN1 48 1 IF input 1

IFIN2 49 2 IF input 2

EHT/PRO 50 3 EHT/overvoltage protection input

VSAW 51 4 vertical sawtooth capacitor

Iref 52 5 reference current input

DECAGC 53 6 AGC decoupling capacitor

AGCOUT 54 7 tuner AGC output

AUDEEM 55 8 audio deemphasis

DEC 56 9 decoupling sound demodulator

i.c. −12 internally connected

i.c. −41 internally connected

i.c. −42 internally connected

i.c. −43 internally connected

i.c. −44 internally connected

SYMBOL PIN DESCRIPTION

SDIP56 QFP64

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I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

Fig.5 Pin configuration (SDIP56).

handbook, halfpage

TDA837x

MGK284

SIF

AUDI

VCO1

VCO2

PLL

IFVO

SCL

SDA

DECBG

CHROMA

CVBS/Y

VP1

CVBSint

GND1

AUDO

DECFT

CVBSext

BLKIN

BCLIN

RGBIN

YIN

YOUT

DEC

AUDEEM

AGCOUT

DECAGC

Iref

VSAW

EHT/PRO

IFIN2

IFIN1

VDOA

VDOB

EWD

GND2

PH1

PH2

FBI/SCO

HOUT

BLPH

CVBSO

VP2

LFBP

XTAL2

XTAL1

SECref

BYI

RYI

RYO

BYO

1997 Jul 01 12

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I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

Fig.6 Pin configuration (QFP64).

handbook, full pagewidth

TDA837xH

MGK285

BYI

RYI

RYO

BYO

i.c.

YOUT

YIN

RGBIN

BCLIN

IFIN1

IFIN2

EHT/PRO

VSAW

Iref

DECAGC

AGCOUT

AUDEEM

DEC

SIF

AUDI

i.c.

VCO1

VCO2

PLL

IFVO 33

VDOA

VDOB

EWD

GND2

PH1

PH2

FBI/SCO

HOUT

BLPH

CVBSO

VP2

LFBP

XTAL2

XTAL1

SECref

SCL

SDA

DECBG

CHROMA

CVBS/Y

VP1

CVBSint

GND1

AUDO

DECFT

CVBSext

BLKIN

GO 49

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

FUNCTIONAL DESCRIPTION

Vision IF ampliﬁer

The IF amplifier contains 3 AC-coupled control stages with

a total gain control range which is higher than 66 dB.

The sensitivity of the circuit is comparable with that of

modern IF-ICs.

The video signal is demodulated by a PLL carrier

regenerator. This circuit contains a frequency detector and

a phase detector. During acquisition the frequency

detector will tune the VCO to the correct frequency.

The initial adjustment of the oscillator is realized via the

I2C-bus.

The switching, between SECAM L and L’, can also be

realized via the I2C-bus. After lock-in the phase detector

controls the VCO so that a stable phase relationship

between the VCO and the input signal is achieved.

The VCO operates at twice the IF frequency.

The reference signal for the demodulator is obtained by

using a frequency divider circuit.

The AFC output is obtained by using the VCO control

voltage of the PLL and can be read via the I2C-bus.

For fast search tuning systems the window of the AFC can

be increased by a factor of 3. The setting is realized with

the AFW bit.

Depending on the device type the AGC detector operates

on top-sync level (single standard versions) or on top-sync

and top-white level (multistandard versions).

The demodulation polarity is switched via the I2C-bus.

The AGC detector time constant capacitor is connected

externally. This is mainly because of the flexibility of the

application. The time constant of the AGC system during

positive modulation is rather long, this is to avoid visible

variations of the signal amplitude. To improve the speed of

the AGC system, a circuit has been included which detects

whether the AGC detector is activated every frame period.

When, during 3 frame periods, no action is detected the

speed of the system is increased. For signals without

peak-white information the system switches automatically

to a gated black level AGC. Because a black level clamp

pulse is required for this method of operation the circuit will

only switch to black level AGC in the internal mode.

The circuits contain a second fast video identification

circuit which is independent of the synchronization

identification circuit. Consequently, search tuning is also

possible when the display section of the receiver is used

as a monitor. However, this identification circuit cannot be

made as sensitive as the slower sync identification circuit

(SL) and it is recommended to use both identification

outputs to obtain a reliable search system.

The identification output is applied to the tuning system via

the I2C-bus.

The input of the identification circuit is connected to pin 13,

the internal CVBS input (see Fig.1). This has the

advantage that the identification circuit can also be made

operative when a scrambled signal is received

[descrambler connected between the IF video output

(pin 6) and pin 13]. A second advantage is that the

identification circuit can be used when the IF amplifier is

not used (e.g. with built-in satellite tuners).

The video identification circuit can also be used to identify

the selected CBVS or Y/C signal. The switching between

the two modes can be realized with bit VIM.

Video switches

The circuit has two CVBS inputs (CVBSint and CVBSext)

and a Y/C input. When the Y/C input is not required pin 11

can be used as the third CVBS input. The switch

configuration is illustrated in Fig.7. The selection of the

various sources is made via the I2C-bus.

The output signal of the CVBS switch is externally

available and can be used to drive the teletext decoder, the

SECAM add-on decoder and a comb filter.

In applications with comb filters a Y/C input is only possible

when additional switches are added. In applications

without comb filters the Y/C input signal can be switched

to the CVBS output.

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I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

Fig.7 Configuration CVBS switch and interfacing of video identification.

handbook, full pagewidth

MGK301

VIDEO

IDENTIFICATION

VIM

IDENT

TDA837x

CVBSint

S0 S5 S1

CVBSext

S1 S6 S2

CVBS/Y

S3 S7 S4

CHROMA CVBSO

10 38

to luminance/

sync processing

to chrominance

processing

Sound circuit

The sound band-pass and trap filters have to be

connected externally. The filtered intercarrier signal is fed

to a limiter circuit and is demodulated by a PLL

demodulator. This PLL circuit automatically tunes to the

incoming carrier signal, hence no adjustment is required.

The volume is controlled via the I2C-bus. The de-emphasis

capacitor has to be connected externally.

The non-controlled audio signal can be obtained from this

pin (pin 55) (via a buffer stage).

The FM demodulator can be muted via the I2C-bus. This

function can be used to switch-off the sound during a

channel change so that high output peaks are prevented

(also on the de-emphasis output).

The TDA8373 and TDA8374 contain an Automatic Volume

Levelling (AVL) circuit which automatically stabilizes the

audio output signal to a certain level which can be set by

the user via the volume control. This function prevents big

audio output fluctuations due to variations of the

modulation depth of the transmitter. The AVL function can

be activated via the I2C-bus.

Synchronization circuit

The sync separator is preceded by a controlled amplifier

which adjusts the sync pulse amplitude to a fixed level.

These pulses are fed to the slicing stage which operates at

50% of the amplitude.

The separated sync pulses are fed to the first phase

detector and to the coincidence detector. The coincidence

detector is used to detect whether the line oscillator is

synchronized and can also be used for transmitter

identification. The circuit can be made less sensitive by

using the STM bit. This mode can be used during search

tuning to ensure that the tuning system will not stop at very

weak input signals. The first PLL has a very high static

steepness so that the phase of the picture is independent

of the line frequency.

The line oscillator operates at twice the line frequency.

The oscillator capacitor is internal. Because of the spread

of internal components an automatic calibration circuit has

been added to the IC. The circuit compares the oscillator

frequency with that of the crystal oscillator in the colour

decoder.

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

This results in a free-running frequency which deviates

less than 2% from the typical value. When the IC is

switched on the horizontal output signal is suppressed and

the oscillator is calibrated as soon as all subaddress bytes

have been sent. When the frequency of the oscillator is

correct the horizontal drive signal is switched on. To obtain

a smooth switching on and switching off behaviour of the

horizontal output stage the horizontal output frequency is

doubled during switch-on and switch-off (slow start/stop).

During that time the duty cycle of the output pulse has such

a value that maximum safety is obtained for the output

stage.

To protect the horizontal output transistor, the horizontal

drive is immediately switched off (via the slow stop

procedure) when a power-on reset is detected. The drive

signal is switched on again when the normal switch-on

procedure is followed, i.e. all subaddress bytes must be

sent and, after calibration, the horizontal drive signal will

be released again via the slow start procedure.

When the coincidence detector indicates an out-of-lock

situation the calibration procedure is repeated.

The circuit has a second control loop to generate the drive

pulses for the horizontal driver stage. The horizontal

output is gated with the flyback pulse so that the horizontal

output transistor cannot be switched on during the flyback

time.

Adjustments can be made to the horizontal shift, vertical

shift, vertical slope, vertical amplitude and the S-correction

via the I2C-bus. In the TDA8375A, TDA8377A, TDA8375

and TDA8377 the E-W drive can also be adjusted via the

I2C-bus. The TDA8375 and TDA8377 have a flexible zoom

adjustment possibility for the vertical and horizontal

deflection. When the horizontal scan is reduced to display

4 : 3 pictures on a 16 : 9 picture tube an accurate video

blanking can be switched on to obtain well defined edges

on the screen. The geometry processor has a differential

output for the vertical drive signal and a single-ended

output for the E-W drive (TDA8375A, TDA8377A,

TDA8375 and TDA8377). Overvoltage conditions (X-ray

protection) can be detected via the EHT tracking pin.

When an overvoltage condition is detected the horizontal

output drive signal will be switched off via the slow stop

procedure. However, it is also possible that the drive is not

switched off and that just a protection indication is given in

the I2C-bus output byte. The choice is made via the input

bit PRD. The ICs have a second protection input on the

phase-2 filter capacitor pin. When this input is activated the

drive signal is switched off immediately (without slow stop)

and switched on again via the slow start procedure.

For this reason this protection input can be used as ‘flash

protection’.

The drive pulses for the vertical sawtooth generator are

obtained from a vertical countdown circuit. This countdown

circuit has various windows depending on the incoming

signal (50 or 60 Hz and standard or non-standard).

The countdown circuit can be forced in various modes via

the I2C-bus. To obtain short switching times of the

countdown circuit during a channel change the divider can

be forced in the search window using the NCIN bit.

The vertical deflection can be set in the de-interlace mode

via the I2C-bus.

To avoid damage of the picture tube when the vertical

deflection fails, the guard output current of the TDA8350

and TDA8351 can be supplied to the beam current limiting

input. When a failure is detected the RGB outputs are

blanked and a bit is set (NDF) in the status byte of the

I2C-bus. When no vertical deflection output stage is

connected this guard circuit will also blank the output

signals. This can be overruled using the EVG bit.

Chrominance and luminance processing

The circuit contains a chrominance band-pass and trap

circuit. The filters are realized by using gyrator circuits.

They are automatically calibrated by comparing the tuning

frequency with the crystal frequency of the decoder.

The luminance delay line and the delay for the peaking

circuit are also realized by using gyrator circuits.

The centre frequency of the chrominance band-pass filter

is 10% higher than the subcarrier frequency. This

compensates for the high frequency attenuation of the IF

saw filter. During SECAM reception the centre frequency

of the chrominance trap is reduced to obtain a better

suppression of the SECAM carrier frequencies. All ICs

have a black stretcher circuit which corrects the black level

for incoming video signals which have a deviation between

the black level and the blanking level (back porch).

The TDA8375A, TDA8377A, TDA8375 and TDA8377

have a defeatable coring function in the peaking circuit.

Some of the ICs have a YUV interface so that picture

improvement ICs such as the TDA9170 (contrast

improvement), TDA9177 (sharpness improvement) and

TDA4556 and TDA4566 (CTI) can be applied. When the

TDA4556 or TDA4566 is applied it is possible to increase

the gain of the luminance channel by using the GAI bit in

subaddress 03 so that the resulting RGB output signals

will not be affected.

1997 Jul 01 16

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

Colour decoder

Depending on the IC type the colour decoder can decode

NTSC signals (TDA8373 and TDA8377) or PAL/NTSC

signals (TDA8374 and TDA8375). The circuit contains an

alignment-free crystal oscillator, a killer circuit and two

colour difference demodulators. The 90° phase shift for the

reference signal is made internally.

The TDA8373 and TDA8377 contain an Automatic Colour

Limiting (ACL) circuit which prevents over saturation

occurring when signals with a high chroma-to-burst ratio

are received. This ACL function is also available in the

TDA8374 and TDA8375, however, it is only active during

the reception of NTSC signals.

The TDA8373 and TDA8377 have a switchable colour

difference matrix (via the I2C-bus) so that the colour

reproduction can be adapted to the market requirements.

In the TDA8374 and TDA8375 the colour difference matrix

switches automatically between PAL and NTSC, however,

it is also possible to fix the matrix in the PAL standard.

The TDA8374 and TDA8375 can operate in conjunction

with the SECAM decoder TDA8395 so that an automatic

multistandard decoder can be realized. The subcarrier

reference output for the SECAM decoder can also be used

as a reference signal for a comb filter. Consequently, the

reference signal is continuously available when PAL or

NTSC signals are detected and only present during the

vertical retrace period when a SECAM signal is detected.

Which standard the TDA8374 and TDA8375 can decode

depends on the external crystals. The crystal to be

connected to pin 34 must have a frequency of 3.5 MHz

(NTSC-M, PAL-M or PAL-N). Pin 35 can handle crystals

with a frequency of 4.4 and 3.5 MHz. Because the crystal

frequency is used to tune the line oscillator, the value of

the crystal frequency must be communicated to the IC via

the I2C-bus. It is also possible to use the IC in the so called

‘3-norma’ mode for South America. In that event one

crystal must be connected to pin 35 and the other two to

pin 34. Switching between the 2 latter crystals must be

performed externally. Consequently, the search loop of the

decoder must be controlled by the microcontroller.

To prevent calibration problems of the horizontal oscillator

the external switching between the two crystals should be

performed when the oscillator is forced to pin 35.

For a reliable calibration of the horizontal oscillator it is

very important that the crystal indication bits (XA and XB)

are not corrupted. For this reason the crystal bits can be

read in the output bytes so that the software can check the

I2C-bus transmission.

RGB output circuit and black current stabilization

The colour difference signals are matrixed with the

luminance signal to obtain the RGB signals. Linear

amplifiers have been chosen for the RGB inputs so that the

circuit is suited for signals that are input from the SCART

connector. The insertion blanking can be switched on or off

using the IE1 bit. To ascertain whether the insertion pin

has a (continuous) HIGH level or not can be read via the

IN1 bit. The contrast and brightness control operate on

internal and external signals.

The output signal has an amplitude of approximately 2 V

(black-to-white) at nominal input signals and nominal

settings of the controls. To increase the flexibility of the IC

it is possible to add OSD and/or teletext signals directly at

the RGB outputs. This insertion mode is controlled via the

insertion input. The action to switch the RGB outputs to

black has some delay which must be compensated for

externally.

The black current stabilization is realized by using a

feedback from the video output amplifiers to the RGB

control circuit. The black current of the 3 guns of the

picture tube is internally measured and stabilized.

The black level control is active during 4 lines at the end of

the vertical blanking. The vertical blanking is adapted to

the incoming CVBS signal (50 or 60 Hz). When the flyback

time of the vertical output stage is longer than the 60 Hz

blanking time, or when additional lines need to be blanked

(e.g. for close captioning lines) the blanking can be

increased to the same value as that of the 50 Hz blanking.

This can be set using the LBM bit. The leakage current is

measured during the first line and, during the following

3 lines, the 3 guns are adjusted to the required level.

The maximum acceptable leakage current is ±100 µA.

The nominal value of the black current is 10 µA. The ratio

of the currents for the various guns automatically tracks

with the white point adjustment so that the background

colour is the same as the adjusted white point.

1997 Jul 01 17

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

The input impedance of the black current measuring pin is

14 kΩ. To prevent the voltage on this pin exceeding the

supply voltage during scan an internal protection diode

has been included.

When the TV receiver is switched on the black current

stabilization circuit is not active, the RGB outputs are

blanked and the beam current limiting input pin is

short-circuited. Only during the measuring lines will the

outputs supply a voltage of 4.2 V to the video output stage

to ascertain whether the picture tube is warming up. As

soon as the current supplied to the measuring input

exceeds a value of 190 µA the stabilization circuit will be

activated. After a waiting time of approximately 0.8 s the

blanking and beam current limiting input pins are released.

The remaining switch-on behaviour of the picture is

determined by the external time constant of the beam

current limiting network.

I2C-bus speciﬁcation

Table 3 Slave address (8A)

A6 A5 A4 A3 A2 A1 A0 R/W

1000101I/O

The slave address is identical for all types. The

subaddresses of the various types are slightly different.

The list of subaddresses for each type is given in

Tables 4, 6, 8 and 10.

START-UP PROCEDURE

Read the status bytes until POR = 0 and send all

subaddress bytes. The horizontal output signal is switched

on when the oscillator is calibrated. Each time before the

data in the IC is refreshed, the status bytes must be read.

If POR = 1, then the procedure given above must be

carried out to restart the IC. When this procedure is not

followed the horizontal frequency in the TDA8374 and

TDA8375 may be incorrect after power-up or a power dip.

1997 Jul 01 18

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

TDA8373

Valid subaddresses: 00 to 16 (subaddresses 04 to 07 are not used), subaddress FE is reserved for test purposes.

Auto-increment mode available for subaddresses.

Table 4 Inputs

Table 5 Output status bytes (note 1)

Note

1. X = don’t care.

FUNCTION SUB

ADDRESS DATA BYTE

D7 D6 D5 D4 D3 D2 D1 D0

Control 0 00 INA INB INC 0 FOA FOB 0 0

Control 1 01 0 0 DL STB POC 0 1 1

Hue 02 AVL AKB A5 A4 A3 A2 A1 A0

Horizontal Shift (HS) 03 VIM GAI A5 A4 A3 A2 A1 A0

Vertical Slope (VS) 08 NCIN STM A5 A4 A3 A2 A1 A0

Vertical Amplitude (VA) 09 VID LBM A5 A4 A3 A2 A1 A0

S-Correction (SC) 0A 0 EVG A5 A4 A3 A2 A1 A0

Vertical shift (VSH) 0B SBL PRD A5 A4 A3 A2 A1 A0

White point R 0C 0 0 A5 A4 A3 A2 A1 A0

White point G 0D 0 0 A5 A4 A3 A2 A1 A0

White point B 0E MAT 0 A5 A4 A3 A2 A1 A0

Peaking 0F 0000A3A2A1A0

Brightness 10 RBL 0 A5 A4 A3 A2 A1 A0

Saturation 11 IE1 0 A5 A4 A3 A2 A1 A0

Contrast 12 AFW IFS A5 A4 A3 A2 A1 A0

AGC takeover 13 0 VSW A5 A4 A3 A2 A1 A0

Volume control 14 SM FAV A5 A4 A3 A2 A1 A0

Adjustment IF-PLL 15 L’FA A6 A5 A4 A3 A2 A1 A0

Spare 16 00000000

OUTPUT ADDRESS D7 D6 D5 D4 D3 D2 D1 D0

00 POR X X SL XPR CD2 CD1 CD0

01 NDF IN1 X IFI AFA AFB SXA SXB

02 X X X IVW X ID2 ID1 ID0

1997 Jul 01 19

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

TDA8374, TDA8374AH and TDA8374BH

Valid subaddresses: 00 to 16 (subaddresses 04 to 07 are not used), subaddress FE is reserved for test purposes.

Auto-increment mode available for subaddresses.

Table 6 Inputs (notes 1 and 2)

Notes

1. The AVL and MOD bit are not available in the TDA8374A.

2. In the TDA8374B the AVL and MOD bit is also missing and the CM0 to CM2 and CD0 to CD2 bits have less

possibilities because this IC can only decode PAL or PAL/SECAM signals (when the TDA8395 is applied).

Table 7 Output status bytes (note 1)

Note

1. X = don’t care.

FUNCTION SUB

ADDRESS DATA BYTE

D7 D6 D5 D4 D3 D2 D1 D0

Control 0 00 INA INB INC 0 FOA FOB XA XB

Control 1 01 FORF FORS DL STB POC CM2 CM1 CM0

Hue 02 AVL AKB A5 A4 A3 A2 A1 A0

Horizontal Shift (HS) 03 VIM GAI A5 A4 A3 A2 A1 A0

Vertical Slope (VS) 08 NCIN STM A5 A4 A3 A2 A1 A0

Vertical Amplitude (VA) 09 VID LBM A5 A4 A3 A2 A1 A0

S-Correction (SC) 0A 0 EVG A5 A4 A3 A2 A1 A0

Vertical shift (VSH) 0B SBL PRD A5 A4 A3 A2 A1 A0

White point R 0C 0 0 A5 A4 A3 A2 A1 A0

White point G 0D 0 0 A5 A4 A3 A2 A1 A0

White point B 0E MAT 0 A5 A4 A3 A2 A1 A0

Peaking 0F 0000A3A2A1A0

Brightness 10 RBL 0 A5 A4 A3 A2 A1 A0

Saturation 11 IE1 0 A5 A4 A3 A2 A1 A0

Contrast 12 AFW IFS A5 A4 A3 A2 A1 A0

AGC takeover 13 MOD VSW A5 A4 A3 A2 A1 A0

Volume control 14 SM FAV A5 A4 A3 A2 A1 A0

Adjustment IF-PLL 15 L’FA A6 A5 A4 A3 A2 A1 A0

Spare 16 00000000

OUTPUT ADDRESS D7 D6 D5 D4 D3 D2 D1 D0

00 POR FSI X SL XPR CD2 CD1 CD0

01 NDF IN1 X IFI AFA AFB SXA SXB

02 X X X IVW X ID2 ID1 ID0

1997 Jul 01 20

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

TDA8375 and TDA8375AH

Valid subaddresses: 00 to 16, subaddress FE is reserved for test purposes. Auto-increment mode available for

subaddresses.

Table 8 Inputs

Note

1. The vertical zoom byte and the HBL bit are active only in the TDA8375.

Table 9 Output status bytes (note 1)

Note

1. X = don’t care.

FUNCTION SUB

ADDRESS DATA BYTE

D7 D6 D5 D4 D3 D2 D1 D0

Control 0 00 INA INB INC 0 FOA FOB XA XB

Control 1 01 FORF FORS DL STB POC CM2 CM1 CM0

Hue 02 HBL AKB A5 A4 A3 A2 A1 A0

Horizontal Shift (HS) 03 VIM GAI A5 A4 A3 A2 A1 A0

E-W width (EW) 04 0 0 A5 A4 A3 A2 A1 A0

E-W Parabola/Width (PW) 05 0 0 A5 A4 A3 A2 A1 A0

E-W Corner Parabola (CP) 06 0 0 A5 A4 A3 A2 A1 A0

E-W trapezium (TC) 07 0 0 A5 A4 A3 A2 A1 A0

Vertical Slope (VS) 08 NCIN STM A5 A4 A3 A2 A1 A0

Vertical Amplitude (VA) 09 VID LBM A5 A4 A3 A2 A1 A0

S-Correction (SC) 0A HCO EVG A5 A4 A3 A2 A1 A0

Vertical shift (VSH) 0B SBL PRD A5 A4 A3 A2 A1 A0

White point R 0C 0 0 A5 A4 A3 A2 A1 A0

White point G 0D 0 0 A5 A4 A3 A2 A1 A0

White point B 0E MAT 0 A5 A4 A3 A2 A1 A0

Peaking 0F 0000A3A2A1A0

Brightness 10 RBL COR A5 A4 A3 A2 A1 A0

Saturation 11 IE1 0 A5 A4 A3 A2 A1 A0

Contrast 12 AFW IFS A5 A4 A3 A2 A1 A0

AGC takeover 13 MOD VSW A5 A4 A3 A2 A1 A0

Volume control 14 SM FAV A5 A4 A3 A2 A1 A0

Adjustment IF-PLL 15 L’FA A6 A5 A4 A3 A2 A1 A0

Vertical zoom (VX)(1) 16 0 0 A5 A4 A3 A2 A1 A0

OUTPUT ADDRESS D7 D6 D5 D4 D3 D2 D1 D0

00 POR FSI X SL XPR CD2 CD1 CD0

01 NDF IN1 X IFI AFA AFB SXA SXB

02 X X X IVW X ID2 ID1 ID0

1997 Jul 01 21

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

TDA8377 and TDA8377A

Valid subaddresses: 00 to 16, subaddress FE is reserved for test purposes. Auto-increment mode available for

subaddresses.

Table 10 Inputs

Note

1. The vertical zoom byte and the HBL bit are active only in the TDA8377.

Table 11 Output status bytes (note 1)

Note

1. X = don’t care.

FUNCTION SUB

ADDRESS DATA BYTE

D7 D6 D5 D4 D3 D2 D1 D0

Control 0 00 INA INB INC 0 FOA FOB 0 1

Control 1 01 0 0 DL STB POC 0 1 1

Hue 02 HBL AKB A5 A4 A3 A2 A1 A0

Horizontal Shift (HS) 03 VIM GAI A5 A4 A3 A2 A1 A0

E-W width (EW) 04 0 0 A5 A4 A3 A2 A1 A0

E-W Parabola/Width (PW) 05 0 0 A5 A4 A3 A2 A1 A0

E-W Corner Parabola (CP) 06 0 0 A5 A4 A3 A2 A1 A0

E-W trapezium (TC) 07 0 0 A5 A4 A3 A2 A1 A0

Vertical Slope (VS) 08 NCIN STM A5 A4 A3 A2 A1 A0

Vertical Amplitude (VA) 09 VID 0 A5 A4 A3 A2 A1 A0

S-Correction (SC) 0A HCO EVG A5 A4 A3 A2 A1 A0

Vertical shift (VSH) 0B SBL PRD A5 A4 A3 A2 A1 A0

White point R 0C 0 0 A5 A4 A3 A2 A1 A0

White point G 0D 0 0 A5 A4 A3 A2 A1 A0

White point B 0E MAT 0 A5 A4 A3 A2 A1 A0

Peaking 0F 0000A3A2A1A0

Brightness 10 RBL COR A5 A4 A3 A2 A1 A0

Saturation 11 IE1 0 A5 A4 A3 A2 A1 A0

Contrast 12 AFW IFS A5 A4 A3 A2 A1 A0

AGC takeover 13 0 VSW A5 A4 A3 A2 A1 A0

Volume control 14 SM FAV A5 A4 A3 A2 A1 A0

Adjustment IF-PLL 15 L’FA A6 A5 A4 A3 A2 A1 A0

Vertical zoom (VX)(1) 16 0 0 A5 A4 A3 A2 A1 A0

OUTPUT ADDRESS D7 D6 D5 D4 D3 D2 D1 D0

00 POR X X SL XPR CD2 CD1 CD0

01 NDF IN1 X IFI AFA AFB SXA SXB

02 X X X IVW X ID2 ID1 ID0

1997 Jul 01 22

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

INPUT CONTROL BITS

Table 12 Source select

Table 13 Phase 1 (ϕ-1) time constant

Table 14 Crystal indication

Table 15 Forced ﬁeld frequency TDA8374 and TDA8375

Note

1. When switched to this mode while locked to a 50 Hz signal, the divider will only switch to forced 60 Hz when an

out-of-sync is detected in the horizontal PLL.

INA INB INC SELECTED SIGNALS

(DECODER AND AUDIO) SWITCH OUTPUT

0 0 0 internal CVBS plus audio internal CVBS

0 0 1 external CVBS plus audio external CVBS

0 1 0 Y/C plus external audio Y/C (Y plus C)

0 1 1 CVBS3 plus external audio CVBS3

1 0 0 Y/C plus internal audio internal CVBS

1 1 0 Y/C plus external audio external CVBS

FOA FOB MODE

0 0 normal

0 1 slow and gated

1 0 slow/fast and gated

1 1 fast

XA XB CRYSTAL

0 0 two 3.6 MHz crystals

0 1 one 3.6 MHz crystal (pin 34)

1 0 one 4.4 MHz crystal (pin 35)

1 1 3.6 MHz and 4.4 MHz crystals (pins 34 and 35)

FORF FORS FIELD FREQUENCY

0 0 auto (60 Hz when line not synchronized)

0 1 60 Hz; note 1

1 0 keep last detected ﬁeld frequency

1 1 auto (50 Hz when line not synchronized)

1997 Jul 01 23

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

Table 16 Interlace

Table 17 Standby

Table 18 Synchronization mode

Table 19 Colour decoder mode

Table 20 Automatic volume levelling

(TDA8373 and TDA8374)

Table 21 RGB blanking mode (TDA8375 and TDA8377)

DL STATUS

0 interlace

1 de-interlace

STB MODE

0 standby

1 normal

POC MODE

0 synchronization active

1 synchronization not active

CM2 CM1 CM0 DECODER MODE

0 0 0 not forced, own intelligence, two

crystals

0 0 1 forced crystal pin 34

(PAL/NTSC)

0 1 0 forced crystal pin 34 (PAL)

0 1 1 forced crystal pin 34 (NTSC)

1 0 0 forced crystal pin 35

(PAL/NTSC)

1 0 1 forced crystal pin 35 (PAL)

1 1 0 forced crystal pin 35 (NTSC)

1 1 1 forced SECAM crystal pin 35

AVL LEVEL

0 automatic volume levelling not active

1 automatic volume levelling active

HBL MODE

0 normal blanking with horizontal blanking

pulse

1 wider blanking to obtain well deﬁned edges

Table 22 Black current stabilization

Table 23 Video identiﬁcation mode

Table 24 Gain of luminance channel

Table 25 Vertical divider mode

Table 26 Search tuning mode

Table 27 Video identiﬁcation mode

Table 28 Long blanking mode (TDA8374 and TDA8375)

AKB STABILIZATION

0 black-current stabilization on

1 black-current stabilization off

VIM VIDEO IDENT MODE

0 video identiﬁcation coupled to the internal

CVBS input (pin 13)

1 video identiﬁcation coupled to the selected

CVBS input

GAI GAIN

0 normal gain of luminance channel

[V27 = 1.0 V (b-w)]

1 high gain of luminance channel

[V27 = 0.45 V (p-p)]

NCIN VERTICAL DIVIDER MODE

0 normal operation of the vertical divider

1 vertical divider switched to search window

STM SEARCH TUNING MODE

0 normal operation

1 reduced sensitivity of the coincidence

detector (bit SL)

VID VIDEO IDENT MODE

0 video identiﬁcation switches phase 1 loop on

and off

1 video identiﬁcation not active

LBM BLANKING MODE

0 blanking adapted to standard (50 or 60 Hz)

1 ﬁxed blanking in accordance with 50 Hz

standard

1997 Jul 01 24

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

Table 29 EHT tracking mode (TDA8375 and TDA8377)

Table 30 Enable vertical guard (RGB blanking)

Table 31 Service blanking

Table 32 Overvoltage input mode

Table 33 PAL/NTSC or NTSC matrix

(TDA8374 and TDA8375)

Table 34 PAL/NTSC or NTSC matrix

(TDA8373 and TDA8377)

Table 35 RGB blanking

HCO TRACKING MODE

0 EHT tracking only on vertical

1 EHT tracking on vertical and E-W

EVG VERTICAL GUARD MODE

0 vertical guard not active

1 vertical guard active

SBL SERVICE BLANKING MODE

0 service blanking off

1 service blanking on

PRD OVERVOLTAGE MODE

0 overvoltage detection mode

1 overvoltage protection mode

MAT MATRIX

0 matrix adapted to standard

(NTSC = Japanese)

1 PAL matrix

MAT MATRIX

0 Japanese matrix

1 USA matrix

RBL MODE

0 blanking not active

1 blanking active

Table 36 Noise coring peaking

(TDA8375 and TDA8377))

Table 37 Enable fast blanking

Table 38 AFC window

Table 39 IF sensitivity

Table 40 Modulation standard (TDA8374 and TDA8375)

Table 41 Video mute

Table 42 Sound mute

COR MODE

0 noise coring off

1 noise coring on

IE1 FAST BLANKING

0 fast blanking not active

1 fast blanking active

AFW AFC WINDOW

0 normal window

1 enlarged window

IFS IF SENSITIVITY

0 normal sensitivity

1 reduced sensitivity

MOD MODULATION

0 negative modulation

1 positive modulation

VSW STATE

0 normal operation

1 IF video signal switched off

SM STATE

0 normal operation

1 sound muted

1997 Jul 01 25

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

Table 43 Fixed audio volume

Table 44 Demodulator frequency adjustment

OUTPUT CONTROL BITS

Table 45 Power-on-reset

Table 46 Field frequency (TDA8374 and TDA8375)

Table 47 Phase 1 lock indication

Table 48 X-ray protection

Table 49 Colour decoder mode (TDA8374 and TDA8375)

FAV STATE

0 normal volume control

1 audio output level ﬁxed

L’FA STATE

0 normal IF frequency

1 frequency shift for L’ standard

POR MODE

0 normal mode

1 power-down mode

FSI FREQUENCY

050Hz

160Hz

SL INDICATION

0 not locked

1 locked

XPR OVERVOLTAGE

0 no overvoltage detected

1 overvoltage detected

CD2 CD1 CD0 STANDARD

0 0 0 no colour standard identiﬁed

0 0 1 NTSC with crystal at pin 34

0 1 0 PAL with crystal at pin 35

0 1 1 SECAM

1 0 0 NTSC with crystal at pin 35

1 0 1 PAL with crystal at pin 34

1 1 0 spare

1 1 1 spare

Table 50 Output vertical guard

Table 51 Indication RGB insertion

Table 52 Output video identiﬁcation

Table 53 AFC output

Table 54 Crystal indication

Table 55 Condition vertical divider

NDF VERTICAL OUTPUT STAGE

0 vertical output stage OK

1 failure in vertical output stage

IN1 RGB INSERTION

0 no insertion

1 insertion

IFI VIDEO SIGNAL

0 no video signal identiﬁed

1 video signal identiﬁed

AFA AFB CONDITION

0 0 outside window; too low

0 1 outside window; too high

1 0 inside window; below reference

1 1 inside window; above reference

SXA SXB CRYSTAL

0 0 two 3.6 MHz crystals

0 1 one 3.6 MHz crystal

1 0 one 4.4 MHz crystal

1 1 3.6 MHz and 4.4 MHz crystals

IVW VIDEO SIGNAL

0 no standard video signal detected

1 standard video signal detected

(525 or 625 lines)

1997 Jul 01 26

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

Table 56 IC version indication

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. All pins are protected against ESD by means of internal clamping diodes.

2. Human Body Model (HBM): R = 1.5 kΩ; C = 100 pF.

3. Machine Model (MM): R = 0 Ω; C = 200 pF.

QUALITY SPECIFICATION

In accordance with

“SNW-FQ-611E”

. The number of the quality specification can be found in the

“Quality Reference

Handbook”

. The handbook can be ordered using the code 9397 750 00192.

Latch-up

•Itrigger ≥100 mA or ≥1.5VP(max)

•Itrigger ≤−100 mA or ≤−0.5VP(max).

ID2 ID1 ID0 STANDARD

0 0 0 TDA8373

0 0 1 TDA8377

0 1 0 TDA8374B

0 1 1 TDA8374A

1 0 0 TDA8374

1 0 1 TDA8377A

1 1 0 TDA8375A

1 1 1 TDA8375

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VPsupply voltage −9.0 V

Tstg storage temperature −25 +150 °C

Tamb operating ambient temperature 0 70 °C

Tsld soldering temperature for 5 s −260 °C

Tjoperating junction temperature −150 °C

Ves electrostatic handling HBM; all pins; notes 1 and 2 −2000 +2000 V

MM; all pins; notes 1 and 3 −200 +200 V

1997 Jul 01 27

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

CHARACTERISTICS

VP=8V; T

amb =25°C; the pin numbers given refer to the SDIP56 package; unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

MAIN SUPPLY (PIN 12)

VP1 supply voltage 7.2 8.0 8.8 V

IP1 supply current −110 −mA

Ptot total power dissipation −900 −mW

HORIZONTAL OSCILLATOR SUPPLY (PIN 37)

VP2 supply voltage 7.2 8.0 8.8 V

IP2 supply current −6−mA

IF circuit

VISION IF AMPLIFIER INPUTS (PINS 48 AND 49)

Vi(rms) input sensitivity (RMS value) note 1

fi= 38.90 MHz −70 100 µV

fi= 45.75 MHz −70 100 µV

fi= 58.75 MHz −70 100 µV

Riinput resistance (differential) note 2 −2−kΩ

Ciinput capacitance (differential) note 2 −3−pF

∆Gvvoltage gain control range 64 −−dB

Vi(max)(rms) maximum input signal

(RMS value) 100 150 −mV

PLL DEMODULATOR (PLL FILTER ON PIN 5); note 3

fPLL PLL frequency range 32 −60 MHz

fcr(PLL) PLL catching range −2−MHz

tacq(PLL) PLL acquisition time −−20 ms

∆fVCO(T) VCO frequency variation with

temperature note 4 −tbf −kHz/K

ftune(VCO) VCO tuning range via the I2C-bus −2.5 −MHz

∆fDAC frequency variation per step of

the DAC (A0 to A6) −20 −kHz

fshift(L’) frequency shift with the L’ FA bit −5.5 −MHz

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

VIDEO AMPLIFIER OUTPUT (PIN 6); note 5

Vozero signal output level negative modulation;

note 6 −4.7 −V

positive modulation; note 6 −2.0 −V

V6(ts) top sync level negative modulation 1.9 2.0 2.1 V

V6(w) white level positive modulation when

available −4.5 −V

∆V6difference in amplitude between

negative and positive

modulation

−015%

ovideo output impedance −50 −Ω

bias internal bias current of NPN

emitter follower output transistor 1.0 −−mA

Isource(max) maximum source current −−5mA

B bandwidth of demodulated

output signal at −3dB 6 9 −MHz

Gdiff differential gain note 7 −25%

diff differential phase notes 4 and 7 −−5 deg

NLvid video non-linearity note 8 −−5%

clamp white spot clamp level −5.3 −V

Nth(clamp) noise inverter threshold clamp

level note 9 −1.7 −V

Nins noise inverter insertion level note 9 −2.6 −V

δintermodulation notes 4 and 10

blue Vo= 0.92 or 1.1 MHz 60 66 −dB

Vo= 2.66 or 3.3 MHz 60 66 −dB

yellow Vo= 0.92 or 1.1 MHz 56 62 −dB

Vo= 2.66 or 3.3 MHz 60 66 −dB

S/N signal-to-noise ratio notes 4 and 11

Vi=10mV 52 60 −dB

at end of control range 52 61 −dB

V6(rc) residual carrier signal note 4 −5.5 −mV

V6(2H) residual 2nd harmonic of carrier

signal note 4 −2.5 −mV

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1997 Jul 01 29

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

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IF AND TUNER AGC; note 12

Timing of IF-AGC with a 2.2

F capacitor (pin 53)

modulated video interference 30% AM for 1 to 100 mV;

0 to 200 Hz (system B/G) −−10 %

tres(IFinc) response time to an IF input

signal amplitude increase of

52 dB

positive (when available)

and negative modulation −2−ms

tres(IFdec) response to an IF input signal

amplitude decrease of 52 dB negative modulation −50 −ms

positive modulation (when

available) −100 −ms

I53 allowed leakage current of the

AGC capacitor negative modulation −−10 µA

positive modulation (when

available) −−200 nA

Tuner take-over adjustment (via I

C-bus)

Vi(min)(rms) minimum starting level for tuner

take-over (RMS value) −0.4 0.8 mV

Vi(max)(rms) maximum starting level for tuner

take-over (RMS value) 40 80 −mV

Tuner control output (pin 54)

VoAGC(max) maximum tuner AGC output

voltage maximum tuner gain;

note 2 −−V

+1 V

o(sat) output saturation voltage minimum tuner gain;

I54 =2mA −−300 mV

IoAGC(max) maximum tuner AGC output

swing 5−−mA

ILI(RF) leakage current RF AGC −−1µA

∆V

iinput signal variation for a

control current variation of 1 mA 0.5 2 4 dB

AFC OUTPUT (VIA I2C-BUS); note 13

RESAFC AFC resolution −2−bits

wsen window sensitivity 65 80 100 kHz

wsenL window sensitivity in large

window mode 195 240 300 kHz

VIDEO IDENTIFICATION OUTPUT (VIA I2C-BUS)

tddelay time of identiﬁcation after

the AGC has stabilized on a

new transmitter

−−10 ms

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Preliminary speciﬁcation

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Sound circuit

DEMODULATOR PART

Vi(crPLL)(rms) input limiting voltage for PLL

catching range (RMS value) −12mV

cr(PLL) PLL catching range note 14 4.2 −6.8 MHz

Riinput resistance note 2 −8.5 −kΩ

Ciinput capacitance note 2 −−5pF

AMR AM rejection Vi= 50 mV (RMS); note 15 60 66 −dB

DE-EMPHASIS

Vo(rms) output signal amplitude

(RMS value) note 14 −500 −mV

Rooutput resistance −15 −kΩ

VODC output voltage −3−V

AUDIO ATTENUATOR CIRCUIT

Vo(rms) controlled output signal

amplitude (RMS value) at −6 dB; note 14 500 700 900 mV

VoAVL(rms) output signal level when AVL is

activated (RMS value) note 16 300 400 500 mV

VoFAV(rms) output signal level when FAV is

activated (RMS value) note 14 −500 −mV

Rooutput resistance −500 −Ω

ODC output voltage −3.3 −V

THD total harmonic distortion note 17 −−0.5 %

FAV = 1; note 18 −−tbf %

PSRR power supply ripple rejection note 4 −tbf −dB

S/Nint internal signal-to-noise ratio notes 4 and 19 −60 −dB

S/Next external signal-to-noise ratio notes 4 and 19 −80 −dB

Tdep(out) temperature dependancy of

output level notes 4 and 20 −−tbf dB

CR control range tbf 80 tbf dB

VCstep step size volume control −1.5 −dB

control curve see Fig.8

OSS suppression of output signal

when the mute is active −80 −dB

Vshift DC shift of the output level when

the mute is activated −10 50 mV

EXTERNAL AUDIO INPUT

Vi(rms) input signal amplitude

(RMS value) −500 1500 mV

Riinput resistance −25 −kΩ

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

Gv(in-out) voltage gain between input and

output maximum volume −12 −dB

αct crosstalk between audio signals 60 −−

AUTOMATIC VOLUME LEVELLING CIRCUIT (TDA8373 AND TDA8374 ONLY;CAPACITOR CONNECTED TO PIN 45)

Gmax gain maximum boost; note 16 −6−dB

Gmin gain minimum boost −−14 −dB

Iatt attack charge current −1−mA

Idec decay discharge current −200 −nA

Vctrl(max) control voltage maximum boost −1−V

Vctrl(min) control voltage minimum boost −5−V

CVBS, Y/C, RGB, CD inputs and luminance input and output

CVBS AND Y/C SWITCH (PINS 11, 13, 17 AND 38)

V11(p-p) CVBS or Y input voltage

(peak-to-peak value) note 21 −1.0 1.4 V

I17 CVBS input current −4−µA

SSCVBS suppression of non-selected

CVBS input signal notes 4 and 22 50 −−dB

V10(p-p) chrominance input voltage

(burst amplitude) (peak-to-peak

value)

notes 2 and 23 −0.3 0.45 V

V38(p-p) output signal amplitude

(peak-to-peak value) −1.0 −V

Zooutput impedance −−250 Ω

Vsync top sync level −2.5 −V

RGB INPUTS (PINS 23, 24 AND 25)

V23-25(p-p) input signal amplitude for an

output signal of 2 V

(black-to-white) (peak-to-peak

value)

note 24 −0.7 0.8 V

V23-25(p-p) input signal amplitude before

clipping occurs (peak-to-peak

value)

note 4 1.0 −−V

∆V

odifference between black level

of internal and external signals

at the outputs

−−20 mV

I23-25 input currents note 2 −0.1 1 µA

∆tddelay difference for the three

channels note 4 −0−ns

FAST BLANKING (PIN 26)

Viinput voltage no data insertion −−0.3 V

data insertion 0.9 −−V

26(max) maximum input pulse insertion −−3.0 V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Preliminary speciﬁcation

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and NTSC TV-processors TDA837x family

∆td(blank,RGB) delay difference of blanking and

RGB signals note 4 −−50 ns

tsw switching speed of blanking

circuit −10 −ns

I26 input current −−0.2 mA

SSint suppression of internal RGB

signals insertion; fi= 0 to 5 MHz;

notes 4 and 22 −55 −dB

SSext suppression of external RGB

signals no insertion;

fi= 0 to 5 MHz;

notes 4 and 22

−55 −dB

Viinput voltage to insert black level

at the RGB outputs to facilitate

‘On Screen Display’ signals

being applied to the outputs

4−−V

d(blank-RGB) delay between blanking input

and RGB outputs −−80 ns

COLOUR DIFFERENCE INPUT SIGNALS (PINS 31 AND 32)

V31(p-p) input signal amplitude (R −Y)

(peak-to-peak value) note 2 −1.05 −V

V32(p-p) input signal amplitude (B −Y)

(peak-to-peak value) note 2 −1.35 −V

I31,32 input current for both inputs note 2 −0.1 1.0 µA

LUMINANCE INPUTS AND OUTPUTS (PINS 27 AND 28); note 25

V27,28 output signal amplitude

(black-to-white) −1−V

Chrominance ﬁlters

CHROMINANCE TRAP CIRCUIT; note 26

ftrap trap frequency −fosc −MHz

QF trap quality factor note 27 −2−

CSR colour subcarrier rejection 20 −−dB

ftrap(SECAM) trap frequency during SECAM reception −4.3 −MHz

CHROMINANCE BAND-PASS CIRCUIT

fccentre frequency −1.1fosc −MHz

Qbp band-pass quality factor −3−

Luminance processing

YDELAY LINE

td(Y) delay time note 4 −480 −ns

Bdel(int) bandwidth of internal delay line note 4 8 −−MHz

PEAKING CONTROL; note 28

tWwidth of preshoot or overshoot at 50% of pulse; note 8 −160 −ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Sc(th) peaking signal compression

threshold −50 −IRE

OS overshoot at maximum peaking positive −45 −%

negative −80 −%

neg/pos ratio of negative and positive

overshoots −1.8 −

peaking control curve 16 steps see Fig.9

NOISE CORING STAGE

S coring range −15 −IRE

BLACK LEVEL STRETCHER; note 29

BLshift(max) maximum black level shift 15 21 27 IRE

BLshift level shift at 100% of peak white −1 0 +1 IRE

at 50% of peak white −1−+3 IRE

at 15% of peak white 6 8 10 IRE

Horizontal and vertical synchronization and drive circuits

SYNC VIDEO INPUT (PINS 11, 13 AND 17)

V11,13,17 sync pulse amplitude note 2 50 300 350 mV

SLHS slicing level for horizontal sync note 30 −50 −%

SLVS slicing level for vertical sync note 30 −30 −%

HORIZONTAL OSCILLATOR

ffr free running frequency −15625 −Hz

∆ffr spread on free running

frequency −−±2%

∆f/∆VPfrequency variation with respect

to the supply voltage VP= 8.0 V ±10%; note 4 −0.2 0.5 %

∆f(max)(T) maximum frequency variation

with temperature Tamb = 0 to 70 °C; note 4 −−80 Hz

FIRST CONTROL LOOP (FILTER CONNECTED TO PIN 43); note 31

fhr(PLL) holding range PLL −±0.9 ±1.2 kHz

fcr(PLL) catching range PLL note 4 ±0.6 ±0.9 −kHz

S/N signal-to-noise ratio of the video

input signal at which the time

constant is switched

−20 −dB

HYS hysteresis at the switching point −1−dB

SECOND CONTROL LOOP (CAPACITOR CONNECTED TO PIN 42)

∆ϕi/∆ϕocontrol sensitivity −150 −µs/µs

tcr control range from start of

horizontal output to ﬂyback at

nominal shift position

11 12 −µs

shift horizontal shift range 63 steps ±2−−µs

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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∆ϕ control sensitivity for dynamic

phase compensation −5.3 −µs/V

Vprot voltage to switch-on the ﬂash

protection note 32 6 −−V

i(prot) input current during protection −−1mA

HORIZONTAL OUTPUT (PIN 40); note 33

VOL LOW level output voltage Io=10mA −−0.3 V

Io(max) maximum allowed output

current 10 −−mA

Vo(max) maximum allowed output

voltage −−V

δduty factor note 4 −50 −%

Vo= HIGH −75 −%

fsw frequency during switch-on and

switch-off −2fH−Hz

tsw switch-on time −50 −ms

maximum RGB drive −100 −ms

minimum RGB drive −50 −ms

FLYBACK PULSE INPUT AND SANDCASTLE OUTPUT (PIN 41)

Ii(fb) required input current during the

ﬂyback pulse note 4 100 −300 µA

V41 output voltage during burst key 4.8 5.3 5.8 V

during blanking 1.8 2.0 2.2 V

Vi(clamp) clamped input voltage during

ﬂyback 2.6 3.0 3.4 V

tWpulse width burst key pulse 3.3 3.5 3.7 µs

vertical blanking; note 34 −14 −lines

td(bk-sync) delay of start of burst key to start

of sync 5.2 5.4 5.6 µs

VERTICAL OSCILLATOR; TDA8373 AND TDA8377 OPERATING AT 60 HZ; note 35

ffr free running frequency −50/60 −Hz

flock frequency locking range 45 −64.5 Hz

divider value not locked −625/525 −lines

LR locking range 488 −722 lines/

frame

VERTICAL RAMP GENERATOR (PINS 51 AND 52)

V51(p-p) sawtooth amplitude

(peak-to-peak value) VS = 1FH;

C=100nF;R=39kΩ−3.5 −V

Idch discharge current −1−mA

Ich charge current set by external

resistor note 36 −19 −µA

slope vertical slope control range (63 steps) −20 −+20 %

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Preliminary speciﬁcation

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and NTSC TV-processors TDA837x family

∆Ich charge current increase f = 60 Hz −20 −%

VrampL LOW voltage level of ramp in

the normal or expand mode −2.07 −V

VERTICAL DRIVE OUTPUTS (PINS 46 AND 47)

Io(dif)(p-p) differential output current

(peak-to-peak value) VA = 1FH −0.95 −mA

ICM common mode current −400 −µA

46,47 output voltage range 0 −4.0 V

EHT TRACKING/OVERVOLTAGE PROTECTION (PIN 50)

∆V50 input voltage range 1.2 −2.8 V

mscan scan modulation range −5−+5 %

vsen vertical sensitivity −6.3 −%/V

EWsen E-W sensitivity when switched on −−6.3 −%/V

Ieq E-W equivalent output current +100 −−100 µA

V50 overvoltage detection level note 32 −3.9 −V

DE-INTERLACE

ffdﬁrst ﬁeld delay −0.5H −

E-W WIDTH (TDA8375A, TDA8377A, TDA8375 AND TDA8377); note 37

CR control range 63 steps 100 −65 %

Ieq equivalent E-W output current 0 −700 µA

VoEW E-W output voltage range 1.0 −8.0 V

IoEW E-W output current range 0 −1200 µA

E-W PARABOLA/WIDTH (TDA8375A, TDA8377A, TDA8375 AND TDA8377)

CR control range 63 steps 0 −22 %

Ieq equivalent E-W output current E-W = 3FH 0 −440 µA

E-W CORNER/PARABOLA (TDA8375A, TDA8377A, TDA8375 AND TDA8377)

CR control range 63 steps −43 −0%

eq equivalent E-W output current PW = 3FH; E-W = 3FH −190 −0µA

E-W TRAPEZIUM (TDA8375A, TDA8377A, TDA8375 AND TDA8377)

CR control range 63 steps −5−+5 %

Ieq equivalent E-W output current −100 −+100 µA

VERTICAL AMPLITUDE

CR control range 63 steps; SC = 00H 80 −120 %

Ieq(dif)(p-p) equivalent differential vertical

drive output current

(peak-to-peak value)

SC = 00H 760 −1140 µA

VERTICAL SHIFT

CR control range 63 steps −5−+5 %

Ieq(dif) equivalent differential vertical

drive output current −50 −+50 µA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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S-CORRECTION

CR control range 63 steps 0 −30 %

VERTICAL EXPAND (ZOOM)MODE (TDA8375 AND TDA8377); note 38

Output current variation compared with nominal scan

∆Iovertical expand factor 0.75 1.38 A

Io(lim) output current limiting and RGB

blanking 1.08 A

Colour demodulation part

CHROMINANCE AMPLIFIER

CRACC ACC control range note 39 26 −−dB

∆VACC change in amplitude of the

output signals over the ACC

range

−−2dB

thon threshold colour killer ON −30 −−dB

hysoff hysteresis colour killer OFF at strong signal conditions;

S/N ≥40 dB; note 4 −+3 −dB

at noisy input signals;

note 4 −+1 −dB

ACL CIRCUIT; note 40

chrominance burst ratio at which

the ACL starts to operate −3.0 −

REFERENCE PART

Phase-locked loop; note

fcr frequency catching range ±360 ±600 −Hz

∆ϕ phase shift for a ±400 Hz

deviation of the oscillator

frequency

note 4 −−2 deg

Oscillator

TCosc temperature coefﬁcient of the

oscillator frequency note 4 −2.0 2.5 Hz/K

∆fosc oscillator frequency deviation

with respect to the supply VP=8V±10%; note 4 −−250 Hz

Rneg(min) minimum negative resistance −−1kΩ

L(max) maximum load capacitance −−15 pF

HUE CONTROL

CRhue hue control range 63 steps ±35 ±40 −deg

hue control curve see Fig.10

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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∆hue hue variation for ±10% VPnote 4 −0−deg

∆hue(T) hue variation with temperature Tamb = 0 to 70 °C; note 4 −0−deg

DEMODULATORS (PINS 29 AND 30)

V30(p-p) (R −Y) output signal amplitude

(peak-to-peak value) TDA8374 and TDA8375;

note 42 −0.525 −V

V29(p-p) (B −Y) output signal amplitude

(peak-to-peak value) TDA8374 and TDA8375;

note 42 −0.675 −V

G gain ratio between both

demodulators G(B −Y) and

G(R −Y)

1.60 1.78 1.96

∆V spread of signal amplitude ratio

PAL/NTSC TDA8374 and TDA8375;

note 4 −1−+1 dB

Zooutput impedance between

(R −Y) and (B −Y) note 2 −500 −Ω

B bandwidth of demodulators −3 dB; note 43 −650 −kHz

V29,30(p-p) residual carrier output

(peak-to-peak value) fc; (R −Y) output 5 mV

fc; (B −Y) output −−5mV

2fc; (R −Y) output 5 mV

2fc; (B −Y) output −−5mV

30(p-p) H/2 ripple at (R −Y) output

(peak-to-peak value) −−25 mV

∆Vo(T) change of output signal

amplitude with temperature note 4 −0.1 −%/K

∆Vo/VPchange of output signal

amplitude with supply voltage note 4 −−±0.1 dB

Eϕphase error in the demodulated

signals note 4 −−±5 deg

COLOUR DIFFERENCE MATRICES (IN CONTROL CIRCUIT) TDA8374 AND TDA8375

PAL or (SECAM when TDA8395 is applied); (R

−

Y) and (B

−

Y) not affected

(G −Y)/

(R −Y) ratio of demodulated signals −−0.51

±10% −

(G −Y)/

(B −Y) ratio of demodulated signals −−0.19

±25% −

NTSC mode; the colour-difference matrix results in the following signals (nominal hue setting)

(B −Y) (B −Y) signal 2.03/0°2.03UR

(R −Y) (R −Y) signal 1.59/95°−0.14UR+ 1.58VR

(G −Y) (G −Y) signal 0.61/240°−0.31UR−0.53VR

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Preliminary speciﬁcation

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and NTSC TV-processors TDA837x family

COLOUR DIFFERENCE MATRICES (IN CONTROL CIRCUIT) TDA8373 AND TDA8377

MAT = 0; the colour-difference matrix results in the following signals (nominal hue setting)

(B −Y) (B −Y) signal 2.03/0°2.03UR

(R −Y) (R −Y) signal 1.59/95°−0.14UR+ 1.58VR

(G −Y) (G −Y) signal 0.61/240°−0.31UR−0.53VR

MAT = 1; the colour-difference matrix results in the following signals (nominal hue setting)

(B −Y) (B −Y) signal 1.14/−10°1.12UR−0.20VR

(R −Y) (R −Y) signal 1.14/100°−0.20UR+ 1.12VR

(G −Y) (G −Y) signal 0.30/235°−0.17UR−0.25VR

REFERENCE SIGNAL OUTPUT (PIN 33); note 44

fref reference frequency −3.58 or

4.43 −MHz

V33(p-p) output signal amplitude

(peak-to-peak value) 0.2 0.25 0.3 V

COMMUNICATION WITH THE TDA8395 (TDA8374 AND TDA8375 ONLY)

Vooutput level PAL/NTSC identiﬁed −1.5 −V

no PAL/NTSC identiﬁed;

SECAM (by TDA8395)

identiﬁed

−5.0 −V

I31 required current to stop

PAL/NTSC identiﬁcation circuit

during SECAM

150 −−µA

Control part

SATURATION CONTROL; note 24 (SEE Fig.11)

CRsat saturation control range 63 steps 52 −−dB

CONTRAST CONTROL; note 24 (SEE Fig.12)

CRcon contrast control range 63 steps −15 −dB

tracking between the three

channels over a control range of

10 dB

−−0.5 dB

BRIGHTNESS CONTROL (SEE Fig.13)

CRbri brightness control range 63 steps −±0.7 −V

RGB OUTPUT SIGNALS (PINS 19 TO 21)

V19-21(p-p) output signal amplitude at

nominal luminance input signal,

nominal contrast and white point

adjustment (peak-to-peak value)

note 24 1.8 2.1 2.4 V

Vo(max)(p-p) output signal at maximum white

point setting (peak-to-peak

value)

−3.0 −V

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VBW(max)(p-p) maximum signal amplitude

(black-to-white) note 45 −2.6 −V

VWP(max)(p-p) maximum signal amplitude at

maximum white point setting

(peak-to-peak value)

−3.6 −V

Vred(p-p) output signal amplitude for the

‘red’ channel at nominal settings

for contrast and saturation

control and no luminance signal

to the input (R −Y, PAL)

(peak-to-peak value)

tbf 2.1 tbf V

∆Vblank difference between blanking

level measuring pulse 0.7 0.8 0.9 V

tW(blank) width of the video blanking pulse

when the HBL bit is active TDA8375, TDA8377,

TDA8375A and

TDA8377A; note 46

14.4 14.7 15.0 µs

Ibias internal bias current of NPN

emitter follower output transistor −1.5 −mA

Ioavailable output current −5−mA

Zooutput impedance −150 −Ω

CRbl control range of the black

current stabilization at Vbl = 2.5 V and nominal

brightness and white-point

adjustment (with respect to

the measuring pulse)

−−±1V

bl black level shift with picture

content note 4 −−20 mV

Vo(4L) output voltage of the 4-L pulse

after switch-on −4.2 −V

∆bl(T) variation of black level with

temperature note 4 −1.0 −mV/K

∆bl relative variation in black level

between the three channels

during variations of

note 4

supply voltage (±10%) nominal controls −−20 mV

saturation (50 dB) nominal contrast −−20 mV

contrast (15 dB) nominal saturation −−20 mV

brightness (±0.5 V) nominal controls −−20 mV

temperature (range 40 °C) −−20 mV

S/N signal-to-noise ratio of the

output signals RGB input; note 47 60 −−dB

CVBS input; note 47 50 −−dB

Vr(p-p) residual voltage at the RGB

outputs (peak-to-peak value) at fosc −−15 mV

at 2fosc plus higher

harmonics in RGB outputs −−15 mV

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Notes

1. On set AGC.

2. This parameter is not tested during production and is just given as application information for the designer of the

television receiver.

3. Loop bandwidth BL= 60 kHz (natural frequency fn= 15 kHz; damping factor d = 2; calculated with sync level as FPLL

input signal level). LC-VCO circuit: Q0≥60, Cext = 12 pF, Cint =20pF.

4. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix

batches which are made in the pilot production period.

5. Measured at 10 mV (RMS) top sync input signal.

6. So called projected zero point, i.e. with switched demodulator.

B bandwidth of output signals RGB input at −3dB 8 −−MHz

CVBS input at −3 dB;

fosc = 3.6 MHz −2.8 −MHz

CVBS input at −3 dB;

fosc = 4.44 MHz −3.5 −MHz

S-VHS input; at −3dB 5 −−MHz

WHITE-POINT ADJUSTMENT

I2C-bus setting for nominal gain HEX code −20H −

Ginc(max) maximum increase of the gain HEX code 3FH 40 50 60 %

Gdec(max) maximum decrease of the gain HEX code 00H 35 45 55 %

BLACK CURRENT STABILIZATION (PIN 18); note 48

Ibias bias current for the picture tube

cathode nominal white point setting −10 −µA

Lacceptable leakage current −±100 −µA

scan(max) maximum current during scan −0.3 −mA

Ziinput impedance −15 −kΩ

BEAM CURRENT LIMITING/VERTICAL GUARD INPUT (PIN 22); note 49

VCR contrast reduction starting

voltage −3.1 −V

VdifCR voltage difference for full

contrast reduction −2−V

VBR brightness reduction starting

voltage −1.6 −V

VdifBR voltage difference for full

brightness reduction −1−V

Vbias internal bias voltage −3.3 −V

Zint internal impedance −40 −kΩ

Vdet detection level for vertical guard −3.65 −V

Ii(min) minimum input current to

activate the guard circuit −100 −µA

i(max) maximum allowable input

current −1−mA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1997 Jul 01 41

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

7. Measured in accordance with the test line given in Fig.14. For the differential phase test the peak white setting is

reduced to 87%.

a) The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and

smallest value relative to the subcarrier amplitude at blanking level.

b) The phase difference is defined as the difference in degrees between the largest and smallest phase angle.

8. This figure is valid for the complete video signal amplitude (peak white-to-black), see Fig.15.

9. The noise inverter is only active in the ‘strong signal mode’ (no noise detected in the incoming signal).

10. The test set-up and input conditions are given in Fig.16. The figures are measured with an input signal of

10 mV (RMS).

11. Measured with a source impedance of 75 Ω, where:

12. The AGC response time is also dependent on the acquisition time of the PLL demodulator. The values given are valid

when the PLL is in lock.

13. The AFC control voltage is obtained from the control voltage of the VCO of the PLL demodulator. The tuning

information is supplied to the tuning system via the I2C-bus. Two bits are reserved for this function. The AFC value

is valid only when the SL bit = 1.

14. Vi= 100 mV (RMS), FM: 1 kHz, ∆f=±50 kHz.

15. Vi= 50 mV (RMS), f = 4.5 to 5.5 MHz; FM: 70 Hz, ±50 kHz deviation; AM: 1 kHz, 30% modulation.

16. The Automatic Volume Levelling (AVL) circuit automatically stabilizes the audio output signal to a certain level which

can be set by means of the volume control. This AVL function prevents big audio output fluctuations due to variation

of the modulation depth of the transmitter. The AVL can be switched on and off via the I2C-bus.

For the TDA8373 the AVL is active over an input voltage range (measured at the de-emphasis output) between

75 and 750 mV (RMS). For the TDA8374 this input level is dependent on the crystals which are connected to the

colour decoder. When only 3.5 MHz crystals are connected (indicated via the XA/XB bits) the active input level is

identical to that of the TDA8373. When a 4.4 MHz crystal is connected the input signal range is increased to

150 to 1500 mV (RMS), this to cope with the larger FM swing of European transmitters.

The AVL control curve for the 2 standards is given in Fig.29 and Fig.30. The control range of +6 to −14 dB is valid

for input signals with 50% of the maximum frequency deviation.

17. Vi= 100 mV (RMS), f = 5.5 MHz; FM: 1 kHz, ±17.5 kHz deviation, 15 kHz bandwidth; audio attenuator at −6 dB.

18. Vi= 100 mV (RMS), f = 4.5 to 5.5 MHz, FM: 1 kHz, ±100 kHz deviation.

19. Unweighted RMS value, Vi= 100 mV (RMS), FM: 1 kHz, ±50 kHz deviation, volume control: −6 dB.

20. Audio attenuator at −20 dB; temperature range = 10 to 50 °C.

21. Signal with negative-going sync. Amplitude includes sync pulse amplitude.

22. This parameter is measured at nominal settings of the various controls.

23. Indicated as a signal for a colour bar with 75% saturation (chroma-to-burst ratio = 2.2 : 1).

24. Nominal contrast is specified with the DAC in position 20H. Nominal saturation as maximum −10 dB. At nominal

settings of brightness and white point the black level at the outputs is 300 mV lower than the level of the black current

measuring pulses.

25. The luminance output and input of the TDA8375A, TDA8377A, TDA8375 and TDA8377 can be connected directly.

When additional picture improvement ICs (such as the TDA9170) are applied the inputs of these ICs must be

AC-coupled because of the black level clamp requirement. The output of the picture improvement ICs can be directly

coupled to the luminance input as long as the DC level of the signal has a value between 1 and 7 V.

To be able to apply CTI ICs such as the TDA4565 and TDA4566 the gain of the luminance channel can be increased

via the setting of the GAI bit in the I2C-bus subaddress 03.

S/N = 20 log VO(b-w)

Vm rms()

B=5MHz()

---------------------------------------------------------

1997 Jul 01 42

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

26. When the colour decoder is forced to a fixed subcarrier frequency (via the XA/XB or the CM bits) the chroma trap is

always switched on, also when no colour signal is identified. When 2 crystals are active the chroma trap is switched

off when no colour signal is identified.

27. The −3 dB bandwidth of the circuit can be calculated using the following equation:

28. Valid for a signal amplitude on the Y input of 0.7 V (black-to-white) (100 IRE) with a rise time (10% to 90%) of 70 ns

and the video switch in the Y/C mode. During production the peaking function is not tested by measuring the

overshoots but by measuring the frequency response of the Y output.

29. For video signals with a black level which deviates from the back porch blanking level the signal is ‘stretched’ to the

blanking level. The amount of correction depends on the IRE value of the signal (see Fig.17). The black level is

detected by means of an external capacitor. The black level stretcher can be made inoperative by connecting the pin

to ground. The values given are valid only when the luminance input signal has an amplitude of 1 V (p-p).

30. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing

level and the black level (back porch). When the amplitude of the sync pulse exceeds the value of 350 mV the sync

separator will slice the sync pulse at a level of 175 mV above top sync. The maximum sync pulse amplitude is

4 V (p-p).

31. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is

switched depending on the input signal condition and the condition of the bus. Therefore the circuit contains a noise

detector and the time constant is switched to ‘slow’ when too much noise is present in the signal. In the ‘fast’ mode,

during the vertical retrace time, the phase detector current is increased by 50% so that phase errors due to the head

switching of the VCR are corrected as soon as possible. Switching between the two modes can be made

automatically or overruled by the bus (see Tables 4, 6, 8 and 10).

The circuit contains a video identification circuit which is independent of first loop. This identification circuit can be

used to close or open the first control loop when a video signal is present or not on the input. This ensures a stable

On-Screen-Display (OSD) when just noise is present at the input. The coupling of the video identification circuit with

the first loop can be overruled via the I2C-bus. The coupling between the phase 1 detector and the videoidentiﬁcation

circuit is only active for ‘internal’ CVBS signals.

To prevent the horizontal synchronization being disturbed by anti-copy guard signals, such as Macrovision, the

phase detector is gated during the vertical retrace period so that pulses during scan have no effect on the output

voltage. The width of the gate pulse is approximately 22 µs. Furthermore the phase detector is gated during the lower

part of the picture (pulse width = 12 µs) to prevent disturbances due to overmodulated subtitles. The latter gating is

active only with standard signals (number of lines per frame 625 or 525). During weak signal conditions (noise

detector active) the gating is active during the complete scan period and the width of the gate pulse is reduced to

5.7 µs so that the effect of the noise is reduced to a minimum. The output current of the phase detector in the various

conditions are given in Table 57.

32. The ICs have 2 protection inputs.

The protection at pin 42 is intended to be used as ‘flash’ protection. When this protection is activated the horizontal

drive is switched off immediately and then switched on again via the slow start procedure.

The protection on pin 50 is intended for overvoltage (X-ray) protection. When this protection is activated the

horizontal drive can be switched off directly (via the slow stop procedure). It is also possible to continue the horizontal

drive and to set the protection bit (XPR) in the output bytes of the I2C-bus. The choice between the 2 modes of

operation is made with the PRD bit.

f3dB–f

osc 11

--------

–





1997 Jul 01 43

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

33. During switch-on the horizontal output starts with twice the frequency and with a duty cycle of 75% (Vo= HIGH). After

approximately 50 ms the frequency is changed to the normal value. Because of the high frequency the peak currents

in the horizontal output transistor are limited. Also during switch-off the frequency is switched to twice the value and

the RGB drive is set to maximum so that the EHT capacitor is discharged. This switching to maximum drive occurs

only when RBL = 0, for RBL = 1 the drive voltage remains minimum during switch-off. After approximately 100 ms

the RGB drive is set to minimum and 50 ms later the horizontal drive is switched off.

The horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched on

during the flyback time.

34. The vertical blanking pulse in the RGB outputs has a width of 26 or 21 lines (50 or 60 Hz system). The width of the

vertical sync pulse in the sandcastle pulse has a width of 14 lines. This to prevent a phase distortion on top of the

picture due to timing modulation of the incoming flyback pulse.

35. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. This

divider circuit has 3 modes of operation. A brief explanation is given below. For the TDA8373 and TDA8377 only the

60 Hz figures are valid.

a) Search mode ‘large window’:

This mode is switched on when the circuit is not synchronized or when a non-standard signal (number of lines

per frame in the 50 Hz mode is between 311 and 314 and in the 60 Hz mode between 261 and 264) is received.

In the search mode the divider can be triggered between line 244 and line 361 (approximately 45 to 64.5 Hz).

b) Standard mode ‘narrow window’:

This mode is switched on when more than 15 succeeding vertical sync pulses are detected in the narrow window.

When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp

generator is started at the end of the window. Consequently, the disturbance of the picture is very small.

The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found

within the window.

c) Standard TV-norm (divider ratio 525 (60 Hz) or 625 (50 Hz):

When the system is switched to the narrow window it is checked whether the incoming vertical sync pulses are

in accordance with the TV-norm. When 15 standard TV-norm pulses are counted the divider system is switched

to the standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical

sync pulse is missing.

When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this

window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window.

The vertical divider needs some waiting time during channel-switching of the tuner. When a fast reaction of the

divider is required during channel-switching the system can be forced to the search window by means of the NCIN bit

in subaddress 08.

36. Conditions: frequency is 60 Hz; normal mode; VS = 1F.

37. The output range percentages mentioned for E-W control parameters are based on the assumption that 400 µA

variation in E-W output current is equivalent to 20% variation in picture width. Because of the horizontal and vertical

zoom feature in the TDA8375 and TDA8377 (see also note 38) the E-W width control range is increased compared

with previous ICs such as the TDA8366. The increased E-W width control is also available in the TDA8375A and

TDA8377A although these devices do not have the vertical zoom feature.

38. The TDA8375 and TDA8377 have a zoom adjustment possibility for the vertical and horizontal deflection. For this

reason an extra DAC has been added in the vertical amplitude control which controls the vertical scan amplitude

between 0.75 and 1.38 of the nominal scan. At an amplitude of 1.08 of the nominal scan the output current is limited

and the blanking of the RGB outputs is activated (see Fig.28). In addition to the variation of the vertical amplitude the

vertical slope control range is also increased. This gives the possibility to vary the position of the bottom part of the

picture independent from the upper part. The nominal scan height must be adjusted at a position of 19H of the vertical

‘zoom’ DAC

1997 Jul 01 44

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

39. At a chrominance input voltage of 660 mV (p-p) [colour bar with 75% saturation i.e. burst signal amplitude

300 mV (p-p)] the dynamic range of the ACC is +6 and −20 dB.

40. The ACL function is available in the NTSC devices and is active in the PAL/NTSC devices when NTSC signals are

received. The ACL circuit reduces the gain of the chroma amplifier for input signals with a chroma-to-burst ratio which

exceeds a value of 3.0.

41. All frequency variations are referenced to 3.58 or 4.43 MHz carrier frequency. All oscillator specifications are

measured with the Philips crystal series 9922 520 with a series capacitor of 18 pF. The oscillator circuit is rather

insensitive to the spurious responses of the crystal. As long as the resonance resistance of the 3rd overtone is higher

than that of the fundamental frequency the oscillator will operate at the correct frequency. Typical parameters for the

above mentioned crystals are as follows:

a) Load resonance frequency f0= 4.433619 or 3.579545 MHz (CL= 20 pF).

b) Motional capacitance Cmot = 20.6 fF (4.43 MHz crystal) or 14.7 fF (3.58 MHz crystal).

c) Parallel capacitance Cpar = 5 pF for both crystals.

The minimum detuning range can only be specified if both the IC and the crystal tolerances are known and the figures

given are therefore valid for the specified crystal series. In this figure tolerances of the crystal with respect to nominal

frequency, motional capacitance and ageing have been taken into account and have been counted for gaussian

addition. Whenever different typical crystal parameters are used the following equation might be helpful for

calculating the impact on the detuning capabilities:

The detuning range divided by

The resulting detuning range should be corrected for temperature shift and supply deviation of both the IC and the

crystal. The actual series capacitance in the application should be CL= 18 pF to account for parasitic capacitances

on and off chip. For 3-norma applications with 2 crystals connected to one pin the maximum parasitic capacitance of

the crystal pin should not exceed 15 pF.

42. The (R −Y) and (B −Y) signals are demodulated with a phase difference of the reference carrier of 90° and a gain

ratio .

The output signal amplitudes of the TDA8373 and TDA8377A have twice the value. This is necessary to compensate

for the gain of the baseband delay line (TDA4665). The matrixing to the required signals is realized in the control part.

43. This parameter indicates the bandwidth of the complete chrominance circuit including the chrominance band-pass

filter. The bandwidth of the low-pass filter of the demodulator is approximately 1 MHz.

44. The sub-carrier output signal can be used as reference signal of external comb filter ICs (all ICs) and as a reference

signal for the SECAM decoder TDA8395 (only TDA8374 and TDA8375). In the latter types the output signal is

continuously available when PAL or NTSC signals are detected. When the system identifies a SECAM signal the

reference signal is only present in the vertical retrace period. This to prevent interference between the reference

signal and the SECAM input signal. For comb filter applications the DC load on this pin should be limited to 50 µA to

avoid problems with SECAM identification.

45. At nominal setting of the gain control. When this amplitude is exceeded the signal will be clipped.

46. When the reproduction of 4 : 3 pictures on a 16 : 9 picture tube is realized by means of a reduction of the horizontal

scan amplitude, the edges of the picture may be slightly disturbed. This effect can be prevented by adding additional

blanking to the RGB signals. This blanking pulse is derived from the horizontal oscillator and is directly related to the

incoming video signal (independent of the flyback pulse). The additional blanking overlaps the normal blanking signal

with approximately 1 µs on both sides. This blanking is activated with the HBL bit (only in the TDA8375 and

TDA8377).

47. Signal-to-noise ratio (S/N) is specified as a peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz).

Cmot

1Cpar

-----------







-------------------------------

BY–()

RY–()

-------------------- 1.78=

1997 Jul 01 45

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

48. This is a current input. The indicated value of the nominal bias current is obtained at the nominal setting of the gain

(white point) control. The actual value of the bias current depends on the gain control setting of each channel. As a

result the ‘black current’ of each gun is adapted to the white point setting so that the background colour will follow

the white point adjustment.

49. The beam current limiting and the vertical guard function have been combined on this pin. The beam current limiting

function is active during the vertical scan period.

Table 57 Output current of the phase detector in the various conditions

Note

1. During vertical retrace the width is 22 µs and during the lower part of the picture 12 µs. In the other conditions the

width is 5.7 µs and the gating is continuous.

I2C-BUS COMMANDS IC CONDITIONS ϕ-1 CURRENT/MODE

VID POC FOA FOB IDENT COIN NOISE SCAN V-RETR GATING MODE

−0 0 0 yes yes no 180 270 yes(1) auto

−0 0 0 yes yes yes 30 30 yes auto

−0 0 0 yes no −180 270 no auto

−0 0 1 yes yes −30 30 yes slow

−0 0 1 yes no −180 270 no slow

−0 1 0 yes yes no 180 270 yes fast

−0 1 0 yes yes yes 30 30 yes slow

−−11−−−180 270 no fast

00−−no −−6 6 no OSD

−1−−−−−−−−off

Fig.8 Volume control curve.

handbook, halfpage

MGK290

−20

−40

−60

−80

−100 10

(dB)

DAC (HEX)

20 30 40

Fig.9 Peaking control curve.

Positive overshoot.

handbook, halfpage

(%)

DAC (HEX)

8C10F

MGK291

1997 Jul 01 46

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

Fig.10 Hue control curve.

handbook, halfpage

−40

−20

(deg)

DAC (HEX)

20 30 40

MGK292

Fig.11 Saturation control curve.

handbook, halfpage

300

250

200

150

100

(%)

DAC (HEX)

20 30 40

MGK293

Fig.12 Contrast control curve.

handbook, halfpage

MGK294

100

(%)

010 DAC (HEX)

20 30 40

Fig.13 Brightness control curve.

Relative variation with respect to the measuring pulse.

handbook, halfpage

MGK295

0.7

0.35

−0.35

−0.7

(V)

DAC (HEX)

20 30 40

1997 Jul 01 47

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

MBC212

100%

92%

30%

16 %

for negative modulation

100% = 10% rest carrier

Fig.14 Video output signal.

handbook, full pagewidth

MBC211

100%

86%

72%

58%

44%

30%

646056524844403632221210 26 µs

Fig.15 Test signal waveform.

1997 Jul 01 48

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

handbook, full pagewidth

MBC213

SC CC PC

30 dB

13.2 dB

3.2 dB

SC CC PC

30 dB

13.2 dB

10 dB

BLUE YELLOW

Fig.16 Test set-up intermodulation.

Input signal conditions: SC = Sound Carrier; CC = Colour Carrier; PC = Picture Carrier.

All amplitudes with respect to top sync level.

Value at 0.92 or 1.1 MHz 20 log VOat 3.58 or 4.4 MHz

VOat 0.92 or 1.1 MHz

------------------------------------------------------------ 3.6 dB+=

Value at 2.66 or 3.3 MHz 20 log VOat 3.58 or 4.4 MHz

VOat 2.66 or 3.3 MHz

------------------------------------------------------------

MBC210

ATTENUATOR SPECTRUM

ANALYZER

TEST

CIRCUIT

SC Σ

gain setting

adjusted for blue

1997 Jul 01 49

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

TEST AND APPLICATION INFORMATION

Fig.17 Input/output relationship of the black level stretcher.

handbook, halfpage

40 80 10060200

100

−20

MGK297

in (IRE)

out

(IRE)

A-A = maximum black level shift; B-B = level shift at 15% of peak white.

Fig.18 Simplified application diagram.

handbook, full pagewidth

MGK302

3.5

MHz

4.4

MHz

SAW

FILTER

from

tuner

TDA8395

TDA837x

TDA4665

BAND-

PASS

TRAP

4316 11

54 50 51 39 47 48 57

46 45

35 36 37 38

10 27 17 18

1997 Jul 01 50

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

East-West output stage

In order to obtain correct tracking of the vertical and horizontal EHT correction, the E-W output stage should be

dimensioned as illustrated in Fig.19.

Resistor Rew determines the gain of the E-W output stage. Resistor Rc determines the reference current for both the

vertical sawtooth generator and the geometry processor. The preferred value of Rc is 39 kΩ which results in a reference

current of 100 µA (Vref = 3.9 V).

The value of Rew must be:

Example: With Vref = 3.9 V; Rc=39kΩ and Vscan = 120 V then Rew ≈68 kΩ.

Control ranges of geometry control parameters

Typical case curves; Rc=39kΩ, CSAW = 100 nF.

Figures 20 to 23 are valid for all types. Figures 24 to 27 are valid for TDA8375 and TDA8377.

Rew RcVscan

18 Vref

-----------------------

×=

Fig.19 East-West output stage.

handbook, full pagewidth

TDA8375

TDA8377

52 51

45 DIODE

MODULATOR

MGK300

100 nF

(5%)

Csaw

39 kΩ

(2%)

Rew

Vref

VEW

Vsupply

E-W

OUTPUT

STAGE

HORIZONTAL

DEFLECTION

STAGE

E-W drive

Vscan

1997 Jul 01 51

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

Fig.20 Control range of vertical amplitude.

VA = 0, 31H and 63H; VSH = 31H; SC = 0.

handbook, halfpage

−400

time

200

−200

400

−600

600

1/2 t

MGH366

Ivert

(µA)

Fig.21 Control range of vertical slope.

VS = 0, 31H and 63H; VA = 31H; VHS = 31H; SC = 0.

handbook, halfpage

−500

time

100

−300

−100

300

−700

500

1/2 t

MGH367

Ivert

(µA)

Fig.22 Control range of vertical shift.

VSH = 0, 31H and 63H; VA = 31H; SC = 0.

handbook, halfpage

−400

time

200

−200

400

−600

600

1/2 t

MGH368

Ivert

(µA)

Fig.23 Control range of S-correction.

SC = 0, 31H and 63H; VA = 31H; VHS = 31H.

Picture height does not change with S-correction for

nominal vertical amplitude (VA = 31).

handbook, halfpage

−400

time

200

−200

400

−600

600

1/2 t

MGH369

Ivert

(µA)

1997 Jul 01 52

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

Fig.24 Control range of E-W width.

EW = 0, 31H and 63H; PW = 31H; CP = 31H.

handbook, halfpage

200

time

800

400

1000

600

1200

01/2 t

MBK039

Iew

(µA)

Fig.25 Control range of E-W parabola/width ratio.

PW = 0, 31H and 63H; EW = 31H; CP = 31H.

handbook, halfpage

time

800

300

600

400

700

500

900

1/2 t

MBK040

Iew

(µA)

Fig.26 Control range of E-W corner/parabola ratio.

CP = 0, 31H and 63H; EW = 31H; PW = 63H.

handbook, halfpage

time

800

300

600

400

700

500

900

1/2 t

MBK041

Iew

(µA)

Fig.27 Control range of E-W trapezium correction.

TC = 0, 31H and 63H; EW = 31H; PW = 31H; CP = 0.

handbook, halfpage

time

300

600

400

700

500

1/2 t

MBK042

Iew

(µA)

1997 Jul 01 53

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled economy PAL/NTSC

and NTSC TV-processors TDA837x family

Adjustment of geometry control parameters

The deflection processor of the TDA8373 and TDA8374

offers 5 control parameters for picture alignment:

•Vertical picture alignment

– S-correction

– vertical amplitude

– vertical slope

– vertical shift

– Horizontal shift alignment.

The TDA8375, TDA8377, TDA8375A and TDA8377A offer

in addition the following functions for horizontal alignment:

•E-W width

•E-W parabola/width

•E-W corner/parabola

•E-W trapezium correction.

It is important to notice that the ICs are designed for use

with a DC-coupled vertical deflection stage. This is the

reason why a vertical linearity alignment is not necessary

(and, therefore, not available).

For a particular combination of picture tube type and

vertical output stage and E-W output stage, it is

determined which are the required values for the settings

of S-correction. These parameters can be preset via the

I2C-bus and do not need any additional adjustment.

The remainder of the parameters are preset with the

mid-value of their control range (i.e. 1FH), or with the

values obtained by previous TV set adjustments.

The vertical shift control is intended for compensation of

off-sets in the external vertical output stage or in the

picture tube. It can be shown that without compensation

these off-sets will result in a certain linearity error,

especially with picture tubes that need large S-correction.

The total linearity error is in 1st order approximation

proportional to the value of the off-set and to the square of

the S-correction needed. The necessity to use the vertical

shift alignment depends on the expected off-sets in vertical

output stage and picture tube, on the required value of the

S-correction and on the demands upon vertical linearity.

For adjustment of the vertical shift and vertical slope

independent of each other, a special service blanking

mode can be entered by setting the SBL bit HIGH. In this

mode the RGB outputs are blanked during the second half

of the picture. There are 2 different methods for alignment

of the picture in vertical direction. Both methods make use

of the service blanking mode.

The first method is recommended for picture tubes that

have a marking for the middle of the screen. With the

vertical shift control the last line of the visible picture is

positioned exactly in the middle of the screen. After this

adjustment the vertical shift should not be changed.

The top of the picture is placed by adjusting the vertical

amplitude and the bottom by adjusting the vertical slope.

The second method is recommended for picture tubes that

have no marking for the middle of the screen. For this

method a video signal is required in which the middle of the

picture is indicated (e.g. the white line in the circle test

pattern). With the vertical slope control the beginning of the

blanking is positioned exactly on the middle of the picture.

Then the top and bottom of the picture are placed

symmetrically with respect to the middle of the screen by

adjustment of the vertical amplitude and vertical shift. After

this adjustment the vertical shift has the correct setting and

should not be changed.

If the vertical shift alignment is not required VSH should be

set to its mid-value (i.e. VSH = 1FH). The top of the picture

is then placed by adjusting the vertical amplitude and the

bottom by adjusting the vertical slope. After the vertical

picture alignment the picture is positioned in the horizontal

direction by adjusting the horizontal shift.

To obtain the full range of the vertical zoom function with

the TDA8375 and TDA8377 the adjustment of the vertical

geometry should be carried out at a nominal setting of the

zoom DAC at position 19H.

1997 Jul 01 54

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Fig.28 Sawtooth waveform and blanking pulse of the TDA8375 and TDA8377.

handbook, full pagewidth

75%

100%

138%

−10

−20

−30

−40

−50

−60

time

top

picture

bottom

picture

blanking for exponential 138%

1/2 t

vertical

position

(%)

MGK296

Fig.29 AVL characteristics of the TDA8373 and TDA8374 for 3.5 MHz standard.

handbook, halfpage

104

103

102

MGK298

10 102103104

audio

output

(mV) (RMS)

de-emphasis (mV) (RMS)

25 kHz (norm)

6 dB

AVL on

AVL off

14 dB

See Table 58.

1997 Jul 01 55

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Table 58 Explanation to Fig.29

Table 59 Explanation to Fig.30

A B C D DESCRIPTION

50 100 250 500 de-emphasis pin 55 [mV (RMS)]

5 10 25 50 FM swing (kHz)

50 100 250 500 AVL input [mV (RMS)]

100 200 500 1000 external input [mV (RMS)]

A B C D DESCRIPTION

100 200 250 1000 de-emphasis pin 55 [mV (RMS)]

10 20 25 100 FM swing (kHz)

50 100 125 500 AVL input [mV (RMS)]

100 200 250 1000 external input [mV (RMS)]

Fig.30 AVL characteristics of the TDA8374 for 4.4 MHz standard.

handbook, halfpage

104

103

102

MGK299

10 102103104

audio

output

(mV) (RMS)

de-emphasis (mV) (RMS)

50 kHz (norm)

BA ED

AVL on

AVL off

6 dB

14 dB

See Table 59.

1997 Jul 01 56

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INTERNAL PIN CONFIGURATION

Fig.31 Pin 1.

MGK303

TSTCON

2.2 kΩ300 Ω10 pF

sound limiter

plus demodulator

kΩ15

kΩ

Fig.32 Pin 2.

MGK304

2100 Ω

4 V

sound switch

plus amplifier

kΩ

Fig.33 Pins 3, 4 and 5.

MGK305

3 4

kΩ6

kΩ

Fig.34 Pin 6.

MGK306

200

Ω

Fig.35 Pin 7.

MGK343

300 Ω

5 V

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Fig.36 Pin 8.

MGK307

300 Ω

30 Ω

5 V

Fig.37 Pin 9.

MGK308

Fig.38 Pin 10.

MGK309

30 kΩ

100

kΩ

100

kΩ

DECODER PIP

TXT

10 pF

TSTCON

300 Ω

Vref

Fig.39 Pins 11, 13 and 17.

MGK310

100 Ω

decoder

chroma switch

output

decoder

luma sync switch control

DUMMY

CLAMP

11, 13, 17

Fig.40 Pins 12 and 37.

MGK344

analog supply

12, 37

Fig.41 Pin 14.

MGK333

14 GND1

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Fig.42 Pin 15.

MGK312

2 kΩ

300 Ω

sound

amplifier

100 µA

Fig.43 Pin 16.

MGK313

16 50 kΩ

300 Ω

−100 µA/ +100 µA

10 pF

filter

tuning

Fig.44 Pin 18.

MGK314

10 pF

Vref = 4 V

200

µA10

µA

18 14 kΩ

+V/I

Fig.45 Pins 19, 20 and 21.

MGK315

100 Ω

2 mA

19, 20, 21

Fig.46 Pin 22.

MGK316

peak white

limiting

Vref1

Vref2

200 µA

22 1 kΩ

kΩ

brightness

control

contrast

control

4 V

vertical

guard

1997 Jul 01 59

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Fig.47 Pins 23, 24 and 25.

MGK317

50 µA

300 Ω

6 V

23, 24, 25

Fig.48 Pin 26.

MGK318

26 300 Ω

4 V

insertion

blanking

Fig.49 Pin 27.

MGK319

10 Ω

0.2 µA

6 V

Fig.50 Pin 28.

MGK320

10 Ω

500 µA

500 Ω

Fig.51 Pins 29 and 30.

MGK321

100 Ω

29, 30

Fig.52 Pins 31 and 32.

MGK322

100 Ω

2.5 V

31, 32

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Fig.53 Pin 33.

MGK323

2.7 V

30 Ω

250 µA

Fig.54 Pins 34 and 35.

MGK324

3.7 V

pin 34: crystal = 3.58 MHz; R = 1 kΩ

pin 35: crystal = 4.43 MHz; R = 1 kΩ

34, 35

Fig.55 Pin 36.

MGK325

100 Ω

3.8 V

Fig.56 Pin 38.

MGK326

400 Ω

600

µA

38 100 Ω

TSTCON

Fig.57 Pin 39.

MGK327

Fig.58 Pin 40.

MGK328

30 Ω

protection

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Fig.59 Pin 41.

MGK329

2 µA

30 Ω

burstkey

V blank

5.3 V

3 V

2.9 V

Fig.60 Pin 42.

MGK330

300 Ω42

5.3 V

flash

level

Fig.61 Pin 43.

MGK331

HOSC

300 Ω300 Ω

++J

3.3 V 4.7 V

(NC plus POR)

4 V 4 V

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Fig.62 Pin 44.

MGK311

44 GND2, connected to substrate

Fig.63 Pin 45.

MGK332

600 Ω

Fig.64 Pins 46 and 47.

MGK334

46, 47

Fig.65 Pins 48 and 49.

MGK335

100 Ω

1 kΩ

100 Ω

2.4 pF

IF amplifier

Fig.66 Pin 50.

MGK336

300 Ω

2 V

3.9 V

XPR

Fig.67 Pin 51.

MGK337

1997 Jul 01 63

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Fig.68 Pin 52.

MGK338

Iref

Vref

Fig.69 Pin 53.

MGK339

clamp

1.5

µA600

µA

500

gating

AGC det

LSPEED

NEGMOD

Fig.70 Pin 54.

MGK340

TSTCON

Fig.71 Pin 55.

MGK341

55 sound switch

plus amplifier

sound

demodulator

3 V

20 kΩ

1997 Jul 01 64

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Fig.72 Pin 56.

MGK342

stabilisation

100 µA

−50/50 µA

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PACKAGE OUTLINES

UNIT A1A2A3bpcE

(1) eH

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

mm 0.36

0.10 2.87

2.57 0.25 0.50

0.35 0.25

0.13 14.1

13.9 118.2

17.6 1.43

1.23 1.2

0.8 7

0.2 0.10.21.95

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

1.0

0.6

SOT319-1 92-11-17

95-02-04

D(1) (1)(1)

20.1

19.9

24.2

23.6

1.2

0.8

EA1

detail X

(A )

HA2

vMB

vMA

52 51 33 32

0 5 10 mm

scale

pin 1 index

64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height

QFP64: plastic quad flat package; SOT319-1

max.

3.3

1997 Jul 01 66

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UNIT b1cEe M

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

DIMENSIONS (mm are the original dimensions)

SOT400-1 95-12-06

bmax.

1.3

0.8 0.53

0.40 0.32

0.23 52.4

51.6 14.0

13.6 3.2

2.8 0.181.778 15.24 15.80

15.24 17.15

15.90 2.3

5.08 0.51 4.0

c(e )

seating plane

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

(1) (1)

D(1)

pin 1 index

max. 12

min. A

max.

SDIP56: plastic shrink dual in-line package; 56 leads (600 mil) SOT400-1

1997 Jul 01 67

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SOLDERING

Introduction

There is no soldering method that is ideal for all IC

packages. Wave soldering is often preferred when

through-hole and surface mounted components are mixed

on one printed-circuit board. However, wave soldering is

not always suitable for surface mounted ICs, or for

printed-circuits with high population densities. In these

situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our

“IC Package Databook”

(order code 9398 652 90011).

SDIP

SOLDERING BY DIPPING OR BY WAVE

The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact

with the joint for more than 5 seconds. The total contact

time of successive solder waves must not exceed

5 seconds.

The device may be mounted up to the seating plane, but

the temperature of the plastic body must not exceed the

specified maximum storage temperature (Tstg max). If the

printed-circuit board has been pre-heated, forced cooling

may be necessary immediately after soldering to keep the

temperature within the permissible limit.

REPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the

lead(s) of the package, below the seating plane or not

more than 2 mm above it. If the temperature of the

soldering iron bit is less than 300 °C it may remain in

contact for up to 10 seconds. If the bit temperature is

between 300 and 400 °C, contact may be up to 5 seconds.

QFP

REFLOW SOLDERING

Reflow soldering techniques are suitable for all QFP

packages.

The choice of heating method may be influenced by larger

plastic QFP packages (44 leads, or more). If infrared or

vapour phase heating is used and the large packages are

not absolutely dry (less than 0.1% moisture content by

weight), vaporization of the small amount of moisture in

them can cause cracking of the plastic body. For more

information, refer to the Drypack chapter in our

“Quality

Reference Handbook”

(order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,

thermal conduction by heated belt. Dwell times vary from

50 to 300 seconds depending on heating method. Typical

reflow temperatures range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate

the binding agent. Preheat for 45 minutes at 45 °C.

WAVE SOLDERING

Wave soldering is not recommended for QFP packages.

This is because of the likelihood of solder bridging due to

closely-spaced leads and the possibility of incomplete

solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following

conditions must be observed:

•A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)

soldering technique should be used.

•The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves

downstream and at the side corners.

Even with these conditions, do not consider wave

soldering the following packages: QFP52 (SOT379-1),

QFP100 (SOT317-1), QFP100 (SOT317-2),

QFP100 (SOT382-1) or QFP160 (SOT322-1).

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured. Maximum permissible solder

temperature is 260 °C, and maximum duration of package

immersion in solder is 10 seconds, if cooled to less than

150 °C within 6 seconds. Typical dwell time is 4 seconds

at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

REPAIRING SOLDERED JOINTS

Fix the component by first soldering two diagonally-

opposite end leads. Use only a low voltage soldering iron

(less than 24 V) applied to the flat part of the lead. Contact

time must be limited to 10 seconds at up to 300 °C. When

using a dedicated tool, all other leads can be soldered in

one operation within 2 to 5 seconds between

270 and 320 °C.

1997 Jul 01 68

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DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

PURCHASE OF PHILIPS I2C COMPONENTS

Data sheet status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development.

Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later.

Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Short-form speciﬁcation The data in this speciﬁcation is extracted from a full data sheet with the same type

number and title. For detailed information see the relevant data sheet or data handbook.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the

components in the I2C system provided the system conforms to the I2C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

1997 Jul 01 69

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and NTSC TV-processors TDA837x family

NOTES

1997 Jul 01 70

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and NTSC TV-processors TDA837x family

NOTES

1997 Jul 01 71

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and NTSC TV-processors TDA837x family

NOTES

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Printed in The Netherlands 547047/1200/01/pp72 Date of release: 1997 Jul 01 Document order number: 9397 750 01808