128K x 8 Static RAM
fax id: 1072
CY62128
PRELIMINARY
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 1996 - Re vised November 1996
1CY62128
Features
• 4.5V − 5.5V operation
• CMOS for optimum speed/power
• Low active power (7 0 ns, LL version)
—330 mW (max.) (6 0 mA)
• Low standby power (70 ns, LL version)
—110 µW (max.) ( 20 µA)
• Automatic power-down when deselected
• TTL-compatibl e inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options
Functional Description
The CY62128 is a high-performance CMOS static RAM orga-
nized as 131,072 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enab le (CE 1), an active HIGH
chip enable (CE2), an active LOW output enable (OE), and
three-state drivers. T his device ha s an automatic power-down
feature that reduces power consumption by more than 75%
when deselected.
Writing to the device is accomplished by taking chip enable
one (CE1) and write enable (WE) inputs LOW and chip enable
two (CE2) input HIGH. Data on the eigh t I /O pins ( I/O0 through
I/O7) is then written into the location specified on the address
pins (A 0 through A16).
Reading from the device is accomplished by taking chip en-
able one (CE1) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CE2) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW) , the outputs ar e disabled (OE HIGH), or
during a write operation (CE1 LOW , CE2 HIGH, and WE LOW).
The CY62128 is available in a standard 400-mil-wide SOJ,
525-mil wide (450-mil-wide body width) SOIC and 32-pin
TSOP type I.
Logic Block Diagram Pin Configurations
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
CE2
I/O1
I/O2
I/O3
512 x 256 x 8
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
CE1
62128-1
62128-2
1
2
3
4
5
6
7
8
9
10
11
14 19
20
24
23
22
21
25
28
27
26
Top View
SOJ / SOIC
12
13
29
32
31
30
16
15 17
18
GND
A16
A14
A12
A7
A6
A5
A4
A3
WE
VCC
A15
A13
A8
A9
I/O7
I/O6
I/O5
I/O4
A2
NC
I/O0
I/O1
I/O2
CE1
OE
A10
I/O3
A1
A0
A11
CE2
A6
A7
A16
A14
A12
WE
VCC
A4
A13
A8
A9OE
TSOP I
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O2
I/O1
GND
I/O7
I/O4
I/O5
I/O6
I/O0
CE1
A11
A517
18
8
9
10
11
12
13
14
15
16
CE2
A15
NC
A10
I/O3
A1
A0
A3
A2
CY62128
2
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature . ................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Volt a ge on VCC to Relative GND[1] ....–0.5V to +7.0V
DC Voltage Applied to Output s
in High Z State[1]..................................... –0.5V to VCC +0.5V
DC Input Voltage[1].................................. –0.5V to VCC +0.5V
Current into Output s (LOW) ................ ........................20 mA
Static Discharge Voltage ...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Selectio n G uide
CY62128–55 CY62128–70
Maximum Access Time (ns) 55 70
M aximum Operating Current Commercial 115 mA 110 mA
L 70 mA 60 mA
LL 70 mA 60 mA
Maxim um CMOS Standby Current Commercial 10 mA 10 mA
L100 µA 100 µA
LL 20 µA 20 µA
Operating Range
Range Ambient
Temperature[2] VCC
Commercial 0°C to +70°C 5V ± 10%
Electrical Characteristics Over the Operating Range[3]
62128–55 62128–70
Parameter Description Test Conditions Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = – 1.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 2.1mA 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC+
0.3 2.2 VCC+
0.3 V
VIL Input LOW Voltage[1] –0.3 0.8 –0.3 0.8 V
IIX In put Load Current GND ≤ VI ≤ VCC –1 +1 –1 +1 µA
IOZ Outp ut Leakage Current GND ≤ VI ≤ VCC, Output Disabled –5 +5 –5 +5 µA
IOS Output Short Circuit Current[4] VCC = Max., VOUT = GND –300 –300 mA
ICC VCC Operating
Supply Current VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
Com’l 115 110 mA
L70 60 mA
LL 70 60 mA
ISB1 Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE 1 ≥ VIH
or CE2 < VIL,
VIN ≥ VIH or
VIN ≤ VIL, f = fMAX
Com’l 25 25 mA
L10 10 mA
LL 2 2 mA
ISB2 Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC,
CE1 ≥ VCC – 0.3V,
or CE2 ≤ 0.3V,
VIN ≥ VCC – 0.3V,
or VIN ≤ 0.3V, f=0
Com’l 10 10 mA
L100 100 µA
LL 20 20 µA
Shaded areas contain advance information
Notes:
1. VIL (mi n.) = – 2.0V fo r pu lse dura tions of less tha n 20 ns.
2. TA is the “ins tant o n” case temper ature.
3. See the last page of this specification for Group A subgroup testing information.
4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
CY62128
3
PRELIMINARY
Capacitance[5]
Parameter Description Test C onditions Max. Unit
CIN Input Capacitance TA = 25 °C, f = 1 MHz,
VCC = 5.0V 9pF
COUT Output C apacitance 9 pF
AC Test Loads and Waveforms
Switching Characteristics[3,6] Over the Operating Range
62128–55 62128–70
Parameter Description Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 55 70 ns
tAA Address to Data Valid 55 70 ns
tOHA Data Hold from Address Change 5 5 ns
tACE CE1 LOW to Data Valid, CE2 HIGH to Data Valid 55 70 ns
tDOE OE LOW to Data Valid 20 35 ns
tLZOE OE LOW to Low Z 0 0 ns
tHZOE OE HIGH to High Z[7, 8] 20 25 ns
tLZCE CE1 LOW to Low Z, CE2 HIGH to Low Z[8] 5 5 ns
tHZCE CE1 HIGH to Hig h Z, CE2 LOW to High Z[7, 8] 20 25 ns
tPU CE1 LOW to Power-Up, CE2 HIGH to Power-Up 0 0 ns
tPD CE1 HIGH to Power-Down, CE2 LOW to Power- Down 55 70 ns
WRITE CYCLE[9]
tWC Write Cycle Time 55 70 ns
tSCE CE1 LOW to Write End, CE2 HIGH to Write End 45 60 ns
tAW Address Set-Up to Write E n d 45 60 ns
tHA Addre ss H old from Write E nd 0 0 ns
tSA Address Set-Up to Write Start 0 0 ns
tPWE WE Pulse W idth 45 50 ns
tSD Data Set-Up to Write End 45 55 ns
Shaded areas contain advance information
Notes:
5. Tested initially and after any design or process changes that may affect these parameters.
6. Test conditions assume s ignal trans ition time of 5ns or less, timing r eference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100 pF load capaci tance.
7. tHZOE, tHZCE, and tHZWE are s pecifi ed with a load capacita nce of 5 pF as i n part ( b) of AC Test Loads. Tran sition is measured ±500 mV from s teady-s tate voltag e.
8. At any given temperature and voltage condition, tHZCE is l ess t han tLZCE, tHZOE is less tha n tLZOE, and tHZWE is less th an tLZWE for any g iven device.
9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW . CE1 and WE mus t be LO W and CE2 HIGH to initiate a write,
and the tr ansi tion of an y of th ese s ignals c an te rminate the wr ite. T he inp ut dat a set-up a nd hol d timing s hould be refer enced t o th e leading edge o f the s ignal that termi nates
the write .
62128-3 62128-4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT 100 pF
INCLUDING
JIG AN D
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
≤ 5ns ≤5ns
OUTPUT
R 1 1800 ΩR1 1800 Ω
R2
990ΩR2
990Ω
639Ω
Equivalent to: THÉVENIN EQUIVALENT
1.77V
CY62128
4
PRELIMINARY
tHD Data Hold from Write E nd 0 0 ns
tLZWE WE HIGH to Low Z[8] 5 5 ns
tHZWE WE LOW to High Z[7,8] 20 25 ns
Shaded area contains advanced information.
Switching Characteristics[3,6] Over the Operating Range (continued)
62128–55 62128–70
Parameter Description Min. Max. Min. Max. Unit
Switching Waveforms
Read Cycle No.1[10,11]
Read Cycle No. 2 (OE Controlled)[11,12]
Notes:
1 0 . Device is co ntinuously selected. OE, CE1 = VIL, CE2 = VIH.
11. WE is HI GH for read cy cle.
12. Address valid prior to or coincident with CE 1 t ransition LOW an d CE2 t ransition HIGH.
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
62128-5
ADDRESS
DATA OUT
62128-6
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
HIGH
OE
CE1
ICC
ISB
IMPEDANCE
ADDRESS
CE2
DATA OUT
VCC
SUPPLY
CURRENT
CY62128
5
PRELIMINARY
Write Cycle No. 1 (CE1 or CE 2 Controlled)[13,14]
Write Cycle No. 2 (W E Controlled, OE HIGH During Write)[13,14]
Notes:
13. Data I/O is high impedance if OE = VIH.
14. If CE1 goes HIGH or CE2 goes LOW si multaneo usly w ith WE going H IGH, t he out put r emains in a hi gh-impedanc e state.
15. During this period the I/Os are in the output state and input s ignals should not be applied.
Switching Waveforms (continued)
62128-7
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
tSCE
CE1
ADDRESS
CE2
WE
DATA I/O
62128-8
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tSCE
tWC
tHZOE
DATAIN VALID
CE1
ADDRESS
CE2
WE
DATA I/O
OE
NOTE15
CY62128
6
PRELIMINARY
Document #: 38–00524
Write Cycle No.3 (WE Controlled, OE LOW)[13,14]
Switching Waveforms (continued)
62128-9
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tSCE
tWC
tHZWE
CE1
ADDRESS
CE2
WE
DATAI/O NOTE 15
Tr uth Tabl e
CE1CE2OE WE I/O0 – I/O 7Mode Power
H X X X High Z Power-Down Standby (ISB)
X L X X High Z Power-Down Standby (ISB)
L H L H Data Out Read Active (ICC)
L H X L Data In Write Active (ICC)
L H H H High Z Selected, Outputs Disabled Active (ICC)
Orde rin g Inf orm a tio n
Speed
(ns) Or deri ng Code Package
Name Package Type Operating
Range
55 CY62128–55VC V33 32-Lead ( 400-Mil) Molded SOJ Commercial
CY62128–55SC S34 32- Lead (450-Mil) Molded SOIC
CY62128−55ZC Z32 32-Lead TSOP TypeI
70 CY62128–70VC V33 32-Lead ( 400-Mil) Molded SOJ Commercial
CY62128–70SC S34 32- Lead (450-Mil) Molded SOIC
CY62128−70ZC Z32 32-Lead TSOP Type I
CY62128L−70SC S34 32-Lead (450-Mil) Molded SOIC
CY62128L−70ZC Z32 32-Lead TSOP Type I
CY62128LL−70SC S34 32-Lead (450-Mil) Molded SOIC
CY62128LL−70ZC Z32 32-Lead TSOP Type I
Shaded area contains advanced information.
CY62128
7
PRELIMINARY
Package Diagrams
32- Le ad (450 Mil) Molded SOIC S34
32-Lead Thin Small Outline Package Z32
CY62128
PRELIMINARY
© Cypress Semiconductor Corporation, 1996. T he information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry othe r than circui try embodi ed in a Cypress Semi conductor prod uct. Nor do es it convey or im ply an y li cens e under p atent or other rights . Cypress Semi conductor does not authori ze
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems appli cation implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagrams (con tinue d)
32-Lead (400-Mil) Molded SOJ V33
