DP83222 - National Semiconductor

TL/F/11885

DP83222 CYCLONE Twisted Pair FDDI Stream Cipher Device

August 1994

DP83222

CYCLONETM Twisted Pair FDDI Stream Cipher Device

General Description

The DP83222 CYCLONE Stream Cipher Scrambler/

Descrambler Device is an integrated circuit designed to in-

terface directly with the serial bit streams of a Twisted Pair

FDDI PMD. The DP83222 is designed to be fully compatible

with the National Semiconductor FDDI Chip Sets, including

the DP83223 TWISTERTM (Twisted Pair Transceiver). The

DP83222 requires a 125 MHz Transmit Clock and corre-

sponding Receive Clock for synchronous data scrambling

and descrambling. The DP83222 is compliant with the ANSI

X3T9.5 TP-PMD draft standard and is required for the re-

duction of EMI emission over unshielded media. The

DP83222 is specified to work in conjunction with existing

twisted pair transceiver signalling schemes such as MLT-3

or NRZI and enables high bandwidth transmission over

Twisted Pair copper media.

Features

YEnables 100 Mbps FDDI signalling over Category 5

Unshielded Twisted Pair (UTP) cable and Type 1

Shielded Twisted Pair (STP)

YReduces EMI emissions over Twisted Pair media

YCompatible with ANSI X3T9.5 TP-PMD Standard

YRequires a single a5V supply

YTransparent mode of operation

YFlexible NRZ and NRZI format options

YAdvanced BiCMOS process

YSignal Detect and Clock Detect inputs provided for en-

hanced functionality

YSuitable for Fiber Optic PMD replacement applications

Block Diagram

TL/F/11885–1

FIGURE 1. DP83222 Block Diagram

CYCLONETM, CDDTM, CDLTM , PLAYERTM, PLAYERaTM and TWISTERTM are trademarks of National Semiconductor Corporation.

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

1.0 Functional Description

1.1 OVERVIEW

The DP83222 Stream Cipher Scrambler/Descrambler De-

vice consists of 7 major functional blocks as shown in

Fig-

ure 1

The Scrambler section is comprised of an Encoder, a De-

coder, a linear Feedback Shift Register with support gates

and the Control Logic block. The Decoder accepts synchro-

nous differential clock and data (data can be either NRZ or

NRZI formatted) from the Physical Layer and delivers NRZ

data to the 11-bit LFSR block.

The LFSR scrambler and support gates exclusive-OR the

incoming unscrambled data stream with the resultant data

stream of the LFSR. This data becomes the scrambled data

stream. The Encoder accepts scrambled data from the

11-bit LFSR block and delivers either NRZ or NRZI asyn-

chronous data to the external PMD Transceiver.

The Control Logic block functions as the Encode/Decode

switch, selecting NRZ or NRZI formats, and also controls

the disabling of the scrambler for use in transparent mode.

The Descrambler section is comprised of an Encoder, a De-

coder, the Descrambler Logic block and the Control Logic

block (shared with the Scrambler section). The Encoder and

Decoder blocks work in conjunction with the corresponding

blocks within the Scrambler section. A truth table describing

the available encode/decode format algorithms can be

found in Table II.

The Stream Cipher Logic functions as a ‘‘Sample and Hold’’

state machine that, when in sample mode, continuously

evaluates incoming words by searching for identifiable FDDI

line states. When valid line states are detected, the Stream

Cipher enters the hold state. During the hold state, an 11-bit

LFSR operates to descramble the incoming data completing

the translation. A more in-depth analysis of the stream ci-

pher algorithm is given in Section 1.3.

The descrambled data is accompanied by a time aligned

version of the descramble clock allowing for synchronous

delivery of the data to the Physical Layer device.

Finally, the Control Logic block, which is shared by both the

Scramble and Descramble sections, controls several func-

tions. The Encode/Decode switch controls the selection of

NRZ or NRZI conversion as well as the transparent mode of

operation. Clock Detect (CD) and Signal Detect (SD) inputs,

also part of the Control Logic block, control certain stream

cipher logic modes.

1.2 DATA SCRAMBLING

A more in-depth analysis of the scrambler function, as illus-

trated in

Figure 2

, reveals a fairly elementary design. The

scrambler logic requires that the incoming data be NRZ for-

matted, which the DP83222 accomplishes via the input de-

coder. After being decoded to NRZ, the data, UD, is routed

to one input of the Exclusive OR gate, XOR-A. The other

input to XOR-A is connected to the output of a closed loop

11-bit Linear Feedback Shift Register (LFSR).

ed to another XOR function, XOR-B, is performed. The re-

sult of XOR-B, LDS, is then routed to the input of Register S

(this circuit forms a linear feedback shift register, LFSR).

LDS is also routed to the other input of XOR-A which, in

turn, outputs the final scrambled data stream SD. The data

sequences shown in

Figure 2

are defined as:

UD eUnscrambled Data (originating from PHY)

LDS eScrambler LFSR Feedback data

SD e(LFSRÐS xor UD)

TL/F/11885–2

FIGURE 2. Stream Cipher Scrambler Logic

1.0 Functional Description (Continued)

1.3 STREAM CIPHER (DATA DESCRAMBLING)

The analysis of the Stream Cipher descrambler design is

somewhat more complex than the scrambler circuit shown

below. The concept of the stream cipher is based upon hy-

pothetical comparison. Because FDDI signalling includes

known line states comprised of unique 5-bit patterns, it is

possible to utilize these patterns as comparison information

when analyzing the incoming scrambled datastream.

Four FDDI line state patterns are commonly transmitted

within an FDDI ring during ring initialization and sustained

ring operation. Three of these line state patterns, HALT,

MASTER and QUIET, are used during PCM initialization and

ring fault indication. The fourth pattern, the IDLE, is em-

ployed during PCM initialization and normal ring operation.

The stream cipher operates in two modes, Sample mode

and Hold mode. While it is possible to become synchronized

in the Sample mode during the reception of HALT,

MASTER or QUIET patterns, synchronization is lost as soon

as anything other than these patterns are received. It is only

the IDLE line state that allows synchronization and asser-

tion of the Hold mode. The Hold mode allows fully synchro-

nized descrambling of all incoming data regardless of sym-

bol type. The IDLE line state is both sufficient and required

for assertion of the Hold mode of synchronization due to

frequent interspersion among normal FDDI traffic such as

Tokens and Frames.

The IDLE line state pattern will be analyzed for this exam-

ple. The IDLE symbol pair, in the NRZ 5B format, becomes

ten ones or 11111 11111. The analysis begins by examining

the logic design provided in

Figure 3

. The NRZ scrambled

data, SD, is routed to Register A which is an 11-bit serial

shift register with taps at registers 9 and 11. Taps 9 and 11

are input to the XOR-C gate which outputs the SDÊdata-

stream. SDÊis connected to one input of XOR-D. The other

input to XOR-D is the original SD datastream.

TL/F/11885–3

FIGURE 3. Simplified Stream Cipher Descrambler Logic

1.0 Functional Description (Continued)

The result from XOR-D is a hypothetical data sequence, HD,

that should match the original unscrambled NRZ IDLE data,

barring any noise events. The Boolean progression in

Figure

demonstrates that HD should equal the original unscram-

bled IDLE bits. Over time, Register H is loaded with the

hypothetical data sequence, HD.

Before the Line State Monitor detects a valid IDLE se-

quence (no less than 50 consecutive IDLE bits), the Stream

Cipher logic remains in the Sample mode. While in Sample

mode, the MUX select input ‘‘sel’’ routes the ‘‘inÐsample’’

input to Register B. The MUX input ‘‘inÐsample’’ is con-

nected to the original SD datastream which continuously

loads and updates Register B so that its contents dynami-

cally match Register A. This dynamic match is important as

it ensures synchronization with the LFSR in the scrambler

section.

When the Line State Monitor logic within the Register H

block recognizes sufficient consecutive IDLE bits, it will out-

put a Hold Flag, HF, which controls the MUX feeding Regis-

ter B. When HF becomes true, the MUX ‘‘inÐhold’’ input is

selected which routes the LDD data sequence back into

LFSR (identical to that in the scrambler logic in Section 1.2).

datastream, SD, allowing XOR-F to descramble SD by a

simple XOR function with LDD. To ensure continuous syn-

chronization for valid conditions, the Hold Timer in the Reg-

ister H block will hold HF true for a sufficient time until more

IDLE bits can be decoded which resets the timer. The Hold

Timer time-out period is based on the maximum time, under

normal operation, between IDLE occurrences (l722 ms).

If IDLE symbols cease to be decoded, the Hold Timer will

time out, forcing HF false. This will cause the stream cipher

to fall into the sample mode again awaiting further valid line

states for resynchronization.

This analysis is intended to provide a general understanding

of the mechanisms involved in the stream cipher process.

Some circuit details were omitted for simplification. A more

detailed logical and Boolean description of the stream ci-

pher process is generally available.

1.4 STREAM CIPHER BOOLEAN

The following Boolean analysis supports the stream cipher

logic for IDLE reception example stated herein.

Given that the character ! denotes an exclusive OR func-

tion:

UD[n]eUnscrambled Data (‘‘IDLE’’ ones)

LDS[n]eScrambler’s LFSR feedback data (Pseudo Ran-

dom)

SD[n]escrambled data (LDS[n]!UD

[

]

)

SDÊ[n]eresult of XOR-C

HD[n]eHypothetical Data (SD[n]!SD

[

]

)

HF eHold Flag

LDD[n]eDescrambler LFSR feedback data

DD[n]eDescrambled Data (SD[n]! LDD[n])

Since LDS[n]e(LDS[n-9]! LDS[n-11])

Then SD e(UD[n]! LDS[n])

And Since UD[n]e1...IDLE bits

Then SD[n]eLDS[n]

Since SDÊ[n]eSD[n-9]!SD

[

n-11]

And SDÊ[n]e(LDS[n-9]! LDS[n-11])

Then SDÊ[n]e(LDS[n-9]! LDS[n-11])eLDS[n]

And Since SD[n]eLDS[n]

Then HD[n]e(SD[n]!SD

[

]

)e(LDS[n]! LDS[n])e1...IDLE bits

If HF e1...duetothedetection of sufficient valid IDLE symbols

And LDD[n]eLDS[n]. . . because LDD dynamically tracks LDS

And Since DD[n]e(LDS[n]! SD) e(LDS[n]!UD

[

]! LDS[n])

Then DD[n]eUD[n]

FIGURE 4. Stream Cipher Boolean Analysis

2.0 Pin Table

TABLE I. Pinout Summary

Signal Pin No. Description Type

VCC 7, 16, 28 VCC Supply

GND 1, 4, 11, 15 GND Supply Return

ECLVCC 21 ECLVCC Supply

ECLGND 22 ECLGND Supply Return

EXTVCC 23 External VCC Supply

RXDg3, 2 Received Data from PMD Receiver Diff. 100K ECL In

RXCg5, 6 125 MHz Clock from Receiver PLL Diff. 100K ECL In

TXDg18, 17 Transmit Data from PHY PMRD Diff. 100K ECL In

TXCg13, 14 125 MHz Clock from PHY Diff. 100K ECL In

SCOg19, 20 Scrambled Data to PMD Transmitter Diff. ECL Out

DSCOg27, 26 Descrambled Data to PHY Diff. ECL Out

RXCOg24, 25 Realigned 125 MHz Clock to PHY Diff. ECL Out

ENC0 9 Encode 0 TTL Compatible CMOS In

ENC1 8 Encode 1 TTL Compatible CMOS In

CD 10 Clock Detect Input from Receive PLL TTL Compatible CMOS In

SD 12 Signal Detect Input from PMD Receiver Single-Ended ECL ln

3.0 Pin Definitions and Connection Diagrams

28-Pin PLCC

TL/F/11885–4

FIGURE 5. DP83222 Pinout

VCC (7, 16, 28): Positive power supply for all internal

CMOS circuitry. The Stream Cipher

Scrambler/Descrambler operates from

a single a5V DC power supply.

GND (1, 4, 11, 15): Return path for internal CMOS circuitry

power supply.

ECLVCC (21): Positive power supply for all internal

ECL circuitry. This power supply is in-

tentionally separated from others to re-

duce coupled supply noise.

ECLGND (22): Return path for all internal ECL circuit-

ry. This Power supply return is inten-

tionally separated from others to re-

duce coupled supply noise.

EXTVCC (23): Positive power supply for emitter fol-

lower output circuitry.

RXDg(3, 2): Differential 100K ECL data inputs.

These inputs receive the ECL signals

generated by the National Semicon-

ductor DP83231 Clock Recovery De-

vice (CRDTM) or the DP83256/7VF-AP

Enhanced Physical Layer Devices

(PLAYERaTM).

RXCg(5, 6): Differential 100K ECL clock inputs.

These inputs receive the 125 MHz

clock regenerated by the National

Semiconductor DP83231 Clock Re-

covery Device (CRD), the DP83257VF

or the DP83256VF-AP Enhanced

Physical Layer Devices (PLAYERa).

3.0 Pin Definitions and Connection Diagrams (Continued)

TL/F/11885–5

TL/F/11885–6

FIGURE 6. System Connection Diagrams

TXDg(18, 17): Differential 100K ECL data inputs. This

is the NRZ or NRZI transmit data origi-

nating from the DP83251/5 Physical

Layer Devices (PLAYERTM ), the

DP83256/7VF or the DP83256VF-AP

Enhanced Physical Layer Devices

(PLAYERa).

TXCg(13, 14): Differential 100K ECL clock inputs.

This is the transmit clock generated by

the National Semiconductor Clock

Distribution Device (CDDTM ), the

DP83257 or the DP83256VF-AP

Enhanced Physical Layer Devices

(PLAYERa).

SCOg(19, 20): Differential 100K ECL data outputs.

These outputs present the scrambled

transmit data to the PMD transmitter.

DSCOg(27, 26): Differential 100K ECL outputs. These

outputs present the descrambled data

back to the National Semiconductor

DP83251/55 PLAYER, the DP83256/

7VF or DP83256VF-AP devices

(PLAYERa).

RXCOg(24, 25): Differential 100K ECL clock outputs.

These outputs supply a time aligned

version of RXCg(insuring proper set

and hold times relative to DSCOg)

to the National Semiconductor

DP83251/55 PLAYER, the DP83256/

7VF or DP83256VF-AP devices

(PLAYERa) for clocking-in the final

descrambled data stream, DSCOg.

ENC0, 1 (9, 8): TTL compatible inputs. These pins

work in conjunction with one another

to select different encoding schemes

or to place the DP83222 device into

transparent mode where no scram-

bling or encoding occurs. Refer to Ta-

ble II for details of operation.

CD (10): TTL compatible input data. This input

accepts the CD (Clock Detect) signal

from the receive Clock Recovery cir-

cuit if available. If CD goes to a logic

low level, due to insufficient data edg-

es for clock recovery, the Stream Ci-

pher will switch to Sample mode in or-

der to restart the synchronization pro-

cess.

SD (12): Single-ended ECL data input. This in-

put accepts the SDasignal from the

PMD. If SD goes to a logic low level,

due to loss of signal from the media,

the DP83222 will switch to Sample

mode in order to restart the synchroni-

zation process.

4.0 Electrical Characteristics

4.1 ABSOLUTE MAXIMUM RATINGS

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Logic Power (VCC)

Referenced to GND b0.5V to a6.0V

ECL Power (ECLVCC)

Referenced to ECLGND b0.5V to a6.0V

ECL Output Power (EXTVCC)

Referenced to GND b0.5V to a6.0V

DC Output Current (High) (IECL)b50 mA

ESD (Electrostatic Discharge

Human Body Model) 1500V

Storage Temperature (TSTG)b65§Ctoa

150§C

Lead Temperature (TL)

(Soldering 10 Seconds)

(IR or Vapor) (Phase Reflow) 230§C

4.2 RECOMMENDED OPERATING CONDITIONS

Min Max Units

Supply Voltage (VCC) 4.5 5.5 V

Operating Temperature (TA)0 70 §

Power Dissipation (PD) 690 mW

4.3 DC ELECTRICAL CHARACTERISTICS TAe25§C, VCC e5V

Symbol Parameter Conditions Min Typ Max Units

VIHt TTL High Level Input 2.0 V

VILt TTL Low Level Input 0.8 V

VIHe ECL High Level Input VCC b1165 VCC b880 mV

VILe ECL Low Level Input VCC b1810 VCC b1475 mV

IIH CMOS Current In (Logic High) b10 10 mA

IIL CMOS Current In (Logic Low) b10 10 mA

VOHe ECL High Level Output VCC b1090 VCC b880 mV

VOLe ECL Low Level Output VCC b1850 VCC b1600 mV

ICCecl ECL Supply Current Refer to

Figure 7

65 mA

ICCcmos CMOS Supply Current Refer to

Figure 7

40 mA

ICCext External Supply Current Refer to

Figure 7

95 mA

ICCT Total Supply Current Refer to

Figure 7

200 mA

4.4 AC ELECTRICAL CHARACTERISTICS

The AC Characteristics are specified over the operating range, unless otherwise noted.

Symbol Parameter Conditions Min Typ Max Units

T1TXD/TXC Setup Time Refer to

Figure 8

1.0 ns

T2TXD/TXC Hold Time Refer to

Figure 8

3.0 ns

T3RXD/RXC Setup Time Refer to

Figure 9

3.0 ns

T4RXD/RXC Hold Time Refer to

Figure 9

1.0 ns

T5RXCO/DSCO Change Time Refer to

Figure 10

0.5 3.0 ns

T6RXCOaPulse Width (High) Refer to

Figure 10

4.0 6.0 ns

RXCObPulse Width (Low)

T7Transition Time 20%– 80% Refer to

Figure 11,

(Note 1) 1.5 ns

T8Transition Time 80%– 20% Refer to

Figure 11,

(Note 1) 1.5 ns

T9Scrambler Data Valid TXCaRefer to

Figure 12,

to SCOa(Mode 1) (Note 2), Table 2 (Includes 39 ns

Asynchronous Delay of 15 ns)

T9Scrambler Data Valid TXCaRefer to

Figure 12,

to SCOa(Mode 2) (Note 2), Table 2 (Includes 39 ns

Asynchronous Delay of 15 ns)

T9Scrambler Data Valid TXCaRefer to

Figure 12,

to SCOa(Mode 3) (Note 2), Table 2 (Includes 47 ns

Asynchronous Delay of 15 ns)

T9Scrambler Data Valid TXCaRefer to

Figure 12,

to SCOa(Mode 4) (Note 2), Table 2 (Includes 47 ns

Asynchronous Delay of 15 ns)

T10 Descrambler Data Valid RXCaRefer to

Figure 13,

to DSCOa(Mode 1) (Note 2), Table 2 (Includes 231 ns

Asynchronous Delay of 15 ns)

T10 Descrambler Data Valid RXCaRefer to

Figure 13,

to DSCOa(Mode 2) (Note 2), Table 2 (Includes 239 ns

Asynchronous Delay of 15 ns)

T10 Descrambler Data Valid RXCaRefer to

Figure 13,

to DSCOa(Mode 3) (Note 2), Table 2 (Includes 239 ns

Asynchronous Delay of 15 ns)

T10 Descrambler Data Valid RXCaRefer to

Figure 13,

to DSCOa(Mode 4) (Note 2), Table 2 (Includes 159 ns

Asynchronous Delay of 15 ns)

T10 Stream Cipher Hold Mode From Receipt of First Valid Line, 400 ns

Acquisition Time (Modes 1, 2, 3) Symbol (Includes Async. Delay of 15 ns)

T12 Clock Period TXC eRXC, (Note 3) 8 ns

T13 Total Jitter/Scrambler Referenced to TXCa, (Note 1) 1 ns

T14 Total Jitter/Descrambler Referenced to RXCOa, (Note 1) 1 ns

Note 1: This parameter is not tested, but is assured by correlation with characterization data.

Note 2: Data Valid and Hold Acquisition timing specifications are based on Transmit and Receive clocks of 125 MHz (8 ns period) and include finite asynchronous

delay.

Note 3: The DP83222 is FDDI compliant and will perform to specification over typical g50 ppm variation in clock frequency.

TL/F/11885–7

FIGURE 7. ICC Diagram

TL/F/11885–8

FIGURE 8. TX Set and Hold Times

TL/F/11885–9

FIGURE 9. RX Set and Hold Times

TL/F/11885–10

FIGURE 10. Descramble Change Time

TL/F/11885–11

FIGURE 11. ECL Transition Times

TL/F/11885–12

FIGURE 12. Scrambler Data Valid Time

TL/F/11885–13

FIGURE 13. Descrambler Data Valid Time

TABLE II. Datastream Encoding Truth Table

PHY Interface PMD Interface

Mode ENC1 ENC0 (TXD and SCO) (RXD and DSCO)

Expected Data Format Expected Data Format

1 0 0 NRZI NRZI

2 0 1 NRZI NRZ

3 1 0 NRZ NRZ

411 *Transparent *Transparent

*Transparent mode of operation refers to the ability of the DP83222 to pass a given datastream

through without imposing any scrambling or descrambling on the data.

(i.e. Data into Scrambler eData out of Scrambler also Data into Descrambler eData out of

Descrambler)

TABLE III. Clock Detect and Signal Detect

CD SD Stream-Cipher Logic

0 0 Sample Mode

0 1 Sample Mode

1 0 Sample Mode

11*Stream Cipher Initialization

*Stream-Cipher Initialization refers to the algorithm employed by the Stream Cipher logic which, by

processing the encoded datastream, ultimately enters the Hold state allowing for synchronized

descrambling.

TL/F/11885–14

All ECL signals require a standard ECL termination of 50Xto VCC b2V or equivalent for proper functionality.

FIGURE 14. Typical Schematic for TP-PMD Application

Contact National Semiconductor for

further information relating to PMD

Transceiver availability.

DP83222 CYCLONE Twisted Pair FDDI Stream Cipher Device

Physical Dimensions inches (millimeters)

28-Pin Plastic Leaded Chip Carrier (V)

Order Number DP83222V

NS Package Number V28A

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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life

systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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