NCV7344 High Speed Low Power CAN, CAN FD Transceiver Description The NCV7344 CAN transceiver is the interface between a controller area network (CAN) protocol controller and the physical bus. The transceiver provides differential transmit capability to the bus and differential receive capability to the CAN controller. The NCV7344 is an addition to the CAN high-speed transceiver family complementing NCV734x CAN stand-alone transceivers and previous generations such as AMIS42665, AMIS3066x, etc. The NCV7344 guarantees additional timing parameters to ensure robust communication at data rates beyond 1 Mbps to cope with CAN flexible data rate requirements (CAN FD). These features make the NCV7344 an excellent choice for all types of HS-CAN networks, in nodes that require a low-power mode with wake-up capability via the CAN bus. Features * Compatible with ISO 11898-2:2016 * Specification for Loop Delay Symmetry up to 5 Mbps * VIO pin on NCV7344-3 Version Allowing Direct Interfacing with * * * * * * * * * * * 3 V to 5 V Microcontrollers Very Low Current Standby Mode with Wake-up via the Bus Low Electromagnetic Emission (EME) and High Electromagnetic Immunity Very Low EME without Common-mode (CM) Choke No Disturbance of the Bus Lines with an Un-powered Node Transmit Data (TxD) Dominant Timeout Function Under All Supply Conditions the Chip Behaves Predictably Very High ESD Robustness of Bus Pins, >8 kV System ESD Pulses Thermal Protection Bus Pins Short Circuit Proof to Supply Voltage and Ground Bus Pins Protected Against Transients in an Automotive Environment These are Pb-free Devices Quality www.onsemi.com MARKING DIAGRAM 1 1 1 1 Typical Applications * Automotive * Industrial Networks NV7344xy ALYWG G DFN8 MW SUFFIX CASE 507AB NV7344xy= Specific Device Code x = - or A y = 0 or 3 - = long filter time A = short filter time A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) PIN ASSIGNMENT TxD STB GND CANH VCC CANL RxD NC (-0) VIO (-3) NCV7344D1x (Top View) * Wettable Flank Package for Enhanced Optical Inspection * NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q100 Qualified and PPAP Capable NV7344xy ALYW G G SOIC-8 D1 SUFFIX CASE 751AZ TxD GND VCC RxD EP Flag NCV7344MWx (Top View) STB CANH CANL NC (-0) VIO (-3) ORDERING INFORMATION See detailed ordering and shipping information on page 11 of this data sheet. (c) Semiconductor Components Industries, LLC, 2017 March, 2018 - Rev. 3 1 Publication Order Number: NCV7344/D NCV7344 BLOCK DIAGRAM VCC NC 3 5 NCV7344-0 VCC TxD 1 Thermal shutdown 7 CANH Driver control 6 CANL 7 CANH 6 CANL Timer VCC STB RxD GND 8 Mode & Wake-up control 4 Wake-up Filter COMP 2 COMP Figure 1. NCV7344-0 Block Diagram VCC VIO 3 5 NCV7344-3 VIO TxD Thermal shutdown 1 Timer VIO STB RxD GND 8 4 Mode & Wake-up control Driver control Wake-up Filter COMP 2 COMP Figure 2. NCV7344-3 Block Diagram www.onsemi.com 2 NCV7344 TYPICAL APPLICATION VBAT IN 5V -reg OUT VCC NC VCC 5 STB 7 8 TxD NCV7344 Micro- controller 1 RxD 3 4 CAN BUS 6 2 GND RLT = 60 W CANH CANL RLT = 60 W GND Figure 3. Application Diagram NCV7344-0 VBAT IN 5V -reg OUT IN 3V -reg OUT VIO VCC 5 Micro- controller 8 TxD 1 RxD 4 NCV7344-3 STB 3 2 GND 7 RLT = 60 W CANH CAN BUS 6 CANL RLT = 60 W GND Figure 4. Application Diagram NCV7344-3 Table 1. PIN FUNCTION DESCRIPTION Pin Name Description 1 TxD Transmit data input; low input U dominant driver; internal pull-up current 2 GND Ground 3 VCC Supply voltage 4 RxD Receive data output; dominant transmitter U low output 5 5 NC VIO Not connected. On NCV7344-0 only Digital Input / Output pins and other functions supply voltage. On NCV7344-3 only 6 CANL Low-level CAN bus line (low in dominant mode) 7 CANH High-level CAN bus line (high in dominant mode) 8 STB EP Standby mode control input; internal pull-up current Exposed Pad. Recommended to connect to GND or left floating in application (DFN8 package only). www.onsemi.com 3 NCV7344 FUNCTIONAL DESCRIPTION Operating Modes Overtemperature Detection NCV7344 provides two modes of operation as illustrated in Table 2. These modes are selectable through pin STB. A thermal protection circuit protects the IC from damage by switching off the transmitter if the junction temperature exceeds a value of approximately 180C. Because the transmitter dissipates most of the power, the power dissipation and temperature of the IC is reduced. All other IC functions continue to operate. The transmitter off-state resets when the temperature decreases below the shutdown threshold and pin TxD goes high. The thermal protection circuit is particularly needed when a bus line short circuits. Table 2. OPERATING MODES Pin STB Mode Pin RxD Low Normal Low when bus dominant High when bus recessive High Standby Follows the bus when wake-up detected High when no wake-up request detected TxD Dominant Timeout Function A TxD dominant timeout timer circuit prevents the bus lines being driven to a permanent dominant state (blocking all network communication) if pin TxD is forced permanently low by a hardware and/or software application failure. The timer is triggered by a negative edge on pin TxD. If the duration of the low-level on pin TxD exceeds the internal timer value tdom(TxD), the transmitter is disabled, driving the bus into a recessive state. The timer is reset by a positive edge on pin TxD. This TxD dominant timeout time tdom(TxD) defines the minimum possible bit rate to 17 kbps. Normal Mode In the normal mode, the transceiver is able to communicate via the bus lines. The signals are transmitted and received to the CAN controller via the pins TxD and RxD. The slopes on the bus lines outputs are optimized to give low EME. Standby Mode In standby mode both the transmitter and receiver are disabled and a very low-power differential receiver monitors the bus lines for CAN bus activity. The bus lines are biased to ground and supply current is reduced to a minimum, typically 10 mA. When a wake-up request is detected by the low-power differential receiver, the signal is first filtered and then verified as a valid wake signal after a time period of twake_filt, the RxD pin is driven low by the transceiver (following the bus) to inform the controller of the wake-up request. Fail Safe Features A current-limiting circuit protects the transmitter output stage from damage caused by accidental short circuit to either positive or negative supply voltage, although power dissipation increases during this fault condition. Standby undervoltage on VCC pin prevents the chip sending data on the bus when there is not enough VCC supply voltage by entering standby mode. Undervoltage detection on VIO pin (NCV7344-3 version only) also causes transition to standby mode. Switch-off undervoltage detection level on supply pin(s) forces transceiver to disengage from the bus until the supply is recovered. After supply is recovered TxD pin must be first released to high to allow sending dominant bits again. Recovery time from undervoltage detection is equal to td(stb-nm) time. The pins CANH and CANL are protected from automotive electrical transients (according to ISO 7637; see Figure 7). Pins TxD and STB are pulled high internally should the input become disconnected. Pins TxD, STB and RxD will be floating, preventing reverse supply should the VCC supply be removed. Wake-up When a valid wake-up pattern (phase in order dominant - recessive - dominant) is detected during the standby mode the RxD pin follows the bus. Minimum length of each phase is twake_filt - see Figure 5. Pattern must be received within twake_to to be recognized as valid wake-up otherwise internal logic is reset. twake_filt twake_filt twake_filt CANH CANL < twake_to t dwakerd t dwakedr VIO Supply Pin The VIO pin (available only on NCV7344-3 version) should be connected to microcontroller supply pin. By using VIO supply pin shared with microcontroller the I/O levels between microcontroller and transceiver are properly adjusted. See Figure 4. Pin VIO also provides the internal supply voltage for low-power differential receiver of the transceiver. This allows detection of wake-up request even when there is no supply voltage on pin VCC. RxD Figure 5. NCV7344 Wake-up Behavior www.onsemi.com 4 NCV7344 ELECTRICAL CHARACTERISTICS Definitions All voltages are referenced to GND (pin 2). Positive currents flow into the IC. Sinking current means the current is flowing into the pin; sourcing current means the current is flowing out of the pin. ABSOLUTE MAXIMUM RATINGS Table 3. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Unit -0.3 +6 V 0 < VCC < 5.25 V; no time limit -42 +42 V 0 < VCC < 5.25 V; no time limit -42 +42 V DC voltage between CANH and CANL -42 +42 V DC voltage at pin TxD, RxD, STB -0.3 +6 V VSUP Supply voltage VCC, VIO VCANH DC voltage at pin CANH VCANL DC voltage at pin CANL VCANH-CANL VI/O Conditions VesdHBM Electrostatic discharge voltage at all pins, Component HBM (Note 1) -8 +8 kV VesdCDM Electrostatic discharge voltage at all pins, Component CDM (Note 2) -750 +750 V VesdIEC Electrostatic discharge voltage at pins CANH and CANL, System HBM (Note 4) (Note 3) -8 +8 kV Vschaff Voltage transients, pins CANH, CANL. According to ISO7637-3, Class C (Note 4) test pulses 1 -100 test pulses 2a +75 test pulses 3a Latch-up V Static latch-up at all pins -150 V V test pulses 3b +100 V (Note 5) 150 mA Tstg Storage temperature -55 +150 C TJ Maximum junction temperature -40 +170 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA-JESD22. Equivalent to discharging a 100 pF capacitor through a 1.5 kW resistor. 2. Standardized charged device model ESD pulses when tested according to AEC-Q100-011 3. System human body model electrostatic discharge (ESD) pulses in accordance to IEC 61000-4-2. Equivalent to discharging a 150 pF capacitor through a 330 W resistor referenced to GND. 4. Results were verified by external test house. 5. Static latch-up immunity: Static latch-up protection level when tested according to EIA/JESD78. Table 4. THERMAL CHARACTERISTICS Parameter Symbol Value Unit Thermal characteristics, SOIC-8 (Note 6) Thermal Resistance Junction-to-Air, Free air, 1S0P PCB (Note 7) Thermal Resistance Junction-to-Air, Free air, 2S2P PCB (Note 8) RqJA RqJA 131 81 C/W C/W Thermal characteristics, DFN8 (Note 6) Thermal Resistance Junction-to-Air, Free air, 1S0P PCB (Note 7) Thermal Resistance Junction-to-Air, Free air, 2S2P PCB (Note 8) RqJA RqJA 125 58 C/W C/W 6. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 7. Values based on test board according to EIA/JEDEC Standard JESD51-3, signal layer with 10% trace coverage. 8. Values based on test board according to EIA/JEDEC Standard JESD51-7, signal layers with 10% trace coverage. www.onsemi.com 5 NCV7344 ELECTRICAL CHARACTERISTICS Table 5. ELECTRICAL CHARACTERISTICS VCC = 4.75 V to 5.25 V; VIO = 2.8 to 5.25 V; TJ = -40 to +150C; RLT = 60 W, CLT = 100 pF, C1 not used, CRxD = 15 pF unless specified otherwise. Parameter Symbol Conditions Min Typ Max Unit SUPPLY (Pin VCC) VCC Power supply voltage ICC Supply current ICCS Supply current in standby mode (Note 9) 4.75 5 5.25 V Dominant; VTxD = Low 20 45 70 mA Recessive; VTxD = High 1.9 5 10 mA TJ 100C, (Note 10) - 10 15 mA VUVD(VCC)(stby) Standby undervoltage detection VCC pin 3.5 4 4.3 V VUVD(VCC)(swoff) Switch-off undervoltage detection VCC pin 2.0 2.3 2.6 V 2.8 - 5.5 V VIO SUPPLY VOLTAGE (Pin VIO) Only for NCV7344-3 version VIO Supply voltage on pin VIO IIOS Supply current on pin VIO in standby mode TJ 100C, (Note 10) - - 11 mA ICCS Supply current on pin VCC in standby mode TJ 100C, (Note 10) - 0 4.0 mA IIONM Supply current on pin VIO during normal mode Dominant; VTxD = Low 0.45 0.65 0.9 mA Recessive; VTxD = High 0.32 0.43 0.58 2.0 2.3 2.6 V VUVDVIO Undervoltage detection voltage on VIO pin TRANSMITTER DATA INPUT (Pin TxD) VIH High-level input voltage Output recessive 2.0 - - V VIL Low-level input voltage Output dominant - - 0.8 V IIH High-level input current VTxD = VCC/VIO -5 0 +5 mA IIL Low-level input current VTxD = 0 V -300 -150 -75 mA Ci Input capacitance (Note 10) - 5 10 pF TRANSMITTER MODE SELECT (Pin STB) VIH High-level input voltage Standby mode 2.0 - - V VIL Low-level input voltage Normal mode - - 0.8 V IIH High-level input current VSTB = VCC/VIO -1 0 +1 mA IIL Low-level input current VSTB = 0 V -15 - -1 mA Ci Input capacitance (Note 10) - 5 10 pF RECEIVER DATA OUTPUT (Pin RxD) IOH High-level output current Normal mode VRxD = VCC/VIO - 0.4 V -8 -3 -1 mA IOL Low-level output current VRxD = 0.4 V 1 6 12 mA -27 V < VCANH, VCANL < +32 V; Normal mode -5 - +5 mA 0 W < R(VCC to GND) < 1 MW VCANL = VCANH = 5 V -5 0 +5 mA BUS LINES (Pins CANH and CANL) Io(rec) ILI Recessive output current at pins CANH and CANL Input leakage current Vo(rec)(CANH) Recessive output voltage at pin CANH Normal mode, VTxD = High; RLT and CLT not used 2.0 2.5 3.0 V Vo(rec)(CANL) Recessive output voltage at pin CANL Normal mode, VTxD = High; RLT and CLT not used 2.0 2.5 3.0 V Vo(off)(CANH) Recessive output voltage at pin CANH Standby mode; RLT and CLT not used -0.1 0 0.1 V www.onsemi.com 6 NCV7344 Table 5. ELECTRICAL CHARACTERISTICS VCC = 4.75 V to 5.25 V; VIO = 2.8 to 5.25 V; TJ = -40 to +150C; RLT = 60 W, CLT = 100 pF, C1 not used, CRxD = 15 pF unless specified otherwise. Symbol Parameter Conditions Min Typ Max Unit Recessive output voltage at pin CANL Standby mode; RLT and CLT not used -0.1 0 0.1 V Differential bus output voltage (VCANH - VCANL) Standby mode; RLT and CLT not used -0.2 0 0.2 V BUS LINES (Pins CANH and CANL) Vo(off)(CANL) Vo(off)(diff) Vo(dom)(CANH) Dominant output voltage at pin CANH VTxD = 0 V; t < tdom(TxD); 50 W < RLT < 65 W 2.75 3.5 4.5 V Vo(dom)(CANL) Dominant output voltage at pin CANL VTxD = 0 V; t < tdom(TxD); 50 W < RLT < 65 W 0.5 1.5 2.25 V VTxD = 0 V; dominant; 45 W < RLT < 65 W 1.5 2.25 3.0 V RLT = 2.24 kW (Note 10) 1.5 - 5.0 V Differential bus output voltage (VCANH - VCANL) VTxD = High; recessive; no load -50 0 +50 mV Vo(dom)(sym) Dominant output voltage driver symmetry (VCANH + VCANL) RLT = 60 W; C1 = 4.7 nF; TxD = square wave up to 1 MHz 0.9 1.0 1.1 VCC Io(sc)(CANH) Short circuit output current at pin CANH -3 V < VCANH < +18 V -100 -70 1.5 mA Io(sc)(CANL) Short circuit output current at pin CANL -3 V < VCANL < +36 V -1.5 70 100 mA Differential input voltage range recessive state Normal or Silent mode; -12 V VCANH, VCANL +12 V; no load -3.0 - 0.5 V Standby or Sleep mode; -12 V VCANH, VCANL +12 V; no load -3.0 0.4 V Normal or Silent mode; -12 V VCANH, VCANL +12 V; no load 0.9 8.0 V Standby or Sleep mode; -12 V VCANH, VCANL +12 V; no load 1.05 8.0 V Vo(dom)(diff) Vo(dom)(diff)_arb Vo(rec)(diff) Vi(rec)(diff)_NM Differential bus output voltage (VCANH - VCANL) Differential bus output voltage during arbitration (VCANH - VCANL) Vi(rec)(diff)_LP Vi(dom)(diff)_NM Differential input voltage range dominant state Vi(dom)(diff)_LP - Vi(diff)(th)_NORM Differential receiver threshold voltage in normal mode -12 V VCANL +12 V; -12 V VCANH +12 V 0.5 - 0.9 V Vi(diff)(th)_NORM_H Differential receiver threshold voltage in normal mode, extended range -30 V < VCANL < +35 V; -30 V < VCANH < +35 V 0.4 - 1.0 V Vi(diff)(th)_STDBY Differential receiver threshold voltage in standby mode -12 V VCANL +12 V; -12 V VCANH +12 V 0.4 - 1.05 V Ri(cm)(CANH) Common-mode input resistance at pin CANH -2 V VCANH +7 V; -2 V VCANL +7 V 15 26 37 kW Ri(cm)(CANL) Common-mode input resistance at pin CANL -2 V VCANH +7 V; -2 V VCANL +7 V 15 26 37 kW Ri(cm)(m) Matching between pin CANH and pin CANL common mode input resistance VCANH = VCANL = +5 V -1 0 +1 % Differential input resistance -2 V VCANH +7 V; -2 V VCANL +7 V 25 50 75 kW Ci(CANH) Input capacitance at pin CANH VTxD = High; (Note 10) - 7.5 20 pF Ci(CANL) Input capacitance at pin CANL VTxD = High; (Note 10) - 7.5 20 pF Differential input capacitance VTxD = High; (Note 10) - 3.75 10 pF Ri(diff) Ci(diff) www.onsemi.com 7 NCV7344 Table 5. ELECTRICAL CHARACTERISTICS VCC = 4.75 V to 5.25 V; VIO = 2.8 to 5.25 V; TJ = -40 to +150C; RLT = 60 W, CLT = 100 pF, C1 not used, CRxD = 15 pF unless specified otherwise. Symbol Parameter Conditions Min Typ Max Unit TIMING CHARACTERISTICS (see Figures 6 and 8) td(TxD-BUSon) Delay TxD to bus active - 75 - ns td(TxD-BUSoff) Delay TxD to bus inactive - 85 - ns td(BUSon-RxD) Delay bus active to RxD - 24 - ns td(BUSoff-RxD) Delay bus inactive to RxD - 32 - ns tpd_dr Propagation delay TxD to RxD dominant to recessive transition 50 100 210 ns tpd_rd Propagation delay TxD to RxD recessive to dominant transition 50 120 210 ns td(stb-nm) Delay standby mode to normal mode 5 11 20 ms twake_filt Filter time for wake-up via bus NCV7344 version 0.5 - 5 ms NCV7344A version 0.15 - 1.8 ms tdwakerd Delay to flag wake event (recessive to dominant transitions) Valid bus wake-up event 0.5 2.6 6 ms tdwakedr Delay to flag wake event (dominant to recessive transitions) Valid bus wake-up event 0.5 2.6 6 ms twake_to Bus time for wake-up timeout Standby mode 1 - 10 ms tdom(TxD) TxD dominant time for timeout VTxD = Low; Normal mode 1 - 10 ms tBit(RxD) Bit time on RxD pin tBit(TxD) = 500 ns 400 - 550 ns tBit(TxD) = 200 ns 120 - 220 ns tBit(TxD) = 500 ns 435 - 530 ns tBit(TxD) = 200 ns 155 - 210 ns tBit(TxD) = 500 ns -65 - +40 ns tBit(TxD) = 200 ns -45 - +15 ns Junction temperature rising 160 180 200 C tBit(Vi(diff)) DtRec Bit time on bus (CANH - CANL pin) Receiver timing symmetry DtRec = tBit(RxD) - tBit(Vi(diff)) THERMAL SHUTDOWN TJ(sd) Shutdown junction temperature 9. In the range between VUVD(VCC)(stby) and 4.75 V and from 5.25 V to 6 V the chip is fully functional; some parameters may be outside of the specification. 10. Values based on design and characterization, not tested in production www.onsemi.com 8 NCV7344 MEASUREMENT SETUPS AND DEFINITIONS 0.7*VCC * TxD 0.3*VCC * 0.3*VCC * tpd_rd tbit(TxD) td(TxD-BUSon) 5*tbit(TxD) Vi(diff)= VCANH -VCANL td(BUSon-RxD) 900 mV 500 mV tbit(Vi(diff)) td(TxD-BUSoff) tpd_dr 0.7*VCC * RxD 0.3*VCC * *On NCV7344-3 VCC is replaced by VIO Edge length below 10 ns tbit(RxD) Figure 6. Transceiver Timing Diagram +5 V 100nF VIO 3 5 TxD CANH 7 1 NCV7344 RxD VCC 4 8 15pF 1 nF Transient Generator 1 nF 6 CANL 2 STB GND Figure 7. Test Circuit for Automotive Transients +5 V 100 nF 3 5 RxD 7 1 NCV7344 TxD 4 8 15 pF VCC VIO RLT/2 CLT 6 2 STB CANH C1 RLT/2 CANL 100 pF 2x 30 W GND Figure 8. Test Circuit for Timing Characteristics www.onsemi.com 9 NCV7344 Table 6. ISO 11898-2:2016 Parameter Cross-Reference Table ISO 11898-2:2016 Specification Parameter NCV7344 Datasheet Notation Symbol Single ended voltage on CAN_H VCAN_H Vo(dom)(CANH) Single ended voltage on CAN_L VCAN_L Vo(dom)(CANL) Differential voltage on normal bus load VDiff Vo(dom)(diff) Differential voltage on effective resistance during arbitration VDiff Vo(dom)(diff)_arb Differential voltage on extended bus load range (optional) VDiff Vo(dom)(diff) VSYM Vo(dom)(sym) Absolute current on CAN_H ICAN_H Io(SC)(CANH) Absolute current on CAN_L ICAN_L Io(SC)(CANL) Single ended output voltage on CAN_H VCAN_H Vo(rec)(CANH) Single ended output voltage on CAN_L VCAN_L Vo(rec)(CANL) VDiff Vo(rec)(diff) Single ended output voltage on CAN_H VCAN_H Vo(off)(CANH) Single ended output voltage on CAN_L VCAN_L Vo(off)(CANL) VDiff Vo(off)(diff) Transmit dominant timeout, long tdom tdom(TxD) Transmit dominant timeout, short tdom NA Recessive state differential input voltage range VDiff Vi(rec)(diff)_NM Dominant state differential input voltage range VDiff Vi(dom)(diff)_NM Dominant output characteristics Driver symmetry Driver symmetry Driver output current Receiver output characteristics, bus biasing active Differential output voltage Receiver output characteristics, bus biasing inactive Differential output voltage Optional transmit dominant timeout Static receiver input characteristics, bus biasing active Static receiver input characteristics, bus biasing inactive Recessive state differential input voltage range VDiff Vi(rec)(diff)_LP Dominant state differential input voltage range VDiff Vi(dom)(diff)_LP RDiff Ri(diff) RCAN_H RCAN_L Ri(cm)(CANH) Ri(cm)(CANL) mR Ri(cm)(m) tLoop tpd_rd tpd_dr Receiver input resistance Differential internal resistance Single ended internal resistance Receiver input resistance matching Matching a of internal resistance Implementation loop delay requirement Loop delay Optional implementation data signal timing requirements for use with bit rates above 1 Mbit/s and up to 2 Mbit/s Transmitted recessive bit width @ 2 Mbit/s tBit(Bus) tBit(Vi(diff)) Received recessive bit width @ 2 Mbit/s tBit(RXD) tBit(RxD) www.onsemi.com 10 NCV7344 Table 6. ISO 11898-2:2016 Parameter Cross-Reference Table Parameter Receiver timing symmetry @ 2 Mbit/s Notation Symbol DtRec DtRec Optional implementation data signal timing requirements for use with bit rates above 2 Mbit/s and up to 5 Mbit/s Transmitted recessive bit width @ 5 Mbit/s tBit(Bus) tBit(Vi(diff)) Transmitted recessive bit width @ 5 Mbit/s tBit(RXD) tBit(RxD) DtRec DtRec VDiff VCANH-CANL General maximum rating VCAN_H and VCAN_L VCAN_H VCAN_L VCANH VCANL Optional: Extended maximum rating VCAN_H and VCAN_L VCAN_H VCAN_L NA ICAN_H ICAN_L ILI CAN activity filter time, long tFilter twake_filt CAN activity filter time, short tFilter twake_filt Wake-up timeout, short tWake NA Wake-up timeout, long tWake twake_to tSilence NA tBias NA Received recessive bit width @ 5 Mbit/s Maximum ratings of VCAN_H, VCAN_L and VDiff Maximum rating VDiff Maximum leakage currents on CAN_H and CAN_L, unpowered Leakage current on CAN_H, CAN_L Bus biasing control timings Timeout for bus inactivity (Required for selective wake-up implementation only) Bus Bias reaction time (Required for selective wake-up implementation only) DEVICE ORDERING INFORMATION (High Speed Low Power CAN, CANFD Transceiver) Part Number Long FT Short FT Vio NCV7344D10R2G X NCV7344D13R2G X NCV7344AD10R2G X NCV7344MW3R2G X Package Shipping SOIC 150 8 GREEN (Matte Sn, JEDEC MS-012) (Pb-Free) X X NCV7344MW0R2G Temperature Range X X NCV7344AD13R2G NC X X DFN 8 Wettable Flank (Pb-Free) X NCV7344AMW0R2G X NCV7344AMW3R2G X 3000 / Tape & Reel -40C to +150C X X X For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 11 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFNW8 3x3, 0.65P CASE 507AB ISSUE D 1 SCALE 2:1 DATE 03 JUL 2018 A B D L3 L L3 L ALTERNATE CONSTRUCTION EEE EEE EEE DETAIL A E PIN ONE REFERENCE EXPOSED COPPER TOP VIEW DETAIL B 0.05 C A DETAIL B A3 C C 0.05 C NOTE 4 A4 C SIDE VIEW SEATING PLANE 1 L3 PLATED SURFACES D2 DETAIL A DIM A A1 A3 A4 b D D2 E E2 e K L L3 PLATING A1 A4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.10 AND 0.20mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. THIS DEVICE CONTAINS WETTABLE FLANK DESIGN FEATURES TO AID IN FILLET FORMATION ON THE LEADS DURING MOUNTING. GENERIC MARKING DIAGRAM* SECTION C-C 4 1 8X L E2 K 8 5 e/2 8X b 0.05 C BOTTOM VIEW NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* 2.55 2.28 8X 0.75 8 5 1 4 XXXXXX XXXXXX ALYWG G XXXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) 0.10 C A B e MILLIMETERS MIN NOM MAX 0.80 0.85 0.90 --- --- 0.05 0.20 REF 0.10 --- --- 0.25 0.30 0.35 2.95 3.00 3.05 2.30 2.40 2.50 2.95 3.00 3.05 1.50 1.60 1.70 0.65 BSC 0.30 REF 0.35 0.40 0.45 0.00 0.05 0.10 *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot " G", may or may not be present. Some products may not follow the Generic Marking. 3.30 1.76 0.65 PITCH PACKAGE OUTLINE 8X 0.33 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON14978G DFNW8 3x3, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. (c) Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC-8 NB CASE 751-07 ISSUE AK 8 1 SCALE 1:1 -X- DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. A 8 5 S B 0.25 (0.010) M Y M 1 4 -Y- K G C N X 45 _ SEATING PLANE -Z- 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb-Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb-Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb-Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot "G", may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC-8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. (c) Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC-8 NB CASE 751-07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N-SOURCE 2. N-GATE 3. P-SOURCE 4. P-GATE 5. P-DRAIN 6. P-DRAIN 7. N-DRAIN 8. N-DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC-8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. (c) Semiconductor Components Industries, LLC, 2019 www.onsemi.com ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. "Typical" parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Email Requests to: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com TECHNICAL SUPPORT North American Technical Support: Voice Mail: 1 800-282-9855 Toll Free USA/Canada Phone: 011 421 33 790 2910 www.onsemi.com 1 Europe, Middle East and Africa Technical Support: Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative