HEXFET® Power MOSFET
Fifth Generation HEXFET® power MOSFETs from
International Rectifier utilize advanced processing
techniques to achieve extremely low on-resistance per
silicon area. This benefit, combined with the fast switching
speed and ruggedized device design that HEXFET power
MOSFETs are well known for, provides the designer with
an extremely efficient and reliable device for use in a wide
variety of applications.
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on-
resistance in any existing surface mount package. The
D2Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate
up to 2.0W in a typical surface mount application.
The through-hole version (IRL1004L) is available for low-
profile application.
S
D
G
VDSS = 40V
RDS(on) = 0.0065Ω
ID = 130A
lAdvanced Process Technology
lUltra Low On-Resistance
lDynamic dv/dt Rating
l175°C Operating Temperature
lFast Switching
lFully Avalanche Rated
lLead-Free
Description
07/19/04
www.irf.com 1
IRL1004SPbF
IRL1004LPbF
D2Pak
IRL1004S TO-262
IRL1004L
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 0.75
RθJA Junction-to-Ambient ( PCB Mounted,steady-state)* – – – 4 0
Thermal Resistance
°C/W
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 130
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 92 A
IDM Pulsed Drain Current 520
PD @TA = 25°C Power Dissipation 3.8 W
PD @TC = 25°C Power Dissipation 200 W
Linear Derating Factor 1.3 W/°C
VGS Gate-to-Source Voltage ± 16 V
EAS Single Pulse Avalanche Energy700 mJ
IAR Avalanche Current78 A
EAR Repetitive Avalanche Energy20 mJ
dv/dt Peak Diode Recovery dv/dt 5.0 V/ns
TJOperating Junction and -55 to + 175
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case) °C
Absolute Maximum Ratings
lLogic-Level Gate Drive
PD - 95575
IRL1004S/LPbF
2www.irf.com
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11)
ISD ≤ 78A, di/dt ≤ 370A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Notes:
Starting TJ = 25°C, L = 0.23mH
RG = 25Ω, IAS = 78A. (See Figure 12)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
S
D
G
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode)––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode) ––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 78A, VGS = 0V
trr Reverse Recovery Time ––– 78 120 ns TJ = 25°C, IF = 78A
Qrr Reverse Recovery Charge ––– 180 270 nC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
130
520
A
Calculated continuous current based on maximum allowable
junction temperature; for recommended current-handing of the
package refer to Design Tip # 93-4
* When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
Uses IRL1004 data and test conditions
Source-Drain Ratings and Characteristics
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 40 – –– ––– V V GS = 0V, ID = 250µA
∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient ––– 0.04 ––– V/°C Reference to 25°C, I D = 1mA
0.0065 VGS = 10V, ID = 78A
0.009 ΩVGS = 4.5V, ID = 65A
VGS(th) Gate Threshold Voltage 1.0 ––– V VDS = VGS, ID = 250µA
gfs Forward Transconductance 63 SV
DS = 25V, ID = 78A
25 µA VDS = 40V, VGS = 0V
––– ––– 250 VDS = 32V , VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 16V
Gate-to-Source Reverse Leakage ––– ––– -100 nA VGS = -16V
QgTotal Gate Charge –– – – – – 100 ID = 78A
Qgs Gate-to-Source Charge –– – ––– 32 nC V DS = 32V
Qgd Gate-to-Drain ("Miller") Charge ––– ––– 43 VGS = 4.5V, See Fig. 6 and 13
td(on) Turn-On Delay Time ––– 16 ––– VDD = 20V,
trRise Time ––– 2 10 ––– ID = 78A,
td(off) Turn-Off Delay Time ––– 25 ––– n s RG = 2.5Ω,
tfFall Time ––– 14 ––– RD = 0.18Ω, See Fig. 10
Between lead,
––– ––– and center of die contact
Ciss Input Capacitance ––– 5330 ––– V GS = 0V
Coss Output Capacitance ––– 1480 ––– pF VDS = 25V
Crss Reverse Transfer Capacitance ––– 32 0 ––– ƒ = 1.0MHz, See Fig. 5
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on) Static Drain-to-Source On-Resistance
IGSS
IDSS Drain-to-Source Leakage Current
LSInternal Source Inductance 7.5 nH
IRL1004S/LPbF
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Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.1
1
10
100
1000
10000
0.1 1 10 100
20µs PULSE WIDTH
T = 25 C
J°
TOP
BOTTOM
VGS
15V
10V
7.0V
5.5V
4.5V
4.0V
3.5V
2.7V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
2.7V
1
10
100
1000
0.1 1 10 100
20µs PU LSE WIDTH
T = 175 C
J°
TOP
BOTTOM
VGS
15V
10V
7.0V
5.5V
4.5V
4.0V
3.5V
2.7V
V , Drain -to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
2.7V
0.1
1
10
100
1000
2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0
V = 5 0 V
20µs PULSE WIDTH
DS
V , Gate-to-Source Voltage (V)
I , Drain-to-Source Current (A)
GS
D
T = 25 C
J°
T = 175 C
J°
-60 -40 -20 020 40 60 80 100 120 140 160 180
0.0
0.5
1.0
1.5
2.0
2.5
T , Juncti on Temperature ( C)
R , Drain-to-Source On Resistance
(Normalized)
J
DS(on)
°
V =
I =
GS
D
10V
130A
IRL1004S/LPbF
4www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
1 10 100
0
2000
4000
6000
8000
10000
V , Drain-to-Source Voltage (V)
C, Capacitance (pF)
DS
V
C
C
C
=
=
=
=
0V,
C
C
C
f = 1M Hz
+ C
+ C
C SHOR TED
GS
iss gs gd , ds
rss gd
oss ds gd
Ciss
Coss
Crss
030 60 90 120 150 180
0
2
4
6
8
10
12
Q , Total Gate Charge (nC)
V , Gate-to-Source Voltage (V)
G
GS
FOR TEST CIRCUIT
SEE FIGURE
I =
D
13
78 A V = 20V
DS
V = 32V
DS
0.1
1
10
100
1000
0.0 0.5 1.0 1.5 2.0 2.5 3.0
V ,Source-to-Drain Vol tage (V)
I , Reverse Drain Current (A)
SD
SD
V = 0 V
GS
T = 25 C
J°
T = 175 C
J°
1
10
100
1000
10000
1 10 100
OPERATION IN THIS AREA LIMITED
BY RDS(on)
Single Pulse
T
T = 175 C
= 25 C
°°
J
C
V , Drain-to-Source Voltage (V)
I , Drain Current (A)I , Drain Current (A)
DS
D
10us
100us
1ms
10ms
IRL1004S/LPbF
www.irf.com 5
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10a. Switching Time Test Circuit
V
DS
9
0%
1
0%
V
GS t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
25 50 75 100 125 150 175
0
20
40
60
80
100
120
140
T , C a se Temperature ( C)
I , Drain Current (A)
°
C
D
LIMITED BY PACKAGE
0.01
0.1
1
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Duty factor D = t / t
2. Peak T =P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Recta ngular Pulse Durati on ( sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
IRL1004S/LPbF
6www.irf.com
D.U.T. V
D
S
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 13b. Gate Charge Test Circuit
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
25 50 75 100 125 150 175
0
300
600
900
1200
1500
1800
Starting T , Junctio n T empera ture ( C )
E , Single Pulse Avalanche Energy (mJ)
J
AS
°
ID
TOP
BOTTOM
32A
55A
78A
Fig 12a. Unclamped Inductive Test Circuit
Fig 12b. Unclamped Inductive Waveforms
V
DS
L
D.U.T.
V
D
D
I
AS
t
p
0.01Ω
R
G
+
-
tp
V
DS
I
AS
VDD
V
(BR)DSS
4.5 V
QG
QGS QGD
V
G
Charge
Fig 13a. Basic Gate Charge Waveform
4.5 V
IRL1004S/LPbF
www.irf.com 7
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
R
e-Applied
V
oltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
Fig 14. For N-channel HEXFET® Power MOSFETs
* VGS = 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
RG
VDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
*
IRL1004S/LPbF
8www.irf.com
D2Pak Part Marking Information
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
Note: "P" in assembly line
position indicates "Lead-Free"
F530S
THIS IS AN IRF530S WITH
LOT CODE 8024
ASSEMBLED ON WW 02, 2000
IN THE AS SE MB LY LINE "L"
AS S EMBLY
LOT CODE
INTERNATIONAL
RECTIFIER
LOGO
PART NUMBER
DATE CODE
YEAR 0 = 2000
WEEK 02
LINE L
OR
F530S
A = ASSEMBLY SITE CODE
WEE K 02
P = DES IGNAT E S LEAD-FREE
PRODU CT (OPTI ONAL)
RECTIFIER
INTERNATIONAL
LOGO
LOT CODE
AS S EMBLY YEAR 0 = 2000
DATE CODE
PART NUMBER
IRL1004S/LPbF
www.irf.com 9
TO-262 Part Marking Information
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
AS S EMBLY
LOT CODE
RECTIFIER
INTERNATIONAL
ASSEMBLED ON WW 19, 1997
Note: "P" in assembly line
pos ition in dicates "Lead- F r ee"
IN THE ASSEMBLY LINE "C" LOGO
T H IS IS AN IRL3103L
L OT CODE 1789
EXAMPLE:
LINE C
DATE CODE
WEEK 19
YE AR 7 = 1997
PART NUMBER
PART NUMBER
LOGO
LOT CODE
AS S EMBL Y
INTERNATIONAL
RECTIFIER
PR ODUCT (OPTIONAL)
P = DESIGNATES LEAD-FRE E
A = ASSEMBLY SITE CODE
WEEK 19
YE AR 7 = 1997
DATE CODE
OR
IRL1004S/LPbF
10 www.irf.com
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
3
4
4
TRR
F
EED DIRECTION
1.85 (.07 3)
1.65 (.06 5)
1.60 (.06 3)
1.50 (.05 9)
4.10 (.161)
3.90 (.153)
TRL
F
EED DIRECTION
10.90 (.429)
10.70 (.421) 16. 10 ( .634 )
15. 90 ( .626 )
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449) 15.42 (.609)
15.22 ( .601)
4.72 (.136)
4.52 (.178)
24. 30 ( .957
)
23. 90 ( .941
)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
27.40 (1.079)
23.90 (.941)
60.00 (2.362
)
MIN.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCL UD ES FLANGE DISTORTION @ OUTER EDGE.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 07/04
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
