PRELIMINARY CYBLE-214015-01 EZ-BLETM PSoC(R) Bluetooth 4.2 Module EZ-BLETM PSoC(R) Bluetooth 4.2 Module General Description The Cypress CYBLE-214015-01 is a fully certified and qualified module supporting Bluetooth Low Energy (BLE) wireless communication. The CYBLE-214015-01 is a turnkey solution and includes onboard crystal oscillators, trace antenna, passive components, and the Cypress PSoC(R) 4 BLE. Refer to the PSoC(R) 4 BLE datasheet for additional details on the capabilities of the PSoC 4 BLE device used on this module. Programmable Analog The EZ-BLE PSoC(R) module is a scalable and reconfigurable platform architecture. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The CYBLE-214015-01 also includes digital programmable logic, high-performance analog-to-digital conversion (ADC), opamps with comparator mode, and standard communication and timing peripherals. The CYBLE-214015-01 includes a royalty-free BLE stack compatible with Bluetooth 4.2 and provides up to 25 GPIOs in a small 11 x 11 x 1.80 mm package. The CYBLE-214015-01 is drop-in compatible with the CYBLE-014008-00 and CYBLE-214009-00 EZ-BLE Modules. The CYBLE-214015-01 is a complete solution and an ideal fit for applications seeking a highly integrated BLE wireless solution. Module Description Low power mode support Deep Sleep: 1.3 A with watch crystal oscillator (WCO) on Hibernate: 150 nA with SRAM retention Stop: 60 nA with GPIO (P2.2) or XRES wakeup Four opamps with reconfigurable high-drive external and high-bandwidth internal drive, comparator modes, and ADC input buffering capability; can operate in Deep-Sleep mode 12-bit, 1-Msps SAR ADC with differential and single-ended modes; channel sequencer with signal averaging Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin One low-power comparator that operate in Deep-Sleep mode Programmable Digital Four programmable logic blocks called universal digital blocks, (UDBs), each with eight macrocells and datapath Cypress-provided peripheral Component library, user-defined state machines, and Verilog input Capacitive Sensing Cypress CapSense Sigma-Delta (CSD) provides best-in-class SNR (> 5:1) and liquid tolerance Module size: 11.0 mm x 11.0 mm x 1.80 mm (with shield) Drop-in compatible with CYBLE-014008-00 and CYBLE-214009-00 Cypress-supplied software component makes capacitive-sensing design easy Automatic hardware-tuning algorithm (SmartSenseTM) 256-KB flash memory, 32-KB SRAM memory Up to 25 GPIOs configurable as open drain high/low, pull-up/pull-down, HI-Z analog, HI-Z digial, or strong output LCD drive supported on all GPIOs (common or segment) Operates in Deep-Sleep mode with four bits per pin memory Bluetooth 4.2 qualified single-mode module QDID: 79480 Declaration ID: D029646 Serial Communication Certified to FCC, CE, MIC, KC, and IC regulations Timing and Pulse-Width Modulation Industrial temperature range: -40 C to +85 C 32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit multiply, operating at up to 48 MHz Four 16-bit timer, counter, pulse-width modulator (TCPWM) blocks Center-aligned, Edge, and Pseudo-random modes Watchdog timer with dedicated internal low-speed oscillator (ILO) Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications Two-pin SWD for programming Up to 25 Programmable GPIOs Segment LCD Drive Power Consumption TX output power: -18 dbm to +3 dbm Received signal strength indicator (RSSI) with 1-dB resolution TX current consumption of 15.6 mA (radio only, 0 dbm) RX current consumption of 16.4 mA (radio only) Cypress Semiconductor Corporation Document Number: 002-15923 Rev. ** * 198 Champion Court Two independent runtime reconfigurable serial communication blocks (SCBs) with I2C, SPI, or UART functionality Any GPIO pin can be CapSense, LCD, analog, or digital * San Jose, CA 95134-1709 * 408-943-2600 Revised September 7, 2016 PRELIMINARY CYBLE-214015-01 More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design. Overview: EZ-BLE Module Portfolio, Module Roadmap EZ-BLE PSoC Product Overview PSoC 4 BLE Silicon Datasheet Application notes: Cypress offers a number of BLE application notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with EZ-BLE modules are: AN96841 - Getting Started with EZ-BLE Module (R) AN94020 - Getting Started with PSoC 4 BLE (R) AN97060 - PSoC 4 BLE and PRoCTM BLE - Over-The-Air (OTA) Device Firmware Upgrade (DFU) Guide AN91162 - Creating a BLE Custom Profile AN91184 - PSoC 4 BLE - Designing BLE Applications AN92584 - Designing for Low Power and Estimating Battery Life for BLE Applications (R) (R) AN85951 - PSoC 4 CapSense Design Guide (R) AN95089 - PSoC 4/PRoCTM BLE Crystal Oscillator Selection and Tuning Techniques AN91445 - Antenna Design and RF Layout Guidelines Knowledge Base Articles KBA97095 - EZ-BLETM Module Placement KBA213976 - FAQ for BLE and Regulatory Certifications with EZ-BLE modules KBA210802 - Queries on BLE Qualification and Declaration Processes Technical Reference Manual (TRM): (R) PSoC 4 BLE Technical Reference Manual PSOC(R) 4 BLE Registers Technical Reference Manual (TRM) Development Kits: CYBLE-214015-EVAL, CYBLE-214015-01 Evaluation Board (R) CY8CKIT-042-BLE, Bluetooth Low Energy (BLE) Pioneer Kit (R) CY8CKIT-002, PSoC MiniProg3 Program and Debug Kit Test and Debug Tools: (R) CYSmart, Bluetooth LE Test and Debug Tool (Windows) (R) CYSmart Mobile, Bluetooth LE Test and Debug Tool (Android/iOS Mobile App) PSoC(R) CreatorTM Integrated Design Environment (IDE) PSoC Creator is an Integrated Design Environment (IDE) that enables concurrent hardware and firmware editing, compiling and debugging of PSoC 3, PSoC 4, PSoC 5LP, PSoC 4 BLE, PRoC BLE and EZ-BLE module systems with no code size limitations. PSoC peripherals are designed using schematic capture and simple graphical user interface (GUI) with over 120 pre-verified, production-ready PSoC ComponentsTM. PSoC Components are analog and digital "virtual chips," represented by an icon that users can drag-and-drop into a design and configure to suit a broad array of application requirements. Bluetooth Low Energy Component The Bluetooth Low Energy Component inside PSoC Creator provides a comprehensive GUI-based configuration window that lets you quickly design BLE applications. The Component incorporates a Bluetooth Core Specification v4.2 compliant BLE protocol stack and provides API functions to enable user applications to interface with the underlying Bluetooth Low Energy Sub-System (BLESS) hardware via the stack. Technical Support Frequently Asked Questions (FAQs): Learn more about our BLE ECO System. Forum: See if your question is already answered by fellow developers on the PSoC 4 BLE and PRoC BLE forums. Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States, you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt. Document Number: 002-15923 Rev. ** Page 2 of 42 PRELIMINARY CYBLE-214015-01 Contents Overview ............................................................................ 4 Module Description ...................................................... 4 Pad Connection Interface ................................................ 6 Recommended Host PCB Layout ................................... 7 Power Supply Connections and Recommended External Components .................. 11 Connection Options ................................................... 11 External Component Recommendation .................... 11 Critical Components List ........................................... 14 Antenna Design ......................................................... 14 Electrical Specification .................................................. 15 GPIO ......................................................................... 17 XRES ......................................................................... 18 Analog Peripherals .................................................... 18 Digital Peripherals ..................................................... 22 Serial Communication ............................................... 24 Memory ..................................................................... 25 System Resources .................................................... 26 Environmental Specifications ....................................... 31 Environmental Compliance ....................................... 31 RF Certification .......................................................... 31 Environmental Conditions ......................................... 31 Document Number: 002-15923 Rev. ** ESD and EMI Protection ........................................... 31 Regulatory Information .................................................. 32 FCC ........................................................................... 32 Industry Canada (IC) Certification ............................. 33 European R&TTE Declaration of Conformity ............ 33 MIC Japan ................................................................. 34 KC Korea ................................................................... 34 Packaging ........................................................................ 35 Ordering Information ...................................................... 37 Part Numbering Convention ...................................... 37 Acronyms ........................................................................ 38 Document Conventions ................................................. 40 Units of Measure ....................................................... 40 Document History Page ................................................. 41 Sales, Solutions, and Legal Information ...................... 42 Worldwide Sales and Design Support ....................... 42 Products .................................................................... 42 PSoC(R)Solutions ....................................................... 42 Cypress Developer Community ................................. 42 Technical Support ..................................................... 42 Page 3 of 42 PRELIMINARY CYBLE-214015-01 Overview Module Description The CYBLE-214015-01 module is a complete module designed to be soldered to the main host board. Module Dimensions and Drawing Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE module functionality. Such selections will guarantee that all height restrictions of the component area are maintained. Designs should be completed with the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm). Table 1. Module Design Dimensions Dimension Item Module dimensions Specification Length (X) 11.00 0.15 mm Width (Y) 11.00 0.15 mm Length (X) 11.00 0.15 mm Width (Y) 4.62 0.15 mm PCB thickness Height (H) 0.80 0.10 mm Shield height Height (H) 1.00 0.10 mm Antenna location dimensions Maximum component height Height (H) 1.00 mm typical (shield) Total module thickness (bottom of module to highest component) Height (H) 1.80 mm typical See Figure 1 on page 5 for the mechanical reference drawing for CYBLE-214015-01. Document Number: 002-15923 Rev. ** Page 4 of 42 PRELIMINARY CYBLE-214015-01 Figure 1. Module Mechanical Drawing Top View Side View Bottom View Note 1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see Figure 3 on page 6, Figure 4 and Figure 5 on page 7, and Figure 6 and Table 3 on page 8. Document Number: 002-15923 Rev. ** Page 5 of 42 PRELIMINARY CYBLE-214015-01 Pad Connection Interface As shown in the bottom view of Figure 1 on page 5, the CYBLE-214015-01 connects to the host board via solder pads on the back of the module. Table 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-214015-01 module. Table 2. Solder Pad Connection Description Name SP Connections Connection Type 32 Solder Pads Pad Length Dimension Pad Width Dimension Pad Pitch Pad9/Pad24: 0.74 mm All Others: 0.79 mm 0.41 mm 0.66 mm Figure 2. Solder Pad Dimensions (Seen from Bottom) To maximize RF performance, the host layout should follow these recommendations: 1. The ideal placement of the Cypress BLE module is in a corner of the host board with the antenna located on the edge of the host board. This placement minimizes the additional recommended keep-out area stated in item 2. Please refer to AN96841 for module placement best practices. 2. To maximize RF performance, the area immediately around the Cypress BLE module trace antenna should contain an additional keep-out area, where no grounding or signal traces are contained. The keep-out area applies to all layers of the host board. The recommended dimensions of the host PCB keep-out area are shown in Figure 3 (dimensions are in mm). Figure 3. Recommended Host PCB Keep-Out Area Around the CYBLE-214015-01 Trace Antenna Host PCB Keep-Out Area Around Trace Antenna Document Number: 002-15923 Rev. ** Page 6 of 42 PRELIMINARY CYBLE-214015-01 Recommended Host PCB Layout Figure 4 through Figure 6 and Table 3 provide details that can be used for the recommended host PCB layout pattern for the CYBLE-214015-01. Dimensions are in millimeters unless otherwise noted. Pad length of 0.99 mm (0.494 mm from center of the pad on either side) shown in Figure 6 is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure 4, Figure 5, or Figure 6. It is not necessary to use all figures to complete the host PCB layout pattern. Figure 4. Host Layout Pattern for CYBLE-214015-01 Document Number: 002-15923 Rev. ** Figure 5. Module Pad Location from Origin Page 7 of 42 PRELIMINARY CYBLE-214015-01 Table 3 provides the center location for each solder pad on the CYBLE-214015-01. All dimensions reference the to the center of the solder pad. Refer to Figure 6 for the location of each module solder pad. Table 3. Module Solder Pad Location Figure 6. Solder Pad Reference Location Solder Pad (Center of Pad) Location (X,Y) from Orign (mm) Dimension from Orign (mils) 1 (0.30, 4.83) (11.81, 190.16) 2 (0.30, 5.49) (11.81, 216.14) 3 (0.30, 6.15) (11.81, 242.13) 4 (0.30, 6.81) (11.81, 268.11) 5 (0.30, 7.47) (11.81, 294.09) 6 (0.30, 8.13) (11.81, 320.08) 7 (0.30, 8.79) (11.81, 346.06) 8 (0.30, 9.45) (11.81, 372.05) 9 (0.27, 10.11) (10.63, 398.03) 10 (1.21, 10.70) (47.64, 421.26) 11 (1.87, 10.70) (73.62, 421.26) 12 (2.53, 10.70) (99.61, 421.26) 13 (3.19, 10.70) (125.59, 421.26) 14 (3.85, 10.70) (151.57, 421.26) 15 (4.51, 10.70) (177.56, 421.26) 16 (5.17, 10.70) (203.54, 421.26) 17 (5.84, 10.70) (229.92, 421.26) 18 (6.50, 10.70) (255.91, 421.26) 19 (7.16, 10.70) (281.89, 421.26) 20 (7.82, 10.70) (307.87, 421.26) 21 (8.48, 10.70) (333.86, 421.26) 22 (9.14, 10.70) (359.84, 421.26) 23 (9.80, 10.70) (385.83, 421.26) 24 (10.73, 10.11) (422.44, 398.03) 25 (10.70, 9.45) (421.26, 372.05) 26 (10.70, 8.79) (421.26, 346.06) 27 (10.70, 8.13) (421.26, 320.08) 28 (10.70, 7.47) (421.26, 294.09) 29 (10.70, 6.81) (421.26, 268.11) 30 (10.70, 6.15) (421.26, 242.13) 31 (10.70, 5.49) (421.26, 216.14) 32 (10.70, 4.83) (421.26, 190.16) Document Number: 002-15923 Rev. ** Page 8 of 42 PRELIMINARY CYBLE-214015-01 Table 4 and Table 5 detail the solder pad connection definitions and available functions for each connection pad. Table 4 lists the solder pads on CYBLE-214015-01, the BLE device port-pin, and denotes whether the digital function shown is available for each solder pad. Table 5 denotes whether the analog function shown is available for each solder pad. Each connection is configurable for a single option shown with a . Table 4. Digital Peripheral Capabilities Pad Number Device Port Pin 1 GND[3] 2 P1.1 3 P1.0 4 P1.5 5 P0.1 6 P0.7 UART SPI I2 C TCPWM[2] Cap Sense Ground Connection (SCB1_SS1) (SCB0_TX) (SCB0_MISO) (SCB0_SCL) (SCB1_TX) (SCB1_MISO) (SCB1_SCL) (SCB0_CTS) (SCB0_SCLK) (TCPWM0_N) (TCPWM0_P) (TCPWM2_N) (TCPWM0_N) (TCPWM2_N) WCO ECO Out OUT LCD SWD GPIO (SWDCLK) 7 VDD 8 P1.4 9 P0.4 10 P0.5 11 P0.6 12 P1.2 13 VDDR 14 P2.6 15 P1.3 16 P3.0 17 P2.1 18 P2.2 19 P2.3 20 VDDA 21 P3.4 22 P3.1 23 P3.7 24 P3.5 25 P3.3 26 VREF 27 P3.2 28 P3.6 29 XRES 30 P2.4 31 P2.5 32 GND[3] (SCB0_RX) (SCB0_RX) (SCB0_TX) (SCB0_RTS) Digital Power Supply Input (1.71 to 5.5V) (SCB0_MOSI) (SCB0_SDA) (SCB0_MOSI) (SCB0_SDA) (SCB0_MISO) (SCB0_SCL) (SCB0_SS0) (SCB1_SS2) (TCPWM2_P) (TCPWM1_P) (TCPWM1_N) (TCPWM2_P) (TCPWM1_P) Radio Power Supply (1.9V to 5.5V) (SCB0_RX) (SCB1_SS3) (SCB0_SS2) (SCB0_SS3) (SCB1_RX) (SCB0_TX) (SCB1_CTS) (SCB1_TX) (SCB0_CTS) (SCB0_RTS) (SCB1_RTS) (SCB0_SDA) (TCPWM1_N) (TCPWM0_P) Analog Power Supply Input (1.71 to 5.5V) (SCB1_SDA) (TCPWM2_P) (SCB0_SCL) (TCPWM0_N) (TCPWM3_N) (SCB1_SCL) (TCPWM2_N) (TCPWM1_N) Reference Voltage Input (TCPWM1_P) (TCPWM3_P) External Reset Hardware Connection Input (SWDIO) Ground Connection Notes 2. TCPWM stands for timer, counter, and PWM. If supported, the pad can be configured to any of these peripheral functions. 3. The main board needs to connect both GND connections (Pad 1 and Pad 32) on the module to the common ground of the system. Document Number: 002-15923 Rev. ** Page 9 of 42 PRELIMINARY CYBLE-214015-01 Table 5. Analog Peripheral Capabilities Pad Number Device Port Pin 1 GND[3] 2 P1.1 3 P1.0 4 P1.5 5 P0.1 6 P0.7 7 VDD 8 P1.4 9 P0.4 10 P0.5 11 P0.6 12 P1.2 13 VDDR 14 P2.6 15 P1.3 16 P3.0 17 P2.1 18 P2.2 19 P2.3 20 VDDA 21 P3.4 22 P3.1 23 P3.7 24 P3.5 25 P3.3 26 VREF 27 P3.2 28 P3.6 29 XRES 30 P2.4 31 P2.5 32 GND Document Number: 002-15923 Rev. ** SARMUX OPAMP LPCOMP Ground Connection (CTBm1_OA0_INN) (CTBm1_OA0_INP) (CTBm1_OA1_INP) Digital Power Supply Input (1.71 to 5.5V) (CTBm1_OA1_INN) (COMP1_INP) (COMP1_INN) (CTBm1_OA0_OUT) Radio Power Supply (1.9V to 5.5V) (CTBm1_OA0_INP) (CTBm1_OA1_OUT) (CTBm1_OA0_INN) (CTBm1_OA0_OUT) (CTBm1_OA1_OUT) Analog Power Supply Input (1.71 to 5.5V) Reference Voltage Input (Optional) External Reset Hardware Connection Input (CTBm1_OA1_INN) (CTBm1_OA1_INP) Ground Connection Page 10 of 42 PRELIMINARY CYBLE-214015-01 Power Supply Connections and Recommended External Components Power Connections External Component Recommendation The CYBLE-214015-01 contains three power supply connections, VDD, VDDA, and VDDR. The VDD and VDDA connections supply power for the digital and analog device operation respectively. VDDR supplies power for the device radio. In either connection scenario, it is recommended to place an external ferrite bead between the supply and the module connection. The ferrite bead should be positioned as close as possible to the module pin connection. VDD and VDDA accept a supply range of 1.71 V to 5.5 V. VDDR accepts a supply range of 1.9 V to 5.5 V. These specifications can be found in Table 10. The maximum power supply ripple for both power connections on the module is 100 mV, as shown in Table 8. Figure 7 details the recommended host schematic options for a single supply scenario. The use of one or two ferrite beads will depend on the specific application and configuration of the CYBLE-214015-01. The power supply ramp rate of VDD and VDDA must be equal to or greater than that of VDDR when the radio is used. Connection Options Figure 8 details the recommended host schematic for an independent supply scenario. The recommended ferrite bead value is 330 , 100 MHz (Murata BLM21PG331SN1D). Two connection options are available for any application: 1. Single supply: Connect VDD, VDDA, and VDDR to the same supply. 2. Independent supply: Power VDD, VDDA, and VDDR separately. Figure 7. Recommended Host Schematic Options for Single Supply Option Single Ferrite Bead Option Document Number: 002-15923 Rev. ** Three Ferrite Bead Option Page 11 of 42 PRELIMINARY CYBLE-214015-01 Figure 8. Recommended Host Schematic for Independent Supply Option Document Number: 002-15923 Rev. ** Page 12 of 42 PRELIMINARY CYBLE-214015-01 The CYBLE-214015-01 schematic is shown in Figure 9. Figure 9. CYBLE-214015-01 Schematic Diagram Document Number: 002-15923 Rev. ** Page 13 of 42 PRELIMINARY CYBLE-214015-01 Critical Components List Table 6 details the critical components used in the CYBLE-214015-01 module. Table 6. Critical Component List Component Reference Designator Silicon U1 Description 76-pin WLCSP Programmable System-on-Chip (PSoC) with BLE Crystal Y1 24.000 MHz, 10 pF Crystal Y2 32.768 kHz, 12.5 pF Antenna Design Table 7 details antenna used on the CYBLE-214015-01 module. The Cypress module performance improves many of these characteristics. For more information, see Table 9 on page 15. Table 7. Trace Antenna Specifications Item Frequency Range Description 2400 MHz-2500 MHz Peak Gain 0.5 dBi typical Average Gain -0.5 dBi typical Return Loss 10 dB minimum Document Number: 002-15923 Rev. ** Page 14 of 42 PRELIMINARY CYBLE-214015-01 Electrical Specification Table 8 details the absolute maximum electrical characteristics for the Cypress BLE module. Table 8. CYBLE-214015-01 Absolute Maximum Ratings Parameter Description Min Typ Max Unit Details/Conditions VDDD_ABS VDD, VDDA or VDDR supply relative to VSS (VSSD = VSSA) -0.5 - 6 V Absolute maximum VCCD_ABS Direct digital core voltage input relative to VSSD -0.5 - 1.95 V Absolute maximum VDDD_RIPPLE Maximum power supply ripple for VDD, VDDA and VDDR input voltage - - 100 mV VGPIO_ABS GPIO voltage -0.5 - VDD +0.5 V Absolute maximum IGPIO_ABS Maximum current per GPIO -25 - 25 mA Absolute maximum IGPIO_injection GPIO injection current: Maximum for VIH > VDD and minimum for VIL < VSS -0.5 - 0.5 mA Absolute maximum current injected per pin LU Pin current for latch up -200 200 mA - Unit Details/Conditions 3.0V supply Ripple frequency of 100 kHz to 750 kHz Table 9 details the RF characteristics for the Cypress BLE module. Table 9. CYBLE-214015-01 RF Performance Characteristics Parameter Description Min Typ Max -18 0 3 dBm Configurable via register settings - -87 - dBm Guaranteed by design simulation RFO RF output power on ANT RXS RF receive sensitivity on ANT FR Module frequency range 2400 - 2480 MHz - GP Peak gain - 0.5 - dBi - GAvg Average gain - -0.5 - dBi - RL Return loss - -10 - dB - Table 10 through Table 51 list the module level electrical characteristics for the CYBLE-214015-01. All specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71V to 5.5V, except where noted. Table 10. CYBLE-214015-01 DC Specifications Parameter Description Min VDD1 Power supply input voltage (VDD = VDDA = VDDR) 1.71 VDD2 Power supply input voltage unregulated (VDD = VDDA = VDDR) 1.71 VDDR1 Radio supply voltage (radio on) 1.9 VDDR2 Radio supply voltage (radio off) Typ Max Unit Details/Conditions - 5.5 V With regulator enabled 1.8 1.89 V Internally unregulated supply - 5.5 V - 1.71 - 5.5 V - 1.7 - mA T = 25 C, VDD = 3.3 V Active Mode, VDD = 1.71 V to 5.5 V IDD3 Execute from flash; CPU at 3 MHz - IDD4 Execute from flash; CPU at 3 MHz - - - mA T = -40 C to 85 C IDD5 Execute from flash; CPU at 6 MHz - 2.5 - mA T = 25 C, VDD = 3.3 V IDD6 Execute from flash; CPU at 6 MHz - - - mA T = -40 C to 85 C IDD7 Execute from flash; CPU at 12 MHz - 4 - mA T = 25 C, VDD = 3.3 V Document Number: 002-15923 Rev. ** Page 15 of 42 PRELIMINARY CYBLE-214015-01 Table 10. CYBLE-214015-01 DC Specifications (continued) Parameter Description Min Typ Max Unit Details/Conditions IDD8 Execute from flash; CPU at 12 MHz - - - mA T = -40 C to 85 C IDD9 Execute from flash; CPU at 24 MHz - 7.1 - mA T = 25 C, VDD = 3.3 V IDD10 Execute from flash; CPU at 24 MHz - - - mA T = -40 C to 85 C IDD11 Execute from flash; CPU at 48 MHz - 13.4 - mA T = 25 C, VDD = 3.3 V IDD12 Execute from flash; CPU at 48 MHz - - - mA T = -40 C to 85 C - - - mA T = 25 C, VDD = 3.3 V, SYSCLK = 3 MHz - - - mA T = 25 C, VDD = 3.3 V, SYSCLK = 3 MHz T = 25 C, VDD = 3.3 V Sleep Mode, VDD = 1.71 V to 5.5 V IDD13 IMO on Sleep Mode, VDD and VDDR = 1.9 V to 5.5 V IDD14 ECO on Deep-Sleep Mode, VDD = 1.71 V to 3.6 V IDD15 WDT with WCO on - 1.3 - A IDD16 WDT with WCO on - - - A T = -40 C to 85 C IDD17 WDT with WCO on - - - A T = 25 C, VDD = 5 V IDD18 WDT with WCO on - - - A T = -40 C to 85 C Deep-Sleep Mode, VDD = 1.71 V to 1.89 V (Regulator Bypassed) IDD19 WDT with WCO on - - - A T = 25 C IDD20 WDT with WCO on - - - A T = -40 C to 85 C Hibernate Mode, VDD = 1.71 V to 3.6 V IDD27 GPIO and reset active - 150 - nA T = 25 C, VDD = 3.3 V IDD28 GPIO and reset active - - - nA T = -40 C to 85 C Hibernate Mode, VDD = 3.6 V to 5.5 V IDD29 GPIO and reset active - - - nA T = 25 C, VDD = 5 V IDD30 GPIO and reset active - - - nA T = -40 C to 85 C Stop Mode, VDD = 1.71 V to 3.6 V IDD33 Stop-mode current (VDD) - 20 - nA T = 25 C, VDD = 3.3 V IDD34 Stop-mode current (VDDR) - 40 - nA T = 25 C, VDDR = 3.3 V IDD35 Stop-mode current (VDD) - - - nA T = -40 C to 85 C IDD36 Stop-mode current (VDDR) - - - nA T = -40 C to 85 C, VDDR = 1.9 V to 3.6 V Stop Mode, VDD = 3.6 V to 5.5 V IDD37 Stop-mode current (VDD) - - - nA T = 25 C, VDD = 5 V IDD38 Stop-mode current (VDDR) - - - nA T = 25 C, VDDR = 5 V IDD39 Stop-mode current (VDD) - - - nA T = -40 C to 85 C IDD40 Stop-mode current (VDDR) - - - nA T = -40 C to 85 C Document Number: 002-15923 Rev. ** Page 16 of 42 PRELIMINARY CYBLE-214015-01 Table 11. AC Specifications Parameter Description Min Typ Max Unit Details/Conditions 1.71V VDD 5.5V FCPU CPU frequency DC - 48 MHz TSLEEP Wakeup from Sleep mode - 0 - s Guaranteed by characterization TDEEPSLEEP Wakeup from Deep-Sleep mode - - 25 s 24-MHz IMO. Guaranteed by characterization THIBERNATE Wakeup from Hibernate mode - - 800 s Guaranteed by characterization TSTOP Wakeup from Stop mode - - 2 ms XRES wakeup Min Typ Max Unit GPIO Table 12. GPIO DC Specifications Parameter [4] VIH VIL VOH VOL Description Input voltage HIGH threshold 0.7 x VDD - - V LVTTL input, VDD < 2.7 V 0.7 x VDD - - V LVTTL input, VDD 2.7 V 2.0 - - V - - 0.3 x VDD V Input voltage LOW threshold Details/Conditions CMOS input - - CMOS input LVTTL input, VDD < 2.7 V - - 0.3 x VDD V - LVTTL input, VDD 2.7 V - - 0.8 V - Output voltage HIGH level VDD - 0.6 - - V IOH = 4 mA at 3.3-V VDD Output voltage HIGH level VDD - 0.5 - - V IOH = 1 mA at 1.8-V VDD Output voltage LOW level - - 0.6 V IOL = 8 mA at 3.3-V VDD Output voltage LOW level - - 0.6 V IOL = 4 mA at 1.8-V VDD IOL = 3 mA at 3.3-V VDD - - 0.4 V RPULLUP Output voltage LOW level Pull-up resistor 3.5 5.6 8.5 k RPULLDOWN Pull-down resistor 3.5 5.6 8.5 k IIL Input leakage current (absolute value) - - 2 nA IIL_CTBM Input leakage on CTBm input pins - - 4 nA - CIN Input capacitance - - 7 pF - - - 25 C, VDD = 3.3 V VHYSTTL Input hysteresis LVTTL 25 40 - mV VHYSCMOS Input hysteresis CMOS 0.05 x VDD - - 1 - IDIODE Current through protection diode to VDD/VSS - - 100 A - ITOT_GPIO Maximum total source or sink chip current - - 200 mA - VDD > 2.7 V Note 4. VIH must not exceed VDD + 0.2 V. Document Number: 002-15923 Rev. ** Page 17 of 42 PRELIMINARY CYBLE-214015-01 Table 13. GPIO AC Specifications Parameter TRISEF Description Rise time in Fast-Strong mode Min 2 Typ - Max 12 TFALLF Fall time in Fast-Strong mode 2 - 12 TRISES Rise time in Slow-Strong mode 10 - 60 ns 3.3-V VDDD, CLOAD = 25 pF TFALLS Fall time in Slow-Strong mode 10 - 60 ns 3.3-V VDDD, CLOAD = 25 pF FGPIOUT1 GPIO Fout; 3.3 V VDD 5.5 V Fast-Strong mode - - 33 MHz 90/10%, 25 pF load, 60/40 duty cycle FGPIOUT2 GPIO Fout; 1.7 VVDD 3.3 V Fast-Strong mode GPIO Fout; 3.3 V VDD 5.5 V Slow-Strong mode - - 16.7 MHz 90/10%, 25 pF load, 60/40 duty cycle - - 7 MHz 90/10%, 25 pF load, 60/40 duty cycle FGPIOUT4 GPIO Fout; 1.7 V VDD 3.3 V Slow-Strong mode - - 3.5 MHz 90/10%, 25 pF load, 60/40 duty cycle FGPIOIN GPIO input operating frequency 1.71 V VDD 5.5 V - - 48 MHz 90/10% VIO FGPIOUT3 Unit Details/Conditions ns 3.3-V VDDD, CLOAD = 25 pF ns 3.3-V VDDD, CLOAD = 25 pF XRES Table 14. XRES DC Specifications Parameter VIH Description Input voltage HIGH threshold VIL Input voltage LOW threshold RPULLUP Pull-up resistor Min Typ 0.7 x VDDD - Max - Unit Details/Conditions V CMOS input - - 0.3 x VDDD V 3.5 5.6 8.5 k CMOS input - CIN Input capacitance - 3 - pF - VHYSXRES Input voltage hysteresis - 100 - mV - IDIODE Current through protection diode to VDD/VSS - - 100 A - Min 1 Typ - Max - Unit s Details/Conditions Table 15. XRES AC Specifications Parameter TRESETWIDTH Description Reset pulse width - Analog Peripherals Opamp Table 16. Opamp Specifications Parameter Description Min Typ Max Unit Details/Conditions 1300 A - IDD (Opamp Block Current. VDD = 1.8 V. No Load) IDD_HI Power = high - 1000 IDD_MED Power = medium - 500 - A - IDD_LOW Power = low - 250 350 A - 6 - - MHz - GBW (Load = 20 pF, 0.1 mA. VDDA = 2.7 V) GBW_HI Power = high GBW_MED Power = medium 4 - - MHz - GBW_LO Power = low - 1 - MHz - 10 - - mA - IOUT_MAX (VDDA 2.7 V, 500 mV from Rail) IOUT_MAX_HI Power = high Document Number: 002-15923 Rev. ** Page 18 of 42 PRELIMINARY CYBLE-214015-01 Table 16. Opamp Specifications (continued) Parameter Description Min Typ Max Unit Details/Conditions IOUT_MAX_MID Power = medium 10 - - mA - IOUT_MAX_LO Power = low - 5 - mA - IOUT (VDDA = 1.71 V, 500 mV from Rail) IOUT_MAX_HI Power = high 4 - - mA - IOUT_MAX_MID Power = medium 4 - - mA - IOUT_MAX_LO Power = low - 2 - mA - VIN Charge pump on, VDDA 2.7 V -0.05 - VDDA - 0.2 V - VCM Charge pump on, VDDA 2.7 V -0.05 - VDDA - 0.2 V - VOUT (VDDA 2.7 V) VOUT_1 Power = high, ILOAD = 10 mA 0.5 - VDDA - 0.5 V - VOUT_2 Power = high, ILOAD = 1 mA 0.2 - VDDA - 0.2 V - VOUT_3 Power = medium, ILOAD = 1 mA 0.2 - VDDA - 0.2 V - VOUT_4 Power = low, ILOAD = 0.1 mA 0.2 - VDDA - 0.2 V VOS_TR Offset voltage, trimmed 1 0.5 1 mV High mode VOS_TR Offset voltage, trimmed - 1 - mV Medium mode VOS_TR Offset voltage, trimmed - 2 - mV Low mode - VOS_DR_TR Offset voltage drift, trimmed -10 3 10 V/C High mode VOS_DR_TR Offset voltage drift, trimmed - 10 - V/C Medium mode VOS_DR_TR Offset voltage drift, trimmed - 10 - V/C Low mode CMRR DC 65 70 - dB VDDD = 3.6 V, High-power mode PSRR At 1 kHz, 100-mV ripple 70 85 - dB VDDD = 3.6 V VN1 Input referred, 1 Hz-1 GHz, power = high - 94 - Vrms VN2 Input referred, 1 kHz, power = high - 72 - nV/rtHz - VN3 Input referred, 10 kHz, power = high - 28 - nV/rtHz - VN4 Input referred, 100 kHz, power = high - 15 - nV/rtHz - CLOAD Stable up to maximum load. Performance specs at 50 pF - - 125 pF Slew_rate Cload = 50 pF, Power = High, VDDA 2.7 V 6 - - V/sec T_op_wake From disable to enable, no external RC dominating - 300 - sec Noise - - - - Comp_mode (Comparator Mode; 50-mV Drive, TRISE = TFALL (Approx.) TPD1 Response time; power = high - 150 - ns - TPD2 Response time; power = medium - 400 - ns - TPD3 Response time; power = low - 2000 - ns - Vhyst_op Hysteresis - 10 - mV - - kHz - Deep-Sleep Mode (Deep-Sleep mode operation is only guaranteed for VDDA > 2.5 V) GBW_DS Gain bandwidth product - 50 IDD_DS Vos_DS Current - 15 - A - Offset voltage - 5 - mV - - 20 - V/C - 0.2 - VDD - 0.2 V - Vos_dr_DS Offset voltage drift Vout_DS Output voltage Document Number: 002-15923 Rev. ** Page 19 of 42 PRELIMINARY CYBLE-214015-01 Table 16. Opamp Specifications (continued) Parameter Vcm_DS Description Common mode voltage Min Typ Max Unit Details/Conditions 0.2 - VDD - 1.8 V - Min Typ Max Unit Details/Conditions - - 10 mV - Table 17. Comparator DC Specifications Parameter Description VOFFSET1 Input offset voltage, Factory trim VOFFSET2 Input offset voltage, Custom trim - - 6 mV - VOFFSET3 Input offset voltage, ultra-low-power mode - 12 - mV - VHYST Hysteresis when enabled - 10 35 mV VICM1 Input common mode voltage in normal mode 0 - VDDD - 0.1 V VICM2 Input common mode voltage in low-power mode 0 - VDDD V - VICM3 Input common mode voltage in ultra low-power mode 0 - VDDD - 1.15 V - CMRR Common mode rejection ratio 50 - - dB VDDD 2.7 V CMRR Common mode rejection ratio 42 - - dB VDDD 2.7 V - Modes 1 and 2 ICMP1 Block current, normal mode - - 400 A - ICMP2 Block current, low-power mode - - 100 A - ICMP3 Block current in ultra-low-power mode - 6 - A - ZCMP DC input impedance of comparator 35 - - M - Table 18. Comparator AC Specifications Min Typ Max Unit TRESP1 Parameter Response time, normal mode, 50-mV overdrive Description - 38 - ns 50-mV overdrive Details/Conditions TRESP2 Response time, low-power mode, 50-mV overdrive - 70 - ns 50-mV overdrive TRESP3 Response time, ultra-low-power mode, 50-mV overdrive - 2.3 - s 200-mV overdrive Min -5 Typ 1 Max 5 Unit C Temperature Sensor Table 19. Temperature Sensor Specifications Parameter TSENSACC Description Temperature-sensor accuracy Details/Conditions -40 to +85 C SAR ADC Table 20. SAR ADC DC Specifications Parameter Description Min Typ Max Unit Details/Conditions A_RES Resolution - - 12 bits A_CHNIS_S Number of channels - single-ended - - 8 - 8 full-speed A-CHNKS_D Number of channels - differential - - 4 - Diff inputs use neighboring I/O A-MONO Monotonicity - - - - Yes A_GAINERR Gain error - - 0.1 % With external reference Document Number: 002-15923 Rev. ** - Page 20 of 42 PRELIMINARY CYBLE-214015-01 Table 20. SAR ADC DC Specifications (continued) Parameter A_OFFSET Description Input offset voltage Min Typ Max Unit - - 2 mV Details/Conditions Measured with 1-V VREF A_ISAR Current consumption - - 1 mA - A_VINS Input voltage range - single-ended VSS - VDDA V - A_VIND Input voltage range - differential VSS - VDDA V - A_INRES Input resistance - - 2.2 k - A_INCAP Input capacitance - - 10 pF VREFSAR Trimmed internal reference to SAR -1 - 1 % Typ Max Unit - Percentage of Vbg (1.024 V) Table 21. SAR ADC AC Specifications Parameter Description Min Details/Conditions Measured at 1-V reference A_PSRR Power-supply rejection ratio 70 - - dB A_CMRR Common-mode rejection ratio 66 - - dB - A_SAMP Sample rate - - 1 Msps - Fsarintref SAR operating speed without external ref. bypass - - 100 Ksps A_SNR Signal-to-noise ratio (SNR) 65 - - dB FIN = 10 kHz A_BW Input bandwidth without aliasing - - A_SAMP/2 kHz - A_INL Integral nonlinearity. VDD = 1.71V to 5.5V, 1 Msps -1.7 - 2 LSB VREF = 1 V to VDD A_INL Integral nonlinearity. VDDD = 1.71 V to 3.6 V, 1 Msps -1.5 - 1.7 LSB VREF = 1.71 V to VDD A_INL Integral nonlinearity. VDD = 1.71 V to 5.5 V, 500 Ksps -1.5 - 1.7 LSB VREF = 1 V to VDD A_dnl Differential nonlinearity. VDD = 1.71 V to 5.5 V, 1 Msps -1 - 2.2 LSB VREF = 1 V to VDD A_DNL Differential nonlinearity. VDD = 1.71 V to 3.6 V, 1 Msps -1 - 2 LSB VREF = 1.71 V to VDD A_DNL Differential nonlinearity. VDD = 1.71 V to 5.5 V, 500 Ksps -1 - 2.2 LSB VREF = 1 V to VDD A_THD Total harmonic distortion - - -65 dB Min Typ Max Unit Details/Conditions 1.71 - 5.5 V - 12-bit resolution FIN = 10 kHz CSD Table 22. CSD Block Specifications Parameter Description VCSD Voltage range of operation IDAC1 DNL for 8-bit resolution -1 - 1 LSB - IDAC1 INL for 8-bit resolution -3 - 3 LSB - IDAC2 DNL for 7-bit resolution -1 - 1 LSB - IDAC2 INL for 7-bit resolution -3 - 3 LSB - Document Number: 002-15923 Rev. ** Page 21 of 42 PRELIMINARY CYBLE-214015-01 Table 22. CSD Block Specifications (continued) Parameter Description Min Typ Max Unit Details/Conditions SNR Ratio of counts of finger to noise 5 - - Ratio Capacitance range of 9 pF to 35 pF, 0.1-pF sensitivity. Radio is not operating during the scan IDAC1_CRT1 Output current of IDAC1 (8 bits) in High range - 612 - A - IDAC1_CRT2 Output current of IDAC1 (8 bits) in Low range - 306 - A - IDAC2_CRT1 Output current of IDAC2 (7 bits) in High range - 305 - A - IDAC2_CRT2 Output current of IDAC2 (7 bits) in Low range - 153 - A - Digital Peripherals Timer Table 23. Timer DC Specifications Min Typ Max Unit ITIM1 Parameter Block current consumption at 3 MHz Description - - 42 A 16-bit timer Details/Conditions ITIM2 Block current consumption at 12 MHz - - 130 A 16-bit timer ITIM3 Block current consumption at 48 MHz - - 535 A 16-bit timer Min Typ Max Unit Details/Conditions FCLK - 48 MHz - Table 24. Timer AC Specifications Parameter Description TTIMFREQ Operating frequency TCAPWINT Capture pulse width (internal) 2 x TCLK - - ns - TCAPWEXT Capture pulse width (external) 2 x TCLK - - ns - TTIMRES Timer resolution TCLK - - ns - TTENWIDINT Enable pulse width (internal) 2 x TCLK - - ns - TTENWIDEXT Enable pulse width (external) 2 x TCLK - - ns - TTIMRESWINT Reset pulse width (internal) 2 x TCLK - - ns - TTIMRESEXT Reset pulse width (external) 2 x TCLK - - ns - Min Typ Max Unit Details/Conditions Counter Table 25. Counter DC Specifications Parameter Description ICTR1 Block current consumption at 3 MHz - - 42 A 16-bit counter ICTR2 Block current consumption at 12 MHz - - 130 A 16-bit counter ICTR3 Block current consumption at 48 MHz - - 535 A 16-bit counter Table 26. Counter AC Specifications Parameter TCTRFREQ Description Operating frequency Min FCLK Typ - Max 48 Unit MHz Details/Conditions TCTRPWINT Capture pulse width (internal) 2 x TCLK - - ns - TCTRPWEXT Capture pulse width (external) 2 x TCLK - - ns - Document Number: 002-15923 Rev. ** - Page 22 of 42 PRELIMINARY CYBLE-214015-01 Table 26. Counter AC Specifications (continued) Parameter Min TCLK Typ - Max - Unit ns Details/Conditions TCTRES Description Counter Resolution TCENWIDINT Enable pulse width (internal) 2 x TCLK - - ns - TCENWIDEXT Enable pulse width (external) 2 x TCLK - - ns - TCTRRESWINT Reset pulse width (internal) 2 x TCLK - - ns - TCTRRESWEXT Reset pulse width (external) 2 x TCLK - - ns - - Pulse Width Modulation (PWM) Table 27. PWM DC Specifications Min Typ Max Unit IPWM1 Parameter Block current consumption at 3 MHz Description - - 42 A 16-bit PWM Details/Conditions IPWM2 Block current consumption at 12 MHz - - 130 A 16-bit PWM IPWM3 Block current consumption at 48 MHz - - 535 A 16-bit PWM Min Typ Max Unit Details/Conditions Table 28. PWM AC Specifications Parameter Description TPWMFREQ Operating frequency FCLK - 48 MHz - TPWMPWINT Pulse width (internal) 2 x TCLK - - ns - TPWMEXT Pulse width (external) 2 x TCLK - - ns - TPWMKILLINT Kill pulse width (internal) 2 x TCLK - - ns - TPWMKILLEXT Kill pulse width (external) 2 x TCLK - - ns - TPWMEINT Enable pulse width (internal) 2 x TCLK - - ns - TPWMENEXT Enable pulse width (external) 2 x TCLK - - ns - TPWMRESWINT Reset pulse width (internal) 2 x TCLK - - ns - TPWMRESWEXT Reset pulse width (external) 2 x TCLK - - ns - LCD Direct Drive Table 29. LCD Direct Drive DC Specifications Spec ID SID228 Parameter Description Operating current in low-power mode Min - Typ 17.5 Max - Unit A Details/Conditions 16 x 4 small segment display at 50 Hz ILCDLOW SID229 CLCDCAP LCD capacitance per segment/common driver - 500 5000 pF - SID230 LCDOFFSET SID231 ILCDOP1 Long-term segment offset - 20 - mV LCD system operating current VBIAS = 5 V - 2 - mA SID232 ILCDOP2 LCD system operating current VBIAS = 3.3 V - 2 - mA Min 10 Typ 50 Max 150 Unit Hz - 32 x 4 segments. 50 Hz at 25 C 32 x 4 segments 50 Hz at 25 C Table 30. LCD Direct Drive AC Specifications Spec ID SID233 Parameter FLCD Description LCD frame rate Document Number: 002-15923 Rev. ** Details/Conditions - Page 23 of 42 PRELIMINARY CYBLE-214015-01 Serial Communication Table 31. Fixed I2C DC Specifications Parameter Description Min Typ Max Unit Details/Conditions II2C1 Block current consumption at 100 kHz - - 50 A - II2C2 Block current consumption at 400 kHz - - 155 A - II2C3 Block current consumption at 1 Mbps - - 390 A - - - 1.4 A - Min Typ Max Unit Details/Conditions - - 400 kHz - 2 II2C4 I C enabled in Deep-Sleep mode Table 32. Fixed I2C AC Specifications Parameter Description Bit rate FI2C1 Table 33. Fixed UART DC Specifications Description Min Typ Max Unit Details/Conditions IUART1 Parameter Block current consumption at 100 kbps - - 55 A - IUART2 Block current consumption at 1000 kbps - - 312 A - Min Typ Max Unit Details/Conditions - - 1 Mbps - Table 34. Fixed UART AC Specifications Parameter FUART Description Bit rate Table 35. Fixed SPI DC Specifications Min Typ Max Unit Details/Conditions ISPI1 Parameter Block current consumption at 1 Mbps Description - - 360 A - ISPI2 Block current consumption at 4 Mbps - - 560 A - ISPI3 Block current consumption at 8 Mbps - - 600 A - Table 36. Fixed SPI AC Specifications Parameter FSPI Description Min Typ Max Unit Details/Conditions SPI operating frequency (master; 6x over sampling) - - 8 MHz - Table 37. Fixed SPI Master Mode AC Specifications Parameter Description Min Typ Max Unit Details/Conditions - TDMO MOSI valid after SCLK driving edge - - 18 ns TDSI MISO valid before SCLK capturing edge Full clock, late MISO sampling used 20 - - ns Full clock, late MISO sampling THMO Previous MOSI data hold time 0 - - ns Referred to Slave capturing edge Document Number: 002-15923 Rev. ** Page 24 of 42 PRELIMINARY CYBLE-214015-01 Table 38. Fixed SPI Slave Mode AC Specifications Parameter Description Min Typ Max Unit TDMI MOSI valid before SCLK capturing edge 40 - - ns TDSO MISO valid after SCLK driving edge - - 42 + 3 x TCPU ns TDSO_ext MISO Valid after SCLK driving edge in external clock mode. VDD < 3.0V - - 50 ns THSO Previous MISO data hold time 0 - - ns TSSELSCK SSEL valid to first SCK valid edge 100 - - ns Memory Table 39. Flash DC Specifications Parameter VPE Description Erase and program voltage Min 1.71 Typ - Max 5.5 TWS48 Unit V Details/Conditions Number of Wait states at 32 MHz-48 MHz 2 - - - CPU execution from flash TWS32 Number of Wait states at 16 MHz-32 MHz 1 - - - CPU execution from flash TWS16 Number of Wait states for 0 MHz-16 MHz 0 - - - CPU execution from flash - Table 40. Flash AC Specifications Parameter TROWWRITE[5] TROWERASE[5] Min Typ Max Unit Row (block) write time (erase and program) Description - - 20 ms Details/Conditions 13 ms - Row (block) = 256 bytes Row erase time - - TROWPROGRAM[5] TBULKERASE[5] TDEVPROG[5] Row program time after erase - - 7 ms - Bulk erase time (256 KB) - - 35 ms - FEND Flash endurance FRET FRET2 Total device program time - - 25 seconds - 100 K - - cycles - Flash retention. TA 55 C, 100 K P/E cycles. 20 - - years - Flash retention. TA 85 C, 10 K P/E cycles. 10 - - years - Note 5. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. Document Number: 002-15923 Rev. ** Page 25 of 42 PRELIMINARY CYBLE-214015-01 System Resources Power-on-Reset (POR) Table 41. POR DC Specifications Min Typ Max Unit Details/Conditions VRISEIPOR Parameter Rising trip voltage Description 0.80 - 1.45 V - VFALLIPOR Falling trip voltage 0.75 - 1.40 V - VIPORHYST Hysteresis 15 - 200 mV - Min - Typ - Max 1 Unit s Details/Conditions - Description Min Typ Max Unit Details/Conditions VFALLPPOR BOD trip voltage in Active and Sleep modes 1.64 - - V - VFALLDPSLP BOD trip voltage in Deep Sleep 1.4 - - V - Table 42. POR AC Specifications Parameter TPPOR_TR Description Precision power-on reset (PPOR) response time in Active and Sleep modes Table 43. Brown-Out Detect Parameter Table 44. Hibernate Reset Parameter VHBRTRIP Description BOD trip voltage in Hibernate Min 1.1 Typ - Max - Unit V Details/Conditions - Min Typ Max Unit Details/Conditions Voltage Monitors (LVD) Table 45. Voltage Monitor DC Specifications Parameter Description VLVI1 LVI_A/D_SEL[3:0] = 0000b 1.71 1.75 1.79 V - VLVI2 LVI_A/D_SEL[3:0] = 0001b 1.76 1.80 1.85 V - VLVI3 LVI_A/D_SEL[3:0] = 0010b 1.85 1.90 1.95 V - VLVI4 LVI_A/D_SEL[3:0] = 0011b 1.95 2.00 2.05 V - VLVI5 LVI_A/D_SEL[3:0] = 0100b 2.05 2.10 2.15 V - VLVI6 LVI_A/D_SEL[3:0] = 0101b 2.15 2.20 2.26 V - VLVI7 LVI_A/D_SEL[3:0] = 0110b 2.24 2.30 2.36 V - VLVI8 LVI_A/D_SEL[3:0] = 0111b 2.34 2.40 2.46 V - VLVI9 LVI_A/D_SEL[3:0] = 1000b 2.44 2.50 2.56 V - VLVI10 LVI_A/D_SEL[3:0] = 1001b 2.54 2.60 2.67 V - VLVI11 LVI_A/D_SEL[3:0] = 1010b 2.63 2.70 2.77 V - VLVI12 LVI_A/D_SEL[3:0] = 1011b 2.73 2.80 2.87 V - VLVI13 LVI_A/D_SEL[3:0] = 1100b 2.83 2.90 2.97 V - VLVI14 LVI_A/D_SEL[3:0] = 1101b 2.93 3.00 3.08 V - VLVI15 LVI_A/D_SEL[3:0] = 1110b 3.12 3.20 3.28 V - VLVI16 LVI_A/D_SEL[3:0] = 1111b 4.39 4.50 4.61 V - LVI_IDD Block current - - 100 A - Document Number: 002-15923 Rev. ** Page 26 of 42 PRELIMINARY CYBLE-214015-01 Table 46. Voltage Monitor AC Specifications Parameter Description TMONTRIP Min Typ Max Unit Details/Conditions - - 1 s - Min Typ Max Voltage monitor trip time SWD Interface Table 47. SWD Interface Specifications Parameter Description Unit Details/Conditions F_SWDCLK1 3.3 V VDD 5.5 V - - 14 MHz SWDCLK 1/3 CPU clock frequency F_SWDCLK2 1.71 V VDD 3.3 V - - 7 MHz SWDCLK 1/3 CPU clock frequency T_SWDI_SETUP T = 1/f SWDCLK 0.25 x T - - ns - T_SWDI_HOLD 0.25 x T - - ns - T = 1/f SWDCLK T_SWDO_VALID T = 1/f SWDCLK - - 0.5 x T ns - T_SWDO_HOLD 1 - - ns - T = 1/f SWDCLK Internal Main Oscillator Table 48. IMO DC Specifications Parameter Description Min Typ Max Unit Details/Conditions IIMO1 IMO operating current at 48 MHz - - 1000 A - IIMO2 IMO operating current at 24 MHz - - 325 A - IIMO3 IMO operating current at 12 MHz - - 225 A - IIMO4 IMO operating current at 6 MHz - - 180 A - IIMO5 IMO operating current at 3 MHz - - 150 A - Min Typ Max Unit Details/Conditions Table 49. IMO AC Specifications Parameter Description FIMOTOL3 Frequency variation from 3 to 48 MHz - - 2 % FIMOTOL3 IMO startup time - 12 - s - Min Typ Max Unit Details/Conditions - 0.3 1.05 A - With API-called calibration Internal Low-Speed Oscillator Table 50. ILO DC Specifications Parameter IILO2 Description ILO operating current at 32 kHz Table 51. ILO AC Specifications Min Typ Max Unit Details/Conditions TSTARTILO1 Parameter ILO startup time Description - - 2 ms - FILOTRIM1 32-kHz trimmed frequency 15 32 50 kHz - Table 52. Recommended ECO Trim Value Parameter ECOTRIM Description 24-MHz trim value (firmware configuration) Document Number: 002-15923 Rev. ** Value Details/Conditions 0x00009595 Recommended trim value that needs to be loaded to register CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG Page 27 of 42 PRELIMINARY CYBLE-214015-01 Table 53. UDB AC Specifications Parameter Description Min Typ Max Unit Details/Conditions FMAX-TIMER Max frequency of 16-bit timer in a UDB pair - - 48 MHz - FMAX-ADDER Max frequency of 16-bit adder in a UDB pair - - 48 MHz - FMAX_CRC Max frequency of 16-bit CRC/PRS in a UDB pair - - 48 MHz - - - 48 MHz - Data Path performance PLD Performance in UDB FMAX_PLD Max frequency of 2-pass PLD function in a UDB pair Clock to Output Performance TCLK_OUT_UDB1 Prop. delay for clock in to data out at 25 C, Typical - 15 - ns - TCLK_OUT_UDB2 Prop. delay for clock in to data out, Worst case - 25 - ns - Table 54. BLE Subsystem Parameter Description RF Receiver Specification RXS, IDLE RX sensitivity with idle transmitter RX sensitivity with idle transmitter excluding Balun loss RXS, DIRTY RX sensitivity with dirty transmitter RXS, HIGHGAIN RX sensitivity in high-gain mode with idle transmitter PRXMAX Maximum input power CI1 CI2 CI3 CI4 CI5 CI3 OBB1 OBB2 Cochannel interference, Wanted signal at -67 dBm and Interferer at FRX Adjacent channel interference Wanted signal at -67 dBm and Interferer at FRX 1 MHz Adjacent channel interference Wanted signal at -67 dBm and Interferer at FRX 2 MHz Adjacent channel interference Wanted signal at -67 dBm and Interferer at FRX 3 MHz Adjacent channel interference Wanted Signal at -67 dBm and Interferer at Image frequency (FIMAGE) Adjacent channel interference Wanted signal at -67 dBm and Interferer at Image frequency (FIMAGE 1 MHz) Out-of-band blocking, Wanted signal at -67 dBm and Interferer at F = 30 MHz-2000 MHz Out-of-band blocking, Wanted signal at -67 dBm and Interferer at F = 2003 MHz-2399 MHz Document Number: 002-15923 Rev. ** Min Typ Max Unit Details/Conditions - - -89 -91 - - dBm dBm - -87 -70 dBm - -91 - dBm - Guaranteed by design simulation RF-PHY Specification (RCV-LE/CA/01/C) - -10 -1 - dBm - 9 21 dB - 3 15 dB - -29 - dB RF-PHY Specification (RCV-LE/CA/03/C) - -39 - dB RF-PHY Specification (RCV-LE/CA/03/C) - -20 - dB RF-PHY Specification (RCV-LE/CA/03/C) - -30 - dB RF-PHY Specification (RCV-LE/CA/03/C) -30 -27 - dBm RF-PHY Specification (RCV-LE/CA/04/C) -35 -27 - dBm RF-PHY Specification (RCV-LE/CA/04/C) RF-PHY Specification (RCV-LE/CA/06/C) RF-PHY Specification (RCV-LE/CA/03/C) RF-PHY Specification (RCV-LE/CA/03/C) Page 28 of 42 PRELIMINARY CYBLE-214015-01 Table 54. BLE Subsystem (continued) Parameter OBB3 OBB4 IMD RXSE1 RXSE2 Description Out-of-band blocking, Wanted signal at -67 dBm and Interferer at F = 2484 MHz-2997 MHz Out-of-band blocking, Wanted signal a -67 dBm and Interferer at F = 3000 MHz-12750 MHz Intermodulation performance Wanted signal at -64 dBm and 1-Mbps BLE, third, fourth, and fifth offset channel Receiver spurious emission 30 MHz to 1.0 GHz Receiver spurious emission 1.0 GHz to 12.75 GHz RF Transmitter Specifications TXP, ACC RF power accuracy TXP, RANGE RF power control range TXP, 0dBm Output power, 0-dB Gain setting (PA7) TXP, MAX Output power, maximum power setting (PA10) TXP, MIN Output power, minimum power setting (PA1) F2AVG Average frequency deviation for 10101010 pattern F1AVG Average frequency deviation for 11110000 pattern EO Eye opening = F2AVG/F1AVG Min -35 Typ -27 Max - Unit dBm Details/Conditions RF-PHY Specification (RCV-LE/CA/04/C) -30 -27 - dBm RF-PHY Specification (RCV-LE/CA/04/C) -50 - - dBm RF-PHY Specification (RCV-LE/CA/05/C) - - -57 dBm - - -47 dBm 100-kHz measurement bandwidth ETSI EN300 328 V1.8.1 1-MHz measurement bandwidth ETSI EN300 328 V1.8.1 - - - - - 185 1 20 0 3 -18 - - - - - - - dB dB dBm dBm dBm kHz 225 250 275 kHz 0.8 - - FTX, ACC Frequency accuracy -150 - 150 kHz FTX, MAXDR Maximum frequency drift -50 - 50 kHz FTX, INITDR Initial frequency drift -20 - 20 kHz FTX, DR Maximum drift rate -20 - 20 IBSE1 In-band spurious emission at 2-MHz offset - - -20 kHz/ 50 s dBm IBSE2 In-band spurious emission at 3-MHz offset - - -30 dBm - - -55.5 dBm - - - - - RF-PHY Specification (TRM-LE/CA/05/C) RF-PHY Specification (TRM-LE/CA/05/C) RF-PHY Specification (TRM-LE/CA/05/C) RF-PHY Specification (TRM-LE/CA/06/C) RF-PHY Specification (TRM-LE/CA/06/C) RF-PHY Specification (TRM-LE/CA/06/C) RF-PHY Specification (TRM-LE/CA/06/C) RF-PHY Specification (TRM-LE/CA/03/C) RF-PHY Specification (TRM-LE/CA/03/C) FCC-15.247 - - -41.5 dBm FCC-15.247 - - - - - - 18.7 16.4 21.5 20 16.5 15.6 - - - - - - mA mA mA mA mA mA - Measured at VDDR - - - Measured at VDDR TXSE1 Transmitter spurious emissions (average), <1.0 GHz TXSE2 Transmitter spurious emissions (average), >1.0 GHz RF Current Specifications IRX Receive current in normal mode IRX_RF Radio receive current in normal mode IRX, HIGHGAIN Receive current in high-gain mode ITX, 3dBm TX current at 3-dBm setting (PA10) ITX, 0dBm TX current at 0-dBm setting (PA7) ITX_RF, 0dBm Radio TX current at 0 dBm setting (PA7) Document Number: 002-15923 Rev. ** Page 29 of 42 PRELIMINARY CYBLE-214015-01 Table 54. BLE Subsystem (continued) Parameter ITX_RF, 0dBm Description Radio TX current at 0 dBm excluding Balun loss Min - Typ 14.2 Max - Unit mA ITX,-3dBm ITX,-6dBm ITX,-12dBm ITX,-18dBm Iavg_1sec, 0dBm TX current at -3-dBm setting (PA4) TX current at -6-dBm setting (PA3) TX current at -12-dBm setting (PA2) TX current at -18-dBm setting (PA1) Average current at 1-second BLE connection interval - - - - - 15.5 14.5 13.2 12.5 17.1 - - - - - mA mA mA mA A Iavg_4sec, 0dBm Average current at 4-second BLE connection interval - 6.1 - A 2400 - - - - - 2 1000 120 75 2482 - - 140 120 MHz MHz kbps s s - - - - - - - - 5 1 6 - - - dB dB s - - - General RF Specifications FREQ RF operating frequency CHBW Channel spacing DR On-air data rate IDLE2TX BLE.IDLE to BLE. TX transition time IDLE2RX BLE.IDLE to BLE. RX transition time RSSI Specifications RSSI, ACC RSSI accuracy RSSI, RES RSSI resolution RSSI, PER RSSI sample period Document Number: 002-15923 Rev. ** Details/Conditions Guaranteed by design simulation - - - - TXP: 0 dBm; 20-ppm master and slave clock accuracy. For empty PDU exchange. TXP: 0 dBm; 20-ppm master and slave clock accuracy. For empty PDU exchange. Page 30 of 42 PRELIMINARY CYBLE-214015-01 Environmental Specifications Environmental Compliance This Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant. RF Certification The CYBLE-214015-01 module is certified under the following RF certification standards: FCC ID: WAP4008 CE IC: 7922A-4008 MIC: 203-JN0505 KC: MSIP-CRM-Cyp-4008 Environmental Conditions Table 55 describes the operating and storage conditions for the Cypress BLE module. Table 55. Environmental Conditions for CYBLE-214015-01 Description Operating temperature Operating humidity (relative, non-condensation) Thermal ramp rate Minimum Specification Maximum Specification -40 C 85 C 5% 85% - 3 C/minute -40 C 85 C Storage temperature and humidity - 85 C at 85% ESD: Module integrated into system Components[6] - 15 kV Air 2.2 kV Contact Storage temperature ESD and EMI Protection Exposed components require special attention to ESD and electromagnetic interference (EMI). A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability. Note 6. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM. Document Number: 002-15923 Rev. ** Page 31 of 42 PRELIMINARY CYBLE-214015-01 Regulatory Information FCC FCC NOTICE: The device CYBLE-214015-01 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407. Transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. CAUTION: The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user's authority to operate the equipment. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates and can radiate radio frequency energy and, if not installed and used in accordance with the instructions,e may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help LABELING REQUIREMENTS: The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: WAP4008. In any case the end product must be labeled exterior with "Contains FCC ID: WAP4008" ANTENNA WARNING: This device is tested with a standard SMA connector and with the antennas listed in Table 7 on page 14. When integrated in the OEMs product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions. RF EXPOSURE: To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved antenna in the previous. The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas in Table 7 on page 14, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed. The radiated output power of CYBLE-214015-01 is far below the FCC radio frequency exposure limits. Nevertheless, use CYBLE-214015-01 in such a manner that minimizes the potential for human contact during normal operation. End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance. Document Number: 002-15923 Rev. ** Page 32 of 42 PRELIMINARY CYBLE-214015-01 Industry Canada (IC) Certification CYBLE-214015-01 is licensed to meet the regulatory requirements of Industry Canada (IC), License: IC: 7922A-4008 Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca. This device has been designed to operate with the antennas listed in Table 7 on page 14, having a maximum gain of 0.5 dBi. Antennas not included in this list or having a gain greater than 0.5 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. IC NOTICE: The device CYBLE-214015-01 complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. IC RADIATION EXPOSURE STATEMENT FOR CANADA This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Le present appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisee aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioelectrique subi, meme si le brouillage est susceptible d'en compromettre le fonctionnement. LABELING REQUIREMENTS: The Original Equipment Manufacturer (OEM) must ensure that IC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the IC Notice above. The IC identifier is 7922A-4008. In any case, the end product must be labeled in its exterior with "Contains IC: 7922A-4008". European R&TTE Declaration of Conformity Hereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-214015-01 complies with the essential requirements and other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the Directive 1999/5/EC, the end-customer equipment should be labeled as follows: All versions of the CYBLE-214015-01 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway. Document Number: 002-15923 Rev. ** Page 33 of 42 PRELIMINARY CYBLE-214015-01 MIC Japan CYBLE-214015-01 is certified as a module with type certification number 203-JN0505. End products that integrate CYBLE-214015-01 do not need additional MIC Japan certification for the end product. End product can display the certification label of the embedded module. KC Korea CYBLE-214015-01 is certified for use in Korea with certificate number MSIP-CRM-Cyp-4008. Document Number: 002-15923 Rev. ** Page 34 of 42 PRELIMINARY CYBLE-214015-01 Packaging Table 56. Solder Reflow Peak Temperature Module Part Number Package CYBLE-214015-01 32-pad SMT Maximum Peak Temperature Maximum Time at PeakTemperature 260 C 30 seconds No. of Cycles 2 Table 57. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Module Part Number Package MSL CYBLE-214015-01 32-pad SMT MSL 3 The CYBLE-214015-01 is offered in tape and reel packaging. Figure 10 details the tape dimensions used for the CYBLE-214015-01. Figure 10. CYBLE-214015-01 Tape Dimensions Figure 11 details the orientation of the CYBLE-214015-01 in the tape as well as the direction for unreeling. Figure 11. Component Orientation in Tape and Unreeling Direction Document Number: 002-15923 Rev. ** Page 35 of 42 PRELIMINARY CYBLE-214015-01 Figure 12 details reel dimensions used for the CYBLE-214015-01. Figure 12. Reel Dimensions The CYBLE-214015-01 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The center-of-mass for the CYBLE-214015-01 is detailed in Figure 13. Figure 13. CYBLE-214015-01 Center of Mass Document Number: 002-15923 Rev. ** Page 36 of 42 PRELIMINARY CYBLE-214015-01 Ordering Information Table 58 lists the CYBLE-214015-01 part number and features. Table 59 lists the reel shipment quantities for the CYBLE-214015-01. Table 58. Ordering Information SRAM (KB) UDB Opamp (CTBm) CapSense Direct LCD Drive 12-bit SAR ADC LP Comparators TCPWM Blocks SCB Blocks PWMs (using UDBs) I2S (using UDB) GPIO Package CYBLE-214015-01 Flash (KB) MPN Max CPU Speed (MHz) Features 48 256 32 4 4 1 Msps 1 4 2 4 25 32-SMT Table 59. Tape and Reel Package Quantity and Minimum Order Amount Description Minimum Reel Quantity Maximum Reel Quantity Reel Quantity 500 500 Minimum Order Quantity (MOQ) 500 - Order Increment (OI) 500 - Comments Ships in 500 unit reel quantities. The CYBLE-214015-01 is offered in tape and reel packaging. The CYBLE-214015-01 ships with a maximum of 500 units/reel. Part Numbering Convention The part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows. For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website. U.S. Cypress Headquarters Address U.S. Cypress Headquarter Contact Info Cypress website address Document Number: 002-15923 Rev. ** 198 Champion Court, San Jose, CA 95134 (408) 943-2600 http://www.cypress.com Page 37 of 42 PRELIMINARY CYBLE-214015-01 Acronyms Table 60. Acronyms Used in this Document Acronym Description ABUS analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus Table 60. Acronyms Used in this Document (continued) Acronym Description EMIF external memory interface EOC end of conversion EOF end of frame EPSR execution program status register ESD electrostatic discharge ETM embedded trace macrocell ALU arithmetic logic unit FCC Federal Communications Commission AMUXBUS analog multiplexer bus FET field-effect transistor API application programming interface FIR finite impulse response, see also IIR APSR application program status register FPB flash patch and breakpoint ARM(R) advanced RISC machine, a CPU architecture FS full-speed ATM automatic thump mode BLE Bluetooth Low Energy GPIO general-purpose input/output, applies to a PSoC pin Bluetooth SIG Bluetooth Special Interest Group HCI host controller interface HVI high-voltage interrupt, see also LVI, LVD BW bandwidth IC integrated circuit CAN Controller Area Network, a communications protocol IDAC current DAC, see also DAC, VDAC CE European Conformity IDE integrated development environment CSA Canadian Standards Association I2C, or IIC Inter-Integrated Circuit, a communications protocol CMRR common-mode rejection ratio IC Industry Canada CPU central processing unit IIR infinite impulse response, see also FIR CRC cyclic redundancy check, an error-checking protocol ILO internal low-speed oscillator, see also IMO IMO internal main oscillator, see also ILO INL integral nonlinearity, see also DNL I/O input/output, see also GPIO, DIO, SIO, USBIO IPOR initial power-on reset interrupt program status register DAC digital-to-analog converter, see also IDAC, VDAC DFB digital filter block DIO digital input/output, GPIO with only digital capabilities, no analog. See GPIO. DMIPS Dhrystone million instructions per second IPSR DMA direct memory access, see also TD IRQ interrupt request DNL differential nonlinearity, see also INL ITM instrumentation trace macrocell DNU do not use KC Korea Certification DR port write data registers LCD liquid crystal display DSI digital system interconnect LIN Local Interconnect Network, a communications protocol. LR link register LUT lookup table LVD low-voltage detect, see also LVI LVI low-voltage interrupt, see also HVI LVTTL low-voltage transistor-transistor logic DWT data watchpoint and trace ECC error correcting code ECO external crystal oscillator EEPROM electrically erasable programmable read-only memory EMI electromagnetic interference Document Number: 002-15923 Rev. ** Page 38 of 42 PRELIMINARY Table 60. Acronyms Used in this Document (continued) Acronym Description CYBLE-214015-01 Table 60. Acronyms Used in this Document (continued) Acronym Description MAC multiply-accumulate SDA I2C serial data MCU microcontroller unit S/H sample and hold MIC Ministry of Internal Affairs and Communications (Japan) SINAD signal to noise and distortion ratio MISO master-in slave-out SIO special input/output, GPIO with advanced features. See GPIO. NC no connect NMI nonmaskable interrupt SMT NRZ non-return-to-zero surface-mount technology; a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBs NVIC nested vectored interrupt controller SOC start of conversion NVL nonvolatile latch, see also WOL SOF start of frame SPI Serial Peripheral Interface, a communications protocol SR slew rate Opamp operational amplifier PAL programmable array logic, see also PLD PC program counter PCB printed circuit board PGA programmable gain amplifier PHUB peripheral hub PHY physical layer PICU port interrupt control unit PLA programmable logic array PLD programmable logic device, see also PAL PLL phase-locked loop PMDD package material declaration data sheet POR power-on reset PRES precise power-on reset PRS pseudo random sequence PS port read data register (R) SRAM static random access memory SRES software reset STN super twisted nematic SWD serial wire debug, a test protocol SWV single-wire viewer TD transaction descriptor, see also DMA THD total harmonic distortion TIA transimpedance amplifier TN twisted nematic TRM technical reference manual TTL transistor-transistor logic TUV Germany: Technischer Uberwachungs-Verein (Technical Inspection Association) TX transmit UART Universal Asynchronous Transmitter Receiver, a communications protocol PSoC Programmable System-on-ChipTM PSRR power supply rejection ratio PWM pulse-width modulator UDB universal digital block QDID qualification design ID USB Universal Serial Bus RAM random-access memory RISC reduced-instruction-set computing USBIO USB input/output, PSoC pins used to connect to a USB port RMS root-mean-square VDAC voltage DAC, see also DAC, IDAC RTC real-time clock RTL register transfer language RTR remote transmission request RX receive SAR successive approximation register SC/CT switched capacitor/continuous time SCL I2C serial clock Document Number: 002-15923 Rev. ** WDT watchdog timer WOL write once latch, see also NVL WRES watchdog timer reset XRES external reset I/O pin XTAL crystal Page 39 of 42 PRELIMINARY CYBLE-214015-01 Document Conventions Units of Measure Table 61. Units of Measure Symbol Unit of Measure C degrees Celsius dB decibel dBm decibel-milliwatts fF femtofarads Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohour kHz kilohertz k kilo ohm ksps kilosamples per second LSB least significant bit Mbps megabits per second MHz megahertz M mega-ohm Msps megasamples per second A microampere F microfarad H microhenry s microsecond V microvolt W microwatt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond nV nanovolt ohm pF picofarad ppm parts per million ps picosecond s second sps samples per second sqrtHz square root of hertz V volt Document Number: 002-15923 Rev. ** Page 40 of 42 PRELIMINARY CYBLE-214015-01 Document History Page Document Title: CYBLE-214015-01, EZ-BLETM PSoC(R) Bluetooth 4.2 Module Document Number: 002-15923 Revision ECN Orig. of Change Submission Date ** 5428716 DSO 09/07/2016 Document Number: 002-15923 Rev. ** Description of Change Preliminary datasheet for CYBLE-214015-01 module. Page 41 of 42 PRELIMINARY CYBLE-214015-01 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC(R)Solutions Products ARM(R) Cortex(R) Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Lighting & Power Control cypress.com/iot cypress.com/powerpsoc Memory PSoC Touch Sensing USB Controllers Wireless/RF PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/memory cypress.com/psoc cypress.com/touch cypress.com/usb cypress.com/wireless (c) Cypress Semiconductor Corporation, 2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. 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Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-15923 Rev. ** Revised September 7, 2016 Page 42 of 42