SCAN921821
SCAN921821 Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1 (JTAG),
and At-Speed BIST
Literature Number: SNLS173B
SCAN921821
Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1
(JTAG), and At-Speed BIST
General Description
The SCAN921821 is a dual channel 18-bit serializer featur-
ing signal conditioning, boundary SCAN, and at-speed BIST.
Each serializer block transforms an 18-bit parallel LVCMOS/
LVTTL data bus into a single Bus LVDS data stream with
embedded clock. This single serial data stream with embed-
ded clock simplifies PCB design and reduces PCB cost by
narrowing data paths that in turn reduce PCB size and
layers. The single serial data stream also reduces cable
size, the number of connectors, and eliminates clock-to-data
and data-to-data skew.
Each channel also has an 8-level selectable pre-emphasis
feature that significantly extends performance over lossy
interconnect. Each channel also has its own powerdown pin
that saves power by reducing supply current when the chan-
nel is not being used.
The SCAN921821 also incorporates advanced testability
features including IEEE 1149.1 and at-speed BIST PRBS
pattern generation to facilitate verification of board and link
integrity
Features
n15-66 MHz Dual 18:1 Serializer with 2.376 Gbps total
throughput
n8-level selectable pre-emphasis on each channel drives
lossy cables and backplanes
n>15kV HBM ESD protection on Bus LVDS I/O pins
nRobust BLVDS serial data transmission with embedded
clock for exceptional noise immunity and low EMI
nPower saving control pin for each channel
nIEEE 1149.1 "JTAG" Compliant
nAt-Speed BIST - PRBS generation
nNo external coding required
nInternal PLL, no external PLL components required
nSingle +3.3V power supply
nLow power: 260 mW (typ) per channel at 66 MHz with
PRBS-15 pattern
nSingle 3.3 V supply
nFabricated with advanced CMOS process technology
nIndustrial −40 to +85˚C temperature range
nCompact 100-ball FBGA package
Block Diagram
20084401
November 2004
SCAN921821 - Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1 (JTAG), and At-Speed BIST
© 2004 National Semiconductor Corporation DS200844 www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
DD
) −0.3V to +4V
Supply Voltage (V
DD
)
Ramp Rate <30 V/ms
LVCMOS/LVTTL Input
Voltage −0.3V to (V
DD
+0.3V)
LVCMOS/LVTTL Output
Voltage −0.3V to (V
DD
+0.3V)
Bus LVDS Driver Output
Voltage −0.3V to +3.9V
Bus LVDS Output Short
Circuit Duration 10ms
Junction Temperature +150˚C
Storage Temperature −65˚C to +150˚C
Lead Temperature
(Soldering, 4 seconds) +220˚C
Maximum Package Power Dissipation at 25˚C
FBGA-100 3.57 W
Derating Above 25˚C 28.57 mW/˚C
Thermal resistance θ
JA
35˚C/W
θ
JC
11.1˚C/W
ESD Rating
HBM, 1.5 KΩ, 100 pF
All pins >8kV
Bus LVDS pins >15 kV
MM, 0Ω, 200 pF >1200 V
CDM >2kV
Recommended Operating
Conditions
Min Nom Max Units
Supply Voltage (V
DD
) 3.15 3.3 3.45 V
Operating Free Air
Temperature (T
A
)−40 +25 +85 ˚C
Clock Rate 15 66 MHz
Supply Noise 100 mV p-p
DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
LVCMOS/LVTTL Input DC Specifications
V
IH
High Level Input
Voltage 2.0 V
DD
V
V
IL
Low Level Input
Voltage GND 0.8 V
V
CL
Input Clamp Voltage I
CL
= −18 mA −1.5 -0.7 V
I
INH
High Level Input
Current V
IN
=V
DD
=V
DDMAX
−20 ±2 +20 µA
I
INL
Low Level Output
Current V
IN
=V
SS
,V
DD
=V
DDMAX
−10 ±2 +10 µA
1149.1 (JTAG) DC Specifications
V
IH
High Level Input
Voltage 2.0 V
DD
V
V
IL
Low Level Input
Voltage GND 0.8 V
V
CL
Input Clamp Voltage I
CL
= −18 mA −1.5 -0.7 V
I
INH
High Level Input
Current V
IN
=V
DD
=V
DDMAX
-20 +20 µA
I
INL
Low Level Output
Current V
IN
=V
SS
,V
DD
=V
DDMAX
-200 +200 µA
V
OH
High Level Output
Voltage I
OH
=−9mA 2.3 V
DD
mV
V
OL
Low Level Output
Voltage I
OL
= 9 mA GND 0.5 mV
I
OS
Output Short Circuit
Current V
OUT
= 0 V -100 -80 -50 mA
I
OZ
Output Tri-state
Current
PWDN or EN = 0.8V, V
OUT
=0V -10 +10 µA
PWDN or EN = 0.8V, V
OUT
= VDD -30 +30 µA
SCAN921821
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DC Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
Bus LVDS Output DC Specifications
V
OD
Output Differential
Voltage (DO+) -
(DO-)
Figure 10,R
L
= 100Ω450 500 550 mV
∆V
OD
Output Differential
Voltage Unbalance 215mV
V
OS
Offset Voltage 1.05 1.2 1.25 V
∆V
OS
Offset Voltage
Unbalance 2.7 15 mV
Q
POV
Pre-Emphasis Output
Voltage Ratio
|V
ODPRE
/V
OD
|
Pre-Emphasis Level = 1 1.10 1.24 1.35
Pre-Emphasis Level = 2 1.35 1.47 1.55
Pre-Emphasis Level = 3 1.55 1.70 1.80
Pre-Emphasis Level = 4 1.80 1.91 1.95
Pre-Emphasis Level = 5 1.95 2.08 2.20
Pre-Emphasis Level = 6 2.10 2.21 2.35
Pre-Emphasis Level = 7 2.15 2.30 2.50
I
OS
Output Short Circuit
Current DO = 0V, Din = H, PWDN and EN = 2.4V -10 -25 -75 mA
I
OZ
TRI-STATE Output
Current
PWDN or EN = 0.8V, DO = 0V (Note 4) -10 ±1 +10 µA
PWDN or EN = 0.8V, DO = VDD (Note 4) -55 ±6 +55 µA
Power Supply Current (DVDD, PVDD and AVDD Pins)
I
DD
Total Supply Current
(includes load
current)
C
L
= 15pF,
R
L
= 100 Ω
f = 66 MHz, PRBS-15
Pattern 160 225 mA
f = 66 MHz, Worst
Case Pattern
(Checker-Board
Pattern)
180 mA
I
DDP
Total Supply Current
with Pre-Emphasis
(includes load
current)
C
L
= 15pF,
R
L
= 100 Ω
f = 66 MHz, PRBS-15
Pattern 240 mA
f = 66 MHz, Worst
Case Pattern
(Checker-Board
Pattern)
280 325 mA
I
DDX
Supply Current
Powerdown PWDN = 0.8V, EN = 0.8V 1.0 3.0 mA
Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
t
TCP
Transmit Clock
Period 15.2 T 66.7 ns
t
TCIH
Transmit Clock High
Time 0.4T 0.5T 0.6T ns
t
TCIL
Transmit Clock Low
Time 0.4T 0.5T 0.6T ns
t
CLKT
TCLK Input
Transition Time 36ns
t
JIT
TCLK Input Jitter (Note 5) 80 ps (RMS)
SCAN921821
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AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
Serializer AC Specifications
t
LLHT
Bus LVDS
Low-to-High
Transition Time Figure 2, (Note 5)
R
L
= 100Ω,
C
L
=10pF to GND
0.3 0.4 ns
t
LHLT
Bus LVDS
High-to-Low
Transition Time
0.3 0.4 ns
t
DIS
DIN (0-17) Setup to
TCLK Figure 4, (Note 5)
R
L
= 100Ω,
C
L
=10pF to GND
1.9 ns
t
DIH
DIN (0-17) Hold from
TCLK 0.6 ns
t
HZD
DO ±HIGH to
TRI-STATE Delay
Figure 5
R
L
= 100Ω,
C
L
=10pF to GND
3.9 10 ns
t
LZD
DO ±LOW to
TRI-STATE Delay 3.5 10 ns
t
ZHD
DO ±TRI-STATE to
HIGH Delay 3.2 10 ns
t
ZLD
DO ±TRI-STATE to
LOW Delay 2.4 10 ns
t
SPW
SYNC Pulse Width Figure 7,
R
L
= 100Ω5*t
TCP
6*t
TCP
ns
t
PLD
Serializer PLL Lock
Time
Figure 6,
R
L
= 100Ω510*t
TCP
1024*t
TCP
ns
t
SD
Serializer Delay Figure 8 ,R
L
= 100Ωt
TCP
+ 2.5 t
TCP
+ 4.5 t
TCP
+ 6.5 ns
t
SKCC
Channel to Channel
Skew 70 ps
t
RJIT
Random Jitter Room Temperature, V
DD
= 3.3V,
66 MHz 6.1 ps
(RMS)
t
DJIT
Deterministic Jitter
Figure 9, (Note 5)
15 MHz -390 320 ps
66 MHz -60 30 ps
1149.1 (JTAG) AC Specifications
f
MAX
Maximum TCK Clock
Frequency
C
L
= 15pF,
R
L
= 500 Ω
25 MHz
t
S
TDI or TMS Setup to
TCK,HorL 2.4 ns
t
H
TDI or TMS Hold
from TCK, H or L 2.8 ns
t
W1
TCK Pulse Width, H
or L 10 ns
t
W2
TRST Pulse Width, L 10 ns
t
REC
Recovery Time,
TRST to TCK 2ns
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for VCC = 3.3V and TA= +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ∆VOD,
VTH and VTL which are differential voltages.
Note 4: IOZ is measured at each pin. The DOUT pin not under test is floated to isolate the TRI-STATE current flow.
Note 5: Guaranteed by Design (GBD) using statistical analysis.
SCAN921821
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AC Timing Diagrams and Test Circuits
20084403
FIGURE 1. “Worst Case” Serializer IDD Test Pattern
20084405
FIGURE 2. Serializer Bus LVDS Distributed Output Load and Transition Times
20084407
FIGURE 3. Serializer Input Clock Transition Time
20084408
FIGURE 4. Serializer Setup/Hold Times
SCAN921821
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AC Timing Diagrams and Test Circuits (Continued)
20084409
FIGURE 5. Serializer TRI-STATE Test Circuit and Timing
20084410
FIGURE 6. Serializer PLL Lock Time, and PWRDN TRI-STATE Delays
SCAN921821
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AC Timing Diagrams and Test Circuits (Continued)
20084434
FIGURE 7. SYNC Timing Delay
20084411
FIGURE 8. Serializer Delay
SCAN921821
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AC Timing Diagrams and Test Circuits (Continued)
Pre-emphasis Truth Table
PEM LEVEL PEM2 PEM1 PEM0
0 LLL
1LLH
2LHL
3LHH
4HLL
5HLH
6HHL
7 HHH
20084429
FIGURE 9. Deterministic Jitter and Ideal Bit Position
20084416
VOD = (DO+)–(DO−).
Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode.
FIGURE 10. V
OD
Diagram
SCAN921821
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Pin Diagram
SCAN921821TVV
Top View
20084402
SCAN921821
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Pin Descriptions
Pin Name Pin Count I/O, Type Description
DATA PINS
DINA0-17 18 I, LVCMOS Transmitter inputs. There is a pull-down circuitry on each of these pins which are
active if respective PWDNA or PWDNB pin is pulled high.
DINB0-17 18
DOUTAP 1
O,BLVDS Inverting and non-inverting differential transmitter outputs.
DOUTAN 1
DOUTBP 1
DOUTAN 1
TIMING AND CONTROL PINS
TxCLK 1 I, LVCMOS Transmitter reference clock. Used to strobe data at the inputs and to drive the
transmitter PLL. There is a pull-up circuitry on this pin which is always active.
ENA 1
I, LVCMOS
Transmitter outputs enable pins. There is a pull-down circuitry on each of these
pins that are active if corresponding PWDNA or PWDNB pin is pulled high.
When these pins are set to LOW, the transmitter outputs will be disabled. The
PLL will remain locked.
ENB 1
PWDNA 1
I, LVCMOS
Stand-by mode pins. There is a pull-down circuitry on each of these pins that are
always active. When these pins are set to LOW, the transmitter will be put in low
power mode and the PLL will lose lock.
PWDNB 1
SYNCA 1
I, LVCMOS
Transmitter synchronization pins. There is a pull-down circuitry on each of these
pins that are active if corresponding PWDNA or PWDNB pin is pulled high.
When these pins are set to HIGH, the transmitter will ignore incoming data and
send SYNC patterns to provide a locking reference to receiver(s).
SYNCB 1
PRE-EMPHASIS PINS
PEMA0-2 3
I, LVCMOS
8-level pre-emphasis selection pins. There is a pull-down circuitry on each of
these pins which are active if corresponding PWDNA or PWDNB pin is pulled
high.
PEMB0-2 3
JTAG PINS
TDI 1 I, LVCMOS Test Data Input to support IEEE 1149.1. There is a pull-up circuitry on this pin
which is always active.
TDO 1 O, LVCMOS Test Data Output to support IEEE 1149.1.
TMS 1 I, LVCMOS Test Mode Select Input to support IEEE 1149.1. There is a pull-up circuitry on
this pin which is always active.
TCK 1 I, LVCMOS Test Clock Input to support IEEE 1149.1. There is no failsafe circuitry on this pin.
TRST 1 I, LVCMOS Test Reset Input to support IEEE 1149.1. There is a pull-up circuitry on this pin
which is always active.
BIST PINS
BISTA 1 I, LVCMOS BIST selection pins. These pins select which transmitter will generate a PRBS
like data. There is a pull-down circuitry on these pins which are active if
corresponding PWDNA or PWDNB pin is pulled high.
BISTB 1
POWER PINS
AVDD 6 I, POWER Power Supply for the LVDS circuitry.
DVDD 8 I, POWER Power Supply for the digital circuitry.
PVDD 5 I, POWER Power Supply for the PLL and BG circuitry.
AVSS 5 I, POWER Ground reference for the LVDS circuitry.
DVSS 10 I, POWER Ground reference for the digital circuitry.
PVSS 5 I, POWER Ground reference for the PLL and BG circuitry.
OTHER PINS
NC 1 N/A Not connected.
SCAN921821
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Physical Dimensions inches (millimeters) unless otherwise noted
Dimensions shown in millimeters only
Order Number SCAN921821TSM
NS Package Number SLC100A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
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(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
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National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship
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SCAN921821 - Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1 (JTAG), and At-Speed BIST
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