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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2009, Zarlink Semiconductor Inc. All Rights Reserved.
Features
General
• Circuit Emulation Services over Packet (CESoP)
transport for MPLS, IP and Ethernet networks
• On chip timing & synchronization recovery across
a packet network
• Grooming capability for Nx64 Kbps trunking
Circuit Emulation Services
• Supports ITU-T Recommendation Y.1413 and
Y.1453
• Supports IETF RFC4553 and
RFC5086
• Supports MEF8 and MFA 8.0.0
• Structure d, synchronous
CESoP with clock rec overy
• Unstructured, asynch ronous
CESoP, with integral per stream clock recovery
TDM Interfaces
• Up to 32 T1/E1, 8 J2, or 2 T3/E3 ports
• H.110, H-MVIP, ST-BUS backplanes
• Up to 1024 bi-directional 64 Kbps channels
• Direct connection to LIUs, framers, backplanes
• Dual reference Stratum 4 and 4E DPLL for
synchronous operation
Network Interfaces
• Up to 3 x 100 Mbps MII Fast Ethernet or Dual
Redundant 1000 Mbps GMII/TBI Ethernet
Interfaces
System Interfaces
• Flexible 32 bit host CPU interface (Motorola
PowerQUICC™ compatible)
• On-chip packet memory for self-contained
operation, with buffer depths of over 16 ms
• Up to 8 Mbytes of off-chip packet memory,
supporting buffer depths of over 128 ms
October 2009
Ordering Information
ZL50110GAG 552 PBGA Trays, Bake & Drypack
ZL50111GAG 552 PBGA Trays, Bake & Drypack
ZL50112GAG 552 PBGA Trays, Bake & Drypack
ZL50114GAG 552 PBGA Trays, Bake & Drypack
ZL50110GAG2 552 PBGA** Trays, Bake & Dr ypack
ZL50111GAG2 552 PBGA** Trays, Bake & Dr ypack
ZL50112GAG2 552 PBGA** Trays, Bake & Dr ypack
ZL50114GAG2 552 PBGA** Trays, Bake & Dr ypack
**Pb Fee Tin Silver/Copper
-40°C to +85°C
ZL50110/11/12/14
128, 256, 512 and 1024 Channel CESoP
Processors
Data Sheet
Figure 1 - ZL50111 High Level Overview
On Chip Packet Memory
(Jitter B uffer C om pensation for 16-128 ms of P acket D elay Variation)
D ual R eference
DPLL H ost Processo r
Interface E x te rn al Me mo ry
Interface (optional)
H.110, H-MVIP, ST-BUS backplanes
Triple 100 Mbps MII Fast Ethernet
or
Dual Redudnat 1000 Mbps GMII/
TBI Gigabit Ethernet
Backplane
Clocks
32-bit Motorola com patib le P QII®
Multi-Protocol
Packet
Processing
Engine
PW, RTP, UDP,
IP v 4 , IP v 6 , M PL S ,
ECID , VLAN, User
Defined, Others
Triple
Packet
Interface
MAC
(MII, G MII, T BI)
TDM
Interface
(LIU , Fram er, B ackplane)
Per Port DCO for
Clock Recovery
ZBT-SRAM
(0 - 8 Mbytes)
32 T1/E1, 8 J2, 2 T3/E3 ports
ZL50110/11/12/14 Data Sheet
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Zarlink Semiconductor Inc.
Packet Processing Functions
• Flexible, multi-protocol packet encapsulation including support for IPv4, IPv6, RTP, MPLS, L2TPv3, ITU-T
Y.1413, RFC4553, RFC508 6 and user programm able
• Packet re-sequencing to allow lost packet detection
• Four classes of service with programmable prio rity mechanis ms (WFQ and SP) using egress queues
• Flexible classification of incoming packets at layers 2, 3, 4 and 5
• Supports up to 128 separate CESoP connections across the Packet Switched Network
Applications
• Circuit Emulation Services over Packet Networks
• Leased Line support over packet networks
• Multi-Tenant Unit access concentration
• TDM over Cable
• Fibre To The Premises G/E-PON
• Layer 2 VPN services
• Customer-premise and Provide r Edge Routers and Switc hes
• Packet switched backplane applications
ZL50110/11/12/14 Data Sheet
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Zarlink Semiconductor Inc.
Description
The ZL50110/11/12/14 family of CESoP processors are highly functional TDM to Packet bridging devices. The
ZL50110/11/12/14 provides both structured and unstructured circuit emulation services over p acket (CESoP) for up
to 32 T1, 32 E1 and 8 J2 streams across a packet network based on MPLS, IP or Ethernet. The ZL50111 also
supports unstructured T3 and E3 streams.
The circuit emulation features in the ZL50110/11/12/14 family supports the ITU Recommendations Y.1413 and
Y.1453, as well as the CESoP standards from the Metro Ethernet Forum (MEF) and MPLS and Frame Relay
Alliance. The ZL50110/11/ 14 al so supports IETF RFC4553 and RFC5086.
The ZL50110/11/12/14 provides up to triple 100 Mbps MII ports or dual redundant 1000 Mbps GMII/TBI ports.
The ZL50110/11/12/14 incorporates a range of powerful clock recovery mecha nisms for each TDM stream, allo wing
the frequency of the sou rce clo ck to be fa ithfully generated at the destination, enabling greater sy stem performance
and quality. Timing is carried using RTP or similar protocols, and both adaptive and differential clock recovery
schemes are included, allowing the customer to choose the correct scheme for the application. An externally
supplied clock may also be used to drive the TDM interface of the ZL50110/11/12/14.
The ZL50110/11/12/14 incur very low latency for the data flow, thereby increasing QoS when carrying voice
services across the Packet Switched Network. Voice, when carried using CESoP, which typically has latencies of
less than 10 ms, does not require expensive processing such as compression and echo cancellation.
The ZL50110/11/12/14 is capable of assembling user-defined packets of TDM traffic from the TDM interface and
transmitting them out the packet interfaces using a variety of protocols. The ZL50110/11/12/14 supports a range of
different packet switched networks, including Ethernet VLANs, IP and MPLS.
The ZL50110/11/12/14 can support up to 4 protocol stacks at the same time, provided that each protocol stack can
be uniquely identified by a mask & match approach.
Packets received from the packet interfaces are parsed to determine the egress destination, and are appropriately
queued to the TDM interface, they can also be forwarded to the host interface, or back toward the packet interface.
Packets queued to the TDM interface can be re-ordered based on sequence number, and lost packets filled in to
maintain timing integrity.
The ZL50110/11/12/14 family includes sufficient on-chip memory that external memory is not required in most
applications. This reduces system costs and simplifies the design. For applications that do require more memory
(e.g., high stream count or high latency), the device supports up to 8 Mbytes of SSRAM.
A comprehensive evaluation system is available upon request from your local Zarlink representative or distributor.
This system includes the CESoP processor, various TDM interfaces and a fully featured evaluation software GUI
that runs on a Windows PC.
ZL50110/11/12/14 Data Sheet
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Zarlink Semiconductor Inc.
Device Line Up
There are four products within the ZL50110/11/12/14 family, with capacity as shown in the following table:
Note 1: T1/E1/J2 is for unstructured mode, and the H-MVIP/H.110/ST-BUS is for structured mode.
Device TDM Interfaces Ethernet Packet I/F Notes
ZL50114 4 T1, 4 E1, or 1 J2 streams or
4 MVIP/ST-BUS streams at 2.048 Mbps or
1 H.110/H-MVIP/ST-BUS streams at
8.192 Mbps
Dual 100 Mbps MII or
Dual Redundant 1000 Mbps GMII/TBI Note 1
ZL50110 8 T1, 8 E1 or 2 J2 streams or
8 MVIP/ST-BUS streams at 2.048 Mbps or
2 H.110/H-MVIP/ST-BUS streams at
8.192 Mbps
Dual 100 Mbps MII or
Dual Redundant 1000 Mbps GMII/TBI Note 1
ZL50112 16 T1, 16 E1, 4 J2 streams or
16 MVIP/ST-BUS streams at 2.048 Mbps or
4 H.110/H-MVIP/ST-BUS streams at
8.192 Mbps
Triple 100 Mbps MII or
Dual Redundant 1000 Mbp s GMII/TBI
or Single 100 Mbps MII and Single
1000 Mbps GMII/TBI
Note 1
ZL50111 32 T1, 32 E1, 8 J2, 2 T3, 2 E3 streams or
32 MVIP/ST-BUS streams at 2.048 Mbps or
8 H.110/H-MVIP/ST-BUS streams at
8.192 Mbps
Triple 100 Mbps MII or
Dual Redundant 1000 Mbp s GMII/TBI
or Single 100 Mbps MII and Single
1000 Mbps GMII/TBI
Note 1
Table 1 - Capacity of Devices in the ZL50110/11/14 Family
ZL50110/11/12/14 Data Sheet
Table of Contents
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1.0 Changes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.0 Physical Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.0 External Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.1 TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.1.1 ZL50111 Variant TDM Stream Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.1.2 ZL50112 Variant TDM Stream Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.1.3 ZL50110 Variant TDM Stream Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.1.4 ZL50114 Variant TDM Stream Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.1.5 TDM Signals Common to ZL50110, ZL50111, ZL50112 and ZL50114. . . . . . . . . . . . . . . . . . . . . .31
3.2 PAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.3 Packet Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.4 External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
3.5 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
3.6 System Function Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.7 Test Facilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.7.1 Administration, Control and Test Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.7.2 JTAG Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.8 Miscellaneous Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.9 Power and Ground Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.10 ZL50111, ZL50112, ZL50110 and ZA50114 Internal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.11 ZL50112 Internal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.12 ZL50112 Auxiliary Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
4.0 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.1 Leased Line Provision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
4.2 Metropolitan Area Network Aggregation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.3 Digital Loop Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
4.4 Remote Concentrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
4.5 Cell Site Backhaul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4.6 Equipment Architecture Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
5.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
5.2 Data and Control Flows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
5.3 TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
5.3.1 TDM Interface Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
5.3.2 Structured TDM Port Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
5.3.3 TDM Clock Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
5.3.3.1 Synchronous TDM Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
5.3.3.2 Asynchronous TDM Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
5.4 Payload Assembly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.4.1 Structured Payload Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
5.4.1.1 Structured Payload Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
5.4.2 Unstructured Payload Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
5.5 Protocol Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
5.6 Packet Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
5.7 Packet Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
5.8 TDM Formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
6.0 Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.1 Differential Clock Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.2 Adaptive Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
6.3 SYSTEM_CLK Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
7.0 System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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7.1 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.2 Loopback Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
7.3 Host Packet Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
7.4 Loss of Service (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
7.5 External Memory Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
7.6 GIGABIT Ethernet - Recommended Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
7.6.1 Central Ethernet Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
7.6.2 Redundant Ethernet Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
7.7 Power Up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
7.8 JTAG Interface and Board Level Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
7.9 External Component Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
7.9.1 Host Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
7.9.2 Other components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
7.10 Miscellaneous Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
7.11 Test Modes Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
7.11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.11.1.1 System Normal Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
7.11.1.2 System Tri-State Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
7.11.2 Test Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.11.3 System Normal Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
7.11.4 System Tri-state Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
8.0 DPLL Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
8.1 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
8.1.1 Locking Mode (normal operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
8.1.2 Holdover Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.1.3 Freerun Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
8.1.4 Powerdown Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
8.2 Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
8.3 Locking Mode Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8.4 Locking Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
8.5 Locking Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8.6 Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
8.7 Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
8.7.1 Acceptance of Input Wander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
8.7.2 Intrinsic Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
8.7.3 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
8.7.4 Jitter Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
8.8 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.0 Memory Map and Register Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10.0 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
11.0 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
11.1 TDM Interface Timing - ST-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
11.1.1 ST-BUS Slave Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
11.1.2 ST-BUS Master Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
11.2 TDM Interface Timing - H.110 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
11.3 TDM Interface Timing - H-MVIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
11.4 TDM LIU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
11.5 PAC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
11.6 Packet Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
11.6.1 MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
11.6.2 MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
11.6.3 GMII Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
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11.6.4 GMII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
11.6.5 TBI Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
11.6.6 Management Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
11.7 External Memory Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
11.8 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
11.9 System Function Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
11.10 JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.0 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.0 Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.1 High Speed Clock & Data Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
13.1.1 External Memory Interface - special considerations during layout. . . . . . . . . . . . . . . . . . . . . . . .105
13.1.2 GMAC Interface - special considerations during layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
13.1.3 TDM Interface - specia l considerations during layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
13.1.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
13.2 CPU TA Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
13.3 Mx_LINKUP_LED Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
14.0 Reference Documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
14.1 External Standards/Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
14.2 Zarlink Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
15.0 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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Figure 1 - ZL50111 High Level Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - ZL50111 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3 - ZL50112 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 4 - ZL50110 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5 - ZL50114 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6 - Leased Line Services Over a Circuit Emulation Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 7 - Metropolitan Area Network Aggregation using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 8 - Digital Loop Carrier using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 9 - Remote Concentrator using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 10 - Cell Site Backhaul using CESoP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 11 - Equipment example using CESoP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 12 - ZL50110/11/12/14 Family Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 13 - ZL50110/11/12/14 Data and Control Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 14 - Synchronous TDM Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 15 - ZL50110/11/12/14 Packet Format - Structured Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 16 - Channel Order for Packet Formation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 17 - ZL50110/11/12/14 Packet Format - Unstructured Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 18 - Differential Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 19 - Adaptive Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 20 - External Memory Requirement for ZL50111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 21 - External Memory Requirement for ZL50110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 22 - Gigabit Ethernet Connection - Central Ethernet Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 23 - Gigabit Ethernet Connection - Redundant Ethernet Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 24 - Powering Up the ZL50110/11/12/14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 25 - Jitter Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 26 - Jitter Transfer Function - Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 27 - TDM ST-BUS Slave Mode Timing at 8.192 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 28 - TDM ST-BUS Slave Mode Timing at 2.048 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 29 - TDM Bus Master Mode Timing at 8.192 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 30 - TDM Bus Master Mode Timing at 2.048 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 31 - H.110 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 32 - TDM - H-MVIP Timing Diagram for 16 MHz Clock (8.192 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 33 - TDM-LIU Structured Transmission/Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 34 - MII Transmit Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 35 - MII Receive Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 36 - GMII Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 37 - GMII Receive Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 38 - TBI Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 39 - TBI Receive Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 40 - Management Interface Timing for Ethernet Port - Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 41 - Management Interface Timing for Ethernet Port - Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 42 - External RAM Read and Write Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 43 - CPU Read - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 44 - CPU Write - MPC8260. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 45 - CPU DMA Read - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 46 - CPU DMA Write - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 47 - JTAG Signal T i ming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 48 - JTAG Clock and Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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Figure 49 - ZL50110/11/12/14 Power Consumption Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 50 - CPU_TA Board Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 51 - Mx_LINKUP_LED Stuffing Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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Table 1 - Capacity of Devices in the ZL50110/11/14 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2 - TDM Interface ZL50111 Stream Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 3 - TDM Interface ZL50112 Stream Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 4 - TDM Interface ZL50110 Stream Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 5 - TDM Interface ZL50114 Stream Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6 - TDM Interface Common Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7 - PAC Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 8 - Packet Interface Signal Mapping - MII to GMII/TBI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 9 - MII Management Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 10 - MII Port 0 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 11 - MII Port 1 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 12 - MII Port 2 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 13 - MII Port 3 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 14 - External Memory Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 15 - CPU Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 16 - System Function Interface Package Ball Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 17 - Administration/Control Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 18 - JTAG Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 19 - Miscellaneous Inputs Package Ball Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 20 - Power and Ground Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 21 - No Connection Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 22 - No Connection Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 23 - Auxiliary clock Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 24 - Standard Device Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 25 - TDM Services Offered by the ZL50110/11/12/14 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 26 - Some of the TDM Port Formats Accepted by the ZL50110/11/12/14 Family . . . . . . . . . . . . . . . . . . . . 60
Table 27 - DMA Maximum Bandwidths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 28 - Test Mode Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 29 - DPLL Input Reference Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 30 - TDM ST-BUS Master Timing Sp ecification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 31 - TDM H.110 T iming Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 32 - TDM H-MVIP Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 33 - TDM - LIU Structured Transmission/Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 34 - PAC Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 35 - MII Transmit Timing - 100 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 36 - MII Receive T iming - 100 Mbps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 37 - GMII Transmit Timing - 1000 Mbps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 38 - GMII Receive Ti ming - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 39 - TBI Timing - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 40 - MAC Management Timin g Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 41 - External Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 42 - CPU Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 43 - System Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 44 - JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 45 - Mx_LINKUP_LED Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 46 - Mx_LINKUP_LED Stuffing Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
ZL50110/11/12/14 Data Sheet
11
Zarlink Semiconductor Inc.
1.0 Changes Summary
The following table captures the changes from the March 2009 issue.
The following table captures the changes from the January 2009 issue.
The following table captu res the changes from the April 2008 issue.
The following table captures the changes from the October 2006 issue.
Page Item Change
1 MEF logo Added MEF logo to show MEF 18 certification.
Page Item Change
61 & 64 Section 5.4 and Section 5.8 Replaced ZLAN- 202 with ZL50 11x Design Manual section “13.1
Understanding forceDelete”.
67 Section 6.3 Replaced ZLAN-143 with ZL5011x Design Manual section “3.6
System Clock Block.”
69 Section 7.4 Replaced ZLAN-159 with ZL5011x Design Manual section
“3.1.1 Connection to LIU”.
94 Section 11.6.5 Replaced ZLAN-239 with ZL5011x Design Manual section
“7.1.3.1 TBI Interface Timing”.
109 Section 14.1 Removed references to IETF PWE3 draft-ietf-l2tpext-l2tp-base
and IETF PWE3 draft-ietf-pwe3-cesop.
Page Item Change
68 Section 7 .3 Add Note 3
Page Item Change
Several Include ZL50112 device Add description for ZL50112
1, 2 and 3 Standard Updated IETF RFC number and standards in general
1, 58, 74,
75 and 77 Stratum 3 DPLL Updated the description for Stratum 3 DPLL
1, 4, 24, 52
and 59 STS-1 stream Remove STS-1 stream
14 Section 2.0 Combine the packaged descriptions for all devices
33 Section 3.3 Include more detailed description for the packet interface
49 Section 3.7.2 ZL50112 and ZL50111 share the same JTAG ID
56 Section 4.6 Change the title of the section
57 Section 5.0 Add a note about jumbo packets
59 Section 5.3 Include a paragraph to clarify the support for structure and
unstructure modes at the same time
61 Section 5.4 Include more detailed description for the Payload Assembly
63 Section 5.4.2 Add a note at the end of the section
64 Section 5.8 Include more detailed description for the TDM formatter
ZL50110/11/12/14 Data Sheet
12
Zarlink Semiconductor Inc.
The following table captu res the changes from the February 2006 issue.
The following table captu res the changes from the April 2005 issue.
The following table captures the changes from the January 2005 issue.
65 Section 6.0 Include more detailed description for Clock Recovery
65 Section 6.1 Include more detailed description for Differential Clock
Recovery
66 Section 6.2 Updated the description of Adaptive Clock Recovery
73 Section 7.9 Added sub sections
87 Table 32 TDM_HDS Input Setup and TDM_HDS Input Hold, Max. time
corrected.
94 Section 11.6.5 Updated TXD[9:0] output delay
95 Section 11.6.6 UpdatedSection 11.6.6 Management Interface T i ming
(M_MDIO hold time and Figure 40)
97 Figure 43 and Figure 44 CPU_TS_ALE and CPU_TA. Added mode details in Figure 43
and Figure 44
Added the CPU_TA assertion time.
Page Item Change
96 Table 41, Table 41 - External
Memory Timing Added Minimum Values
Page Item Change
Clarified ZL5011 1 supports 3 MII ports, ZL50110/4 support 2 MII
ports.
48, 49 Section 3.6 and Section 3.7.2 Added external pull-up/pull-down resistor recommen dations for
SYSTEM_RST, SYSTEM_DEBUG, JTAG_TRST, JTAG_TCK.
67 Section 6.3 Added Section 6.3 SYSTEM_CLK Considerations.
Page Item Change
Clarified data sheet to indicate ZL50110/11/12/14 supports
clock recovery in both synchron ous and asynchronous modes
of operation.
99 Figure 45 Inverted polarity of CPU_DREQ0 and CPU_DR EQ1 to conform
with default MPC8260. Polarity of CPU_DREQ and
CPU_SDACK remains programmable through API.
99 Figure 46 Inverted polarity of CPU_DREQ0 and CPU_DR EQ1 to conform
with default MPC8260. Polarity of CPU_DREQ and
CPU_SDACK remains programmable through API.
Page Item Change
ZL50110/11/12/14 Data Sheet
13
Zarlink Semiconductor Inc.
The following table captures the changes from the October 2004 issue.
The following table captu res the changes from the September 2004 issue.
Page Item Change
49 Section 3.7.1 Added 5 kohm pulldown recommendation to GPIO signals.
Page Item Change
12, 16, 19 Fig. 2 and Ball Signal
Assignment Table Corrected Mx_LINKUP_LED pin assignment.
73 DC Electrical Characteristics
Table and Output Levels Table Changed Electrical Characteristics to differentiate between
3.3 V and 5 V tolerant signals.
98 Section 13.3 New section added; Mx_LINKUP_LED Outputs.
ZL50110/11/12/14 Data Sheet
14
Zarlink Semiconductor Inc.
2.0 Physical Specification
The ZL50110/11/12/14 is packaged in a PBGA device.
Features:
• Body Size: 35 mm x 35 mm (typ)
• Ball Count: 552
• Ball Pitch: 1.27 m m (typ)
• Ball Matrix: 26 x 26
• Ball Diameter: 0.75 mm (typ)
• Total Package Thickness: 2.33 mm (typ)
ZL50110/11/12/14 Data Sheet
15
Zarlink Semiconductor Inc.
ZL50111 Package view from TOP side. Note that ball A1 is non-chamfered corner.
Figure 2 - ZL50111 Package View and Ball Positions
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
GND TDM_STo[
1] TDM_CLK
o[3] TDM_STo[
4] TDM_STo[
5] TDM_STi[
6] TDM_STo[
7] TDM_STi[
7] TDM_CLK
o[10] TDM_CLKi
[10] TDM_CLKi
[11] TDM_CLK
o[13] GND TDM_STo[
13] TDM_STo[
14] TDM_CLK
o[15] TDM_STo[
16] TDM_CLK
o[18] TDM_STi[
18] TDM_CLKi
[20] TDM_STi[
20] TDM_STo[
21] TDM_STi[
21] TDM_CLK
o[24] TDM_CLK
o[25] GND
1 2 3 4 5 6 7 8 91011121314151617181920212223242526
TDM_FRM
o_REF TDM_STo[
0] TDM_STi[
2] TDM_CLKi
[3] TDM_STi[
4] TDM_CLK
o[6] TDM_STo[
6] TDM_CLK
o[8] TDM_CLKi
[9] TDM_STo[
10] TDM_STi[
10] TDM_CLKi
[12] TDM_STo[
12] TDM_STi[
13] TDM_CLKi
[15] TDM_STi[
15] TDM_STi[
17] TDM_CLKi
[18] TDM_CLK
o[20] TDM_STo[
19] TDM_STo[
22] TDM_CLK
o[23] TDM_STo[
24] TDM_CLK
o[26] TDM_STi[
24] TDM_CLK
o[27]
TDM_CLKi
PTDM_FRM
i_REF TDM_CLKi
_REF TDM_CLK
o[1] TDM_STi[
3] TDM_CLK
o[2] TDM_CLKi
[6] TDM_CLKi
[7] TDM_CLK
o[9] TDM_STo[
9] TDM_STi[
9] TDM_STi[
11] TDM_CLKi
[13] TDM_CLK
o[14] TDM_CLK
o[16] TDM_STi[
16] TDM_CLK
o[17] TDM_STi[
19] TDM_CLK
o[21] TDM_CLKi
[21] TDM_CLKi
[24] TDM_STi[
22] TDM_STo[
26] TDM_CLKi
[27] TDM_STi[
27] TDM_STi[
28]
RAM_DAT
A[3] RAM_DAT
A[1] TDM_CLKi
SRAM_DAT
A[0] TDM_STi[
0] TDM_CLKi
[1] TDM_STo[
3] TDM_STi[
5] TDM_CLKi
[5] TDM_CLK
o[7] TDM_STi[
8] TDM_CLK
o[11] TDM_STi[
12] TDM_STi[
14] TDM_CLKi
[16] TDM_CLK
o[19] TDM_STo[
18] TDM_STo[
20] TDM_CLK
o[22] TDM_STo[
27] TDM_STo[
25] TDM_CLKi
[26] TDM_CLK
o[28] TDM_CLKi
[29] TDM_STi[
29] TDM_STi[
31]
RAM_DAT
A[10] RAM_DAT
A[9] RAM_DAT
A[5] RAM_DAT
A[4] RAM_DAT
A[2] TDM_CLK
o_REF TDM_CLKi
[0] TDM_CLK
o[4] TDM_STi[
1] TDM_CLKi
[4] TDM_STo[
8] TDM_CLKi
[8] TDM_CLK
o[12] TDM_STo[
15] TDM_CLKi
[17] TDM_CLKi
[19] TDM_STo[
23] TDM_STi[
23] TDM_CLKi
[25] TDM_STi[
26] TDM_CLKi
[28] GND TDM_CLK
o[30] TDM_CLKi
[30] TDM_STi[
30] TDM_STo[
29]
RAM_DAT
A[15] RAM_DAT
A[13] RAM_DAT
A[12] RAM_DAT
A[6] RAM_DAT
A[7] GND VDD_COR
ETDM_STo[
2] TDM_CLK
o[0] TDM_CLKi
[2] TDM_CLK
o[5] VDD_COR
ETDM_STo[
11] TDM_CLKi
[14] TDM_STo[
17] TDM_CLKi
[22] TDM_STi[
25] TDM_CLKi
[23] VDD_COR
EGND TDM_CLKi
[31] TDM_CLK
o[29] TDM_STo[
28] TDM_CLK
o[31] M1_LINKU
P_LED
RAM_DAT
A[21] RAM_DAT
A[18] RAM_DAT
A[16] RAM_DAT
A[14] RAM_DAT
A[11] RAM_DAT
A[8] TDM_STo[
31] TDM_STo[
30] M2_LINKU
P_LED M3_LINKU
P_LED M1_GIGA
BIT_LED M_MDIO
RAM_DAT
A[25] RAM_DAT
A[24] RAM_DAT
A[23] RAM_DAT
A[19] RAM_DAT
A[17] VDD_COR
EVDD_COR
EM0_GIGA
BIT_LED M_MDC M3_CRS M3_TXCL
KM3_RXER
RAM_DAT
A[29] RAM_DAT
A[28] RAM_DAT
A[27] RAM_DAT
A[26] RAM_DAT
A[22] RAM_DAT
A[20] VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO M3_RXDVM3_RXD[3
]M3_RXD[2
]M3_RXD[1
]M3_RXD[0
]M3_COL
RAM_PAR
ITY[1] RAM_PAR
ITY[0] RAM_DAT
A[31] RAM_DAT
A[30] GND VDD_COR
EVDD_IO VDD_COR
EGND M3_TXD[3
]M3_TXEN M3_TXER M3_RXCL
K
RAM_PAR
ITY[7] RAM_PAR
ITY[6] RAM_PAR
ITY[5] RAM_PAR
ITY[4] RAM_PAR
ITY[3] RAM_PAR
ITY[2] VDD_IO GND GND GND GND GND GND VDD_IO M1_RXER M1_TXCL
KM1_CRS M3_TXD[0
]M3_TXD[1
]M3_TXD[2
]
RAM_ADD
R[5] RAM_ADD
R[4] RAM_ADD
R[2] RAM_ADD
R[3] RAM_ADD
R[0] RAM_ADD
R[1] VDD_IO GND GND GND GND GND GND VDD_IO VDD_COR
EM1_REFC
LK M1_RXCL
KM1_RXD[5
]M1_RXD[7
]M1_RXDV
GND RAM_ADD
R[6] RAM_ADD
R[7] RAM_ADD
R[8] GND VDD_COR
EVDD_IO GND GND GND GND GND GND VDD_IO M1_GTX_
CLK GND M1_TXERM1_RXD[2
]M1_RXD[3
]GND
RAM_ADD
R[9] RAM_ADD
R[10] RAM_ADD
R[11] RAM_ADD
R[13] RAM_ADD
R[16] GND VDD_IO GND GND GND GND GND GND VDD_IO M1_TXD[2
]M1_TXD[6
]M1_TXEN GND M1_RXD[4
]M1_RXD[6
]
RAM_ADD
R[12] RAM_ADD
R[14] RAM_ADD
R[15] RAM_ADD
R[19] IC_GND IC VDD_IO GND GND GND GND GND GND VDD_IO M1_TXD[0
]M1_TXD[3
]M1_TXD[5
]M1_TXD[7
]M1_COL M1_RXD[1
]
RAM_ADD
R[17] RAM_ADD
R[18] RAM_BW
_B IC_GND GND A1VDD VDD_IO GND GND GND GND GND GND VDD_IO VDD_COR
EM1_TXD[1
]M1_TXD[4
]GND M1_RBC1 M1_RXD[0
]
PLL_PRI RAM_BW
_A RAM_BW
_C RAM_RW SYSTEM_
DEBUG SYSTEM_
CLK VDD_IO VDD_IO M0_GTX_
CLK M0_RXD[2
]M0_RXD[5
]M0_TXCL
KM0_CRS M1_RBC0
PLL_SEC RAM_BW
_D RAM_BW
_F SYSTEM_
RST GPIO[2] VDD_COR
EVDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO M0_TXD[7
]M0_TXER M0_TXENM0_RXD[4
]M0_RXDVM0_RXER
RAM_BW
_E RAM_BW
_G GPIO[0] GPIO[3] GPIO[9] RAM_DAT
A[33] M0_TXD[2
]M0_TXD[5
]M0_TXD[6
]M0_RXD[6
]M0_RXD[7
]M0_RXD[3
]
RAM_BW
_H GPIO[4] GPIO[6] GPIO[10] RAM_DAT
A[32] VDD_COR
EVDD_COR
EM0_TXD[1
]M0_TXD[4
]M0_RBC0 M0_COL M0_RXD[1
]
GPIO[1] GPIO[7] GPIO[8] GPIO[15] RAM_DAT
A[39] GND RAM_DAT
A[45] RAM_DAT
A[52] VDD_COR
EJTAG_TM
SCPU_ADD
R[2] CPU_ADD
R[12] VDD_COR
EVDD_COR
ECPU_DAT
A[8] CPU_DAT
A[15] CPU_DAT
A[23] VDD_COR
EM2_RXCL
KM2_RXDV GND M0_TXD[0
]M0_TXD[3
]M0_REFC
LK M0_RBC1 M0_RXD[0
]
GPIO[5] GPIO[11] GPIO[14] RAM_DAT
A[38] RAM_DAT
A[43] RAM_DAT
A[44] RAM_DAT
A[51] RAM_DAT
A[60] TEST_MO
DE[1] GND CPU_ADD
R[6] CPU_ADD
R[14] CPU_ADD
R[23] CPU_TA CPU_DAT
A[1] CPU_DAT
A[7] CPU_DAT
A[12] CPU_DAT
A[22] CPU_DAT
A[30] M2_TXERM2_RXD[1
]M0_RXCL
KM0_LINKU
P_LED M2_ACTIV
E_LED M1_ACTIV
E_LED M3_ACTIV
E_LED
GPIO[12] GPIO[13] RAM_DAT
A[37] RAM_DAT
A[42] RAM_DAT
A[46] RAM_DAT
A[49] RAM_DAT
A[59] TEST_MO
DE[0] JTAG_TD
OCPU_ADD
R[4] CPU_ADD
R[9] CPU_ADD
R[16] CPU_ADD
R[22] CPU_CLK CPU_DRE
Q0 IC CPU_DAT
A[10] CPU_DAT
A[16] CPU_DAT
A[21] CPU_DAT
A[27] M2_TXD[1
]M2_TXENM2_RXD[2
]M2_RXER M2_CRS M0_ACTIV
E_LED
RAM_DAT
A[34] RAM_DAT
A[36] RAM_DAT
A[41] RAM_DAT
A[47] RAM_DAT
A[53] RAM_DAT
A[58] RAM_DAT
A[63] JTAG_TC
KIC-GND CPU_ADD
R[7] CPU_ADD
R[11] CPU_ADD
R[17] CPU_ADD
R[21] CPU_WE CPU_SDA
CK2 CPU_IRE
Q1 CPU_DAT
A[3] CPU_DAT
A[6] CPU_DAT
A[14] CPU_DAT
A[20] CPU_DAT
A[24] CPU_DAT
A[29] M2_TXD[2
]M2_RXD[0
]M2_RXD[3
]M2_TXCL
K
RAM_DAT
A[35] RAM_DAT
A[40] RAM_DAT
A[48] RAM_DAT
A[54] RAM_DAT
A[57] RAM_DAT
A[62] JTAG_TR
ST IC_GND CPU_ADD
R[3] CPU_ADD
R[8] CPU_ADD
R[13] CPU_ADD
R[18] CPU_ADD
R[20] CPU_OE CPU_TS_
ALE CPU_DRE
Q1 IC CPU_DAT
A[4] CPU_DAT
A[9] CPU_DAT
A[13] CPU_DAT
A[18] CPU_DAT
A[25] CPU_DAT
A[28] M2_TXD[0
]M2_TXD[3
]M2_COL
GND RAM_DAT
A[50] RAM_DAT
A[55] RAM_DAT
A[56] RAM_DAT
A[61] TEST_MO
DE[2] JTAG_TDI IC_GND CPU_ADD
R[5] CPU_ADD
R[10] CPU_ADD
R[15] CPU_ADD
R[19] GND CPU_CS CPU_SDA
CK1 IC_VDD_I
OCPU_IRE
Q0 CPU_DAT
A[0] CPU_DAT
A[5] CPU_DAT
A[2] CPU_DAT
A[11] CPU_DAT
A[17] CPU_DAT
A[19] CPU_DAT
A[26] CPU_DAT
A[31] GND
1 2 3 4 5 6 7 8 91011121314151617181920212223242526
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
VDD_COR
E
VDD_IO
ZL50110/11/12/14 Data Sheet
16
Zarlink Semiconductor Inc.
ZL50112 Package view from TOP side. Note that ball A1 is non-chamfered corner.
Figure 3 - ZL50112 Package View and Ball Positions
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
GND TDM_STo[
1] TDM_CLK
o[3] TDM_STo[
4] TDM_STo[
5] TDM_STi[
6] TDM_STo[
7] TDM_STi[
7] TDM_CLK
o[10] TDM_CLKi
[10] TDM_CLKi
[11] TDM_CLK
o[13] GND TDM_STo[
13] TDM_STo[
14] TDM_CLK
o[15] N/C AUX1_CL
Ko[0] N/C N/C N/C N/C N/C N/C N/C GND
1 2 3 4 5 6 7 8 91011121314151617181920212223242526
TDM_FRM
o_REF TDM_STo[
0] TDM_STi[
2] TDM_CLKi
[3] TDM_STi[
4] TDM_CLK
o[6] TDM_STo[
6] TDM_CLK
o[8] TDM_CLKi
[9] TDM_STo[
10] TDM_STi[
10] TDM_CLKi
[12] TDM_STo[
12] TDM_STi[
13] TDM_CLKi
[15] TDM_STi[
15] N/C AUX1_CL
Ki[0] N/C N/C N/C N/C N/C N/C N/C N/C
TDM_CLKi
PTDM_FRM
i_REF TDM_CLKi
_REF TDM_CLK
o[1] TDM_STi[
3] TDM_CLK
o[2] TDM_CLKi
[6] TDM_CLKi
[7] TDM_CLK
o[9] TDM_STo[
9] TDM_STi[
9] TDM_STi[
11] TDM_CLKi
[13] TDM_CLK
o[14] AUX2_CL
Ko[0] N/C AUX2_CL
Ko[1] N/C N/C N/C N/C N/C N/C N/C N/C N/C
RAM_DAT
A[3] RAM_DAT
A[1] TDM_CLKi
SRAM_DAT
A[0] TDM_STi[
0] TDM_CLKi
[1] TDM_STo[
3] TDM_STi[
5] TDM_CLKi
[5] TDM_CLK
o[7] TDM_STi[
8] TDM_CLK
o[11] TDM_STi[
12] TDM_STi[
14] AUX2_CL
Ki[0] AUX1_CL
Ko[1] N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C
RAM_DAT
A[10] RAM_DAT
A[9] RAM_DAT
A[5] RAM_DAT
A[4] RAM_DAT
A[2] TDM_CLK
o_REF TDM_CLKi
[0] TDM_CLK
o[4] TDM_STi[
1] TDM_CLKi
[4] TDM_STo[
8] TDM_CLKi
[8] TDM_CLK
o[12] TDM_STo[
15] AUX2_CL
Ki[1] AUX1_CL
Ki[1] N/C N/C N/C N/C N/C GND N/C N/C N/C IC
RAM_DAT
A[15] RAM_DAT
A[13] RAM_DAT
A[12] RAM_DAT
A[6] RAM_DAT
A[7] GND VDD_COR
ETDM_STo[
2] TDM_CLK
o[0] TDM_CLKi
[2] TDM_CLK
o[5] VDD_COR
ETDM_STo[
11] TDM_CLKi
[14] N/C N/C N/C N/C VDD_COR
EGND N/C N/C N/C IC M1_LINKU
P_LED
RAM_DAT
A[21] RAM_DAT
A[18] RAM_DAT
A[16] RAM_DAT
A[14] RAM_DAT
A[11] RAM_DAT
A[8] IC IC M2_LINKU
P_LED N/C M1_GIGA
BIT_LED M_MDIO
RAM_DAT
A[25] RAM_DAT
A[24] RAM_DAT
A[23] RAM_DAT
A[19] RAM_DAT
A[17] VDD_COR
EVDD_COR
EM0_GIGA
BIT_LED M_MDC N/C N/C N/C
RAM_DAT
A[29] RAM_DAT
A[28] RAM_DAT
A[27] RAM_DAT
A[26] RAM_DAT
A[22] RAM_DAT
A[20] VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO N/C N/C N/C N/C N/C N/C
RAM_PAR
ITY[1] RAM_PAR
ITY[0] RAM_DAT
A[31] RAM_DAT
A[30] GND VDD_COR
EVDD_IO VDD_COR
EGND N/C N/C N/C N/C
RAM_PAR
ITY[7] RAM_PAR
ITY[6] RAM_PAR
ITY[5] RAM_PAR
ITY[4] RAM_PAR
ITY[3] RAM_PAR
ITY[2] VDD_IO GND GND GND GND GND GND VDD_IO M1_RXER M1_TXCL
KM1_CRS N/C N/C N/C
RAM_ADD
R[5] RAM_ADD
R[4] RAM_ADD
R[2] RAM_ADD
R[3] RAM_ADD
R[0] RAM_ADD
R[1] VDD_IO GND GND GND GND GND GND VDD_IO VDD_COR
EM1_REFC
LK M1_RXCL
KM1_RXD[5
]M1_RXD[7
]M1_RXDV
GND RAM_ADD
R[6] RAM_ADD
R[7] RAM_ADD
R[8] GND VDD_COR
EVDD_IO GND GND GND GND GND GND VDD_IO M1_GTX_
CLK GND M1_TXERM1_RXD[2
]M1_RXD[3
]GND
RAM_ADD
R[9] RAM_ADD
R[10] RAM_ADD
R[11] RAM_ADD
R[13] RAM_ADD
R[16] GND VDD_IO GND GND GND GND GND GND VDD_IO M1_TXD[2
]M1_TXD[6
]M1_TXEN GND M1_RXD[4
]M1_RXD[6
]
RAM_ADD
R[12] RAM_ADD
R[14] RAM_ADD
R[15] RAM_ADD
R[19] IC_GND IC VDD_IO GND GND GND GND GND GND VDD_IO M1_TXD[0
]M1_TXD[3
]M1_TXD[5
]M1_TXD[7
]M1_COL M1_RXD[1
]
RAM_ADD
R[17] RAM_ADD
R[18] RAM_BW
_B IC_GND GND A1VDD VDD_IO GND GND GND GND GND GND VDD_IO VDD_COR
EM1_TXD[1
]M1_TXD[4
]GND M1_RBC1 M1_RXD[0
]
PLL_PRI RAM_BW
_A RAM_BW
_C RAM_RW SYSTEM_
DEBUG SYSTEM_
CLK VDD_IO VDD_IO M0_GTX_
CLK M0_RXD[2
]M0_RXD[5
]M0_TXCL
KM0_CRS M1_RBC0
PLL_SEC RAM_BW
_D RAM_BW
_F SYSTEM_
RST GPIO[2] VDD_COR
EVDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO M0_TXD[7
]M0_TXER M0_TXENM0_RXD[4
]M0_RXDVM0_RXER
RAM_BW
_E RAM_BW
_G GPIO[0] GPIO[3] GPIO[9] RAM_DAT
A[33] M0_TXD[2
]M0_TXD[5
]M0_TXD[6
]M0_RXD[6
]M0_RXD[7
]M0_RXD[3
]
RAM_BW
_H GPIO[4] GPIO[6] GPIO[10] RAM_DAT
A[32] VDD_COR
EVDD_COR
EM0_TXD[1
]M0_TXD[4
]M0_RBC0 M0_COL M0_RXD[1
]
GPIO[1] GPIO[7] GPIO[8] GPIO[15] RAM_DAT
A[39] GND RAM_DAT
A[45] RAM_DAT
A[52] VDD_COR
EJTAG_TM
SCPU_ADD
R[2] CPU_ADD
R[12] VDD_COR
EVDD_COR
ECPU_DAT
A[8] CPU_DAT
A[15] CPU_DAT
A[23] VDD_COR
EM2_RXCL
KM2_RXDV GND M0_TXD[0
]M0_TXD[3
]M0_REFC
LK M0_RBC1 M0_RXD[0
]
GPIO[5] GPIO[11] GPIO[14] RAM_DAT
A[38] RAM_DAT
A[43] RAM_DAT
A[44] RAM_DAT
A[51] RAM_DAT
A[60] TEST_MO
DE[1] GND CPU_ADD
R[6] CPU_ADD
R[14] CPU_ADD
R[23] CPU_TA CPU_DAT
A[1] CPU_DAT
A[7] CPU_DAT
A[12] CPU_DAT
A[22] CPU_DAT
A[30] M2_TXERM2_RXD[1
]M0_RXCL
KM0_LINKU
P_LED M2_ACTIV
E_LED M1_ACTIV
E_LED N/C
GPIO[12] GPIO[13] RAM_DAT
A[37] RAM_DAT
A[42] RAM_DAT
A[46] RAM_DAT
A[49] RAM_DAT
A[59] TEST_MO
DE[0] JTAG_TD
OCPU_ADD
R[4] CPU_ADD
R[9] CPU_ADD
R[16] CPU_ADD
R[22] CPU_CLK CPU_DRE
Q0 IC CPU_DAT
A[10] CPU_DAT
A[16] CPU_DAT
A[21] CPU_DAT
A[27] M2_TXD[1
]M2_TXENM2_RXD[2
]M2_RXER M2_CRS M0_ACTIV
E_LED
RAM_DAT
A[34] RAM_DAT
A[36] RAM_DAT
A[41] RAM_DAT
A[47] RAM_DAT
A[53] RAM_DAT
A[58] RAM_DAT
A[63] JTAG_TC
KIC-GND CPU_ADD
R[7] CPU_ADD
R[11] CPU_ADD
R[17] CPU_ADD
R[21] CPU_WE CPU_SDA
CK2 CPU_IRE
Q1 CPU_DAT
A[3] CPU_DAT
A[6] CPU_DAT
A[14] CPU_DAT
A[20] CPU_DAT
A[24] CPU_DAT
A[29] M2_TXD[2
]M2_RXD[0
]M2_RXD[3
]M2_TXCL
K
RAM_DAT
A[35] RAM_DAT
A[40] RAM_DAT
A[48] RAM_DAT
A[54] RAM_DAT
A[57] RAM_DAT
A[62] JTAG_TR
ST IC_GND CPU_ADD
R[3] CPU_ADD
R[8] CPU_ADD
R[13] CPU_ADD
R[18] CPU_ADD
R[20] CPU_OE CPU_TS_
ALE CPU_DRE
Q1 IC CPU_DAT
A[4] CPU_DAT
A[9] CPU_DAT
A[13] CPU_DAT
A[18] CPU_DAT
A[25] CPU_DAT
A[28] M2_TXD[0
]M2_TXD[3
]M2_COL
GND RAM_DAT
A[50] RAM_DAT
A[55] RAM_DAT
A[56] RAM_DAT
A[61] TEST_MO
DE[2] JTAG_TDI IC_GND CPU_ADD
R[5] CPU_ADD
R[10] CPU_ADD
R[15] CPU_ADD
R[19] GND CPU_CS CPU_SDA
CK1 IC_VDD_I
OCPU_IRE
Q0 CPU_DAT
A[0] CPU_DAT
A[5] CPU_DAT
A[2] CPU_DAT
A[11] CPU_DAT
A[17] CPU_DAT
A[19] CPU_DAT
A[26] CPU_DAT
A[31] GND
1 2 3 4 5 6 7 8 91011121314151617181920212223242526
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
VDD_COR
E
VDD_IO
ZL50110/11/12/14 Data Sheet
17
Zarlink Semiconductor Inc.
ZL50110 Package view from TOP side. Note that ball A1 is non-chamfered corner.
Figure 4 - ZL50110 Package View and Ball Positions
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
GND TDM_STo
[1] TDM_CL
Ko[3] TDM_STo
[4] TDM_STo
[5] TDM_STi[
6] TDM_STo
[7] TDM_STi[
7] N/C N/C N/C N/C GND N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
TDM_FR
Mo_REF TDM_STo
[0] TDM_STi[
2] TDM_CL
Ki[3] TDM_STi[
4] TDM_CL
Ko[6] TDM_STo
[6] N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C
TDM_CL
KiP TDM_FR
Mi_REF TDM_CL
Ki_REF TDM_CL
Ko[1] TDM_STi[
3] TDM_CL
Ko[2] TDM_CL
Ki[6] TDM_CL
Ki[7] N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C
RAM_DA
TA[3] RAM_DA
TA[1] TDM_CL
KiS RAM_DA
TA[0] TDM_STi[
0] TDM_CL
Ki[1] TDM_STo
[3] TDM_STi[
5] TDM_CL
Ki[5] TDM_CL
Ko[7] N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C
RAM_DA
TA[10] RAM_DA
TA[9] RAM_DA
TA[5] RAM_DA
TA[4] RAM_DA
TA[2] TDM_CL
Ko_REF TDM_CL
Ki[0] TDM_CL
Ko[4] TDM_STi[
1] TDM_CL
Ki[4] N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C GND N/C N/C N/C N/C
RAM_DA
TA[15] RAM_DA
TA[13] RAM_DA
TA[12] RAM_DA
TA[6] RAM_DA
TA[7] GND VDD_CO
RE TDM_STo
[2] TDM_CL
Ko[0] TDM_CL
Ki[2] TDM_CL
Ko[5] VDD_CO
RE N/C N/C N/C N/C N/C N/C VDD_CO
RE GND N/C N/C N/C N/C N/C
RAM_DA
TA[21] RAM_DA
TA[18] RAM_DA
TA[16] RAM_DA
TA[14] RAM_DA
TA[11] RAM_DA
TA[8] N/C N/C M1_LINK
UP_LED M0_LINK
UP_LED M1_GIGA
BIT_LED M_MDIO
RAM_DA
TA[25] RAM_DA
TA[24] RAM_DA
TA[23] RAM_DA
TA[19] RAM_DA
TA[17] VDD_CO
RE VDD_CO
RE M0_GIGA
BIT_LED M_MDC N/C N/C N/C
RAM_DA
TA[29] RAM_DA
TA[28] RAM_DA
TA[27] RAM_DA
TA[26] RAM_DA
TA[22] RAM_DA
TA[20] VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO N/C N/C N/C N/C N/C N/C
RAM_PA
RITY[1] RAM_PA
RITY[0] RAM_DA
TA[31] RAM_DA
TA[30] GND VDD_CO
RE VDD_IO VDD_CO
RE GND N/C N/C N/C N/C
RAM_PA
RITY[7] RAM_PA
RITY[6] RAM_PA
RITY[5] RAM_PA
RITY[4] RAM_PA
RITY[3] RAM_PA
RITY[2] VDD_IO GND GND GND GND GND GND VDD_IO M1_RXE
RM1_TXCL
KM1_CRS N/C N/C N/C
RAM_AD
DR[5] RAM_AD
DR[4] RAM_AD
DR[2] RAM_AD
DR[3] RAM_AD
DR[0] RAM_AD
DR[1] VDD_IO GND GND GND GND GND GND VDD_IO VDD_CO
RE M1_REF
CLK M1_RXCL
KM1_RXD[
5] M1_RXD[
7] M1_RXD
V
GND RAM_AD
DR[6] RAM_AD
DR[7] RAM_AD
DR[8] GND VDD_CO
RE VDD_IO GND GND GND GND GND GND VDD_IO M1_GTX_
CLK GND M1_TXER M1_RXD[
2] M1_RXD[
3] GND
RAM_AD
DR[9] RAM_AD
DR[10] RAM_AD
DR[11] RAM_AD
DR[13] RAM_AD
DR[16] GND VDD_IO GND GND GND GND GND GND VDD_IO M1_TXD[
2] M1_TXD[
6] M1_TXEN GND M1_RXD[
4] M1_RXD[
6]
RAM_AD
DR[12] RAM_AD
DR[14] RAM_AD
DR[15] RAM_AD
DR[19] IC_GND IC VDD_IO GND GND GND GND GND GND VDD_IO M1_TXD[
0] M1_TXD[
3] M1_TXD[
5] M1_TXD[
7] M1_COL M1_RXD[
1]
RAM_AD
DR[17] RAM_AD
DR[18] RAM_BW
_B IC_GND GND A1VDD VDD_IO GND GND GND GND GND GND VDD_IO VDD_CO
RE M1_TXD[
1] M1_TXD[
4] GND M1_RBC1M1_RXD[
0]
PLL_PRI RAM_BW
_A RAM_BW
_C RAM_RW SYSTEM
_DEBUG SYSTEM
_CLK VDD_IO VDD_IO M0_GTX_
CLK M0_RXD[
2] M0_RXD[
5] M0_TXCL
KM0_CRS M1_RBC0
PLL_SEC RAM_BW
_D RAM_BW
_F SYSTEM
_RST GPIO[2] VDD_CO
RE VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO M0_TXD[
7] M0_TXERM0_TXENM0_RXD[
4] M0_RXD
VM0_RXE
R
RAM_BW
_E RAM_BW
_G GPIO[0] GPIO[3] GPIO[9] RAM_DA
TA[33] M0_TXD[
2] M0_TXD[
5] M0_TXD[
6] M0_RXD[
6] M0_RXD[
7] M0_RXD[
3]
RAM_BW
_H GPIO[4] GPIO[6] GPIO[10] RAM_DA
TA[32] VDD_CO
RE VDD_CO
RE M0_TXD[
1] M0_TXD[
4] M0_RBC0 M0_COL M0_RXD[
1]
GPIO[1] GPIO[7] GPIO[8] GPIO[15] RAM_DA
TA[39] GND RAM_DA
TA[45] RAM_DA
TA[52] VDD_CO
RE JTAG_TM
SCPU_AD
DR[2] CPU_AD
DR[12] VDD_CO
RE VDD_CO
RE CPU_DAT
A[8] CPU_DAT
A[15] CPU_DAT
A[23] VDD_CO
RE N/C N/C GND M0_TXD[
0] M0_TXD[
3] M0_REF
CLK M0_RBC1M0_RXD[
0]
GPIO[5] GPIO[11] GPIO[14] RAM_DA
TA[38] RAM_DA
TA[43] RAM_DA
TA[44] RAM_DA
TA[51] RAM_DA
TA[60] TEST_M
ODE[1] GND CPU_AD
DR[6] CPU_AD
DR[14] CPU_AD
DR[23] CPU_TA CPU_DAT
A[1] CPU_DAT
A[7] CPU_DAT
A[12] CPU_DAT
A[22] CPU_DAT
A[30] N/C N/C M0_RXCL
KN/C N/C M1_ACTI
VE_LED N/C
GPIO[12] GPIO[13] RAM_DA
TA[37] RAM_DA
TA[42] RAM_DA
TA[46] RAM_DA
TA[49] RAM_DA
TA[59] TEST_M
ODE[0] JTAG_TD
OCPU_AD
DR[4] CPU_AD
DR[9] CPU_AD
DR[16] CPU_AD
DR[22] CPU_CLK CPU_DR
EQ0 IC CPU_DAT
A[10] CPU_DAT
A[16] CPU_DAT
A[21] CPU_DAT
A[27] N/C N/C N/C N/C N/C M0_ACTI
VE_LED
RAM_DA
TA[34] RAM_DA
TA[36] RAM_DA
TA[41] RAM_DA
TA[47] RAM_DA
TA[53] RAM_DA
TA[58] RAM_DA
TA[63] JTAG_TC
KIC_GND CPU_AD
DR[7] CPU_AD
DR[11] CPU_AD
DR[17] CPU_AD
DR[21] CPU_WE CPU_SD
ACK2 CPU_IRE
Q1 CPU_DAT
A[3] CPU_DAT
A[6] CPU_DAT
A[14] CPU_DAT
A[20] CPU_DAT
A[24] CPU_DAT
A[29] N/C N/C N/C N/C
RAM_DA
TA[35] RAM_DA
TA[40] RAM_DA
TA[48] RAM_DA
TA[54] RAM_DA
TA[57] RAM_DA
TA[62] JTAG_TR
ST IC_GND CPU_AD
DR[3] CPU_AD
DR[8] CPU_AD
DR[13] CPU_AD
DR[18] CPU_AD
DR[20] CPU_OE CPU_TS_
ALE CPU_DR
EQ1 IC CPU_DAT
A[4] CPU_DAT
A[9] CPU_DAT
A[13] CPU_DAT
A[18] CPU_DAT
A[25] CPU_DAT
A[28] N/C N/C N/C
GND RAM_DA
TA[50] RAM_DA
TA[55] RAM_DA
TA[56] RAM_DA
TA[61] TEST_M
ODE[2] JTAG_TDI IC_GND CPU_AD
DR[5] CPU_AD
DR[10] CPU_AD
DR[15] CPU_AD
DR[19] GND CPU_CS CPU_SD
ACK1 IC_VDD_I
OCPU_IRE
Q0 CPU_DAT
A[0] CPU_DAT
A[5] CPU_DAT
A[2] CPU_DAT
A[11] CPU_DAT
A[17] CPU_DAT
A[19] CPU_DAT
A[26] CPU_DAT
A[31] GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
VDD_CO
RE
VDD_IO
ZL50110/11/12/14 Data Sheet
18
Zarlink Semiconductor Inc.
ZL50114 Package view from TOP side. Note that ball A1 is non-chamfered corner.
Figure 5 - ZL50114 Package View and Ball Positions
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
GND TDM_STo
[1] TDM_CL
Ko[3] N/C N/C N/C N/C N/C N/C N/C N/C N/C GND N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
TDM_FR
Mo_REF TDM_STo
[0] TDM_STi[
2] TDM_CL
Ki[3] N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C
TDM_CL
KiP TDM_FR
Mi_REF TDM_CL
Ki_REF TDM_CL
Ko[1] TDM_STi[
3] TDM_CL
Ko[2] N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C
RAM_DA
TA[3] RAM_DA
TA[1] TDM_CL
KiS RAM_DA
TA[0] TDM_STi[
0] TDM_CL
Ki[1] TDM_STo
[3] N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C
RAM_DA
TA[10] RAM_DA
TA[9] RAM_DA
TA[5] RAM_DA
TA[4] RAM_DA
TA[2] TDM_CL
Ko_REF TDM_CL
Ki[0] N/C TDM_STi[
1] N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C GND N/C N/C N/C N/C
RAM_DA
TA[15] RAM_DA
TA[13] RAM_DA
TA[12] RAM_DA
TA[6] RAM_DA
TA[7] GND VDD_CO
RE TDM_STo
[2] TDM_CL
Ko[0] TDM_CL
Ki[2] N/C VDD_CO
RE N/C N/C N/C N/C N/C N/C VDD_CO
RE GND N/C N/C N/C N/C N/C
RAM_DA
TA[21] RAM_DA
TA[18] RAM_DA
TA[16] RAM_DA
TA[14] RAM_DA
TA[11] RAM_DA
TA[8] N/C N/C M1_LINK
UP_LED M0_LINK
UP_LED M1_GIGA
BIT_LED M_MDIO
RAM_DA
TA[25] RAM_DA
TA[24] RAM_DA
TA[23] RAM_DA
TA[19] RAM_DA
TA[17] VDD_CO
RE VDD_CO
RE M0_GIGA
BIT_LED M_MDC N/C N/C N/C
RAM_DA
TA[29] RAM_DA
TA[28] RAM_DA
TA[27] RAM_DA
TA[26] RAM_DA
TA[22] RAM_DA
TA[20] VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO N/C N/C N/C N/C N/C N/C
RAM_PA
RITY[1] RAM_PA
RITY[0] RAM_DA
TA[31] RAM_DA
TA[30] GND VDD_CO
RE VDD_IO VDD_CO
RE GND N/C N/C N/C N/C
RAM_PA
RITY[7] RAM_PA
RITY[6] RAM_PA
RITY[5] RAM_PA
RITY[4] RAM_PA
RITY[3] RAM_PA
RITY[2] VDD_IO GND GND GND GND GND GND VDD_IO M1_RXE
RM1_TXCL
KM1_CRS N/C N/C N/C
RAM_AD
DR[5] RAM_AD
DR[4] RAM_AD
DR[2] RAM_AD
DR[3] RAM_AD
DR[0] RAM_AD
DR[1] VDD_IO GND GND GND GND GND GND VDD_IO VDD_CO
RE M1_REF
CLK M1_RXCL
KM1_RXD[
5] M1_RXD[
7] M1_RXD
V
GND RAM_AD
DR[6] RAM_AD
DR[7] RAM_AD
DR[8] GND VDD_CO
RE VDD_IO GND GND GND GND GND GND VDD_IO M1_GTX_
CLK GND M1_TXER M1_RXD[
2] M1_RXD[
3] GND
RAM_AD
DR[9] RAM_AD
DR[10] RAM_AD
DR[11] RAM_AD
DR[13] RAM_AD
DR[16] GND VDD_IO GND GND GND GND GND GND VDD_IO M1_TXD[
2] M1_TXD[
6] M1_TXEN GND M1_RXD[
4] M1_RXD[
6]
RAM_AD
DR[12] RAM_AD
DR[14] RAM_AD
DR[15] RAM_AD
DR[19] IC_GND IC VDD_IO GND GND GND GND GND GND VDD_IO M1_TXD[
0] M1_TXD[
3] M1_TXD[
5] M1_TXD[
7] M1_COL M1_RXD[
1]
RAM_AD
DR[17] RAM_AD
DR[18] RAM_BW
_B IC_GND GND A1VDD VDD_IO GND GND GND GND GND GND VDD_IO VDD_CO
RE M1_TXD[
1] M1_TXD[
4] GND M1_RBC1M1_RXD[
0]
PLL_PRI RAM_BW
_A RAM_BW
_C RAM_RW SYSTEM
_DEBUG SYSTEM
_CLK VDD_IO VDD_IO M0_GTX_
CLK M0_RXD[
2] M0_RXD[
5] M0_TXCL
KM0_CRS M1_RBC0
PLL_SEC RAM_BW
_D RAM_BW
_F SYSTEM
_RST GPIO[2] VDD_CO
RE VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO M0_TXD[
7] M0_TXERM0_TXEN M0_RXD[
4] M0_RXD
VM0_RXE
R
RAM_BW
_E RAM_BW
_G GPIO[0] GPIO[3] GPIO[9] RAM_DA
TA[33] M0_TXD[
2] M0_TXD[
5] M0_TXD[
6] M0_RXD[
6] M0_RXD[
7] M0_RXD[
3]
RAM_BW
_H GPIO[4] GPIO[6] GPIO[10] RAM_DA
TA[32] VDD_CO
RE VDD_CO
RE M0_TXD[
1] M0_TXD[
4] M0_RBC0 M0_COL M0_RXD[
1]
GPIO[1] GPIO[7] GPIO[8] GPIO[15] RAM_DA
TA[39] GND RAM_DA
TA[45] RAM_DA
TA[52] VDD_CO
RE JTAG_TM
SCPU_AD
DR[2] CPU_AD
DR[12] VDD_CO
RE VDD_CO
RE CPU_DAT
A[8] CPU_DAT
A[15] CPU_DAT
A[23] VDD_CO
RE N/C N/C GND M0_TXD[
0] M0_TXD[
3] M0_REF
CLK M0_RBC1M0_RXD[
0]
GPIO[5] GPIO[11] GPIO[14] RAM_DA
TA[38] RAM_DA
TA[43] RAM_DA
TA[44] RAM_DA
TA[51] RAM_DA
TA[60] TEST_M
ODE[1] GND CPU_AD
DR[6] CPU_AD
DR[14] CPU_AD
DR[23] CPU_TA CPU_DAT
A[1] CPU_DAT
A[7] CPU_DAT
A[12] CPU_DAT
A[22] CPU_DAT
A[30] N/C N/C M0_RXCL
KN/C N/C M1_ACTI
VE_LED N/C
GPIO[12] GPIO[13] RAM_DA
TA[37] RAM_DA
TA[42] RAM_DA
TA[46] RAM_DA
TA[49] RAM_DA
TA[59] TEST_M
ODE[0] JTAG_TD
OCPU_AD
DR[4] CPU_AD
DR[9] CPU_AD
DR[16] CPU_AD
DR[22] CPU_CLK CPU_DR
EQ0 IC CPU_DAT
A[10] CPU_DAT
A[16] CPU_DAT
A[21] CPU_DAT
A[27] N/C N/C N/C N/C N/C M0_ACTI
VE_LED
RAM_DA
TA[34] RAM_DA
TA[36] RAM_DA
TA[41] RAM_DA
TA[47] RAM_DA
TA[53] RAM_DA
TA[58] RAM_DA
TA[63] JTAG_TC
KIC_GND CPU_AD
DR[7] CPU_AD
DR[11] CPU_AD
DR[17] CPU_AD
DR[21] CPU_WE CPU_SD
ACK2 CPU_IRE
Q1 CPU_DAT
A[3] CPU_DAT
A[6] CPU_DAT
A[14] CPU_DAT
A[20] CPU_DAT
A[24] CPU_DAT
A[29] N/C N/C N/C N/C
RAM_DA
TA[35] RAM_DA
TA[40] RAM_DA
TA[48] RAM_DA
TA[54] RAM_DA
TA[57] RAM_DA
TA[62] JTAG_TR
ST IC_GND CPU_AD
DR[3] CPU_AD
DR[8] CPU_AD
DR[13] CPU_AD
DR[18] CPU_AD
DR[20] CPU_OE CPU_TS_
ALE CPU_DR
EQ1 IC CPU_DAT
A[4] CPU_DAT
A[9] CPU_DAT
A[13] CPU_DAT
A[18] CPU_DAT
A[25] CPU_DAT
A[28] N/C N/C N/C
GND RAM_DA
TA[50] RAM_DA
TA[55] RAM_DA
TA[56] RAM_DA
TA[61] TEST_M
ODE[2] JTAG_TDI IC_GND CPU_AD
DR[5] CPU_AD
DR[10] CPU_AD
DR[15] CPU_AD
DR[19] GND CPU_CS CPU_SD
ACK1 IC_VDD_I
OCPU_IRE
Q0 CPU_DAT
A[0] CPU_DAT
A[5] CPU_DAT
A[2] CPU_DAT
A[11] CPU_DAT
A[17] CPU_DAT
A[19] CPU_DAT
A[26] CPU_DAT
A[31] GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
VDD_CO
RE
VDD_IO
ZL50110/11/12/14 Data Sheet
19
Zarlink Semiconductor Inc.
Ball Signal Assignment
Ball
Number Signal Name
A1 GND
A2 TDM_STo[1]
A3 TDM_CLKo[3]
A4‡TDM_STo[4]
A5‡TDM_STo[5]
A6‡TDM_STi[6]
A7‡TDM_STo[7]
A8‡TDM_STi[7]
A9†TDM_CLKo[10]
A10†TDM_CLKi[10]
A11†TDM_CLKi[11]
A12†TDM_CLKo[13]
A13 GND
A14†TDM_STo[13]
A15†TDM_STo[14]
A16†TDM_CLKo[15]
A17*TDM_STo[16]
A18†* TDM_CLKo[18]
A19*TDM_STi[18]
A20*TDM_CLKi[20]
A21*TDM_STi[20]
A22*TDM_STo[21]
A23*TDM_STi[21]
A24*TDM_CLKo[24]
A25*TDM_CLKo[25]
A26 GND
B1 TDM_FRMo_REF
B2 TDM_STo[0]
B3 TDM_STi[2]
B4 TDM_CLKi[3]
B5‡TDM_STi[4]
B6‡TDM_CLKo[6]
B7‡TDM_STo[6]
B8†TDM_CLKo[8]
B9†TDM_CLKi[9]
B10†TDM_STo[10]
B11†TDM_STi[10]
B12†TDM_CLKi[12]
B13†TDM_STo[12]
B14†TDM_STi[13]
B15†TDM_CLKi[15]
B16†TDM_STi[15]
B17*TDM_STi[17]
B18†* TDM_CLKi[18]
B19*TDM_CLKo[20]
B20*TDM_STo[19]
B21*TDM_STo[22]
B22*TDM_CLKo[23]
B23*TDM_STo[24]
B24*TDM_CLKo[26]
B25*TDM_STi[24]
B26*TDM_CLKo[27]
C1 TDM_CLKiP
C2 TDM_FRMi_REF
C3 TDM_CLKi_REF
C4 TDM_CLKo[1]
C5 TDM_STi[3]
C6 TDM_CLKo[2]
C7‡TDM_CLKi[6]
C8‡TDM_CLKi[7]
C9†TDM_CLKo[9]
C10†TDM_STo[9]
C11†TDM_STi[9]
C12†TDM_STi[11]
C13†TDM_CLKi[13]
C14†TDM_CLKo[14]
C15*TDM_CLKo[16]
C16*TDM_STi[16]
C17*TDM_CLKo[17]
C18*TDM_STi[19]
C19*TDM_CLKo[21]
C20*TDM_CLKi[21]
C21*TDM_CLKi[24]
C22*TDM_STi[22]
C23*TDM_STo[26]
Ball
Number Signal Name
C24*TDM_CLKi[27]
C25*TDM_STi[27]
C26*TDM_STi[28]
D1 RAM_DATA[3]
D2 RAM_DATA[1]
D3 TDM_CLKiS
D4 RAM_DATA[0]
D5 TDM_STi[0]
D6 TDM_CLKi[1]
D7 TDM_STo[3]
D8‡TDM_STi[5]
D9‡TDM_CLKi[5]
D10‡TDM_CLKo[7]
D11†TDM_STi[8]
D12†TDM_CLKo[11]
D13†TDM_STi[12]
D14†TDM_STi[14]
D15†* TDM_CLKi[16]
D16†TDM_CLKo[19]
D17*TDM_STo[18]
D18*TDM_STo[20]
D19*TDM_CLKo[22]
D20*TDM_STo[27]
D21*TDM_STo[25]
D22*TDM_CLKi[26]
D23*TDM_CLKo[28]
D24*TDM_CLKi[29]
D25*TDM_STi[29]
D26*TDM_STi[31]
E1 RAM_DATA[10]
E2 RAM_DATA[9]
E3 RAM_DATA[5]
E4 RAM_DATA[4]
E5 RAM_DATA[2]
E6 TDM_CLKo_REF
E7 TDM_CLKi[0]
E8‡TDM_CLKo[4]
E9 TDM_STi[1]
Ball
Number Signal N ame
ZL50110/11/12/14 Data Sheet
20
Zarlink Semiconductor Inc.
E10‡TDM_CLKi[4]
E11†TDM_STo[8]
E12†TDM_CLKi[8]
E13†TDM_CLKo[12]
E14†TDM_STo[15]
E15*TDM_CLKi[17]
E16*TDM_CLKi[19]
E17*TDM_STo[23]
E18*TDM_STi[23]
E19*TDM_CLKi[25]
E20*TDM_STi[26]
E21*TDM_CLKi[28]
E22 GND
E23*TDM_CLKo[30]
E24*TDM_CLKi[30]
E25*TDM_STi[30]
E26†* TDM_STo[29]
F1 RAM_DATA[15]
F2 RAM_DATA[13]
F3 RAM_DATA[12]
F4 RAM_DATA[6]
F5 RAM_DATA[7]
F6 GND
F7 VDD_CORE
F8 TDM_STo[2]
F9 TDM_CLKo[0]
F10 TDM_CLKi[2]
F11‡TDM_CLKo[5]
F12 VDD_CORE
F13†TDM_STo[11]
F14†TDM_CLKi[14]
F15 VDD_CORE
F16*TDM_STo[17]
F17*TDM_CLKi[22]
F18*TDM_STi[25]
F19*TDM_CLKi[23]
F20 VDD_CORE
F21 GND
Ball
Number Signal Name
F22*TDM_CLKi[31]
F23*TDM_CLKo[29]
F24*TDM_STo[28]
F25*TDM_CLKo[31]
F26†M1_LINKUP_LED
G1 RAM_DATA[21]
G2 RAM_DATA[18]
G3 RAM_DATA[16]
G4 RAM_DATA[14]
G5 RAM_DATA[11]
G6 RAM_DATA[8]
G21*TDM_STo[31]
G22*TDM_STo[30]
G23 M1/2_LINKUP_LED
G24 M0/3_LINKUP_LED
G25 M1_GIGABIT_LED
G26 M_MDIO
H1 RAM_DATA[25]
H2 RAM_DATA[24]
H3 RAM_DATA[23]
H4 RAM_DATA[19]
H5 RAM_DATA[17]
H6 VDD_CORE
H21 VDD_CORE
H22 M0_GIGABIT_LED
H23 M_MDC
H24*M3_CRS
H25*M3_TXCLK
H26*M3_RXER
J1 RAM_DATA[29]
J2 RAM_DATA[28]
J3 RAM_DATA[27]
J4 RAM_DATA[26]
J5 RAM_DATA[22]
J6 RAM_DATA[20]
J9 VDD_IO
J10 VDD_IO
J11 VDD_IO
Ball
Number Signal Name
J12 VDD_IO
J13 VDD_IO
J14 VDD_IO
J15 VDD_IO
J16 VDD_IO
J17 VDD_IO
J18 VDD_IO
J21*M3_RXDV
J22*M3_RXD[3]
J23*M3_RXD[2]
J24*M3_RXD[1]
J25*M3_RXD[0]
J26*M3_COL
K1 RAM_PARITY[1]
K2 RAM_PARITY[0]
K3 RAM_DATA[31]
K4 RAM_DATA[30]
K5 GND
K6 VDD_CORE
K9 VDD_IO
K18 VDD_IO
K21 VDD_CORE
K22 GND
K23*M3_TXD[3]
K24*M3_TXEN
K25*M3_TXER
K26*M3_RXCLK
L1 RAM_PARITY[7]
L2 RAM_PARITY[6]
L3 RAM_PARITY[5]
L4 RAM_PARITY[4]
L5 RAM_PARITY[3]
L6 RAM_PARITY[2]
L9 VDD_IO
L11 GND
L12 GND
L13 GND
L14 GND
Ball
Number Signal N ame
ZL50110/11/12/14 Data Sheet
21
Zarlink Semiconductor Inc.
L15 GND
L16 GND
L18 VDD_IO
L21 M1_RXER
L22 M1_TXCLK
L23 M1_CRS
L24*M3_TXD[0]
L25*M3_TXD[1]
L26*M3_TXD[2]
M1 RAM_ADDR[5]
M2 RAM_ADDR[4]
M3 RAM_ADDR[2]
M4 RAM_ADDR[3]
M5 RAM_ADDR[0]
M6 RAM_ADDR[1]
M9 VDD_IO
M11 GND
M12 GND
M13 GND
M14 GND
M15 GND
M16 GND
M18 VDD_IO
M21 VDD_CORE
M22 M1_REFCLK
M23 M1_RXCLK
M24 M1_RXD[5]
M25 M1_RXD[7]
M26 M1_RXDV
N1 GND
N2 RAM_ADDR[6]
N3 RAM_ADDR[7]
N4 RAM_ADDR[8]
N5 GND
N6 VDD_CORE
N9 VDD_IO
N11 GND
N12 GND
Ball
Number Signal Name
N13 GND
N14 GND
N15 GND
N16 GND
N18 VDD_IO
N21 M1_GTX_CLK
N22 GND
N23 M1_TXER
N24 M1_RXD[2]
N25 M1_RXD[3]
N26 GND
P1 RAM_ADDR[9]
P2 RAM_ADDR[10]
P3 RAM_ADDR[11]
P4 RAM_ADDR[13]
P5 RAM_ADDR[16]
P6 GND
P9 VDD_IO
P11 GND
P12 GND
P13 GND
P14 GND
P15 GND
P16 GND
P18 VDD_IO
P21 M1_TXD[2]
P22 M1_TXD[6]
P23 M1_TXEN
P24 GND
P25 M1_RXD[4]
P26 M1_RXD[6]
R1 RAM_ADDR[12]
R2 RAM_ADDR[14]
R3 RAM_ADDR[15]
R4 RAM_ADDR[19]
R5 IC_GND
R6 IC
R9 VDD_IO
Ball
Number Signal Name
R11 GND
R12 GND
R13 GND
R14 GND
R15 GND
R16 GND
R18 VDD_IO
R21 M1_TXD[0]
R22 M1_TXD[3]
R23 M1_TXD[5]
R24 M1_TXD[7]
R25 M1_COL
R26 M1_RXD[1]
T1 RAM_ADDR[17]
T2 RAM_ADDR[18]
T3 RAM_BW_B
T4 IC_GND
T5 GND
T6 A1VDD
T9 VDD_IO
T11 GND
T12 GND
T13 GND
T14 GND
T15 GND
T16 GND
T18 VDD_IO
T21 VDD_CORE
T22 M1_TXD[1]
T23 M1_TXD[4]
T24 GND
T25 M1_RBC1
T26 M1_RXD[0]
U1 PLL_PRI
U2 RAM_BW_A
U3 RAM_BW_C
U4 RAM_RW
U5 SYSTEM_DEBUG
Ball
Number Signal N ame
ZL50110/11/12/14 Data Sheet
22
Zarlink Semiconductor Inc.
U6 SYSTEM_CLK
U9 VDD_IO
U18 VDD_IO
U21 M0_GTX_CLK
U22 M0_RXD[2]
U23 M0_RXD[5]
U24 M0_TXCLK
U25 M0_CRS
U26 M1_RBC0
V1 PLL_SEC
V2 RAM_BW_D
V3 RAM_BW_F
V4 SYSTEM_RST
V5 GPIO[2]
V6 VDD_CORE
V9 VDD_IO
V10 VDD_IO
V11 VDD_IO
V12 VDD_IO
V13 VDD_IO
V14 VDD_IO
V15 VDD_IO
V16 VDD_IO
V17 VDD_IO
V18 VDD_IO
V21 M0_TXD[7]
V22 M0_TXER
V23 M0_TXEN
V24 M0_RXD[4]
V25 M0_RXDV
V26 M0_RXER
W1 RAM_BW_E
W2 RAM_BW_G
W3 GPIO[0]
W4 GPIO[3]
W5 GPIO[9]
W6 RAM_DATA[33]
W21 M0_TXD[2]
Ball
Number Signal Name
W22 M0_TXD[5]
W23 M0_TXD[6]
W24 M0_RXD[6]
W25 M0_RXD[7]
W26 M0_RXD[3]
Y1 RAM_BW_H
Y2 GPIO[4]
Y3 GPIO[6]
Y4 GPIO[10]
Y5 RAM_DATA[32]
Y6 VDD_CORE
Y21 VDD_CORE
Y22 M0_TXD[1]
Y23 M0_TXD[4]
Y24 M0_RBC0
Y25 M0_COL
Y26 M0_RXD[1]
AA1 GPIO[1]
AA2 GPIO[7]
AA3 GPIO[8]
AA4 GPIO[15]
AA5 RAM_DATA[39]
AA6 GND
AA7 RAM_DATA[45]
AA8 RAM_DATA[52]
AA9 VDD_CORE
AA10 JTAG_TMS
AA11 CPU_ADDR[2]
AA12 CPU_ADDR[12]
AA13 VDD_CORE
AA14 VDD_CORE
AA15 CPU_DATA[8]
AA16 CPU_DATA[15]
AA17 CPU_DATA[23]
AA18 VDD_CORE
AA19†M2_RXCLK
AA20†M2_RXDV
AA21 GND
Ball
Number Signal Name
AA22 M0_TXD[0]
AA23 M0_TXD[3]
AA24 M0_REFCLK
AA25 M0_RBC1
AA26 M0_RXD[0]
AB1 GPIO[5]
AB2 GPIO[11]
AB3 GPIO[14]
AB4 RAM_DATA[38]
AB5 RAM_DATA[43]
AB6 RAM_DATA[44]
AB7 RAM_DATA[51]
AB8 RAM_DATA[60]
AB9 TEST_MODE[1]
AB10 GND
AB11 CPU_ADDR[6]
AB12 CPU_ADDR[14]
AB13 CPU_ADDR[23]
AB14 CPU_TA
AB15 CPU_DATA[1]
AB16 CPU_DATA[7]
AB17 CPU_DATA[12]
AB18 CPU_DATA[22]
AB19 CPU_DATA[30]
AB20†M2_TXER
AB21†M2_RXD[1]
AB22 M0_RXCLK
AB23†M0_LINKUP_LED
AB24†M2_ACTIVE_LED
AB25 M1_ACTIVE_LED
AB26*M3_ACTIVE_LED
AC1 GPIO[12]
AC2 GPIO[13]
AC3 RAM_DATA[37]
AC4 RAM_DATA[42]
AC5 RAM_DATA[46]
AC6 RAM_DATA[49]
AC7 RAM_DATA[59]
Ball
Number Signal N ame
ZL50110/11/12/14 Data Sheet
23
Zarlink Semiconductor Inc.
* Not connected on ZL50112, ZL50110 and
ZL50114 - leave open circuit.
† Not Connecte d on ZL501 10 and ZL50114 -
leave open circuit.
‡ Not Connected on ZL50114 - leave open
circuit.
N/C - Not Connected - leave open circuit.
* Internally Connected on ZL50112 - leave
open circuit.
IC - Internally Connected - leave open
circuit.
IC_GND - tie to ground
IC_VDD_IO - tie to VDD_I O
AC8 TEST_MODE[0]
AC9 JTAG_TDO
AC10 CPU_ADDR[4]
AC11 CPU_ADDR[9]
AC12 CPU_ADDR[16]
AC13 CPU_ADDR[22]
AC14 CPU_CLK
AC15 CPU_DREQ0
AC16 IC
AC17 CPU_DATA[10]
AC18 CPU_DATA[16]
AC19 CPU_DATA[21]
AC20 CPU_DATA[27]
AC21†M2_TXD[1]
AC22†M2_TXEN
AC23†M2_RXD[2]
AC24†M2_RXER
AC25†M2_CRS
AC26 M0_ACTIVE_LED
AD1 RAM_DATA[34]
AD2 RAM_DATA[36]
AD3 RAM_DATA[41]
AD4 RAM_DATA[47]
AD5 RAM_DATA[53]
AD6 RAM_DATA[58]
AD7 RAM_DATA[63]
AD8 JTAG_TCK
AD9 IC_GND
AD10 CPU_ADDR[7]
AD11 CPU_ADDR[11]
AD12 CPU_ADDR[17]
AD13 CPU_ADDR[21]
AD14 CPU_WE
AD15 CPU_SDACK2
AD16 CPU_IREQ1
AD17 CPU_DATA[3]
AD18 CPU_DATA[6]
AD19 CPU_DATA[14]
Ball
Number Signal Name
AD20 CPU_DATA[20]
AD21 CPU_DATA[24]
AD22 CPU_DATA[29]
AD23†M2_TXD[2]
AD24†M2_RXD[0]
AD25†M2_RXD[3]
AD26†M2_TXCLK
AE1 RAM_DATA[35]
AE2 RAM_DATA[40]
AE3 RAM_DATA[48]
AE4 RAM_DATA[54]
AE5 RAM_DATA[57]
AE6 RAM_DATA[62]
AE7 JTAG_TRST
AE8 IC_GND
AE9 CPU_ADDR[3]
AE10 CPU_ADDR[8]
AE11 CPU_ADDR[13]
AE12 CPU_ADDR[18]
AE13 CPU_ADDR[20]
AE14 CPU_OE
AE15 CPU_TS_ALE
AE16 CPU_DREQ1
AE17 IC
AE18 CPU_DATA[4]
AE19 CPU_DATA[9]
AE20 CPU_DATA[13]
AE21 CPU_DATA[18]
AE22 CPU_DATA[25]
AE23 CPU_DATA[28]
AE24†M2_TXD[0]
AE25†M2_TXD[3]
AE26†M2_COL
AF1 GND
AF2 RAM_DATA[50]
AF3 RAM_DATA[55]
AF4 RAM_DATA[56]
AF5 RAM_DATA[61]
Ball
Number Signal Name
AF6 TEST_MODE[2]
AF7 JTAG_TDI
AF8 IC_GND
AF9 CPU_ADDR[5]
AF10 CPU_ADDR[10]
AF11 CPU_ADDR[15]
AF12 CPU_ADDR[19]
AF13 GND
AF14 CPU_CS
AF15 CPU_SDACK1
AF16 IC_VDD_IO
AF17 CPU_IREQ0
AF18 CPU_DATA[0]
AF19 CPU_DATA[5]
AF20 CPU_DATA[2]
AF21 CPU_DATA[11]
AF22 CPU_DATA[17]
AF23 CPU_DATA[19]
AF24 CPU_DATA[26]
AF25 CPU_DATA[31]
AF26 GND
Ball
Number Signal N ame
ZL50110/11/12/14 Data Sheet
24
Zarlink Semiconductor Inc.
3.0 External Interface Description
The following key applies to all tables:
3.1 TDM Interface
All TDM Interface signals are 5 V tolerant.
All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be
safely left unconnected if not used.
3.1.1 ZL50111 Variant TDM Stream Connectio n
I Input
OOutput
D Internal 100 kΩ pull-down resistor present
U Internal 100 kΩ pull-up resistor present
T Tri-state Output
Signal I /O Package Balls Description
TDM_STi[31:0] I D [31] D26 [15] B16
[30] E25 [14] D14
[29] D25 [13] B14
[28] C26 [12] D13
[27] C25 [11] C12
[26] E20 [10] B11
[25] F18 [9] C11
[24] B25 [8] D11
[23] E18 [7] A8
[22] C22 [6] A6
[21] A23 [5] D8
[20] A21 [4] B5
[19] C18 [3] C5
[18] A19 [2] B3
[17] B17 [1] E9
[16] C16 [0] D5
TDM port serial data input streams. For
different standards these pins are given
differen t identities:
ST-BUS: TDM_STi[31:0]
H.110: TDM_D[31:0]
H-MVIP: TDM_HDS[31:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps only
streams [7:0] are used, with 128 channels
per stream. Streams [7:0] are used for J2,
and streams [1:0] are used for T3 and E3.
Table 2 - TDM Interface ZL50111 Stream Pin Definition
ZL50110/11/12/14 Data Sheet
25
Zarlink Semiconductor Inc.
TDM_STo[31:0] OT [31] G21 [15] E14
[30] G22 [14] A15
[29] E26 [13] A14
[28] F24 [12] B13
[27] D20 [11] F13
[26] C23 [10] B10
[25] D21 [9] C10
[24] B23 [8] E11
[23] E17 [7] A7
[22] B21 [6] B7
[21] A22 [5] A5
[20] D18 [4] A4
[19] B20 [3] D7
[18] D17 [2] F8
[17] F16 [1] A2
[16] A17 [0] B2
TDM port serial data output streams. For
different standards these pins are given
differen t identities:
ST-BUS: TDM_STo[31:0]
H.110: TDM_D[31:0]
H-MVIP: TDM_HDS[31:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps only
streams [7:0] are used, with 128 channels
per stream. Streams [7:0] are used for J2,
and streams [1:0] are used for T3 and E3.
TDM_CLKi[31:0] I D [31] F22 [15] B15
[30] E24 [14] F14
[29] D24 [13] C13
[28] E21 [12] B12
[27] C24 [11] A11
[26] D22 [10] A10
[25] E19 [9] B9
[24] C21 [8] E12
[23] F19 [7] C8
[22] F17 [6] C7
[21] C20 [5] D9
[20] A20 [4] E10
[19] E16 [3] B4
[18] B18 [2] F10
[17] E15 [1] D6
[16] D15 [0] E7
TDM port clock inputs. Programmable as
active high or low. Can accept frequencies
of 1.544 MHz, 2.048 MHz, 4.096 MHz,
6.312 MHz, 8.192 MHz, 16.384 MHz,
34.368 MHz or 44.736 MHz depending on
standard used. At 8.192 Mbps only streams
[7:0] are used. Streams [7:0] are used for
J2, and streams [1:0] are used for T3 and
E3.
Signal I /O Package Balls Description
Table 2 - TDM Interface ZL5 0111 Stream Pin Definition (continued)
ZL50110/11/12/14 Data Sheet
26
Zarlink Semiconductor Inc.
Note: Speed modes:
2.048 Mbps - all 32 streams active (bits [31:0]), with 32 channels per stream - 1024 total channels.
8.192 Mbps - 8 streams active (bits [7:0]), with 128 channels per stream - 1024 total channels.
J2 - 8 streams active (bits [7:0]), with 98 channels per stream - 784 total channels.
E3 - 2 strea ms active (b its [1:0]), with 537 ch annels per st ream - 10 74 total channels.
T3 - 2 streams active (bits [1:0]), with 699 channels per stream - 1398 total channels.
Note: All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely left
unconnected if not used.
3.1.2 ZL5011 2 Va riant TDM Stream Connection
TDM_CLKo[31:0] O [31] F25 [15] A16
[30] E23 [14] C14
[29] F23 [13] A12
[28] D23 [12] E13
[27] B26 [11] D12
[26] B24 [10] A9
[25] A25 [9] C9
[24] A24 [8] B8
[23] B22 [7] D10
[22] D19 [6] B6
[21] C19 [5] F11
[20] B19 [4] E8
[19] D16 [3] A3
[18] A18 [2] C6
[17] C17 [1] C4
[16] C15 [0] F9
TDM port clock outputs. Will generate
1.544 MHz, 2.048 MHz, 4.096 MHz,
6.312 MHz, 8.192 MHz, 16.384 MHz,
34.368 MHz or 44.736 MHz depending on
standard used. At 8.192 Mbps only streams
[7:0] are used. Streams [7:0] are used for
J2, and streams [1:0] are used for T3 and
E3.
Signal I /O Package Balls Description
TDM_STi[15:0] I D [15] B16
[14] D14
[13] B14
[12] D13
[11] C12
[10] B11
[9] C11
[8] D11
[7] A8
[6] A6
[5] D8
[4] B5
[3] C5
[2] B3
[1] E9
[0] D5
TDM port serial data input streams. For
different standards these pins are given
differen t identities:
ST-BUS: TDM_STi[15:0]
H.110: TDM_D[15:0]
H-MVIP: TDM_HDS[15:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps only
streams [3:0] are used, with 128 channels
per stream. Streams [3:0] are used for J2.
Table 3 - TDM Interface ZL50112 Stream Pin Definition
Signal I /O Package Balls Description
Table 2 - TDM Interface ZL5 0111 Stream Pin Definition (continued)
ZL50110/11/12/14 Data Sheet
27
Zarlink Semiconductor Inc.
TDM_STo[15:0] OT [15] E14
[14] A15
[13] A14
[12] B13
[11] F13
[10] B10
[9] C10
[8] E11
[7] A7
[6] B7
[5] A5
[4] A4
[3] D7
[2] F8
[1] A2
[0] B2
TDM port serial data output streams. For
different standards these pins are given
differen t identities:
ST-BUS: TDM_STo[15:0]
H.110: TDM_D[15:0]
H-MVIP: TDM_HDS[15:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps only
streams [3:0] are used, with 128 channels
per stream. Streams [3:0] are used for J2.
TDM_CLKi[15:0] I D [15] B15
[14] F14
[13] C13
[12] B12
[11] A11
[10] A10
[9] B9
[8] E12
[7] C8
[6] C7
[5] D9
[4] E10
[3] B4
[2] F10
[1] D6
[0] E7
TDM port clock inputs. Programmable as
active high or low. Can accept frequencies
of 1.544 MHz, 2.048 MHz, 4.096 MHz,
6.312 MHz, 8.192 MHz, 16.384 MHz,
34.368 MHz or 44.736 MHz depending on
standard used. At 8.192 Mbps only streams
[3:0] are used. Streams [3:0] are used for
J2.
Signal I /O Package Balls Description
Table 3 - TDM Interface ZL50112 Stream Pin Definition (continued)
ZL50110/11/12/14 Data Sheet
28
Zarlink Semiconductor Inc.
Note: Speed modes:
2.048 Mbps - all 16 streams active (bits [15:0]), with 32 channels per stream - 512 total channels.
8.192 Mbps - 4 streams active (bits [3:0]), with 128 channels per stream - 512 total channels.
J2 - 4 streams active (bits [3:0]), with 98 channels per stream - 392 total channels.
Note: All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely left
unconnected if not used.
TDM_CLKo[15:0] O [15] A16
[14] C14
[13] A12
[12] E13
[11] D12
[10] A9
[9] C9
[8] B8
[7] D10
[6] B6
[5] F11
[4] E8
[3] A3
[2] C6
[1] C4
[0] F9
TDM port clock outputs. Will generate
1.544 MHz, 2.048 MHz, 4.096 MHz,
6.312 MHz, 8.192 MHz, 16.384 MHz
depending on standard used. At
8.192 Mbps only streams [3:0] are used.
Streams [3:0] are used for J2.
Signal I /O Package Balls Description
Table 3 - TDM Interface ZL50112 Stream Pin Definition (continued)
ZL50110/11/12/14 Data Sheet
29
Zarlink Semiconductor Inc.
3.1.3 ZL5011 0 Va riant TDM Stream Connection
Note: Speed modes:
2.048 Mbps - all 8 stre ams active (bits [7:0]), with 3 2 channels pe r stream - 256 total channels .
8.192 Mbps - 2 streams active (bits [1:0]), with 128 channels per stream - 256 total channels.
J2 - 2 streams active (bits [1:0]), with 98 channels per stream - 196 total channels.
Note: All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely left
unconnected if not used.
Signal I /O Package Balls Description
TDM_STi[7:0] I D [7] A8
[6] A6
[5] D8
[4] B5
[3] C5
[2] B3
[1] E9
[0] D5
TDM port serial data input streams. For
different standards these pins are given
differen t identities:
ST-BUS: TDM_STi[7:0]
H.110: TDM_D[7:0]
H-MVIP: TDM_HDS[7:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps only
streams [1:0] are used. Streams [1:0] are
used for J2.
TDM_STo[7:0] OT [7] A7
[6] B7
[5] A5
[4] A4
[3] D7
[2] F8
[1] A2
[0] B2
TDM port serial data output streams. For
different standards these pins are given
differen t identities:
ST-BUS: TDM_STo[7:0]
H.110: TDM_D[7:0]
H-MVIP: TDM_HDS[7:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps only
streams [1:0] are used. Streams [1:0] are
used for J2.
TDM_CLKi[7:0] I D [7] C8
[6] C7
[5] D9
[4] E10
[3] B4
[2] F10
[1] D6
[0] E7
TDM port clock inputs
programmable as active high or low. Can
accept frequencie s of 1.544 MHz,
2.048 MHz, 4.096 MHz, 8.192 MHz,
6.312 MHz or 16.384 MHz depending on
standard used. At 8.192 Mbps only
streams [1:0] are used. Streams [1:0] are
used for J2.
TDM_CLKo[7:0] O [7] D10
[6] B6
[5] F11
[4] E8
[3] A3
[2] C6
[1] C4
[0] F9
TDM port clock outputs. Will generate
1.544 MHz, 2.048 MHz, 4.096 MHz,
6.312 MHz, 8.192 MHz or 16.384 MHz
depending on standard used. At
8.192 Mbps only streams [1:0] are used.
Streams [1:0] are used for J2.
Table 4 - TDM Interface ZL50110 Stream Pin Definition
ZL50110/11/12/14 Data Sheet
30
Zarlink Semiconductor Inc.
3.1.4 ZL5011 4 Va riant TDM Stream Connection
Note: Speed modes:
2.048 Mbps - all 4 stre ams active (bits [3:0]), with 3 2 channels pe r stream - 128 total channels .
8.192 Mbps - 2 streams active (bits [1:0]), with 128 channels per stream - 256 total channels.
J2 - 2 streams active (bits [1:0]), with 98 channels per stream - 196 total channels.
Note: All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely left
unconnected if not used.
Signal I/O Package Balls Description
TDM_STi[3:0] I D [3] C5
[2] B3
[1] E9
[0] D5
TDM port serial data input streams. For
different standards these pins are given
different identities:
ST-BUS: TDM_STi[3:0]
H.110: TDM_D[3:0]
H-MVIP: TDM_HDS[3:0]
Triggered on rising edge or falling edge
depending on stand ard. At 8.192 Mbps
only streams [1:0] are used. Streams [1:0]
are used for J2.
TDM_STo[3:0] OT [3] D7
[2] F8
[1] A2
[0] B2
TDM port serial data output streams. For
different standards these pins are given
different identities:
ST-BUS: TDM_STo[3:0]
H.110: TDM_D[3:0]
H-MVIP: TDM_HDS[3:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps only
streams [1:0] are used. Streams [1:0] are
used for J2.
TDM_CLKi[3:0] I D [3] B4
[2] F10
[1] D6
[0] E7
TDM port clock inputs
programmable as active high or low. Can
accept frequencies of 1.544 MHz,
2.048 MHz, 4.096 MHz, 8.192 MHz,
6.312 MHz or 16.384 MHz depending on
standard used. At 8.192 Mbps only
streams [1:0] are used. Streams [1:0] are
used for J2.
TDM_CLKo[3:0] O [3] A3
[2] C6
[1] C4
[0] F9
TDM port clock outputs. Will generate
1.544 MHz, 2.048 MHz, 4.096 MHz,
6.312 MHz, 8.192 MHz or 16.384 MHz
depending on st andard used. At 8.192 Mbps
only streams [1:0] are used. Streams [1:0]
are used for J2.
Table 5 - TDM Interface ZL50114 Stream Pin Definition
ZL50110/11/12/14 Data Sheet
31
Zarlink Semiconductor Inc.
3.1.5 TDM Signals Common to ZL50110, ZL50 111, ZL50112 and ZL50114
Signal I/O Package Balls Description
TDM_CLKi_REF I D C3 TDM port reference clock in put for
backplane operation
TDM_CLKo_REF O E6 TDM port reference clock output for
backplane operation
TDM_FRMi_REF I D C2 TDM port reference frame input. For
different standards this pin is given a
different identity:
ST-BUS: TDM_F0i
H.110: TDM_FRAME
H-MVIP: TDM_F0
Signal is normally active low, but can be
active high depending on standard.
Indicates the start of a TDM frame by
pulsing every 125 µs. Normally will straddle
rising edge or falling edge of clock pulse,
depending on standard and clock frequency.
TDM_FRMo_REF O B1 TDM port reference frame output. For
different standards this pin is given a
different identity:
ST-BUS: TDM_F0o
H.110: TDM_FRAME
H-MVIP: TDM_F0
Signal is normally active low, but can be
active high depending on standard.
Indicates the start of a TDM frame by
pulsing every 125 µs. Normally will straddle
rising edge or falling edge of clock pulse,
depending on standard and clock frequency.
Table 6 - TDM Interface Common Pin Definition
ZL50110/11/12/14 Data Sheet
32
Zarlink Semiconductor Inc.
3.2 PAC In terface
All PAC Interface signals are 5 V tolerant
All PAC Interface outputs are high impedance while System Reset is LOW.
Signal I/O Package Balls Description
TDM_CLKiP I D C1 Primary reference clock input. Should be
driven by external clock source to provide
locking reference to internal / optional
external DPLL in TDM master mode. Also
provides PRS clock for RTP timestamps in
synchronous modes.
Acceptable frequency range: 8 kHz -
34.368 MHz (generally should be between
10 MHz and 25 MHz as per ITU-T Y.1413.
TDM_CLKiS I D D3 Secondary reference clock input. Backup
external reference for automatic switch-over
in case of failure of TDM_CLKiP source.
PLL_PRI OT U1 Primary reference output to optional
external DPLL.
Multiplexed & frequency divided reference
output for support of optional external DPLL.
Expected frequency range:
8 kHz - 16.384 MHz.
PLL_SEC OT V1 Secondary reference output to optional
external DPLL Multiplexed & frequency
divided reference output for support of
optional external DPLL.
Expected frequency range:
8 kHz - 16.384 MHz.
Table 7 - PAC Interface Package Ball Definition
ZL50110/11/12/14 Data Sheet
33
Zarlink Semiconductor Inc.
3.3 Packet Interfaces
For the ZL50111 and ZL50112 variants the packet interface is capable of either 3 MII interfaces, 2 redundant GMII
interfaces or 2 redundant TBI (1000 Mbps) interfaces. The TBI interface is a PCS interface supported by an
integrated 1000BASE-X PCS module. The ZL50110 and ZL50114 variants have either 2 MII interfaces, 2 redundant
GMII interfaces or 2 redundant TBI (1000 Mbps) interfaces. When the packet interface is programmed for PCS/TBI
mode, by default the hardware will not enable auto-negotiation. The TBI auto-negotiation must be done by
application software. Ports 2 and 3 are not available on the ZL50110 and ZL50114 devices.
NOTE: In GMII/TBI mode only 1 GMAC port may be used to receive data. The second GMAC port is for
redundancy purposes only.
Data for all three types of packet switching is based on Specification IEEE Std. 802.3 - 2000. The table below
highlights the valid Ethernet interface combinations:
Note: Port 2 and Port 3 can not be used to receive data simultaneously, they are mutually exclusive for packet
reception. They may both be used for packet transmis sion if required.
The ZL50110/11/12/14 will not take action when receiving a PAUSE frame. It will not pause the transmission of
traffic. It is normally not required to stop CESoP traffic because it is generally constant bit rate and time sensitive. If
necessary, the limiting of egress non-CESoP traffic may be done external to the ZL50110/11/12/14 (e.g. in an
Ethernet switch).
Table 8 maps the signal pins used in the MII interface to those used in the GMII and TBI interface. Table 9 shows
MII Management Interface Package Ball Definition. Table 10, Table 11, Table 12, and Table 13 show respectively
the MII Port 0, Port 1, Port 2 and Port 3 Interface Package Ball Definition.
All Packet Interface signals are 5 V tolerant, and all outputs are high impedance while System Reset is LOW.
MII Port 0 MII Port 1 MII Port 2* MII Port 3**
GE GE*** -- --
GE -- FE --
GE -- -- FE
FE FE -- --
FE FE FE --
FE FE -- FE
Note 1: *ZL50111/112 only
Note 2: ** ZL50 111 only
Note 3: *** Sta ndby only
MII GMII TBI (PCS)
Mn_LINKUP_LED Mn_LINKUP_LED Mn_LINKUP_LED
Mn_ACTIVE_LED Mn_ACTIVE_LED Mn_ACTIVE_LED
-Mn_GIGABIT_LED Mn_GIGABIT_LED
-Mn_REFCLK Mn_REFCLK
Mn_RXCLK Mn_RXCLK Mn_RBC0
Table 8 - Packet Interface Signal M apping - MII to GMII/TBI
ZL50110/11/12/14 Data Sheet
34
Zarlink Semiconductor Inc.
Note: Mn can be either M0, M1, M2, or M3 for ZL50111 and ZL50112 variants; and M0 or M1 for ZL50110 variant.
Mn_COL Mn_COL Mn_RBC1
Mn_RXD[3:0] Mn_RXD[7:0] Mn_RXD[7:0]
Mn_RXDV Mn_RXDV Mn_RXD[8]
Mn_RXER Mn_RXER Mn_RXD[9]
Mn_CRS Mn_CRS Mn_Signal_Detect
Mn_TXCLK - -
Mn_TXD[3:0] Mn_TXD[7:0] Mn_TXD[7:0]
Mn_TXEN Mn_TXEN Mn_TXD[8]
Mn_TXER Mn_TXER Mn_TXD[9]
-Mn_GTX_CLK Mn_GTX_CLK
Signal I/O Package Balls Description
M_MDC O H23 MII management data clock . Common for all
four MII ports. It has a minimum period of
400 ns (maximum freq. 2.5 MHz), and is
independent of the TXCLK and RXCLK.
M_MDIO ID/
OT G26 MII management data I/O. Common for all
four MII ports at up to 2.5 MHz. It is
bi-directional between the ZL501 10/1 1/12/14
and the Ethernet st ation management entity.
Data is passed synchronously with respect
to M_MDC.
Table 9 - MII Manage ment Interface Package B all Defin ition
MII GMII TBI (PCS)
Table 8 - Packet Interface Signal M apping - MII to GMII/TBI
ZL50110/11/12/14 Data Sheet
35
Zarlink Semiconductor Inc.
MII Port 0
Signal I /O Package Balls Description
M0_LINKUP_LED O G24 on ZL50110/4
AB23 on ZL50111/2 LED drive for M A C 0 to indicate port is
linked up.
Logic 0 output = LED on
Logic 1 output = LED off
M0_ACTIV E _ L E D O AC26 LED drive for M A C 0 to in dicate port is
transmitting or receiving packet data.
Logic 0 output = LED on
Logic 1 output = LED off
M0_GIGABIT_LED O H22 LED drive for MAC 0 to in dicate operation at
Gbps
Logic 0 output = LED on
Logic 1 output = LED off
M0_REFCLK I D AA24 GMII/TBI - Reference Clock input at
125 MHz. Can be used to lock receive
circuitry (RX) to M0_GTXCLK rather than
recovering the RXCLK (or RBC0 and
RBC1). Useful, for example, in th e absen ce
of valid serial data.
NOTE: In MII mode this pin must be driven
with the same clock as M0_RXCLK.
M0_RXCLK I U AB22 GMII/MII - M0_RXCLK.
Accepts the following frequencies:
25.0 MHz MII 100 Mbps
125.0 MHz GMII 1 Gbps
M0_RBC0 I U Y24 TBI - M0_RBC0.
Used as a clock when in TBI mod e. Accepts
62.5 MHz, and is 180° out of phase with
M0_RBC1 . Receive data is clocked at
each rising edge of M1_RBC1 and
M1_RBC0, resulting in 125 MHz sample
rate.
M0_RBC1 I U AA25 TBI - M0_RBC1
Used as a clock when in TBI mod e. Accepts
62.5 MHz, and is 180° out of phase with
M0_RBC0 . Receive data is clocked at
each rising edge of M0_RBC1 and
M0_RBC0, resulting in 125 MHz sample
rate.
Table 10 - MII Port 0 Interface Package Ba ll Definition
ZL50110/11/12/14 Data Sheet
36
Zarlink Semiconductor Inc.
M0_COL I D Y25 GMII/MII - M0_COL.
Collision Detection. This signal is
independent of M0_TXCLK and
M0_RXCLK, and is asserted when a
collision is det e cted on an atte m p te d
transmission. It is active high, and only
specified for half-duplex operation.
M0_RXD[7:0] I U [7] W25 [3] W26
[6] W24 [2] U22
[5] U23 [1] Y26
[4] V24 [0] AA26
Receive Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on risin g
edge of M0_RXCLK (GMII/MII) or the rising
edges of M0_RBC0 and M0_RBC1 (TBI).
M0_RXDV /
M0_RXD[8] I D V25 GMII/MII - M0_RXDV
Receive Data Valid. Active high. This
signal is clocked on the rising edge of
M0_RXCLK. It is asserted when valid data
is on the M0_RXD bus.
TBI - M0_RXD[8]
Receive Data. Clocked on the rising edges
of M0_RBC0 and M0_RBC1.
M0_RXER /
M0_RXD[9] I D V26 GMII/MII - M0_RXER
Receive Error. Active high signal indicating
an error has been detected. Normally valid
when M0_RXDV is asserted. Can be used
in conjunction with M0_RXD when
M0_RXDV signal is de-asserted to indicate
a False Carrier.
TBI - M0_RXD[9]
Receive Data. Clocked on the rising edges
of M0_RBC0 and M0_RBC1.
M0_CRS /
M0_Signal_Detect I D U25 GMII/MII - M0_CRS
Carrier Sense. This asynchro nous signal is
asserted when either the transmission or
reception device is non-idle. It is active
high.
TBI - M0_Sig nal Detect
Similar function to M0_CRS.
M0_TXCLK I U U24 MII only - Transmit Clock
Accepts the following frequencies:
25.0 MHz MII 100 Mbps
M0_TXD[7:0] O [7] V21 [3] AA23
[6] W23 [2] W21
[5] W22 [1] Y22
[4] Y23 [0] AA22
Transmit Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on risin g
edge of M0_TXCLK (MII) or the rising edge
of M0_GTXCLK (GMII/TBI).
MII Port 0
Signal I /O Package Balls Description
Table 10 - MII Port 0 Interface Package B all Definition (continued)
ZL50110/11/12/14 Data Sheet
37
Zarlink Semiconductor Inc.
M0_TXEN /
M0_TXD[8] O V23 GMII/MII - M0_TXEN
Transmit Enable. Asserted when the MAC
has data to transmit, synchronously to
M0_TXCLK with the first pre-amble of the
packet to be sent. Remains asserted until
the end of the packet transmiss ion. Active
high.
TBI - M0_TXD[8]
Transmit Data. Clocked on rising edge of
M0_GTXCLK.
M0_TXER /
M0_TXD[9] O V22 GMII/MII - M0_TXER
Transmit Error. Transmitted synchronously
with respect to M0_TXCLK, and active high.
When asserted (with M0_TXEN also
asserted) the ZL50110/11/12/14 will
transmit a non-valid symbol, somewhere in
the transmitted frame.
TBI - M0_TXD[9]
Transmit Data. Clocked on rising edge of
M0_GTXCLK.
M0_GTX_CLK O U21 GMII/TBI only - Gigabit Transmit Clock
Output of a clock for Gigabit operation at
125 MHz.
MII Port 0
Signal I /O Package Balls Description
Table 10 - MII Port 0 Interface Package B all Definition (continued)
ZL50110/11/12/14 Data Sheet
38
Zarlink Semiconductor Inc.
MII Port 1
Signal I/O Package Balls Description
M1_LINKUP_LED O G23 on ZL50110/4
F26 on ZL50111/2 LED drive for MAC 1 to indicate port is link ed
up.
Logic 0 output = LED on
Logic 1 output = LED off
M1_ACTIVE_LED O AB25 LED drive for MAC 1 to indicate port is
transmitting or receiving packet data.
Logic 0 output = LED on
Logic 1 output = LED off
M1_GIGABIT_LED O G25 LED drive for MAC 1 to indicate operation at
Gbps.
Logic 0 output = LED on
Logic 1 output = LED off
M1_REFCLK I D M22 GMII/TBI - Reference Clock input at
125 MHz. Can be used to lock receive
circuitry (RX) to M1_GTXCLK rather than
recovering the RXCLK (or RBC0 and
RBC1). Useful, for example, in the absence
of valid serial data.
NOTE: In MII mode this pin must be driven
with the same clock as M1_RXCLK.
M1_RXCLK I U M23 GMII/MII - M1_RXCLK.
Accepts the following frequencies:
25.0 MHz MII 100 Mbps
125.0 MHz GMII 1 Gbps
M1_RBC0 I U U26 TBI - M1_RBC0.
Used as a clock when in TBI mode. Accept s
62.5 MHz and is 180°C out of phase with
M1_RBC1. Receive dat a is clocked at
each rising edge of M1_RBC1 and
M1_RBC0, resulting in 125 MHz sample
rate.
M1_RBC1 I U T25 TBI - M1_RBC1
Used as a clock when in TBI mode. Accept s
62.5 MHz, and is 180° out of phase with
M1_RBC0. Receive data is clocked at each
rising edge of M1_RBC1 and M1_RBC0,
resulting in 125 MHz sample rate.
M1_COL I D R25 GMII/MII - M1_COL.
Collision Detection. This signal is
independent of M1_TXCLK and
M1_RXCLK, and is asserted when a
collision is detected on an attemp ted
transmission. It is active high, and only
specified for half-duplex operation.
Table 11 - MII Port 1 Interface Package Ball Definition
ZL50110/11/12/14 Data Sheet
39
Zarlink Semiconductor Inc.
M1_RXD[7:0] I U [7] M25 [3] N25
[6] P26 [2] N24
[5] M24 [1] R26
[4] P25 [0] T26
Receive Data. Only half the bus (bits [3:0] )
are used in MII mode. Clocked on rising
edge of M1_RXCLK (GMII/MII) or the rising
edges of M1_RBC0 and M1_RBC1 (TBI).
M1_RXDV /
M1_RXD[8] I D M26 GMII/MII - M1_RXDV
Receive Dat a V a lid. Active high. This s ignal
is clocked on the rising edge of M1_ RXCLK.
It is asserted when valid data is on the
M1_RXD bus.
TBI - M1_RXD[8]
Receive Data. Clocked on the rising edges
of M1_RBC0 and M1_RBC1.
M1_RXER /
M1_RXD[9] I D L21 GMII/MII - M1_RXER
Receive Error. Active high signal indicating
an error has been detected. Normally valid
when M1_RXDV is asserted. Can be used
in conjunction with M1_RXD when
M1_RXDV signal is de-asserted to indicate
a False Carrier.
TBI - M1_RXD[9]
Receive Data. Clocked on the rising edges
of M1_RBC0 and M1_RBC1.
M1_CRS /
M1_Signal_Detect I D L23 G MII/ MII - M1_CRS
Carrier Sense. This asynchronous signal is
asserted when either the transmission or
reception device is non-idle. It is ac tive high.
TBI - M1_Signal Detect
Similar function to M1_CRS.
M1_TXCLK I U L22 MII only - Transmit Clock
Accepts the following frequencies:
25.0 MHz MII 100 Mbps
M1_TXD[7:0] O [7] R24 [3] R22
[6] P22 [2] P21
[5] R23 [1] T22
[4] T23 [0] R21
Transmit Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on rising
edge of M1_TXCLK (MII) or the rising edge
of M1_GTXCLK (GMII/TBI).
M1_TXEN /
M1_TXD[8] O P23 GMII/MII - M1_TXEN
Transmit Enable. Asserted when the MAC
has data to transmit, synchronously to
M1_TXCLK with the first pre-amble of the
packet to be sent. Remains asserted until
the end of the packet transmission. Active
high.
TBI - M1_TXD[8]
Transmit Data. Clocked on rising edge of
M1_GTXCLK.
MII Port 1
Signal I/O Package Balls Description
Table 11 - MII Port 1 Interface Package Ball De finition (contin ued)
ZL50110/11/12/14 Data Sheet
40
Zarlink Semiconductor Inc.
M1_TXER /
M1_TXD[9] O N23 GMII/MII - M1_TXER
Transmit Error. Transmitted synchronously
with respect to M1_TXCLK, and active high.
When asserted (with M1_TXEN also
asserted) the ZL50110/11/12/14 will transmit
a non-valid symbol, somewhere in the
transmitted frame.
TBI - M1_TXD[9]
Transmit Data. Clocked on rising edge of
M1_GTXCLK.
M1_GTX_CLK O N21 GMII/TBI only - Gigabit Transmit Clock
Output of a clock for Gigabit operation at
125 MHz.
MII Port 2 - ZL50111 and ZL50112 variants only.
Note: This port must not be used to receive data at the same time as port 3,
they are mutually exclusive.
Signal I /O Package Balls Description
M2_LINKU P _ L E D O G23 LED drive for MAC 2 to indicate port is
linked up.
Logic 0 output = LED on
Logic 1 output = LED off
M2_ACTIV E _ L E D O AB24 LED drive fo r M A C 2 to indicate port i s
transmitting or receiving packet data.
Logic 0 output = LED on
Logic 1 output = LED off
M2_RXCLK I U AA19 MII only - Receive Clock.
Accepts the following frequencies:
25.0 MHz MII 100 Mbps
M2_COL I D AE26 Collision Detection. This signal is
independent of M2_TXCLK and
M2_RXCLK, and is asserted when a
collision is det e cted on an atte m p te d
transmission. It is active high, and only
specified for half-duplex operation.
M2_RXD[3:0] I U [3] AD25 [1] AB21
[2] AC23 [0] AD24 Receive Data. Clocked on rising edge of
M2_RXCLK.
M2_RXDV I D AA20 Receive Dat a Valid. Active high. This signal
is clocked on the rising edge of M2_RXCLK.
It is asserted when valid data is on the
M2_RXD bus.
Table 12 - MII Port 2 Interface Package Ball D efinition
MII Port 1
Signal I/O Package Balls Description
Table 11 - MII Port 1 Interface Package Ball De finition (contin ued)
ZL50110/11/12/14 Data Sheet
41
Zarlink Semiconductor Inc.
M2_RXER I D AC24 Receive Error. Active high signal indicating
an error has been detected. Normally valid
when M2_RXDV is asserted. Can be used
in conjunction with M2_RXD when
M2_RXDV signal is de-asserted to indicate
a False Carrier.
M2_CRS I D AC25 Carrier Sense. This asynchro nous signa l is
asserted when either the transmission or
reception device is non-idle. It is active
high.
M2_TXCLK I U AD26 MII only - Transmit Clock
Accepts the following frequencies:
25.0 MHz MII 100 Mbps
M2_TXD[3:0] O [3] AE25 [1] AC21
[2] AD23 [0] AE24 Transmit Data. Clocked on rising edge of
M2_TXCLK.
M2_TXEN O AC22 Transmit Enable. Asserted when the MAC
has data to transmit, synchronously to
M2_TXCLK with the first pre-amble of the
packet to be sent. Remains asserted until
the end of the packet transmiss ion. Active
high.
M2_TXER O AB20 Transmit Error. Transmitted synchronously
with respect to M2_TXCLK, and active h igh.
When asserted (with M2_TXEN also
asserted) the ZL50110/12 will transmit a
non-valid symbol, somewhere in the
transmitted frame.
MII Port 3 - ZL50111 variant only
Note: This port must not be used to receive data at the same time as port 2,
they are mutually exclusive.
Signal I /O Package Balls Description
M3_LINKU P _ L E D O G24 LED drive for MAC 3 to indicate port is
linked up.
Logic 0 output = LED on
Logic 1 output = LED off
M3_ACTIV E _ L E D O AB26 LED drive fo r M A C 3 to indicate port i s
transmitting or receiving packet data.
Logic 0 output = LED on
Logic 1 output = LED off
Table 13 - MII Port 3 Interface Package Ball D efinition
MII Port 2 - ZL50111 and ZL50112 variants only.
Note: This port must not be used to receive data at the same time as port 3,
they are mutually exclusive.
Signal I /O Package Balls Description
Table 12 - MII Port 2 Interface Package Ball Definition (continued)
ZL50110/11/12/14 Data Sheet
42
Zarlink Semiconductor Inc.
M3_RXCLK I U K26 MII only - Receive Clock.
Accepts the following frequencies:
25.0 MHz MII 100 Mbps
M3_COL I D J26 Collision Detection. This signal is
independent of M3_TXCLK and
M3_RXCLK, and is asserted when a
collision is det e cted on an atte m p te d
transmission. It is active high, and only
specified for half-duplex operation.
M3_RXD[3:0] I U [3] J22 [1] J24
[2] J23 [0] J25 Receive Data. Clocked on rising edge of
M3_RXCLK.
M3_RXDV I D J21 Receive Dat a Valid. Active high. This signal
is clocked on the rising edge of M3_RXCLK.
It is asserted when valid data is on the
M3_RXD bus.
M3_RXER I D H26 Receive Error. Active high signal indicating
an error has been detected. Normally valid
when M3_RXDV is asserted. Can be used
in conjunction with M3_RXD when
M3_RXDV signal is de-asserted to indicate
a False Carrier.
M3_CRS I D H24 Carrier Sense. This asynchronous signa l is
asserted when either the transmission or
reception device is non-idle. It is active
high.
M3_TXCLK I U H25 MII only - Transmit Clock
Accepts the following frequencies:
25.0 MHz MII 100 Mbps
M3_TXD[3:0] O [3] K23 [1] L25
[2] L26 [0] L24 Transmit Data. Clock ed on rising edge of
M3_TXCLK.
M3_TXEN O K24 Transmit Enable. Asserted when the MAC
has data to transmit, synchronously to
M3_TXCLK with the first pre-amble of the
packet to be sent. Remains asserted until
the end of the packet transmiss ion. Active
high.
M3_TXER O K25 Transmit Error. Tr ansmitted synchronously
with respect to M3_TXCLK, and active h igh.
When asserted (with M3_TXEN also
asserted) the ZL50111 will transmit a
non-valid symbol, somewhere in the
transmitted frame.
MII Port 3 - ZL50111 variant only
Note: This port must not be used to receive data at the same time as port 2,
they are mutually exclusive.
Signal I /O Package Balls Description
Table 13 - MII Port 3 Interface Package Ball Definition (continued)
ZL50110/11/12/14 Data Sheet
43
Zarlink Semiconductor Inc.
3.4 External Memory Interf ace
All External Memory Interface output s are high impedance while System Reset is LOW.
If the External Memory Interface is unused, all input pins may be left unconnected.
Active low signals are designated by a # suffix, in accordance with the convention used in common memory data
sheets.
Signal I/O Package Balls Description
RAM_DATA[63:0] IU/
OT [63] AD7 [31] K3
[62] AE6 [30] K4
[61] AF5 [29] J1
[60] AB8 [28] J2
[59] AC7 [27] J3
[58] AD6 [26] J4
[57] AE5 [25] H1
[56] AF4 [24] H2
[55] AF3 [23] H3
[54] AE4 [22] J5
[53] AD5 [21] G1
[52] AA8 [20] J6
[51] AB7 [19] H4
[50] AF2 [18] G2
[49] AC6 [17] H5
[48] AE3 [16] G3
[47] AD4 [15] F1
[46] AC5 [14] G4
[45] AA7 [13] F2
[44] AB6 [12] F3
[43] AB5 [11] G5
[42] AC4 [10] E1
[41] AD3 [9] E2
[40] AE2 [8] G6
[39] AA5 [7] F5
[38] AB4 [6] F4
[37] AC3 [5] E3
[36] AD2 [4] E4
[35 AE1 [3] D1
[34] AD1 [2] E5
[33] W6 [1] D2
[32] Y5 [0] D4
Buffer memory data. Synchronous to rising
edge of SYSTEM_CLK.
RAM_PARITY[7:0] IU/
OT [7] L1 [3] L5
[6] L2 [2] L6
[5] L3 [1] K1
[4] L4 [0] K2
Buffer memory parity. Synchronous to rising
edge of SYSTEM_CLK. Bit [7] is parity for
data byte [63:5 6], bit [0] is parity for data
byte [7:0].
Table 14 - External Memory Interface Packag e Ball Definition
ZL50110/11/12/14 Data Sheet
44
Zarlink Semiconductor Inc.
RAM_ADDR[19:0] O [19] R4 [9] P1
[18] T2 [8] N4
[17] T1 [7] N3
[16] P5 [6] N2
[15] R3 [5] M1
[14] R2 [4] M2
[13] P4 [3] M4
[12] R1 [2] M3
[11] P3 [1] M6
[10] P2 [0] M5
Buffer memory address output.
Synchronous to risi ng edge of
SYSTEM_CLK.
RAM_BW_A# O U2 Synchronous Byte Write Enable A (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[7:0].
RAM_BW_B# O T3 Synchronous Byte Write Enable B (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[15:8].
RAM_BW_C# O U3 Synchronous Byte Write Enable C (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[23:16].
RAM_BW_D# O V2 Synchronous Byte Write Enable D (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[31:24].
RAM_BW_E# O W1 Synchronous Byte Write Enable E (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[39:32].
RAM_BW_F# O V3 Synchronous Byte Write Enable F (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[47:40].
RAM_BW_G# O W2 Synchronous Byte Write Enable G (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[55:48].
RAM_BW_H# O Y1 Synchronous Byte Write Enable H (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[63:56].
RAM_RW# O U4 Read/Write Enable output
Read = high
Write = low
Signal I/O Package Balls Description
Table 14 - External Memory Interface Packa ge Ball Definition (continu ed)
ZL50110/11/12/14 Data Sheet
45
Zarlink Semiconductor Inc.
3.5 CPU Interface
All CPU Interface signals are 5 V tolerant.
All CPU Interface outputs are high impedance while System Reset is LOW.
Signal I/O Package Balls Description
CPU_DATA[31:0] I/
OT [31] AF25 [15] AA16
[30] AB19 [14] AD19
[29] AD22 [13] AE20
[28] AE23 [12] AB17
[27] AC20 [11] AF21
[26] AF24 [10] AC17
[25] AE22 [9] AE19
[24] AD21 [8] AA15
[23] AA17 [7] AB16
[22] AB18 [6] AD18
[21] AC19 [5] AF19
[20] AD20 [4] AE18
[19] AF23 [3] AD17
[18] AE21 [2] AF20
[17] AF22 [1] AB15
[16] AC18 [0] AF18
CPU Data Bus. Bi-directional data bus,
synchronously transmitted with
CPU_CLK rising edge.
NOTE: as with all ports in the
ZL50110/11/12/14 device,
CPU_DATA[0] is the least significant bit
(lsb).
CPU_ADDR[23:2] I [23] AB13 [11] AD11
[22] AC13 [10] AF10
[21] AD13 [9] AC11
[20] AE13 [8] AE10
[19] AF12 [7] AD10
[18] AE12 [6] AB11
[17] AD12 [5] AF9
[16] AC12 [4] AC10
[15] AF11 [3] AE9
[14] AB12 [2] AA11
[13] AE11
[12] AA12
CPU Address Bus. Address input from
processor to ZL50110/11/12/14,
synchronously transmitted with
CPU_CLK rising edge.
NOTE: as with all ports in the
ZL50110/11/12/14 device,
CPU_ADDR[2] is the least significant bit
(lsb).
CPU_CS I U AF14 CPU Chip Select. Sync hronous to rising
edge of CPU_CLK and active low. Is
asserted with CPU_TS_ALE. Must be
asserted with CPU_OE to
asynchronously enable the CPU_DATA
output during a read, including DMA
read.
CPU_WE I AD14 CPU Write Enable. Synchronously
asserted with respect to CPU_CLK
rising edge, and active low. Used for
CPU writes from the processor to
registers within the ZL50110/11/12/14.
Asserted one clock cycle after
CPU_TS_ALE.
Table 15 - CPU Interface Package Ball Definition
ZL50110/11/12/14 Data Sheet
46
Zarlink Semiconductor Inc.
CPU_OE I AE14 CPU Output Enable.
Synchronously asserted with respect to
CPU_CLK rising edge, and active low.
Used for CPU reads from the processor
to registers within the ZL501 10/11/12/14.
Asserted one clock cycle after
CPU_TS_ALE. Must be asserted with
CPU_CS to asynchronously enable the
CPU_DATA output during a read,
including DMA read.
CPU_TS_ALE I AE15 Synchronous input with rising edge of
CPU_CLK.
Latch Enable (ALE), active high signal.
Asserted with CPU_CS, for a single
clock cycle.
CPU_SDACK1 I AF15 CPU/DMA 1 Acknowledge Input. Active
low synchronous to CPU_CLK rising
edge. Used to acknowledge request
from ZL50110/11/12/14 for a DMA write
transaction. Only used for DMA
transfers, not for normal register access.
CPU_SDACK2 I AD15 CPU/DMA 2 Acknowledge Input Active
low synchronous to CPU_CLK rising
edge. Used to acknowledge request
from ZL50110/11/12/14 for a DMA read
transaction. Only used for DMA
transfers, not for normal register access.
CPU_CLK I AC14 CPU PowerQUICC™ II Bus Interface
clock input. 66 MHz clock, with minimum
of 6 ns high/low time. Use d to tim e all
host interface signals into and out of
ZL50110/11/12/14 device.
Signal I/O Package Balls Description
Table 15 - CPU Interface Package Ball Definition (continue d)
ZL50110/11/12/14 Data Sheet
47
Zarlink Semiconductor Inc.
CPU_TA OT AB14 CPU Transfer Acknowledge. Driven from
tri-state condition on the negative clock
edge of CPU_CLK following the
assertion of CPU_CS. Active low,
asserted from the rising edge of
CPU_CLK. For a read, asserted when
valid data is available at CPU_DATA.
The data is then read by the host on the
following rising edge of CPU_CLK. For a
write, is asserted when the
ZL50110/11/12/14 is ready to accept
data from the host. The data is written
on the rising edge of CPU_CLK
following the assertion. Returns to
tri-state from the negative clock edge of
CPU_CLK following the de-assertion of
CPU_CS.
CPU_DREQ0 OT AC15 CPU DMA 0 Request Output Active low
synchronous to CPU_CLK rising edge.
Asserted by ZL50110/11/12/14 to
request the host initiates a DMA write.
Only used for DMA transfers, not for
normal register access.
CPU_DREQ1 OT AE16 CPU DMA 1 Request
Active low synchronous to CPU_CLK
rising edge. Asserted by
ZL50110/11/12/14 to indicate packet
data is ready for transmission to the
CPU, and request the host initiates a
DMA read. Only used for DMA transfers,
not for normal register access.
CPU_IREQO O AF17 CPU Interrupt 0 Request (Active Low)
CPU_IREQ1 O AD16 CPU Interrupt 1 Request (Active Low)
Signal I/O Package Balls Description
Table 15 - CPU Interface Package Ball Definition (continue d)
ZL50110/11/12/14 Data Sheet
48
Zarlink Semiconductor Inc.
3.6 System Function Inte rface
All System Function Interface signals are 5 V tolerant.
The core of the chip will be held in reset for 16383 SYSTEM_CLK cycles after SYSTEM_RST has gone HIGH to
allow the PLL’s to lock. No chip access should occur at this time.
Signal I/O Package Balls Description
SYSTEM_CLK I U6 System Clock Input. The system clock
frequency is 100 MHz. The quality of
SYSTEM_CLK, or the oscillator that
drives SYSTEM_CLK directly impacts
the adaptive clock recovery
performance. See Section 6.3.
SYSTEM_RST I V4 System Reset Input. Active low. The
system reset is asynchronous, and
causes all registers within the
ZL50110/11/12/14 to be reset to their
default state. Recommend external
pull-up.
SYSTEM_DEBUG I U5 System Debug Enable. This is an
asynchronous signal that, when
de-asserted, prevents the software
assertion of the debug-freeze comman d,
regardless of the internal state of
registers, or any error conditions. Active
high. Recommend external pull-down.
Table 16 - System Function Interface Packag e Ball Definition
ZL50110/11/12/14 Data Sheet
49
Zarlink Semiconductor Inc.
3.7 Test Fa cilities
3.7.1 Administration, Control and Test Interface
All Administration, Control and Test Interface signals are 5 V tolerant.
3.7.2 JTA G Interface
All JTAG Interface signals are 5 V tolerant, and conform to the requirements of IE EE1149.1 (2001).
The ZL50111 and ZL50112 share a common JTAG ID. They also share a common CHIP_ID register value.
Signal I/O Package Balls Description
GPIO[15:0] ID/
OT [15] AA4 [7] AA2
[14] AB3 [6] Y3
[13] AC2 [5] AB1
[12] AC1 [4] Y2
[11] AB2 [3] W4
[10] Y4 [2] V5
[9] W5 [1] AA1
[8] AA3 [0] W3
General Purpose I/O pins. Connected to an
internal register, so customer can set
user-defined parameters. Bits [4:0] reserved
at startup or reset for memory Tapped Delay
Line (TDL) setup. See the ZL501 10/11/12/14
Programmers Model for more details.
Recommend 5 kohm pulldown on these
signals.
TEST_MODE[2:0] I D [2] AF6
[1] AB9
[0] AC8
Test Mode input - ensure these pins are tied
to ground for normal operat ion.
000 SYS_NORMAL_MODE
001-010 RESERVED
011 SYS_TRISTATE_MODE
100-111 RESERVED
Table 17 - Administration/Control Inte rface Package Ball Definition
Signal I/O Package Balls Description
JTAG_TRST I U AE7 JT AG Reset. Async hronous reset. In normal
operation this pin should be pulled low.
Recommend external pull-down.
JTAG_TCK I AD8 JTAG Clock - maximum frequency is
25 MHz, typically run at 10 MHz. In normal
operation this pin should be pulled either
high or low. Recommend external pull-do wn.
JTAG_TMS I U AA10 JTAG test mode select. Synchronous to
JTAG_TCK rising edge. Used by the Test
Access Port controller to set certain test
modes.
JTAG_TDI I U AF7 JTAG test data input. Synchronous to
JTAG_TCK.
JTAG_TDO O AC9 JTAG test data output. Synchronous to
JTAG_TCK.
Table 18 - JTAG Interfac e Package Ba ll Definition
ZL50110/11/12/14 Data Sheet
50
Zarlink Semiconductor Inc.
3.8 Miscellaneous Inputs
3.9 Power and Ground Connections
Signal Package Balls Description
IC_GND AD9, AF8, R5, T4, AE8 Internally Connected. Tie to GND.
IC_VDD_IO AF16 Internally Connected. Tie to VDD_IO.
Table 19 - Miscellaneous Inputs Package Ball Definitions
Signal Package Balls Description
VDD_IO J9 J10 J11 J12
J13 J14 J15 J16
J17 J18 K9 K18
L9 L18 M9 M18
N9 N18 P9 P18
R9 R18 T9 T18
U9 U18 V9 V10
V11 V12 V13 V14
V15 V16 V17 V18
3.3 V VDD Power Supply for IO Ring
GND A1 A13 A26 E22
F6 F21 K5 K22
L11 L12 L13 L14
L15 L16 M11 M12
M13 M14 M15 M16
N1 N5 N11 N12
N13 N14 N15 N16
N22 N26 P6 P11
P12 P13 P14 P15
P16 P24 R11 R12
R13 R14 R15 R16
T5 T11 T12 T13
T14 T15 T16 T24
AA6 AA21 AB10 AF1
AF13 AF26
0 V Ground Supply
VDD_CORE F7 F12 F15
F20 H6 H21
K6 K21 M21
N6 T21 V6
Y6 Y21 AA9
AA13 AA14 AA18
1.8 V VDD Power Supply for Core
Region
A1VDD T6 1.8 V PLL Power Supply
Table 20 - Power and Grou nd Package Ball Definitio n
ZL50110/11/12/14 Data Sheet
51
Zarlink Semiconductor Inc.
3.10 ZL50111, ZL50112, ZL 50110 and ZA50114 Internal Connection s
3.11 Z L50112 Intern al Connec tions
3.12 ZL50112 Au xiliary Clocks
4.0 Typical Applications
4.1 Leased Line Provision
Circuit emulation is typically used to support the provision of leased line services to customers using legacy TDM
equipment. For example, Figure 6 shows a leased line TDM service being carried across a packet network. The
advantages are that a carrier can upgrade to a packet switched network, whilst still maintaining their existing TDM
business.
Signal Package Balls Description
IC R6, AC16, AE17 Internally Connected. Must leave open
circuit.
Table 21 - No Connection Ball D efinition
Signal Package Balls Description
IC G21, F25, E26. G22 Internally Connected. Must leave open
circuit.
Table 22 - No Connection Ball D efinition
Signal Package Balls Description
AUX2_CLKo[1:0] C17, C15 Auxiliary clock output. Typically
AUX2_CLKo[1] is connected to
AUX2_CLKi[1] and AUX2_CLKo[0] is
connected to AUX2_CLKi[0] through a
zero ohm resistor.
AUX2_CLKi[1:0] E15, D15 Auxiliary clock input. Typically
AUX2_CLKi[1] is connected to
AUX2_CLKo[1] and AUX2_CLKi[0] is
connected to AUX2_CLKo[0] through a
zero ohm resistor.
AUX1_CLKo[1:0] D16, A18 Auxiliary clock output. Typically
AUX1_CLKo[1] is connected to
AUX1_CLKi[1] and AUX1_CLKo[0] is
connected to AUX1_CLKi[0]
AUX1_CLKi[1:0] E16, B18 Auxiliary clock input. Typically
AUX1_CLKi[1] is connected to
AUX1_CLKo[1] and AUX1_CLKi[0] is
connected to AUX1_CLKo[0]
Table 23 - Auxiliary clock Ball Definition
ZL50110/11/12/14 Data Sheet
52
Zarlink Semiconductor Inc.
The ZL50110/11/12/14 is capable of handling circuit emulation of both structured T1, E1, and J2 links (e.g., for
support of fractional circuits) and unstructured (or clear channel) T1, E1, J2, T3 and E3 links. The device handles
the data-plane requirements of the provider edge inter-working function (with the exception of the physical
interfaces and line interface units). Control plane functions are forwarded to the host processor controlling the
ZL50110/11/12/14 device.
The ZL50110/11/12/14 provides a per-stream clock recovery function, in unstructured mode, to reproduce the TDM
service frequency at the egress of the packet network. This is required otherwise the queue at the egress of the
packet network will either fill up or empty, depending on whether the regenerated clock is slower or faster than the
original.
Figure 6 - Leased Line Services Over a Circuit Emulation Link
4.2 Metropolitan Area Netwo rk Aggregation
The metro Ethernet application, shown in Figure 7, consists of the metro Ethernet service modules sitting on the
edge of the Metro Ethernet ring. The modules will connect Eth ernet circuits and TDM circuits to the metro ring.
The ZL50110/11/12/14 is used to emulate leased line TDM circuits over Ethernet by establishing CESoP
connections over the Metro Ethernet ring between the MTUs/MDUs and the PSTN. The use of CESoP eliminates
the need for a separate TDM network in the metro core, thereby enabling convergence on a unified Ethernet
network.
Figure 7 - Metropolitan Area Network Aggregation using CESoP
Carrier Network Customer
Premises
Customer
Premises
Extract
Clock
Customer data
~
~
fservice
fservice
TDM
Packet
Network
TDM
Customer data
TDM to
packet
fservice
Provider Edge
Interworking
Function
Provider Edge
Interworking
Function
queue
Metro
Core
Metropolitan
Access Network
(Resilient Packet Ring or
Metro Ethernet)
Multi-Tenant
Units
T1/E1
Links
Campus
CESoP
OC-3, DS3
CESoP
Metro
Access
Metro
Access
T1/E1
Links
ZL50110/11/12/14 Data Sheet
53
Zarlink Semiconductor Inc.
4.3 Digital Loop Carrier
The Broadband Digit al Loop Carrier (BBDLC) application, s hown in F igure 8, consis t s of a B BDLC conn ected to the
Central Office (CO) by a dedicated fiber link running Gigabit Ethernet (GE) rather than by NxT1/E1 or DS3/E3.
The ZL50110/11/12/14 is used to emulate TDM circuits over Ethernet by establishing CESoP connections between
the BBDLC and the CO. At the CO the native IP or Ethernet traffic is split from the CESoP connections at sent
towards the packet network. Multiple T1/E1 CESoP connections from several BBDLC are aggregated in the CO
using a larger ZL50110/11/12/14 variant, converted back to TDM circuits, and connected to a class 5 switch
destined toward s the PSTN.
In this configuration T3/E3 services can also be provided. Using CESoP allows voice and data traffic to be
converged onto a single link.
Figure 8 - Digital Loop Carrier using CESoP
Dedicated
Fiber Links Central
Office
T1/E1
N x T1/E1 PSTN
IP
Broadband
DLC
POTS
Digital
Loop
Carrier
GIGE Over
Fiber
Central Office
Switch (Class 5)
IP Edge Router or
Multi-Service
Switching Platform
N x GIGE
GIGE Over
Fiber
CESoP
ZL50110/11/12/14 Data Sheet
54
Zarlink Semiconductor Inc.
4.4 Remote Concentrator
The remote concentrator application, shown in Figure 9, consists of a remote concentrators connected to the
Central Office (CO) by a dedicated fiber link running Gigabit Ethernet (GE) or Ethernet over SONET (EoS) rather
than by NxT1/E1 or DS3/E3. The remote concentrators provide both TDM service and native Ethernet service to
the MTU/MDU.
The ZL50110/11/12/14 is used to emulate TDM circuits over Ethernet by establishing CESoP connections between
the remote concentrator and the CO. The native IP or Ethernet traffic is multiplexed with the CESoP traffic inside
the remote concentrator and sent across the same GE connection to the CO. At the CO the native IP or Ethernet
traffic is split from the CESoP connections at sent towards the packet network. Multiple T1/E1 CESoP connections
from several remote concentrators are aggregated in the CO using a larger ZL50110/11/12/14 variant, converted
back to TDM circuit s, a nd conn ected to the P STN through a higher bandwid th T DM circuit such as OC-3 or STM-1.
The use of CESoP here allows the convergence of voice and data on a single access network based on Ethernet.
This convergence on Ethernet, a packet technology, rather than SONET/SDH, a switched circuit technology,
provides cost and operational savings.
Figure 9 - Remote Concentrator using CESoP
Multi-Tenant / Multi-Dwelling Units
Dedicated
Fiber Links
Central
Office
(Aggregation)
Remote
Concentrator
Ethernet
10/100 Mbps
Remote
Concentrator
Ethernet
10/100 Mbps
STM1- 4
Nx GIGE
PSTN
IP
T1/E1
Links
GIGE Over
Fiber
T1/E1
Links
T1/E1
Links
GIGE Over
Fiber
CESoP
ZL50110/11/12/14 Data Sheet
55
Zarlink Semiconductor Inc.
4.5 Cell Site Backhaul
The cell site backhaul application, shown in Figure 10, consists of 2G, 2.5G and 3G base stations, co-located at a
cell site, connected to their respective 2G, 2.5G base station controllers and 3G radio network controller. The
traditional leased T1/E1 lines between the cell site and the base station controllers is now replaced by a packet
network such as fixed wireless or Gigabit Ethernet (GE) fiber, that may be owned by the carrier or accessed
through a service provider.
The ZL50110/11/12/14 would sit in a box either external to the base stations, or integrated in them, and would
transparently carry multiple T1/E1s to the Base Station controllers/Radio Network controllers using CESoP
connections. At the base station controller location another ZL50110/11/12/14 would terminate the CESoP
connection and provide th e T1/E1 line to the controllers.
The use of the ZL50110/11/12/14 would allow for lower cost transport between the two locations, due to the
replacement of the leased T1/E1 line cost. The CESoP connection would allow the T1/E1 to meet the strict timing
requirements for 3G base stations. Each T1/E1 may be asynchronous should a service provider be backhauling
T1/E1s from multiple carriers.
Figure 10 - Cell Site Backhaul using CESoP
DS3/
OC3
Packet
Switched
Network
GIGE
over Fiber
CESoP
3G
Base
Station
2.5G
Base
Station
2G
Base
Station
CESoP
ATM over
T1/E1
ATM over
T1/E1
TDM over
T1/E1
3G
Radio
Network
Controller
2.5G
Base
Station
Controller
ATM over
T1/E1
ATM over
T1/E1
2G
Base
Station
Controller
TDM over
T1/E1
DS3/
OC3
DS3/
OC3
Co-Located
Base Stations
CESoP
ZL50110/11/12/14 Data Sheet
56
Zarlink Semiconductor Inc.
4.6 Equipment Architecture Examp le
An equipment architecture example is shown in F igure 11, supporting T1/E1 ports is shown at the board le vel us ing
Zarlink’s CESoP processors. In this example, the equipment consists of three line cards and an uplink card
connected to a pa cket backplane.
The first line card supports up to 32 T1/E1 lines, containing up to 1024 DS0, for Nx64 kbps structured data transfer
(SDT) CESoP connections. The T1/E1 lines are broken down into DS0 channels on an H.110 bus. The
ZL50110/11/12/14 establishes CESoP connections, with each connection taking a number of DS0 channels from
the H.110 bus.
The third line card support up to 32 T1/E1 or 2 T3/E3 lines for private line unstructured data transfer (UDT) CESoP
connections. The T1/E1 lines are not terminated on the card by are transparently packetized into individual CESoP
connections by the ZL50110/11/12/14.
The second line card s upports mu ltiple 10/100/1000 Mbp s Ethern et ports for native Internet, v ideo and dat a service.
The uplink card multiplexes the Ethernet traffic from the three cards, and uplinks the CESoP, Internet, video and
data traffic to the packet switched network (PSN.)
Figure 11 - Equipment example using CESoP
Unstructured, Asynchronous CES
Unstructured, Asynchronous CES
T3/E3
or T1/E 1
LIU
Up to 32 T1/E1
or 2 T3/E3 Per Port
Clock Recovery
Ethernet
PHYs
Optical
Interface
& Drivers
T3/E3
or T1/E 1
LIU
Structured, Synchronous CES
Structured, Synchronous CES
Octal
T1/E1
Framers
MT9072
H.110 / HMVIP BUS
Up to 32 T1/E1
or 1024 Channel DPLL Output
Up to 32
Streams CESoP
Processor
ZL50111
CESoP
Processor
ZL50111
T1/E1
LIUs
Gigabit
Ethernet
Switch
MVTX2801
T1/E1
LIUs
Ethernet
Concentrator
MVTX2601
MVTX2801
Ethernet
Traffic
Voice
and
Data
Services
2 GE
2 GE
Packet
Switched
Networks
ZL50110/11/12/14 Data Sheet
57
Zarlink Semiconductor Inc.
5.0 Functional Description
The ZL50110/11/12/14 family provides the data-plane processing to enable constant bit rate TDM services to be
carried over a packet switched network, such as an Ethernet, IP or MPLS network. The device segments the TDM
data into user-defined packets, and passes it transparently over the packet network to be reconstructed at the far
end. This has a number of ap plications, including emulation of TDM circuits and packet backplanes for TDM-based
equipment.
Figure 12 - ZL50110/11/12/14 Family Operation
Note: The ZL50110/11/12/14 does not support the transmission or reception of jumbo packets, or packet sizes
larger than 1522 bytes.
5.1 Block Diagram
A diagram of the ZL50110/11/12/14 device is given in Figure 13, which shows the major data flows between
functional components.
Figure 13 - ZL50110/11/12/14 Data and Control Flows
co nsta nt bit r ate
TDM link packet sw itched
network cons tant bit ra te
TDM link
ZL5011x
TDM-Packet
conversion
ZL5011x
TDM-Packet
conversion
TDM
equipment
TDM
equipment
interworking
function interworking
function
Transparent data flow between TDM equipment
Up to 32 T1, 32 E1, 8 J2, 2 T3 or 2 E3 port
H.110, H-MVIP, ST-BUS backplanes
Up to triple 100 Mbps MII F ast Ethernet or
Dual Redundant 1000 Mbps GMII/TBI Gigabit Ethernet
Motorola PowerQUI CC
TM
Compatible
Off-chip Packet Memory
0-8 MBytes SSRAM JTAG Interface
Triple
Packet
Interface
MAC
TDM
Formatter
Payload
Assembly
TDM
Interface
Packet
Receive
Packet
Transmit
Admin.
Clock
Recovery
JT
AG Test
Controller
Central
Task
Manager
Host Interface
DMA
Control
Data Flows
Control Fl ows
Protocol
Engine
Memory Management Unit
On-chip RAM and SSRAM Interface Controller
ZL50110/11/12/14 Data Sheet
58
Zarlink Semiconductor Inc.
5.2 Data and Control Flows
There are numerous combinations that can be implemented to pass data through the ZL50110/11/12/14 device
depending on the application requirements. The Task Manager can be considered the central pivot, through which
all flows must operate.
The flow is determined by the Type field in the Task Message (see ZL50110/11/12/14 Programmers Model).
Each of the 11 data flows uses the Task Manager to route packet information to the next block or interface for
onward transmission. This section describes the flows between the TDM interface, the packet interface and the
Task Manager which are the main flow routes used in the ZL50110/11/12/14 family. For example, the TDM->TM
flow is used in flow types 1, 3, 5, and 6, and the TM->PKT flow is used in flow types 1, 3, and 9.
Flow Number Flow Through Device
1 TDM to (TM) to PE to (TM) to PKT
2 PKT to (TM) to PE to (TM) to TDM
3 TDM to (TM) to PKT
4 PKT to (TM) to TDM
5 TDM to (TM) to CPU
6 TDM to (TM) to PE to (TM) to CPU
7 CPU to (TM) to TDM
8 PKT to (TM) to CPU
9 CPU to (TM) to PKT
101TDM to (TM) to TDM
111
1. This flow is for loopback t est purpo ses only
PKT to (TM) to PKT
Table 24 - Standa rd Device Flo ws
ZL50110/11/12/14 Data Sheet
59
Zarlink Semiconductor Inc.
5.3 TDM Interface
The ZL50110/11/12/14 family offers the following types of TDM service across the packet network:
Unstructured services are fully asynchronous, and include full support for clock recovery on a per stream basis.
Both adaptive and differential clock recovery mechanisms can be used. Structured services are synchronous, with
all streams driven by a common clock and frame reference. These services can be offered in two ways:
•Synchronous master mode - the ZL50110 /11/12/14 provides a common clock and frame pulse to all
streams, which may be locked to an incoming clock or fra me reference
•Synchronous slave mode - the ZL50110/11/12/14 a ccepts a common external clock and fram e pu lse to be
used by all streams
In either mode, N x 64 Kbps trunking is supported as detailed in “Structured Payload Order” on page 63.
The ZL50110/11/12/14 supports structured mode or unstructured mode, however it does not support structured
mode and unstructured mode at the same time, all ports are either structured or unstructured. In structured mode,
all TDM inputs must be synchronous.
In addition, it can be used with a variety of different protocols. It includes full support for the IETF RFCs for
CESoPSN (Circuit Emulation Services over Packet Switched Networks) and SAToP (Structure-Agnostic Transport
over Packet) protocols.
5.3.1 TDM Interface Block
The TDM Access Interface consists of up to 32 streams (depending on variant), each with an input and an output
data stream operating at either 1.544 Mbps or 2.048 Mbps. It contains two basic types of interface: unstructured
clock and data, for interfacing directly to a line interface unit; or structured, framed data, for interfacing to a framer
or TDM backplane.
Unstructured data is treated asynchronously, with every stream using its own clock. Clock recovery is provided on
each output stream, to reproduce the T DM service frequency at the egress of the p acket network. Structured data is
treated synchronously, i.e., all data streams are timed by the same clock and frame references. These can either be
supplied from an externa l source (slave mod e) or generated internally using the on-ch ip stratum 4/4E DPLL (mas ter
mode).
Service type TDM interface Interface type Interfaces to
Unstructured
asynchronous T1, E1, J2, E3 and T3 Bit clock in and out
Data in and out Line interface unit
Structured synchronous
(N x 64 Kbps) T1, E1 and J2
Framed TDM data s treams at
2.048 and 8.192 Mbps
Bit clock out
Frame pulse out
Data in and out
Framers
TDM backplane (master)
Bit clock in
Frame in
Data in and out
Framers
TDM backplane (slave)
Table 25 - TDM Services Offered by the ZL50 110/11/12/14 Family
ZL50110/11/12/14 Data Sheet
60
Zarlink Semiconductor Inc.
5.3.2 Structured TDM Port Data Formats
The ZL50110/11/12/14 is programmable such that the frame/clock polarity and clock alignment can be set to any
desired combination. Table 26 shows a brief summary of four different TDM formats; ST-BUS, H.110, H-MVIP, and
Generic (synchronous mode only), for more information see the relevant specifications shown. There are many
additional formats for TDM transmission not depicted in Table 26, but the flexibility of the port will cover almost any
scenario. The overall data format is set for the entire TDM Interface device, rather than on a per stream basis. It is
possible to control the polarity of the master clock and frame pulse outputs, independent of the chosen data format
(used when operating in synchronous master mode).
Data
Format
Data
Rate
(Mbps)
Number
of
channels
per
frame
Clock
Freq.
(MHz)
Nominal
Frame
Pulse
Width
(ns)
Frame
Pulse
Polarity
Frame Boundary
Alignment
Standard
clock frame
pulse
ST-bus 2.048 32 2.048 244 Negative Rising
Edge St raddles
boundary MSAN-126
Rev B
(Issue 4)
Zarlink
2.048 32 4.096 244 Negative Falling
Edge St raddles
boundary
8.192 128 16.384 61 Negative Falling
Edge St raddles
boundary
H.110 8.192 128 8.192 122 Negative Rising
edge St raddles
boundary ECTF
H.110
H-MVIP 2.048 32 2.048 244 Negative Rising
Edge St raddles
boundary H-MVIP
Release
1.1a
2.048 32 4.096 244 Negative Falling
Edge St raddles
boundary
8.192 128 16.384 244 Negative Falling
Edge St raddles
boundary
Generic 2.048 32 2.048 488 Positive Rising
Edge Rising
edge of
clock
8.192 128 8.192 122 Positive Rising
Edge Rising
edge of
clock
Table 26 - Some of the TDM Port Formats Accepted by the ZL50110/11/12/14 Family
ZL50110/11/12/14 Data Sheet
61
Zarlink Semiconductor Inc.
5.3.3 TDM Clock Structure
The TDM interface can operate in two modes, synchronous for structured TDM data, and asynchronous for
unstructured TDM data. The ZL50110/11/12/14 is capable of providing the TDM clock for either of the modes. The
ZL50110/11/12/14 supports clock recovery in both synchronous and asynchronous modes of operation. In
asynchronous operation each stream may have independent clock recovery.
5.3.3.1 Synchronous TDM Clock Generation
In synchronous mode all 32 streams will be driven by a common clock source. When the ZL50110/11/12/14 is
acting as a master de vice, the source c an either be the internal DPLL or an external PLL. In both ca ses, the primary
and secondary reference c locks are ta ken from either two TDM input clocks , or two e xternal clock source s driven to
the chip. The input clocks are then divided down where necessary and sent either to the internal DPLL or to the
output pins for connection to an external DPLL. The DPLL then provides the common clock and frame pulse
required to drive the TDM streams. See “DPLL Specification” on page 75 for further details.
Figure 14 - Synchronous TDM Clock Generation
When the ZL50110/11/12/14 is acting as a slave device, the common clock and frame pulse signals are taken from
an external device providing the TDM master function.
5.3.3.2 Asynchronous TDM Clock Genera tion
Each stream uses a separate internal DCO to provide an asynchronous TDM clock output. The DCO can be
controlled to recover the clock from the original TDM source depending on the timing algorithm used.
5.4 Payload Assembly
Data traffic received on the TDM Access Interface is sampled in the TDM Interface block, and synchronized to the
internal clock. It is then forwarded to the payload as sembly process. Th e ZL50110/11/12/14 Payload Assembler can
handle up to 128 active packet streams or “contexts” simultaneously. Packet payloads are assembled in the format
shown in Figure 15 - on page 62. This meets the requirements of the IETF CESoPSN standard (RFC 5086).
Alternatively, packet payloads are assembled in the format shown in Figure 17 - on page 64. This meets the
requirements of the IETF SAToP standard (RFC 4553).
The Packet Transmit (PTX) circuit adds Layer 2 and Layer 3 protocol headers. The chosen protocol header
combination for addition by the PTX must not exceed 64 bytes. The exception is context 127 (the 128th context),
which must not exceed 56 bytes.
FRAME
CLOCK
TDM_CLKi[31:0]
PLL_SE
C
PLL_PRI
SRS SRD
DIV
DIV
Internal
DPLL
PRS PRD
TDM_CLKiP
TDM_CLKiS
ZL50110/11/12/14 Data Sheet
62
Zarlink Semiconductor Inc.
Contexts in the TDM to PKT direction are placed in the UPDATE state when they are opened, pending the local
clock source generation. If there is no local clock source to generate packets, the context will remain in the
UPDATE state and cannot be closed. ZL5011x Design Manual section “13.1 Understanding forceDelete” describes
the procedure to close transmit contexts in the UPDATE state.
When the payload has been assembled it is written into the centrally managed memory, and a task message is
passed to the Task Manager.
5.4.1 Structured Payload Operation
In structured mode a context may contain any number of 64 kbps channels. These channels need not be
contiguous and they may be selected from any input stream.
Channels may be added or deleted dynamically from a context. This feature can be used to optimize bandwidth
utilisation. Modifications to the context are synchronised with the start of a new packet.
The fixed header at the start of each packet is added by the Packet Transmit block. This consis ts of up to 64 bytes,
containing the Ethernet header, any upper layer protocol headers, and the two byte context descriptor field (see
section below). The header is entirely user programmab le , enab ling the use of any protocol.
The payload header and size must be chosen so that the overall packet size is not less than 64 bytes, the Ethernet
standard minimum p acket size. Where this is likely to be the case, th e header or dat a must be p added (as shown in
Figure 15 and Figure 17) to ensure the packet is large enough. This padding is added by the ZL50110/11/12/14 for
most applications.
Figure 15 - ZL50110/11/12/14 Packet Fo rmat - Structur ed Mode
In applications where large payloads are being used, the payload size must be chosen such that the overall packet
size does not exceed the maximum Ethernet packet size of 1518 bytes (1522 bytes with VLAN tags). Figure 15
Channel 1
Channel 2
Channel
x
Data for TDM Frame 1
Heade
r
Ethernet FCS
TDM Payload
(constructed by Payload Assembler)
Data for TDM Frame
n
Channel 1
Channel 2
Channel
x
Data for TDM Frame 2
Channel 1
Channel 2
Channel
x
Ethernet Header
Network Layers
(added by Packet Transm it)
Upper layer s
(added by Protocol Engine)
e.g. IPv4, IPv6, MPLS
e.g. UDP, L2TP, RTP,
CES o PS N, SA T o P
may include VLAN tagging
Static Padding
(if r equired to mee t minimu m paylo ad size ) may also be placed in the
pack et he ader
ZL50110/11/12/14 Data Sheet
63
Zarlink Semiconductor Inc.
shows the packet format for structured TDM data, where the payload is split into frames, and each frame
concatenated to form the packet.
5.4.1.1 Structured Payload Order
Packets are assembled sequentially, with each channel pl aced into the packet as it arrives at the TDM Access
Interface. A fixed order of channels is maintained (see Figure 16), with channel 0 placed before channel 1,
which is placed before channel 2. It is this order that allows the packet to be correctly disassembled at the far
end. A context must contain only unique channel numbers. As such a context that contains the same channel
from different streams, for example channel 1 from stream 2 and channel 1 from stream 5, would not be
permitted.
Figure 16 - Channel Order for Packet Formation
Each packet contains one or more frames of TDM data, in sequential ord er. This grou ps the selected channels
for the first frame, followed by the same se t of channels for the subse quent frame, and so on .
5.4.2 Unstructured Payload Operation
In unstructured mode, the p ayl oad is not split by d efined frame s or timeslot s, so the p a cket c onsist s of a continuou s
stream of data. Each packet contains a programmable number of octets, as shown in Figure 17. The number of
octets in a packet need not be an integer number of frames. A typical value for N may be 192, as defined in the
IETF PWE3 RFC. For example, consider mapping the unstructured data of a 25 timeslot DS0 stream. The data for
each T1 frame would normally consist of 193 bits, 192 data bits and 1 framing bit. If the payload consists of 24
octets it will be 1 bit short of a complete frames worth of dat a, if the pay load consist s of 25 octet s it will be 7 bits over
a complete frames worth of data. NOTE: No align ment of the octets with the T1 framing structure can be assumed.
Figure 17 - ZL50110/11/12/14 Packet Format - Unstructured Mode
C hannel 0 C han nel 1 C han nel 2 C hannel 31
Stream 0
C hannel 0 C han nel 1 C han nel 2 C hannel 31
Stream 31
C hannel 0 C han nel 1 C han nel 2 C hannel 31
Stream 1
C hannel 0 C han nel 1 C han nel 2 C hannel 31
Stream 2
C hannel Assem bly O rder
Heade
r
N octets of data from u nstructured stream
NOTE:
No frame or chan nel alignmen
t
may include VLAN tagging
e.g . IPv4, IPv6, MPLS
e.g. UDP , L2TP, R TP ,
CESoPSN, SAToP
TDM Payload
(constructed by Payload Assembler)
46 to 1500 bytes
may also b e place d in the
packet header
Octe t 1
Octe t 2
Oc tet N
Ethernet Header
Ne two rk Layers
(added by Packet Transmit)
Upper layers
(added by Protocol Engine)
Ethernet FCS
Static Padding
(if required to meet minimum payload size)
ZL50110/11/12/14 Data Sheet
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Zarlink Semiconductor Inc.
Note: To change the p acket siz e of a context, firs t close the context and then re-open the contex t with a new pac ket
size.
5.5 Protocol Engine
In general, the next processing block for TDM packets is the Protocol Engine. This handles the data-plane
requirements of the main higher level protocols (layers 4 and 5) expected to be used in typical applications of the
ZL50110/11/12/14 family: UDP, RTP, L2TP, CESoPSN and SAToP. The Protocol Engine can add a header to the
datagram containing up to 24 bytes. This header is largely static information, and is programmed directly by the
CPU. It may contain a number of dynamic fields, including a length field, checksum, sequence number and a
timestamp. The location, and in some cases the length of these fields is also programmable, allowing the various
protocols to be placed at variable locations within the header.
5.6 Packet Transmission
Packets ready for transmission are queued to the switch fabric interface by the Queue Manager. Four classes of
service are provided, allowing some packet streams to be prioritized over others. On transmission, the Packet
Transmit block appends a programmable header, which has been set up in advance by the control processor.
Typically this contains the data-link and network layer headers (layers 2 and 3), such as Ethernet, IP (versions 4
and 6) and MPLS.
5.7 Packet Reception
Incoming data traffic on the packet interface is received by the MACs. The well-formed packets are forwarded to a
packet classifier to determine the destination. When a packet is successfully classified the destination can be the
TDM interface, the LAN interface or the host interface . TDM traf fic is then furthe r classified to determine the context
it is intended for.
Each TDM interface context has an individual queue, and the TDM re-formatting process re-creates the TDM
streams from the incoming packet streams. This queue is used as a jitter buffer, to absorb variation in packet delay
across the network. The size of the jitter buffer can be programmed in units of TDM frames (i.e., steps of 125 μs).
There is also a queue to the host interface, allowing a traffic flow to the host CPU for processing. Again the host’s
DMA controller can be used to retrieve packet data and write it out into the CPU’s own memory.
5.8 TDM Formatter
At the receiving end of the packet network, the original TDM data must be re-constructed from the packets
received. This is known as re-formatting, and follows the reverse process from the Payload Assembler. The TDM
Formatter plays out the packets in the correct sequence, directing each octet to the selected timeslot on the output
TDM interface.
When lost or late packets are detected, the TDM Formatter plays out underrun data for the same number of TDM
frames as were included in the missing packet. Underrun data can either be the last value played out on that
timeslot, or a pre-programmed value (e .g., 0xFF). If the p acket subsequently turns up it is discard ed. In this way, the
end-to-end latency through the system is maintained at a constant value.
Contexts in the Packet to TDM direction are placed in the UPDATE state when they are opened, pending first
packet arrival. If a packet never arrives the context will remain in the UDPATE state. ZL5011x Design Manual
section “13.1 Understanding forceDelete” describes the procedure to close receive contexts in the UPDATE state.
ZL50110/11/12/14 Data Sheet
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Zarlink Semiconductor Inc.
6.0 Clock Recovery
One of the main issues with circuit emulation is that the clock used to drive the TDM link is not necessarily linked
into the central office reference clock, and hence may be any value within the tolerance defined for that service.
The reverse link may also be independently timed, and operating at a slightly different frequency. In the
plesiochronous dig ital h ierarchy the d if fere nce in clock fre quencies betwe en TDM lin ks is comp ensated fo r using bit
stuffing techniques, allowing the clock to be accurately regenerated at the remote end of the carrier network.
With a packet network, that connection between the ingress and egress frequency is broken, since packets are
discontinuous in time. From Figure 6, the TDM service frequency fservice at the customer premises must be exactly
reproduced at the egress of the packet network. The consequence of a long-term mismatch in frequ ency is that the
queue at the egress of the p acket network will either fill up or empty, depending on whether the regenerated clock is
slower or faster than the original. This will cause loss of data and degra dation of the service.
The ZL50110/11/12/14 provides clock recovery function to reproduce the TDM service frequency at the egress of
the packet network for structured and unstructured mode. Two schemes are employed, depending on the
availability of a common reference clock at each provider edge unit, differential and adaptive .
The adaptive and dif ferential a lgorithms assume that the re are no bit errors in the received p acket header sequenc e
number or timestamp fields. If there are bit errors in the sequence number or timestamp fields, especially in the
most significant bits, then it is likely to cause a temporary degradation of the recovered clock performance. It is
advised to protect packets end-to-end (e.g., by using Ethernet FCS) such that packets with bit errors are discarded
and do not impact the recovered clock performance.
The clock recovery itself is performed by software in the host processor, with support from on-chip hardware to
gather the required statistics.
6.1 Differential Clock Recov ery
For applications where the wander characteristics of the recovered clock are very important, such as when the
emulated circuit must be connected into the plesiochronous digital hierarchy (PDH), the ZL50110/11/12/14 also
offers a differential clock recovery technique. This relies on having a common reference clock available at each
provider edge point.
The differential algorithm assumes that the common clock is always present. There is no internal holdover
capability for the common clock source (e.g. TDM_CLKiP). If the availability of the common clock can not be
guaranteed, then it is recommended to use an external DPLL with holdover capability to provide a clock source at
all times. The external DPLL may enter holdover while the common clock is absent to maintain a relatively close
frequency to the original common clock.
In a diff erential technique, the timing of data pa cket formation is sent relative to the commo n reference clock. Since
the same reference is available at the packet egress point and the packet size is fixed, the original service clock
frequency can be recovered. This technique is unaffected by any low frequency components in the packet delay
variation. The disadvantage is the requirement for a common reference clock at each end of the packet network,
which could either be the central office TDM clock, or provided by a global position system (GPS) receiver.
ZL50110/11/12/14 Data Sheet
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Zarlink Semiconductor Inc.
Figure 18 - Differential Clock Recovery
For in-band differential algorithm, the ZL50110/11/12/14 inserts the timestamp after the packet payload is fully
assembled. The insertion-time may be in error by up to 8 UI of the nominal service clock (for example 8 * 488 ns of
an E1 interface).This variable error will occur in unstructured mode only, and result in degradation of performance
at the remote end, which uses the timestamps to recover a clock frequency. This error is most likely to occur when
there are many asynchronous (PDH) clocks that are close in frequency. In this case it is recommended to used the
Zarlink proprietary in-band differential.
Also, for in-band differential clock recovery, the frequency must be the same as the common clock frequency.
6.2 Adaptive Clock Recovery
For applications where there is no common reference clock between provider edge units, an adaptive clock
recovery technique is provided. The Adaptive clock recovery solution provided in the Zarlink CESoP products is a
combination hardware and software. The chip cont ains a DCO per TDM port in unstructu red mode, that en ables the
recovery of up to 32 in dependent clo cks. The timing algo rithm resides in the API and runs out of the host processor.
The basic information is transmitted using timestamps. Current CES standards allow for using of timestamps.
Timestamps may be implied by the value of the sequence numbers, or it can be formatted as RTP timestamps.
When a packet containing TDM data is sent, an RTP timestamp and/or sequence number is placed into the packet
header. On arrival at the receiving device, the arrival time is noted in the form of a local timestamp, driven by the
output clock of the TDM port it is destined for.
The recovered clock at the egress point of the ZL50110/11/12/14 is based on non-linear filtering of the timestamps
that are carried in the CESoP p acket s. The performanc e of the clock recovery is greatly improved by applying thes e
non-liner filtering techniques. The adaptive clock recovery performance is dependent on the network configuration
and operation, if the loading of the network is constrained, then the wander of the recovered clock will not exceed
the specified limits.
LIU LIU
ZL5011x
source
node
ZL5011x
destination
node
Timestamp
generation
Timestamp
extraction
Host CPU
Timing
recovery
DCO
Data
Source
Clock
Data
Dest'n
Clock
Packets Packets
PRS
clock
Network
ZL50110/11/12/14 Data Sheet
67
Zarlink Semiconductor Inc.
Figure 19 - Adaptive Clock Recovery
6.3 SYSTEM_CLK Considerations
The quality of the 100 MHz SYSTEM_CLK or the oscillator that drives SYSTEM_CLK directly impacts the adaptive
clock recovery performance. Zarlink has a recommended oscillator and guidelines for the selection of an oscillator.
Please refer to ZL5011x Design Manual section “3.6 System Clock Block” before choosing an oscillator.
ZL5011x
source
node
ZL5011x
destination
node
Host CPU
Queue
monitor
DCO
Source
Clock Dest'n
Clock
Packets Packets
Network Queue
Time
Stamp
ZL50110/11/12/14 Data Sheet
68
Zarlink Semiconductor Inc.
7.0 System Features
7.1 Latency
The following lists the intrinsic processing latency of the ZL50110/11/12/14, regardless of the number of active
channels or contexts.
• TDM to Packet transmission processing latency le ss than 125 μs
• Packet to TDM transmission processing latency le ss than 250 μs (unstructured)
• Packet to TDM transmission processing latency le ss than 250 μs (structured, more than 16 channels in
context)
• Packet to TDM transmission processing latency less than 375 μs (structured, 16 or less cha nnels in con text)
End-to-end latency may be estimated as the transmit latency + packet network latency + receive latency. The
transmit latency is the sum of the transmit processing and the number of frames per packet x 125 μs. The receive
latency is the sum of the receive processing and the delay through the jitter buffer which is programmed to
compensate for packet network PDV.
The ZL50110/11/12/14 is capable of creating an extremely low latency connection, with end to end delays of less
than 0.5 ms, depending on user con figuration.
7.2 Loopback Modes
The ZL50110/11 /12/14 devices support loopback of the TDM circuits and the circuit emulation packe ts.
TDM loopback is achieved by first packetizing the TDM circuit as normal via the TDM Interface and Payload
Assembly blocks. The pa cketized dat a is then routed by the Task Manager back to the same TDM port via the TDM
Formatter and TDM Interface.
Loopback of the emulated services is achieved by redirecting classified packets from the Packet Receive blocks,
back to the packet network. The Packet Transmit blocks are setup to strip the original header and add a new
header directing the packets back to the source.
7.3 Host Packet Generation
The control processor c an generate p ac ket s dire ctly, allowing it to use the network for out-of-band commu nications.
This can be used for transmission of control data or network setup information, e.g., routing information. The host
interface can also be used by a local resource for network transmission of processed data.
The device supports dual address DMA transfers of packets to and from the CPU memory, using the host's own
DMA controller. Table 27 illustrates the maximum bandwidths achievable by an external DMA master.
Note 1: M aximum band widths are the m aximum the ZL50110/11/12/14 d evices can tr ansfer under host control, and assum es only
minimal packet processing by the host.
Note 2: Combined figures assume the same amount of data is to be transferred each way.
Note 3: DM A with external memory m ust use si ngle packet mod e. Refer to Z L5011x Design Manu al for details.
DMA Path Packet Size Max Bandwidth Mbps1
ZL50110/11/12/14 to CPU only >1000 bytes 50
ZL50110/11/12/14 to CPU only 60 bytes 6.7
CPU to ZL50110/11/12/14 only >1000 bytes 60
CPU to ZL50110/11/12/14 only 60 bytes 43
Combined2>1000 bytes 58 (29 each way)
Combined260 bytes 11 (5.5 each way)
Table 27 - DMA Maximum Bandwidths
ZL50110/11/12/14 Data Sheet
69
Zarlink Semiconductor Inc.
7.4 Loss of Service (LOS)
During normal operation, a s ituation may arise where a Loss of Service occurs . This may be caus ed by a disruption
in the transmission line due to engineering works or cable disconnection, for example. The locally detected LOS
should be transferred across the emulated T1/E1 to the far end. The far end, in turn, should propagate AIS
downstream.
The handling of LOS over a CESoP connection is typically performed using (setting/clearing) the L bit in the
CESoPSN or SAToP control word of the packet header.
Refer to ZL5011x Design Manual section “3.1.1 Connection to LIU” for details on a variety of different ways that
LOS may be handled in an application.
7.5 External Memory Requirement
The ZL50110/11/12/14 family includes a large amount of on-chip memory, such that for most applications, external
memory will not be required. However, for certain combinations of header size, packet size and jitter buffer size,
there may be a requirement for external memory. Therefore the device allows the connection of up to 8 Mbytes of
synchronous ZBT-SRAM.
The following charts show how much memory is required by the ZL50111 (32 T1 streams) and the ZL50110 (8 T1
streams) for a variety of packet sizes (expressed in number of frames of TDM data) and jitter buffer sizes. It is
assumed that each packet contains a full Ethernet/MPLS/MPLS/RTP/CESoPSN header.
Figure 20 - External Memory Requirement for ZL50111
External Memory Requirements for different packet sizes
32 T1 streams, w ith Ethernet/MPLS/MPLS/RTP/CESoPSN headers
0
1024
2048
3072
4096
5120
6144
7168
8192
4 8 16 32 64 128 256
Jitter Buffer Size, ms
External memory requirement,
KBytes
1 frame packets
8 frame packets
16 frame packets
1 T3 stream (1 frame)
ZL50110/11/12/14 Data Sheet
70
Zarlink Semiconductor Inc.
Figure 21 - External Memory Requirement for ZL 50110
7.6 GIGABIT Ethernet - Recommended Configurations
NOTE: In GMII/TBI mode only 1 GMAC port may be used. The second GMAC port is for redundancy purposes
only.
This section outlines connection methods for the ZL50110/11/12/14 in a Gigabit Ethernet environment
recommended to ensure optimum performance. Two areas are covered:
• Central Ethernet Switch
• Redundant Ethernet Switch
External Memory Requirements for different packet sizes
8 T1 streams, with Ethernet/MPLS/MPLS/RTP/CESoPSN headers
0
1024
2048
3072
4096
5120
6144
7168
8192
4 8 16 32 64 128 256
Jitter Buffer Size, ms
External memory requirement, KBytes
1 frame packets
8 frame packets
16 frame packets
ZL50110/11/12/14 Data Sheet
71
Zarlink Semiconductor Inc.
7.6.1 Central Ethernet Switch
Figure 22 - Gigabit Ethernet Connection - Central Ethernet Switch
TDM data and control packets are directed to the appropriate ZL50110/11/12/14 device through the Ethernet
Switch. There is no limit on the number of ZL50110/11/12/14 devices that can be connected in this configuration.
GMII GMII
ZL5011x
TDM
GMII GMII
ZL5011x
TDM
GMII GMII
ZL5011x
TDM
GMII GMII
ZL5011x
TDM
Ethernet Switch
Network
ZL50110/11/12/14 Data Sheet
72
Zarlink Semiconductor Inc.
7.6.2 Redundant Ethernet Switch
Figure 23 - Gigabit Ethernet Connection - Redundant Ethernet Switch
The central Ethernet Switch configuration can be extended to include a redundant switch connected to the second
ZL50110/11/12/14 GMII port. One port should be used for all the TDM-to-Packet and Packet-to-TDM data with the
other port idle. If the current port fails then data must be transferred to the spare port.
7.7 Power Up sequence
To power up the ZL50110/11/12/14 the following procedure must be used:
• The I/O supply should lead th e Core supply, or both can be brought up together
• The I/O supply must never excee d the Core supply by more than 2.0VDC
• The Core supply must never exceed the I/O sup ply by more than 0.5VDC
• The System Reset and the JT AG Reset must remain low until at least 100 µs after the 100 MHz system clock
has stabilised. Note that if JTAG Reset is not used it must be tied low.
This is illustrated in the diagram shown in Figure 24.
GMII GMII
ZL5011x
TDM
GMII GMII
ZL5011x
TDM
GMII GMII
ZL5011x
TDM
GMII GMII
ZL5011x
TDM
Ethernet Switch
Network
Ether n et Switch
Network
ZL50110/11/12/14 Data Sheet
73
Zarlink Semiconductor Inc.
Figure 24 - Powering Up the ZL50110/11/12/14
7.8 JTAG Interface and Board Level Test Features
The JTAG interface is used to access the boundary scan logic for board level production testing.
7.9 External Component Re quirements
7.9.1 Host Processor
ZL50110/11/12/14 family offers direct connection to PowerQUICC™ II (MPC8260) host processor and associated
memory, but can support other processors with appropriate interface logic.
7.9.2 Other components
• TDM Framers and/or Line Interface Units
• Ethernet PHY for each MAC port
• Optional ZBT-SRAM for exten ded packet memo ry buffer depth
7.10 Miscellaneous Features
• System clock speed of 100 MHz
• Host clock speed of up to 66 MHz
• Debug option to freeze all internal state machines
• JTAG (IEEE1149) Test Ac cess Port
• 3.3 V I/O Supply rail with 5 V tolerance
• 1.8 V Core Supply rail
• Fully compatible with the MT90880/1/2/3 Zarlink products
RST
SCLK
VDD
I/O supply (3.3 V)
Core supply (1.8 V)
10 ns
> 100 µs
<0.5 VDC
t
t
t
ZL50110/11/12/14 Data Sheet
74
Zarlink Semiconductor Inc.
7.11 Test Modes Operation
7.11.1 Overview
The ZL50110/11/12/14 family supports the following modes of operation.
7.11 .1.1 Sys tem N orm al Mode
This mode is the device's normal operating mode. Boundary scan testing of the peripheral ring is accessible in this
mode via the dedicated JTAG pins. The JTAG interface is compliant with the IEEE Std. 1149.1-2001; Te st Access
Port and Boundary Scan Architecture.
Each variant has it's own dedicated.bsdl file which fully describes it's boundary scan architecture.
7.11 .1.2 Sys tem Tri-State Mode
All output and I/O output drivers are tri-stated allowing the device to be isolated when testing or debugging the
development board.
7.11 .2 Te st Mode Cont rol
The System Test Mode is selected using the dedicated device input bus TEST_MODE[2:0] as follows in Table 28.
7.11.3 System Norm al Mode
Selected by TEST_MODE[2:0] = 3'b000. As the test_mode[2:0] inputs have internal pull-downs this is the default
mode of operation if no exte rnal pull-up/downs a re connected. The GPIO[15:0] bus is captured on th e rising edge of
the external reset to provide interna l b ootstrap options. After the internal reset has been d e-asse rted the GPIO pins
may be configured by the ADM module as either inputs or outputs.
7.11.4 System Tri-state Mode
Selected by TEST_MODE[2:0] = 3'b011. All device output and I/O output drivers are tri-stated.
System Test Mode test_mode[2:0]
SYS_NORMAL_MODE 3’b000
SYS_TRI_STATE_MODE 3’b011
Table 28 - Test Mode Control
