LP2966 www.ti.com SNVS028E - APRIL 2000 - REVISED APRIL 2013 Dual 150mA Ultra Low-Dropout Regulator Check for Samples: LP2966 FEATURES KEY SPECIFICATIONS * * * * * * * 1 2 * * * * * * * Ultra Low Drop-Out Voltage Low Ground Pin Current <1A Quiescent Current in Shutdown Mode Independent Shutdown of Each LDO Regulator Output Voltage Accuracy 1% Ensured 150mA Output Current at Each Output Low Output Noise Error Flags Indicate Status of Each Output Available in VSSOP-8 Surface Mount Package Low Output Capacitor Requirements (1F) Operates with Low ESR Ceramic Capacitors in Most Applications Over Temperature/Over Current Protection -40C to +125C Junction Temperature Range APPLICATIONS * * * * * * * * * Cellular and Wireless Applications Palmtop/Laptop Computer GPS Systems Flat Panel Displays Post Regulators USB Applications Hand Held Equipment and Multimeters Wireless Data Terminals Other Battery Powered Applications * * * * Dropout Voltage: Varies Linearly with Load Current. Typically 0.9 mV at 1mA Load Current and 135mV at 150mA Load Current Ground Pin Current: Typically 300A at 1mA Load Current and 340A at 100mA Load Current (with One Shutdown Pin Pulled Low) Shutdown Mode: Less than 1A Quiescent Current when Both Shutdown Pins are Pulled Low Error Flag: Open Drain Output, Goes Low when the Corresponding Output Drops 10% Below Nominal Precision Output Voltage: Multiple Output Voltage Options Available Ranging from 1.8V to 5.0V with an Ensured Accuracy of 1% at Room Temperature DESCRIPTION The LP2966 dual ultra low-dropout (LDO) regulator operates from a +2.70V to +7.0V input supply. Each output delivers 150mA over full temperature range. The IC operates with extremely low drop-out voltage and quiescent current, which makes it very suitable for battery powered and portable applications. Each LDO in the LP2966 has independent shutdown capability. The LP2966 provides low noise performance with low ground pin current in an extremely small VSSOP-8 package (refer to package dimensions and CONNECTION DIAGRAM for more information on VSSOP-8 package). A wide range of preset voltage options are available for each output. In addition, many more are available upon request with minimum orders. In all, 256 voltage combinations are possible. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000-2013, Texas Instruments Incorporated LP2966 SNVS028E - APRIL 2000 - REVISED APRIL 2013 www.ti.com TYPICAL APPLICATION CIRCUIT *SD1 and SD2 must be actively terminated through a pull up resistor. Tie to VIN if not used. **ERROR1 and ERROR2 are open drain outputs. These pins must be connected to ground if not used. # Minimum output capacitance is 1F to insure stability over full load current range. More capacitance improves superior dynamic performance and provides additional stability margin. BLOCK DIAGRAM CONNECTION DIAGRAM Top View Figure 1. VSSOP-8 Package 8-Lead Small Outline Integrated Circuit See Package Number DGK0008A 2 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LP2966 LP2966 www.ti.com SNVS028E - APRIL 2000 - REVISED APRIL 2013 PIN DESCRIPTIONS Pin Name Function 1 VIN Input Supply pin 2 SD1 Active low shutdown pin for output 1 3 SD2 Active low shutdown pin for output 2 4 GND Ground 5 ERROR2 Error flag for output 2 - Normally high impedance, should be connected to ground if not used. 6 ERROR1 Error flag for output 1 - Normally high impedance, should be connected to ground if not used. 7 VOUT2 Output 2 8 VOUT1 Output 1 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) -65 to +150C Storage Temperature Range Lead Temp. (Soldering, 5 sec.) 260C Power Dissipation (3) Internally Limited ESD Rating (4) 2kV -0.3V to 7.5V Input Supply Voltage (Survival) -0.3V to (Vin + 0.3V) Shutdown Input Voltage (Survival) Maximum Voltage for ERROR Pins 10V IOUT (Survival) Short Circuit Protected Output Voltage (Survival) (5) (6) (1) (2) (3) (4) (5) (6) -0.3V to (Vin + 0.3V) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see ELECTRICAL CHARACTERISTICS. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. At elevated temperatures, devices must be derated based on package thermal resistance. The device in the surface-mount package must be derated at jA = 235C/W, junction-to-ambient. Please refer to APPLICATIONS INFORMATION: Maximum Current Capability for further information. The device has internal thermal protection. The human body model is a 100pF capacitor discharged through a 1.5k resistor into each pin. If used in a dual-supply system where the regulator load is returned to a negative supply, the LP2966 output must be diode-clamped to ground. The output PMOS structure contains a diode between the VIN and VOUT terminals that is normally reverse-biased. Reversing the polarity from VIN and VOUT will turn on this diode. OPERATING RATINGS (1) Input Supply Voltage 2.7V to 7.0V -0.3V to (Vin + 0.3V) Shutdown Input Voltage -40C to +125C Operating Junction Temperature Range Maximum Voltage for ERROR pins (1) 10V Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see ELECTRICAL CHARACTERISTICS. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LP2966 3 LP2966 SNVS028E - APRIL 2000 - REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS Limits in standard typeface are for Tj = 25C, and limits in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VIN = VO(NOM) + 1V (1), COUT = 1F, IOUT = 1mA, CIN = 1F, VSD1 = VSD2 = VIN. Symbol Vo (4) Parameter Output Voltage Tolerance Conditions VOUT + 1V < VIN < 7.0V 1mA < IL < 100mA VO/VIN (4) (5) Output Voltage Line Regulation VO/IOUT Output Voltage Load Regulation (6) VO2/IOUT1 VIN -VOUT Typ (2) 0.0 0.0 LP2966IMM (3) Min Max -1 1 -3 3 -1.5 1.5 -3.5 3.5 Unit %VNOM %VNOM 0.1 mV/V 1mA < IL< 100mA (6) 0.1 mV/mA Output Voltage Cross Regulation (7) 1mA < IL1< 100mA (7) 0.0004 Dropout Voltage (8) IL = 1mA 0.9 2.0 IL = 100mA 90 130 mV/mA 3.0 180 IL = 150mA 135 IL = 1mA 300 mV 195 270 IGND(1,0) (9) Ground Pin Current (One LDO On) VSD2 0.1V, VSD1= VIN IL = 100mA A 340 VSD2 0.1V, VSD1= VIN IGND(1,1) Ground Pin Current (Both LDOs On) IL = 1mA 340 IL = 100mA 420 450 500 540 A 600 IGND(0,0) IO(PK) Ground Pin Current in Shutdown Mode VSD1= VSD2 0.1V Peak Output Current See (10) VOUT VOUT(NOM)- 5% 500 See (10) (11) 600 0.006 0.3 10 350 150 A mA Short Circuit Foldback Protection IFB Short Circuit Foldback Knee mA The condition VIN = VO(NOM) + 1V applies when Vout1 = Vout2. If Vout1 Vout2, then this condition would apply to the output which is greater in value. As an example, if Vout1 = 3.3V and Vout2 = 5V, then the condition VIN = VO(NOM)+ 1V would apply to Vout2 only. (2) :Typical numbers are at 25C and represent the most likely parametric norm. (3) :Limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate Averaging Outgoing Quality Level (AOQL). (4) Output voltage tolerance specification also includes the line regulation and load regulation. (5) Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in input line voltage. (6) Output voltage load regulation is defined as the change in output voltage from the nominal value when the load current changes from 1mA to 100mA. (7) Output voltage cross regulation is defined as the percentage change in the output voltage from the nominal value at one output when the load current changes from 1mA to full load in the other output. This is an important parameter in multiple output regulators. The specification for VO1/IOUT2 is equal to the specification for VO2/IOUT1. (8) Dropout voltage is defined as the input to output differential at which the output voltage drops 100mV below the nominal value. Drop-out voltage specification applies only to output voltages greater than 2.7V. For output voltages below 2.7V, the drop-out voltage is nothing but the input to output differential, since the minimum input voltage is 2.7V. (9) The limits for the ground pin current specification, IGND(0,1) will be same as the limits for the specification, IGND(1,0). (10) At elevated temperatures, devices must be derated based on package thermal resistance. The device in the surface-mount package must be derated at jA = 235C/W, junction-to-ambient. Please refer to APPLICATIONS INFORMATION: Maximum Current Capability for further information. The device has internal thermal protection. (11) LP2966 has fold back current limited short circuit protection. The knee is the current at which the output voltage drops 10% below the nominal value. (1) 4 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LP2966 LP2966 www.ti.com SNVS028E - APRIL 2000 - REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (continued) Limits in standard typeface are for Tj = 25C, and limits in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VIN = VO(NOM) + 1V(1), COUT = 1F, IOUT = 1mA, CIN = 1F, VSD1 = VSD2 = VIN. Symbol Parameter Conditions Typ (2) LP2966IMM (3) Min Max Unit Over Temperature Protection Tsh(t) Shutdown Threshold 165 C Tsh(h) Thermal Shutdown Hysteresis 25 C Shutdown Input VSDT Shutdown Threshold (12) Output = Low 0 Output = High VIN 0.1 V VIN - 0.1 TdOFF Turn-off Delay (13) IL = 100 mA 20 sec TdON Turn-on Delay (13) IL = 100 mA 25 sec ISD SD Input Current VSD = VIN 1 VSD = 0 V 1 10 5 5 2 nA Error Flag Comparators VT Threshold (output goes high to low) See (14) VTH Threshold Hysteresis See (14) VERR(Sat) Error Flag Saturation IFsink = 100A IEF(leak) Error Flag Pin Leakage Current 1 nA I(EFsink) Error Flag Pin Sink Current 1 mA 0.015 16 % 8 % 0.1 V AC Parameters PSRR Ripple Rejection VIN = VOUT + 1V, f = 120Hz, VOUT = 3.3V 60 VIN = VOUT + 0.3V, f = 120Hz, VOUT = 3.3V 40 n(1/f) Output Noise Density f =120Hz en Output Noise Voltage (rms) BW = 10Hz - 100kHz, COUT = 10F 150 BW = 300Hz - 300kHz, COUT = 10F 100 1 dB V/Hz V(rms) (12) VSDT is the shutdown pin voltage threshold below which the output is disabled. (13) Turn-on delay is the time interval between the low to high transition on the shutdown pin to the output voltage settling to within 5% of the nominal value. Turn-off delay is the time interval between the high to low transition on the shutdown pin to the output voltage dropping below 50% of the nominal value. The external load impedance influences the output voltage decay in shutdown mode. (14) Error Flag threshold and hysteresis are specified as the percentage below the regulated output voltage. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LP2966 5 LP2966 SNVS028E - APRIL 2000 - REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified, VIN =VO(NOM) + 1V, VOUT= 3.3V, COUT =1F, IOUT = 1mA, CIN =1F, VSD1 = VSD2 = VIN, and TA = 25C. 6 Ground Pin Current vs Supply Voltage (one LDO on) Ground Pin Current vs Supply Voltage (both LDOs on) Figure 2. Figure 3. Ground Pin Current vs Load Current over temperature (one LDO on) Ground Pin Current vs Load Current over temperature (both LDOs on) Figure 4. Figure 5. Output Voltage vs Temperature Drop-out Voltage vs Temperature Figure 6. Figure 7. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LP2966 LP2966 www.ti.com SNVS028E - APRIL 2000 - REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified, VIN =VO(NOM) + 1V, VOUT= 3.3V, COUT =1F, IOUT = 1mA, CIN =1F, VSD1 = VSD2 = VIN, and TA = 25C. Input Voltage vs Output Voltage Ground Pin Current vs Shutdown Pin Voltage Figure 8. Figure 9. Ground Pin Current vs Input Voltage (Both LDOs off) Short-Circuit Foldback Protection Figure 10. Figure 11. Line Transient Response (COUT = 2.2F, IOUT = 1mA) Line Transient Response (COUT = 2.2F, IOUT = 1mA) Figure 12. Figure 13. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LP2966 7 LP2966 SNVS028E - APRIL 2000 - REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified, VIN =VO(NOM) + 1V, VOUT= 3.3V, COUT =1F, IOUT = 1mA, CIN =1F, VSD1 = VSD2 = VIN, and TA = 25C. 8 Line Transient Response (COUT = 2.2F, IOUT = 100mA) Line Transient Response (COUT = 2.2F, IOUT = 100mA) Figure 14. Figure 15. Line Transient Response (COUT = 10F, IOUT = 1mA) Line Transient Response (COUT = 10F, IOUT = 1mA) Figure 16. Figure 17. Line Transient Response (COUT = 10F, IOUT = 100mA) Line Transient Response (COUT = 10F, IOUT = 100mA) Figure 18. Figure 19. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LP2966 LP2966 www.ti.com SNVS028E - APRIL 2000 - REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified, VIN =VO(NOM) + 1V, VOUT= 3.3V, COUT =1F, IOUT = 1mA, CIN =1F, VSD1 = VSD2 = VIN, and TA = 25C. Load Transient Response (COUT = 2.2F) Load Transient Response (COUT = 10F) Figure 20. Figure 21. Load Transient Response (COUT = 10F) Load Transient Response (COUT = 2.2F) Figure 22. Figure 23. Cross-Channel Isolation vs Frequency (IOUT1 =1mA, IOUT2 = 1mA) Cross-Channel Isolation vs Frequency (IOUT1 = IOUT2 = 100mA) Figure 24. Figure 25. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LP2966 9 LP2966 SNVS028E - APRIL 2000 - REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified, VIN =VO(NOM) + 1V, VOUT= 3.3V, COUT =1F, IOUT = 1mA, CIN =1F, VSD1 = VSD2 = VIN, and TA = 25C. 10 Output Voltage Cross-Coupling Output Noise Density Figure 26. Figure 27. Power Supply Ripple Rejection Peak Output Current vs Temperature Figure 28. Figure 29. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LP2966 LP2966 www.ti.com SNVS028E - APRIL 2000 - REVISED APRIL 2013 APPLICATIONS INFORMATION Input Capacitor Selection LP2966 requires a minimum input capacitance of 1F between the input and ground pins to prevent any impedance interactions with the supply. This capacitor should be located very close to the input pin. This capacitor can be of any type such as ceramic, tantalum, or aluminium. Any good quality capacitor which has good tolerance over temperature and frequency is recommended. Output Capacitor Selection The LP2966 requires a minimum of 1F capacitance on each output for proper operation. To insure stability, this capacitor should maintain its ESR (equivalent series resistance) in the stable region of the ESR curves (Figure 30 and Figure 31) over the full operating temperature range of the application. The output capacitor should have a good tolerance over temperature, voltage, and frequency. The output capacitor can be increased without limit. Larger capacitance provides better stability and noise performance. The output capacitor should be connected very close to the Vout pin of the IC. Figure 30. ESR Curve for VOUT = 5V and COUT = 2.2F Figure 31. ESR Curve for VOUT = 3.3V and COUT = 2.2F LP2966 works best with Tantalum capacitors. However, the ESR and the capacitance value of these capacitors vary a lot with temperature, voltage, and frequency. So while using Tantalum capacitors, it should be ensured that the ESR is within the limits for stability over the full operating temperature range. For output voltages greater than 2.5V, good quality ceramic capacitors (such as the X7R series from Taiyoyuden) can also be used with LP2966 in applications not requiring light load operation (< 5mA for the 5V output option). Once again, it should be ensured that the capacitance value and the ESR are within the limits for stability over the full operating temperature range. The ESRD Series Polymer Aluminium Electrolytic capacitors from Cornell Dubilier are very stable over temperature and frequency. The excellent capacitance and ESR tolerance of these capacitors over voltage, temperature and frequency make these capacitors very suitable for use with LDO regulators. Output Noise Noise is specified in two ways: Spot Noise or Output Noise Density is the RMS sum of all noise sources, measured at the regulator output, at a specific frequency (measured with a 1Hz bandwidth). This type of noise is usually plotted on a curve as a function of frequency. Total Output Noise or Broad-Band Noise is the RMS sum of spot noise over a specified bandwidth, usually several decades of frequencies. Attention should be paid to the units of measurement. Spot noise is measured in units V/Hz or nV/Hz and total output noise is measured in V(rms). Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LP2966 11 LP2966 SNVS028E - APRIL 2000 - REVISED APRIL 2013 www.ti.com The primary source of noise in low-dropout regulators is the internal reference. In CMOS regulators, noise has a low frequency component and a high frequency component, which storngly depend on the silicon area and quiescent current. Noise can be reduced in two ways: by increasing the transistor area or by increasing the current drawn by the internal reference. Increasing the area will increase the die size and decreases the chance of fitting the die into a small package. Increasing the current drawn by the internal reference increases the total supply current (ground pin current) of the IC. Using an optimized trade-off of ground pin current and die size, LP2966 achieves low noise performance with low quiescent current in an VSSOP-8 package. Short-Circuit Foldback Protection In the presence of a short or excessive load current condition, the LP2966 uses an internal short circuit foldback mechanism that regulates the maximum deliverable output current. A strong negative temperature coefficient is designed into the circuit to enable extremely higher peak output current capability (in excess of 400mA per output at room temperature, see TYPICAL PERFORMANCE CHARACTERISTICS ). Thus, a system designer using the LP2966 can achieve higher peak output current capability in applications where the LP2966 internal junction temperature is kept below 125C. Refer to APPLICATIONS INFORMATION on calculating the maximum output current capability of the LP2966 for your application. Error Flag Operation The LP2966 produces a logic low signal at the Error Flag pin (ERROR) when the corresponding output drops out of regulation due to low input voltage, current limiting, or thermal limiting. This flag has a built in Hysteresis. The timing diagram in Figure 32 shows the relationship between the ERROR and the output voltage. In this example, the input voltage is changed to demonstrate the functionality of the Error Flag. Figure 32. Error Flag Operation The internal error flag comparators have open drain output stages. Hence, the ERROR pins should be pulled high through a pull up resistor. Although the ERROR pin can sink current of 1mA, this current adds to the battery drain. Hence, the value of the pull up resistor should be in the range of 100k to 1M. The ERROR pins must be connected to ground if this function is not used. It should also be noted that when the shutdown pins are pulled low, the ERROR pins are forced to be invalid for reasons of saving power in shutdown mode. Shutdown Operation The two LDO regulators in the LP2966 have independent shutdown. A CMOS Logic level signal at the shutdown (SD) pin will turn-off the corresponding regulator. Pins SD1 and SD2 must be actively terminated through a 100k pull-up resistor for a proper operation. If these pins are driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. These pins must be tied to Vin if not used. 12 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LP2966 LP2966 www.ti.com SNVS028E - APRIL 2000 - REVISED APRIL 2013 Drop-Out Voltage The drop-out voltage of a regulator is defined as the minimum input-to-output differential required to stay within 100mV of the output voltage measured with a 1V differential. The LP2966 uses an internal MOSFET with an Rds(on) of 1. For CMOS LDOs, the drop-out voltage is the product of the load current and the Rds(on) of the internal MOSFET. Reverse Current Path The internal MOSFET in the LP2966 has an inherent parasitic diode. During normal operation, the input voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is pulled above the input in an application, then current flows from the output to the input as the parasitic diode gets forward biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to 150mA. Maximum Output Current Capability Each output in the LP2966 can deliver a current of more than 150mA over the full operating temperature range. However, the maximum output current capability should be derated by the junction temperature. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. The LP2966 is available in VSSOP-8 package. This package has a junction to ambient temperature coefficient (ja) of 235 C/W with minimum amount of copper area. The total power dissipation of the device is approximately given by: PD = (Vin - VOUT1)IOUT1 + (Vin-VOUT2)IOUT2 (1) The maximum power dissipation, PDmax, that the device can tolerate can be calculated by using the formula: PDmax = (Tjmax - TA)/ja where * * Tjmax is the maximum specified junction temperature (125C) TA is the ambient temperature (2) Figure 33 through Figure 37 show the variation of thermal coefficient with different layout scenarios. Figure 33. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LP2966 13 LP2966 SNVS028E - APRIL 2000 - REVISED APRIL 2013 14 www.ti.com Figure 34. Figure 35. Figure 36. Figure 37. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LP2966 LP2966 www.ti.com SNVS028E - APRIL 2000 - REVISED APRIL 2013 REVISION HISTORY Changes from Revision D (April 2013) to Revision E * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 14 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LP2966 15 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LP2966IMM-1833/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LCFB LP2966IMM-2525/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LAAB LP2966IMM-3325 NRND VSSOP DGK 8 1000 TBD Call TI Call TI LARB LP2966IMM-3325/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM LARB LP2966IMM-5050/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM LP2966IMMX-3325/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LAFB LARB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP2966IMM-1833/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2966IMM-2525/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2966IMM-3325 VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2966IMM-3325/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2966IMM-5050/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2966IMMX-3325/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP2966IMM-1833/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP2966IMM-2525/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP2966IMM-3325 VSSOP DGK 8 1000 210.0 185.0 35.0 LP2966IMM-3325/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP2966IMM-5050/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP2966IMMX-3325/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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