LP2966
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Dual 150mA Ultra Low-Dropout Regulator
Check for Samples: LP2966
1FEATURES KEY SPECIFICATIONS
2 Ultra Low Drop-Out Voltage Dropout Voltage: Varies Linearly with Load
Current. Typically 0.9 mV at 1mA Load Current
Low Ground Pin Current and 135mV at 150mA Load Current
<1µA Quiescent Current in Shutdown Mode Ground Pin Current: Typically 300µA at 1mA
Independent Shutdown of Each LDO Regulator Load Current and 340µA at 100mA Load
Output Voltage Accuracy ±1% Current (with One Shutdown Pin Pulled Low)
Ensured 150mA Output Current at Each Shutdown Mode: Less than A Quiescent
Output Current when Both Shutdown Pins are Pulled
Low Output Noise Low
Error Flags Indicate Status of Each Output Error Flag: Open Drain Output, Goes Low
Available in VSSOP-8 Surface Mount Package when the Corresponding Output Drops 10%
Below Nominal
Low Output Capacitor Requirements (1µF) Precision Output Voltage: Multiple Output
Operates with Low ESR Ceramic Capacitors in Voltage Options Available Ranging from 1.8V
Most Applications to 5.0V with an Ensured Accuracy of ±1% at
Over Temperature/Over Current Protection Room Temperature
-40°C to +125°C Junction Temperature Range DESCRIPTION
APPLICATIONS The LP2966 dual ultra low-dropout (LDO) regulator
Cellular and Wireless Applications operates from a +2.70V to +7.0V input supply. Each
output delivers 150mA over full temperature range.
Palmtop/Laptop Computer The IC operates with extremely low drop-out voltage
GPS Systems and quiescent current, which makes it very suitable
Flat Panel Displays for battery powered and portable applications. Each
LDO in the LP2966 has independent shutdown
Post Regulators capability. The LP2966 provides low noise
USB Applications performance with low ground pin current in an
Hand Held Equipment and Multimeters extremely small VSSOP-8 package (refer to package
dimensions and CONNECTION DIAGRAM for more
Wireless Data Terminals information on VSSOP-8 package). A wide range of
Other Battery Powered Applications preset voltage options are available for each output.
In addition, many more are available upon request
with minimum orders. In all, 256 voltage combinations
are possible.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2000–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LP2966
SNVS028E APRIL 2000REVISED APRIL 2013
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TYPICAL APPLICATION CIRCUIT
*SD1 and SD2 must be actively terminated through a pull up resistor. Tie to VIN if not used.
**ERROR1 and ERROR2 are open drain outputs. These pins must be connected to ground if not used.
# Minimum output capacitance is 1µF to insure stability over full load current range. More capacitance improves
superior dynamic performance and provides additional stability margin.
BLOCK DIAGRAM
CONNECTION DIAGRAM
Top View
Figure 1. VSSOP-8 Package
8-Lead Small Outline Integrated Circuit
See Package Number DGK0008A
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PIN DESCRIPTIONS
Pin Name Function
1 VIN Input Supply pin
2 SD1 Active low shutdown pin for output 1
3 SD2 Active low shutdown pin for output 2
4 GND Ground
5 ERROR2 Error flag for output 2 - Normally high impedance, should be connected to ground if not used.
6 ERROR1 Error flag for output 1 - Normally high impedance, should be connected to ground if not used.
7 VOUT2 Output 2
8 VOUT1 Output 1
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Storage Temperature Range 65 to +150°C
Lead Temp. (Soldering, 5 sec.) 260°C
Power Dissipation(3) Internally Limited
ESD Rating(4) 2kV
Input Supply Voltage (Survival) 0.3V to 7.5V
Shutdown Input Voltage (Survival) 0.3V to (Vin + 0.3V)
Maximum Voltage for ERROR Pins 10V
IOUT (Survival) Short Circuit Protected
Output Voltage (Survival)(5)(6) 0.3V to (Vin + 0.3V)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see ELECTRICAL CHARACTERISTICS. The ensured specifications apply only for the test conditions listed. Some
performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) At elevated temperatures, devices must be derated based on package thermal resistance. The device in the surface-mount package
must be derated at θjA = 235°C/W, junction-to-ambient. Please refer to APPLICATIONS INFORMATION: Maximum Current Capability
for further information. The device has internal thermal protection.
(4) The human body model is a 100pF capacitor discharged through a 1.5kΩresistor into each pin.
(5) If used in a dual-supply system where the regulator load is returned to a negative supply, the LP2966 output must be diode-clamped to
ground.
(6) The output PMOS structure contains a diode between the VIN and VOUT terminals that is normally reverse-biased. Reversing the polarity
from VIN and VOUT will turn on this diode.
OPERATING RATINGS(1)
Input Supply Voltage 2.7V to 7.0V
Shutdown Input Voltage 0.3V to (Vin + 0.3V)
Operating Junction Temperature Range 40°C to +125°C
Maximum Voltage for ERROR pins 10V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see ELECTRICAL CHARACTERISTICS. The ensured specifications apply only for the test conditions listed. Some
performance characteristics may degrade when the device is not operated under the listed test conditions.
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ELECTRICAL CHARACTERISTICS
Limits in standard typeface are for Tj= 25°C, and limits in boldface type apply over the full operating junction temperature
range. Unless otherwise specified, VIN = VO(NOM) + 1V(1), COUT = 1µF, IOUT = 1mA, CIN = F, VSD1 = VSD2 = VIN.
LP2966IMM(3)
Symbol Parameter Conditions Typ(2) Unit
Min Max
Vo(4) Output Voltage VOUT + 1V < VIN < 7.0V 0.0 1 1 %VNOM
Tolerance -3 3
1mA < IL< 100mA 0.0 1.5 1.5 %VNOM
-3.5 3.5
ΔVO/ΔVIN(4)(5) Output Voltage Line 0.1 mV/V
Regulation
ΔVO/ΔIOUT Output Voltage Load 1mA < IL< 100mA(6) 0.1 mV/mA
Regulation(6)
ΔVO2/ΔIOUT1 Output Voltage Cross 1mA < IL1< 100mA(7) 0.0004 mV/mA
Regulation(7)
VIN -VOUT Dropout Voltage(8) IL= 1mA 0.9 2.0
3.0
IL= 100mA 90 130 mV
180
IL= 150mA 135 195
270
IGND(1,0)(9) Ground Pin Current IL= 1mA 300
(One LDO On) VSD2 0.1V, VSD1= VIN µA
IL= 100mA 340
VSD2 0.1V, VSD1= VIN
IGND(1,1) Ground Pin Current IL= 1mA 340 450
(Both LDOs On) 500 µA
IL= 100mA 420 540
600
IGND(0,0) Ground Pin Current in VSD1= VSD2 0.1V 0.006 0.3 µA
Shutdown Mode 10
IO(PK) Peak Output Current See(10) 500 350 mA
VOUTVOUT(NOM)- 5% 150
Short Circuit Foldback Protection
IFB Short Circuit Foldback See(10)(11) 600 mA
Knee
(1) The condition VIN = VO(NOM) + 1V applies when Vout1 = Vout2. If Vout1 Vout2, then this condition would apply to the output which is
greater in value. As an example, if Vout1 = 3.3V and Vout2 = 5V, then the condition VIN = VO(NOM)+ 1V would apply to Vout2 only.
(2) :Typical numbers are at 25°C and represent the most likely parametric norm.
(3) :Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using
Statistical Quality Control (SQC) methods. The limits are used to calculate Averaging Outgoing Quality Level (AOQL).
(4) Output voltage tolerance specification also includes the line regulation and load regulation.
(5) Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in input line voltage.
(6) Output voltage load regulation is defined as the change in output voltage from the nominal value when the load current changes from
1mA to 100mA.
(7) Output voltage cross regulation is defined as the percentage change in the output voltage from the nominal value at one output when
the load current changes from 1mA to full load in the other output. This is an important parameter in multiple output regulators. The
specification for ΔVO1/ΔIOUT2 is equal to the specification for ΔVO2/ΔIOUT1.
(8) Dropout voltage is defined as the input to output differential at which the output voltage drops 100mV below the nominal value. Drop-out
voltage specification applies only to output voltages greater than 2.7V. For output voltages below 2.7V, the drop-out voltage is nothing
but the input to output differential, since the minimum input voltage is 2.7V.
(9) The limits for the ground pin current specification, IGND(0,1) will be same as the limits for the specification, IGND(1,0).
(10) At elevated temperatures, devices must be derated based on package thermal resistance. The device in the surface-mount package
must be derated at θjA = 235°C/W, junction-to-ambient. Please refer to APPLICATIONS INFORMATION: Maximum Current Capability
for further information. The device has internal thermal protection.
(11) LP2966 has fold back current limited short circuit protection. The knee is the current at which the output voltage drops 10% below the
nominal value.
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ELECTRICAL CHARACTERISTICS (continued)
Limits in standard typeface are for Tj= 25°C, and limits in boldface type apply over the full operating junction temperature
range. Unless otherwise specified, VIN = VO(NOM) + 1V(1), COUT = 1µF, IOUT = 1mA, CIN = 1µF, VSD1 = VSD2 = VIN.
LP2966IMM(3)
Symbol Parameter Conditions Typ(2) Unit
Min Max
Over Temperature Protection
Tsh(t) Shutdown Threshold 165 °C
Tsh(h) Thermal Shutdown 25 °C
Hysteresis
Shutdown Input
VSDT Shutdown Threshold(12) Output = Low 0 0.1 V
Output = High VIN VIN - 0.1
TdOFF Turn-off Delay(13) IL= 100 mA 20 µsec
TdON Turn-on Delay(13) IL= 100 mA 25 µsec
ISD SD Input Current VSD = VIN 1nA
VSD = 0 V 1
Error Flag Comparators
VTThreshold (output goes See(14) 10 5 16 %
high to low)
VTH Threshold Hysteresis See(14) 52 8 %
VERR(Sat) Error Flag Saturation IFsink = 100µA 0.015 0.1 V
IEF(leak) Error Flag Pin Leakage 1 nA
Current
I(EFsink) Error Flag Pin Sink 1 mA
Current
AC Parameters
PSRR Ripple Rejection VIN = VOUT + 1V, f = 120Hz, 60
VOUT = 3.3V dB
VIN = VOUT + 0.3V, f = 120Hz, 40
VOUT = 3.3V
ρn(1/f) Output Noise Density f =120Hz 1 µV/Hz
enOutput Noise Voltage BW = 10Hz 100kHz, 150
(rms) COUT = 10µF µV(rms)
BW = 300Hz 300kHz, 100
COUT = 10µF
(12) VSDT is the shutdown pin voltage threshold below which the output is disabled.
(13) Turn-on delay is the time interval between the low to high transition on the shutdown pin to the output voltage settling to within 5% of the
nominal value. Turn-off delay is the time interval between the high to low transition on the shutdown pin to the output voltage dropping
below 50% of the nominal value. The external load impedance influences the output voltage decay in shutdown mode.
(14) Error Flag threshold and hysteresis are specified as the percentage below the regulated output voltage.
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified, VIN =VO(NOM) + 1V, VOUT= 3.3V, COUT =1µF, IOUT = 1mA, CIN =1µF, VSD1 = VSD2 = VIN, and TA=
25°C.
Ground Pin Current vs Supply Voltage (one LDO on) Ground Pin Current vs Supply Voltage (both LDOs on)
Figure 2. Figure 3.
Ground Pin Current vs Load Current over temperature Ground Pin Current vs Load Current over temperature
(one LDO on) (both LDOs on)
Figure 4. Figure 5.
Output Voltage vs Temperature Drop-out Voltage vs Temperature
Figure 6. Figure 7.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, VIN =VO(NOM) + 1V, VOUT= 3.3V, COUT =1µF, IOUT = 1mA, CIN =1µF, VSD1 = VSD2 = VIN, and TA=
25°C. Input Voltage vs Output Voltage Ground Pin Current vs Shutdown Pin Voltage
Figure 8. Figure 9.
Ground Pin Current vs Input Voltage (Both LDOs off) Short-Circuit Foldback Protection
Figure 10. Figure 11.
Line Transient Response Line Transient Response
(COUT = 2.2µF, IOUT = 1mA) (COUT = 2.2µF, IOUT = 1mA)
Figure 12. Figure 13.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, VIN =VO(NOM) + 1V, VOUT= 3.3V, COUT =1µF, IOUT = 1mA, CIN =1µF, VSD1 = VSD2 = VIN, and TA=
25°C. Line Transient Response Line Transient Response
(COUT = 2.2µF, IOUT = 100mA) (COUT = 2.2µF, IOUT = 100mA)
Figure 14. Figure 15.
Line Transient Response Line Transient Response
(COUT = 10µF, IOUT = 1mA) (COUT = 10µF, IOUT = 1mA)
Figure 16. Figure 17.
Line Transient Response Line Transient Response
(COUT = 10µF, IOUT = 100mA) (COUT = 10µF, IOUT = 100mA)
Figure 18. Figure 19.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, VIN =VO(NOM) + 1V, VOUT= 3.3V, COUT =1µF, IOUT = 1mA, CIN =1µF, VSD1 = VSD2 = VIN, and TA=
25°C. Load Transient Response (COUT = 2.2µF) Load Transient Response (COUT = 10µF)
Figure 20. Figure 21.
Load Transient Response (COUT = 10µF) Load Transient Response (COUT = 2.2µF)
Figure 22. Figure 23.
Cross-Channel Isolation vs Frequency Cross-Channel Isolation vs Frequency
(IOUT1 =1mA, IOUT2 = 1mA) (IOUT1 = IOUT2 = 100mA)
Figure 24. Figure 25.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, VIN =VO(NOM) + 1V, VOUT= 3.3V, COUT =1µF, IOUT = 1mA, CIN =1µF, VSD1 = VSD2 = VIN, and TA=
25°C. Output Voltage Cross-Coupling Output Noise Density
Figure 26. Figure 27.
Power Supply Ripple Rejection Peak Output Current vs Temperature
Figure 28. Figure 29.
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APPLICATIONS INFORMATION
Input Capacitor Selection
LP2966 requires a minimum input capacitance of 1µF between the input and ground pins to prevent any
impedance interactions with the supply. This capacitor should be located very close to the input pin. This
capacitor can be of any type such as ceramic, tantalum, or aluminium. Any good quality capacitor which has
good tolerance over temperature and frequency is recommended.
Output Capacitor Selection
The LP2966 requires a minimum of 1µF capacitance on each output for proper operation. To insure stability, this
capacitor should maintain its ESR (equivalent series resistance) in the stable region of the ESR curves
(Figure 30 and Figure 31) over the full operating temperature range of the application. The output capacitor
should have a good tolerance over temperature, voltage, and frequency. The output capacitor can be increased
without limit. Larger capacitance provides better stability and noise performance. The output capacitor should be
connected very close to the Vout pin of the IC.
Figure 30. ESR Curve for VOUT = 5V and COUT = Figure 31. ESR Curve for VOUT = 3.3V and COUT =
2.2µF 2.2µF
LP2966 works best with Tantalum capacitors. However, the ESR and the capacitance value of these capacitors
vary a lot with temperature, voltage, and frequency. So while using Tantalum capacitors, it should be ensured
that the ESR is within the limits for stability over the full operating temperature range.
For output voltages greater than 2.5V, good quality ceramic capacitors (such as the X7R series from
Taiyoyuden) can also be used with LP2966 in applications not requiring light load operation (< 5mA for the 5V
output option). Once again, it should be ensured that the capacitance value and the ESR are within the limits for
stability over the full operating temperature range.
The ESRD Series Polymer Aluminium Electrolytic capacitors from Cornell Dubilier are very stable over
temperature and frequency. The excellent capacitance and ESR tolerance of these capacitors over voltage,
temperature and frequency make these capacitors very suitable for use with LDO regulators.
Output Noise
Noise is specified in two ways:
Spot Noise or Output Noise Density is the RMS sum of all noise sources, measured at the regulator output, at
a specific frequency (measured with a 1Hz bandwidth). This type of noise is usually plotted on a curve as a
function of frequency.
Total Output Noise or Broad-Band Noise is the RMS sum of spot noise over a specified bandwidth, usually
several decades of frequencies.
Attention should be paid to the units of measurement. Spot noise is measured in units µV/Hz or nV/Hz and
total output noise is measured in µV(rms).
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The primary source of noise in low-dropout regulators is the internal reference. In CMOS regulators, noise has a
low frequency component and a high frequency component, which storngly depend on the silicon area and
quiescent current. Noise can be reduced in two ways: by increasing the transistor area or by increasing the
current drawn by the internal reference. Increasing the area will increase the die size and decreases the chance
of fitting the die into a small package. Increasing the current drawn by the internal reference increases the total
supply current (ground pin current) of the IC. Using an optimized trade-off of ground pin current and die size,
LP2966 achieves low noise performance with low quiescent current in an VSSOP-8 package.
Short-Circuit Foldback Protection
In the presence of a short or excessive load current condition, the LP2966 uses an internal short circuit foldback
mechanism that regulates the maximum deliverable output current. A strong negative temperature coefficient is
designed into the circuit to enable extremely higher peak output current capability (in excess of 400mA per output
at room temperature, see TYPICAL PERFORMANCE CHARACTERISTICS ). Thus, a system designer using the
LP2966 can achieve higher peak output current capability in applications where the LP2966 internal junction
temperature is kept below 125°C. Refer to APPLICATIONS INFORMATION on calculating the maximum output
current capability of the LP2966 for your application.
Error Flag Operation
The LP2966 produces a logic low signal at the Error Flag pin (ERROR) when the corresponding output drops out
of regulation due to low input voltage, current limiting, or thermal limiting. This flag has a built in Hysteresis. The
timing diagram in Figure 32 shows the relationship between the ERROR and the output voltage. In this example,
the input voltage is changed to demonstrate the functionality of the Error Flag.
Figure 32. Error Flag Operation
The internal error flag comparators have open drain output stages. Hence, the ERROR pins should be pulled
high through a pull up resistor. Although the ERROR pin can sink current of 1mA, this current adds to the battery
drain. Hence, the value of the pull up resistor should be in the range of 100kto 1M.The ERROR pins must
be connected to ground if this function is not used. It should also be noted that when the shutdown pins are
pulled low, the ERROR pins are forced to be invalid for reasons of saving power in shutdown mode.
Shutdown Operation
The two LDO regulators in the LP2966 have independent shutdown. A CMOS Logic level signal at the shutdown
(SD) pin will turn-off the corresponding regulator. Pins SD1 and SD2 must be actively terminated through a
100kpull-up resistor for a proper operation. If these pins are driven from a source that actively pulls high and
low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. These pins must be tied to Vin if
not used.
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Drop-Out Voltage
The drop-out voltage of a regulator is defined as the minimum input-to-output differential required to stay within
100mV of the output voltage measured with a 1V differential. The LP2966 uses an internal MOSFET with an
Rds(on) of 1. For CMOS LDOs, the drop-out voltage is the product of the load current and the Rds(on) of the
internal MOSFET.
Reverse Current Path
The internal MOSFET in the LP2966 has an inherent parasitic diode. During normal operation, the input voltage
is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is pulled above
the input in an application, then current flows from the output to the input as the parasitic diode gets forward
biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to
150mA.
Maximum Output Current Capability
Each output in the LP2966 can deliver a current of more than 150mA over the full operating temperature range.
However, the maximum output current capability should be derated by the junction temperature. Under all
possible conditions, the junction temperature must be within the range specified under operating conditions. The
LP2966 is available in VSSOP-8 package. This package has a junction to ambient temperature coefficient (θja) of
235 °C/W with minimum amount of copper area. The total power dissipation of the device is approximately given
by: PD= (Vin - VOUT1)IOUT1 + (Vin-VOUT2)IOUT2 (1)
The maximum power dissipation, PDmax, that the device can tolerate can be calculated by using the formula:
PDmax = (Tjmax - TA)/θja
where
Tjmax is the maximum specified junction temperature (125°C)
TAis the ambient temperature (2)
Figure 33 through Figure 37 show the variation of thermal coefficient with different layout scenarios.
Figure 33.
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Figure 34. Figure 35.
Figure 36. Figure 37.
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REVISION HISTORY
Changes from Revision D (April 2013) to Revision E Page
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LP2966IMM-1833/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LCFB
LP2966IMM-2525/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LAAB
LP2966IMM-3325 NRND VSSOP DGK 8 1000 TBD Call TI Call TI LARB
LP2966IMM-3325/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM LARB
LP2966IMM-5050/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LAFB
LP2966IMMX-3325/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM LARB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
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Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LP2966IMM-1833/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LP2966IMM-2525/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LP2966IMM-3325 VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LP2966IMM-3325/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LP2966IMM-5050/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LP2966IMMX-3325/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 1