BCM8211
®
2.488 GBPS SONET/SDH TRANSCEIVER WITH INTERNAL LOOP TIMING
BCM8211 Application Block Diagram
•2.488- Gbps SONET/SDH transceiver with dual differential
serial I/O
•Fully integrated CDR, MUX, DEMUX, and CMU
•Selectable LVP E CL/CMOS 16-bit, 155.52-Mbps interface to
framer or networ k pr oce s sor
•On-chip PLL-based clock generator
•Line and system loopback modes
•Loss-of-signal output (LOSB) and input (LOSIB)
•TX and RX lock detect
•Elastic buffering with FIFO overflow alarm
•Selectabl e 77.76/155.52-MHz reference clock
•Selectable RX clock and RX data squelch on LOS
•Selectable loop timing mode
•Single 2.5V or dual 2.5V/3.3V supplies
•Power dissipation: 1.2W typical
•14 ∞ 20 mm, 128-pin PQ FP package
•Standard CMOS fabrication process
•Low power consum ptio n el iminates external heat sinks , fan s
for s yst em ai rflo w, an d exp ensi ve hi gh cu rren t pow er su ppli es.
•Supports SONET dual-fib er ring architecture .
•High integration reduces design cycle and tim e to market.
•Provides increased port density per board and system.
•CMOS-based d evice uses th e most effective silicon econom y of
scale.
•Meets SONET jitter requirements.
•Fea t ures lo w ji t t e r: 3 mU I rms typical.
FEATURES SUMMARY OF BENEFITS
•OC-48/STM-16 transmission equipment
•SONET/SDH optical modules
•ADD/DROP multiplexers
•Digital cr o ss- co n nect s
•ATM switch backbone
•SONET/SDH test equipment
•Terabit and edge routers
APPLICATIONS
155
.
52
M
bp
s
2
.
488
G
bp
s
155
.
52
M
bp
s
N
e
t
wo
r
k
I
n
t
e
r
f
ace
P
r
o
cess
o
r
N
e
t
wo
r
k
I
n
t
e
r
f
ace
P
r
o
cess
o
r
OTX O
R
X
O
R
X OTX
BCM8211
BCM8211
16
16
16
16
OVERVIEW
®
Phone: 949-450-8700
Fax: 949-450-8710
E-mail: info@broadcom.com
Web: www.broadcom.com
BROADCOM CORPORATION
16215 Alton Parkway, P.O. Box 57013
Irvine, California 92619-7013
© 2004 by BROADCOM CORPORATION. All rights reserved.
8211-PB06-R 07/02/04
Broadcom®, the pulse logo, and Connecting everything® are trademarks of Broadcom Corporation and/
or its subsidiaries in the United States and certain other countries. All other trademarks mentioned are the
property of their respective owners.
The BCM8211 SONET/SDH transceiver is a fully integrated
serialization/deserialization SONET OC-48 and SDH STM-16 (2.488
Gbps) interface device with an integrated Clock Multiplication Unit
(CMU) and an inte grated Clock and Data Recovery (CDR) circuit. On-
chip clock synthesis is performed by the high-frequency, low-jitter,
phase-locked loop on the BCM8211 transceiver, allowing the use of a
slower 77.76/155.52 MHz external transmit clock reference.
Dual RX and TX 2.488-Gbps interfaces support dual-fiber ring
architectures. Clock recovery is performed on the device by
synchronizing its on -chip VCO dire ctly to the incoming data stream .
The low-jitter LVPECL/CMOS interface guarantees compliance with
the bit error rate requirements of the Telcordia GR-253-CORE, ANSI,
and I TU - T s ta n da r ds . Th e B C M 8211 is p a ck a ge d in a 14 x 20 mm , 128-
pin PQFP.
The BCM8211 operates in either single 2.5V or dual 2.5/3.3V
configuration. The core and CM L I/O operate at 2.5V and the LVPECL
I/O can op erate at either 2.5 V or 3.3V.
F
F
C
D
E
CLK16IP
CLK16IN
DI0
DI15
RESETB
CKSEL
RTSYNC
REF155EN
TXDP
TXDN
TXCKP
TXCKN
TCK16ON
TCK16OP
TXLKDT
RCK16ON
RCK16OP
DO0
DO15
LOSB
RXLKDT
OVFB
REFCKP
REFCKN
DOSQ
RCK16SQ
RDINP0
RDINN0
RDINP1
RDINN1
SELRD1
CLKPMODE
DATPMODE
LOSIB
LP BKFB
TSEL
LPBKSB
A
W
r
i
t
e
P
oin
t
e
r
R
ea
d
P
oin
t
e
r
16
x
5
FIFO
O
u
t
pu
t
R
e
t
i
m
e
FIFO
C
on
t
r
ol
16
:
1
P
a
r
a
ll
e
l
-
t
o
-
S
e
r
i
a
l
I
npu
t
R
e
gi
s
t
e
r
D
E
C
B
E
D
A
B
M
U
X
2
.
488
-
G
H
z
PLL
M
U
X
D
i
v
id
e
-
b
y
-
16
O
u
t
pu
t
R
e
gi
s
t
e
r
1
:
16
S
e
r
i
a
l
-
t
o
-
P
a
r
a
ll
e
l
M
U
X
CDR
D
i
v
id
e
-
b
y
-
16
L
oop
-
b
ack
L
ogi
c
L
o
ss
D
e
t
ec
t
