4309-00 - Peregrine Semiconductor

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This product is a high linearity, 6-bit RF Digital Step Attenuator

(DSA) covering a 31.5 dB attenuation range in 0.5 dB steps.

The Peregr i n e 50Ω RF DSA provides a parallel CMOS control

interface and it operates on 3-volt to 5-volt su pply. It maintains

high attenuation accuracy over frequency and temperature and

exhibits very low insertion loss and low power consumption.

This Peregrine DSA is available in a 4x4 mm 24 lead QFN

footprint with an exposed ground paddle.

The PE4309 is manufactured on Peregrine’s UltraCMOS™

pro cess, a patented variation of silicon-on-in sulator (SO I)

technology on a sapphire substrate, offering the performance

of GaAs with the econom y an d i nte gr ation of conventi on al

CMOS.

Advance Informati on

50 Ω RF Digital Atte nuator

6-bit, 31.5 dB, DC-4.0 GHz

Product Description

Figure 1. Functional Schematic Diagram

PE4309

Features

• Best in class 2.0 kV HBM ESD tolerance

• Low Insertion Loss: 1.6 dB typical

• Attenuation: 0.5 dB s te ps t o 31 .5 dB

• High Linearity: Typical 52 dB IP3

• Best in Class Attenuation accuracy

• Parallel programming interface

• Single supply, 3V to 5V operation

• Stand ar d 3V or 5V CMO S control logi c

independent of supply voltage

• Very low power consumption

• RoHS-compliant 24-lead 4x4 mm QFN

Control Logic Interface

Parallel Control

RF Input RF Output

Switched Attenuator Array

6

Table 1. Electrical Specifications @ +25°C, VDD = 3.0 V - 5.0 V

Notes: 1. Device Linearity will begin to degrade below 1 Mhz

2. Note Absolute Maximum in Table 4.

Fig ur e 2. Pa ck ag e Typ e

4x4 mm 24-Lead QFN

Parameter Test Conditions Frequency Minimum Typical Maximum Units

Operation Frequency DC 4000 MHz

Inser t io n Los s DC - 2.2 GHz

2.2 - 4.0 GHz - 1.6

2.2 dB

dB

Attenuation Accuracy Any Bit or Bit Combination DC ≤ 1.0 GHz

1.0 < 2.8 GHz

2.8 - 3.8 GHz - -

±(0.10 + 3% of atten setting)

±(0.15 + 4% of atten setting)

±(0.20 + 5% of atten setting)

dB

1 dB Compression2 1 MHz - 2.2 GHz

2.2 - 4.0 GHz 32

30 - dBm

dBm

Input IP3 1 Two- t on e inputs +1 8 dBm 1 MHz - 2 .2 GHz - 52 dB m

Return Loss DC - 2.2 GHz

2.2 - 4.0 GHz 20

15 - dB

dB

Switching Speed 50% of control voltage to

90% of final attenuation level - - 1

µs

Advance Information

PE4309

Page 2 of 6

Exposed

Ground

Paddle

N/C

VDD

N/C

RF1 RF2

N/C

C4

C2

C1

C 0.5

C8

N/C

24

23

22

21

20

19

7

8

9

10

11

12

18

17

16

15

14

13

2

3

4

5

6

1

C16

N/C

ACG ACG

ACG

GND

Table 2 . Pin Descriptions

Electrostatic Discharge (ESD) Precautions

When handling this Ult r aCM OS™ device, obs er v e the

same pr ec autions t hat you would us e with other ESD-

sensit iv e devices. Alt hough this devic e contains

circ uitry to protect it from damage due to ESD,

precautions should be taken t o av oid ex c eeding the

rate s pec ified in T able 4.

Expose d Solder Pad Connection

The expos ed s older pad on the bott om of t he pac k age

must be grounded f or pr oper dev ic e oper ation.

Figure 3. Pin Configuration (Top View)

Pin No. Pin Name Description

1 N/C3 No Connect

2 VDD Power supply pin

3 N/C3 No Connect

4 RF1 RF port

5 N/C3 No Connect

6 ACG4 AC Ground connection

7 ACG4 AC Ground connection

8 ACG4 AC Ground connection

9 ACG4 AC Ground connection

10 ACG4 AC Ground connection

11 ACG4 AC Ground connection

12 GND Ground connection.

13 ACG4 AC Ground connection

14 N/C3 No Connect

15 RF2 RF port

16 N/C3 No Connect

17 N/C3 No Connect

18 N/C3 No Connect

19 C16 Attenuation control bit, 16 dB

20 C8 Attenuation control bit, 8 dB

21 C4 Attenuation control bit, 4 dB

22 C2 Attenuation control bit, 2 dB

23 C1 Attenuation control bit, 1 dB

24 C0.5 Attenuation control bit, 0.5 dB

Pad dl e G ND Ground for pr op er operati on

Latc h-Up Avoidance

Unlike conventional CMOS devic es , Ultr aCMOS™

devices are immune to latc h- up.

Table 4. Absolute Maximum Ratings

Table 3. Operating Ranges

C16 C8 C4 C2 C1 C0.5 Attenuation State

1 1 1 1 1 1 Reference Loss (IL)

1 1 1 1 1 0 0.5 dB

1 1 1 1 0 1 1 dB

1 1 1 0 1 1 2 dB

1 1 0 1 1 1 4 dB

1 0 1 1 1 1 8 dB

0 1 1 1 1 1 16 dB

0 0 0 0 0 0 31.5 dB

Table 6. Truth Table

Symbol Parameter/Conditions Min Max Units

VDD Power supply voltage -0.3 6.0 V

VI Voltage on any DC input -0.3 6.0 V

TST Storage temperature range -65 150 °C

TOP Operating temperature

range -40 85 °C

PIN Input pow er (5 0Ω) 34 dBm

VESD ESD voltage (Human Body

Model) 2000 V

Parameter Min Typ Max Units

VDD Power Supply

Voltage 2.7 3.0 5.5 V

IDD Power Supply

Current 100 150 µA

Table 5. Control Voltage

State Bias Condition

Low 0 to +1.0 Vdc at 2 µA (typ)

High +2.0 to +5 Vdc at 10 µA (typ)

Notes: 3. For improved RF performance No Connect pins can be

connected to RF ground.

4. Pins can either be grounded directly or through coupling

capacitors

Advance Information

PE4309

Page 3 of 6

Evaluation Kit

The Di gi tal Att en ua t or E val u ation Kit bo ard w as

designed to eas e c ustomer ev aluation of the

PE4309 Digital Step Attenuator. Co nnect J2 by

mini clip to Vdd to power the IC. Connect J8 by

mini clip to power the evaluation board support

circuits. The control bits for the six parallel data

inputs (C0.5 to C16) are controlled using S2-S7 to

select bits or bit combinations. This allows any

attenuation setting to be specified as shown in

Table 6.

The de-embed trace (J6 to J7) estimate s the PCB

insertion loss for removal from the evaluation

board measurement data.

To evaluate using customer software, J1 can be

installed using a standard 0.100 IDC header

(some circuit modification required, see

schematic).

The ability to supply different voltages for the

Control circuitry (using J8) and IC Vdd (using J2)

circuits allows for evaluation of circuits using

different control vs. supply voltages.

Figure 4. Evaluation Board Layout

Figure 5. Evaluation Board Schematic

Peregr ine S pec ificat ion 101/0299

Peregr ine S pec ificat ion 102/0366

Advance Information

PE4309

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Fig ure 6. Package Dra win g

QFN 4x4 mm

A MAX 0.900

NOM 0.850

MIN 0.800

Advance Information

PE4309

Page 5 of 6

Table 7. Ordering Information

Or der Code Part Marking Description Package Shipping Method

4309-00 PE4309-EK PE4309-24QFN 4x4mm-EK Evaluation Kit 1 / Box

4309-51 4309 PE4309G-24QFN 4x4mm-75A Green 24-lead 4x4mm QFN 75 units / Tube

4309-52 4309 PE4309G-24QFN 4x4mm-3000C Green 24-lead 4x4mm QFN 3000 units / T&R

Figure 8. Marking Specifications

4309

YYWW

ZZZZZ

YYWW = Date Code

ZZZZZ = Last five digits of Lot Number

Figure 7. Tape and Reel Drawing

Advance Information

PE4309

Page 6 of 6

Sales Offices

The Americas

Peregrine Semiconductor Corporation

9450 Carroll Park Drive

San Diego, CA 92121

Tel: 858-731-9400

Fax: 858-731-9499

Europe

Peregrine Semiconductor Europe

Bâtiment Maine

13-15 rue des Quatre Vents

F-92380 Garches , France

Tel: +33-1-4741-9173

Fax : +33-1 -4741 -917 3

For a list of representatives in your area, please refer to our Web site at: www.psemi.com

Data Sheet Identification

Advance Information

The product is in a formative or design stage. The dat a

sheet contains design target specifications for product

development. Specif ications and features may change in

any manner without notice.

Preliminary Specification

The data sheet contains preliminar y data. Additional data

may be added at a later date. Peregrine reserves t he right

to change specifications at any time without notice in or der

to supply t he best possible product.

Product Specification

The data sheet con tains final data. In the event Peregrine

dec ide s to cha nge the spe c ific ations, Pereg rine will not ify

customers of t he intended changes by is s u ing a DCN

(Document Change Notice).

The information in this dat a sheet is believed to be reliable.

Howeve r, Peregrine assum es no liabilit y for the use of this

information. Use shall be entirely at t he user’s own risk.

No patent rights or licenses t o any circuits described in this

data sheet are implied or granted to any third party.

Peregrine’s pr oducts are not designed or int ended for use in

devices or systems intended f or surgical implant, or in other

applications intended t o support or sustain life, or in any

application in which the failure of the Peregrine product could

create a situat ion in which personal injury or death might occur.

Peregr ine assumes no liability for damages, including

consequential or incidental damages, arising out of the use of

its products in such applications.

The Peregrine name, logo, and UTSi are registered t r ademarks

and UltraCM O S and HaRP ar e tr ademarks of Peregrine

Semiconductor Cor p.

Spa ce and De fense Products

Americas:

Tel: 858-731-9453

Europe, Asia Pacific:

180 Rue Jean de G uir amand

13852 Aix-En-Provence Cedex 3, France

Tel: +33-4-4239-3361

Fax: +33-4-4239-7227

Peregri ne Semiconductor, Asia Pacific (APAC)

Shanghai, 200040, P.R. China

Tel: +86-21-5836-8276

Fax: +86-21-5836-7652

Peregrine Semiconductor, Korea

#B-2607, Kolon Tripolis, 210

Geumgok-dong, Bundang- gu, Seongnam-si

Gyeonggi-do, 463-943 Sout h Korea

Tel: +82-31-728-3939

Fax: +82-31-728-3940

Peregrine Semiconductor K.K., Japan

Teiko k u Hote l Tower 10B-6

1- 1-1 Uchisa iwa i-ch o, Ch iy oda- k u

Tokyo 100-0011 Japan

Tel: +81-3-3502-5211

Fax: +81-3-3502-5213