AAT3603IIH-T1 - Advanced Analog Technology, Inc.

AAT3603178

Total Power Solution for Portable Applications

PRODUCT DATASHEET

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General Description

The AAT3603 is a member of AnalogicTech’s Total Power

Management ICTM (TPMICTM) product family. It contains a

single-cell Lithium Ion/Polymer battery charger, a fully

integrated step-down converter and 5 low dropout (LDO)

regulators. The device is ideal for low cost handheld por-

table GSM or CDMA mobile telephones.

The battery charger is a complete thermally regulated

constant current/constant voltage linear charger. It

includes an integrated pass device, reverse blocking pro-

tection, high accuracy current and voltage regulation,

charge status, and charge termination. The charging

current, charge termination current, and recharge volt-

age are programmable with an external resistor and/or

by a standard I2C interface.

The step-down DC/DC converter is integrated with internal

compensation and operates at a switching frequency of

1.5MHz, thus minimizing the size of external components

while keeping switching losses low and efficiency greater

than 95%. All LDO output voltages are programmable

using the I2C interface.

The five LDOs offer 60dB power supply rejection ratio

(PSRR) and low noise operation making them suitable for

powering noise-sensitive loads.

All six voltage regulators operate with low quiescent cur-

rent. The total no load current when the step-down con-

verter and 2 LDOs are enabled is only 170μA.

The AAT3603 is available in a thermally enhanced low

profile 5x5x0.8mm 36-pin TQFN package.

Features

• Voltage Regulator VIN Range: 4.5V to 6V

• Low Cost Power Integration

• Low Standby Current

▪ 170μA (typ) w/ Buck (Core), LDO1 (PowerDigital),

and LDO2 (PowerAnalog) Active, No Load

• One Step-Down Buck Converter (Core)

▪ 1.8V, 300mA Output

▪ 1.5MHz Switching Frequency

▪ Fast Turn-On Time (120μs typ)

• Five LDOs Programmable with I2C

▪ LDO1: 3.0V, 300mA (PowerDigital)

▪ LDO2: 3.0V, 150mA (PowerAnalog or PLL)

▪ LDO3: 3.0V, 150mA (TCXO)

▪ LDO4: 3.0V, 150mA (TX)

▪

LDO5: 3.0V, 150mA (RX)

▪ PSRR: 60dB@10kHz

▪ Noise: 50μVrms for LDO3, LDO4, and LDO5

• One Battery Charger

▪ Digitized Thermal Regulation

▪ Charge Current Programming up to 1.4A

▪ Charge Current Termination Programming

▪ Automatic Trickle Charge for Battery Preconditioning

(2.8V Cutoff)

•

Adapter OK (ADPP) and Reset (RESET) Timer Outputs

• Separate Enable Pins for Supply Outputs

• Over-Current Protection

• Over-Temperature Protection

• 5x5mm TQFN55-36 Package

Applications

• Digital Cameras

• GSM or CDMA Cellular Phones

• Handheld Instruments

• PDAs and Handheld Computers

• Portable Media Players

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Typical Application

LDO2

Enable

LDO1

Enable

LDO4

LDO5

Enable

LDO3

Enable

Step-down

BUCK

CHGIN

UVLO

BAT

PGND

PVIN

OUTBUCK

OUT1

OUT2

VIN

OUT3OUT4

OUT5

REF

AVIN2

EN5

EN4

EN3

EN_TEST

EN_HOLD

RESET

Ref

CNOISE

AGND

AVIN1

VIN

I2C

and

Enable

Control

EN_KEY

ON_KEY

SDA

SCL

ISET

Ref

Charger

Control

STAT

ADPP

ENBAT TS

EN2

10μF

5V from

C Adapter or USB Port

22μF

1 cell

Li+

battery

To BAT To BAT

To BAT

10μF

0.01μF

4.7μF

3.3μH Core : 1.8V

300mA

4.7μF 4.7μF 4.7μF 4.7μF 22μF

TCXO

3.0V

150mA

1.24k

10kΩ

NTC

For BAT

Temp sense

0.1μF

100k

To OUT1

100k

To BAT

100k

BAT

100k

BAT

μC

PowerDigital

3.0V

300mA

3.0V

150mA

PowerAnalog

3.0V

150mA

3.0V

150mA

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Pin Descriptions

Pin # Symbol Function

1 EN_TEST Similar to EN_HOLD but intended for use with the automatic tester or as a hands free enable input pin indi-

cating hands free phone operation with a headset. It is also internally pulled to GND when ﬂ oating.

2 EN_HOLD Enable for the system. EN_HOLD must be held high by the processor to maintain core power. It is internally

pulled to GND when ﬂ oating.

3EN_KEY

Enable for the system. An internal pull-up resistor keeps the pin pulled up to an internal supply to keep the

system off when there is no CHGIN input. Connect a normally-open pushbutton switch from this pin to GND.

There is an internal 300ms debounce delay circuit to ﬁ lter noise.

4ON_KEY Buffered logic output of the EN_KEY pin with a logic signal from ground to OUT1.

5 EN2 Enable for LDO2 (PowerAnalog or PLL). (Internally pulled low when ﬂ oating)

6 EN3 Enable for LDO3 (TCXO). (Internally pulled low when ﬂ oating)

7 EN4 Enable for LDO4 (TX) (Internally pulled low when ﬂ oating)

8 EN5 Enable for LDO5 (RX) (Internally pulled low when ﬂ oating)

9 OUT5 Output for LDO5 (RX) (when shut down, pulled down with 10kΩ)

10 OUT4 Output for LDO4 (TX) (when shut down, pulled down with 10kΩ)

11 AVIN2 Analog voltage input. Must be tied to BAT on the PCB.

12 OUT3 Output for LDO3 (TCXO)

13 OUT2 Output for LDO2 (PowerAnalog)

14 AVIN1 Analog voltage input. Must be tied to BAT on the PCB.

15 OUT1 Output for LDO1 (PowerDigital)

16 AGND Signal ground

17 CNOISE Noise Bypass pin for the internal reference voltage. Connect a 0.01μF capacitor to AGND.

18 RESET

RESET is the open drain output of a 50ms reset timer. RESET is released after the 50ms timer times out.

RESET is active low and is held low during shutdown. RESET should be tied to a 10K or larger pullup to

OUTBUCK.

19 ADPP

Open Drain output. Will pull low when VCHGIN > 4.5V. When this happens, depending on the status of the

USE_USB pin, the charge current will be reset to the default values (see Battery Charger and I2C Serial

Interface and Programmability section)

20 LX Step-down Buck converter (Core) switching node. Connect an inductor between this pin and the output.

21 PGND Power Ground for step-down Buck converter (Core)

22 PVIN Input power for step-down Buck converter (Core). Must be tied to BAT.

23 OUTBUCK Feedback input for the step-down Buck converter (Core)

24, 25 N/C No Connect; do not connect anything to these pins.

26, 27 BAT Connect to a Lithium Ion battery.

28, 29 CHGIN Power input from either external adapter or USB port.

30 ENBAT Active low enable for the battery charger (Internally pulled low when ﬂ oating)

31 TS Battery Temperature Sense pin with 75μA output current. Connect the battery’s NTC resistor to this pin and

ground.

32 ISET Charge current programming input pin (Tie a 1k to GND for maximum fast charge current). Can be used to

monitor charge current.

33 CT Charger Safety Timer Pin. A 0.1μF ceramic capacitor should be connected between this pin and GND. Con-

nect directly to GND to disable the timer function.

34 STAT Battery charging status pin output. Connected internally between GND and OUT1 (PowerDigital). Used to

monitor battery charge status.

35 SDA I2C serial data pin, open drain; requires a pullup resistor.

36 SCL I2C serial clock pin, open drain; requires a pullup resistor.

EP EP

The exposed thermal pad (EP) must be connected to board ground plane and pins 16 and 21. The ground

plane should include a large exposed copper pad under the package for thermal dissipation (see package

outline).

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Pin Configuration

TQFN55-36

(Top View)

EN_TEST

EN_HOLD

EN_KEY

ON_KEY

EN2

EN3

EN4

EN5

OUT5

BAT

N/C

OUTBUCK

PVIN

PGND

ADPP

SCL

SDA

STAT

ISET

ENBAT

CHGIN

OUT4

AVIN2

OUT3

OUT2

AVIN1

OUT1

AGND

CNOISE

RESET

10 11 12 13 14 15 16 17 18

36 35 34 33 32 31 30 29 28

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Absolute Maximum Ratings1

TA = 25°C unless otherwise noted.

Symbol Description Value Units

VIN Input Voltage, CHGIN, BAT -0.3 to 6.5 V

Power and logic pins Maximum Rating VIN + 0.3 V

TJOperating Junction Temperature Range -40 to 85 °C

TSStorage Temperature Range -65 to 150 °C

TLEAD Maximum Soldering Temperature (at leads, 10 sec) 300 °C

Recommended Operating Conditions2

Symbol Description Value Units

θJA Thermal Resistance 25 °C/W

PDMaximum Power Dissipation 4 W

1. Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation at conditions other than the operating conditions

specified is not implied. Only one Absolute Maximum rating should be applied at any one time.

2. Thermal Resistance was measured with the AAT3603 device on the 4-layer FR4 evaluation board in a thermal oven. The amount of power dissipation which will cause the

thermal shutdown to activate will depend on the ambient temperature and the PC board layout ability to dissipate the heat. See Figures 11-14.

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Total Power Solution for Portable Applications

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Electrical Characteristics1

VIN = 5V, VBAT = 3.6V, -40°C ≤ TA ≤ +85°C, unless noted otherwise. Typical values are TA = 25°C.

Symbol Description Conditions Min Typ Max Units

Power Supply

VIN CHGIN Input Voltage 4.5 6 V

IQBattery Standby Current Buck, LDO1 + LDO2, no load 170 μA

ISHDN Battery Shutdown Current EN_TEST, EN_HOLD, EN2, EN3, EN4, EN5

= GND, EN_KEY ﬂ oating 10.0 μA

UVLO

Under-Voltage Lockout for CHGIN CHGIN rising 4.25 4.5 V

CHGIN falling 4.15 V

Battery Under-Voltage Lockout BAT rising 2.6 V

BAT falling 2.35 V

IBAT Leakage Current from BAT Pin VBAT = 4V, VCHGIN = 0V 2 5 μA

Startup Timers

RESET Reset Timer Initiated when OUT1 = 90% of ﬁ nal value 35 ms

Charger Voltage Regulation

VBAT_REG Output Charge Voltage Regulation 0°C ≤ TA ≤ +70°C 4.158 4.200 4.242 V

VMIN Preconditioning Voltage Threshold (No trickle charge option available) 2.6 2.8 3.0 V

VRCH Battery Recharge Voltage Threshold

I2C Recharge Code = 00 (default) 4.00 V

I2C Recharge Code = 01 4.05 V

I2C Recharge Code = 10 4.10 V

I2C Recharge Code = 11 4.15 V

Charger Current Regulation

ICH_CC Constant-Current Mode Charge Current

RISET = 1.24k (for 0.8A), I2C ISET code =

100, VBAT = 3.6V, VCHGIN = 5.0V 864 960 1056 mA

I2C ISET Code = 000, VBAT = 3.6V 85 100 115

KI_SET Charge Current Set Factor: ICH_CC/IISET Constant Current Mode, VBAT = 3.6V 800 mA

ICH_PRE Preconditioning Charge Current RISET = 1.24kΩ12 %

ICH_CC

I2C ISET Code = 000 50 mA

ICH_TERM Charge Termination Threshold Current

I2C Term Code = 00 (default) 5

ICH_CC

I2C Term Code = 01 10

I2C Term Code = 10 15

I2C Term Code = 11 20

Charging Devices

RDS(ON) Charging Transistor ON Resistance VIN = 5V 0.6 0.9 Ω

Logic Control / Protection

VEN_HOLD,

VEN_KEY,

VEN_TEST

Input High Threshold 1.4 V

Input Low Threshold 0.4 V

VADPP Output Low Voltage Pin Sinks 4mA 0.4 V

IADPP Output Pin Current Sink Capability 8mA

VSTAT Output High Voltage VOUT1 V

ISTAT Output Pin Current Source Capability 1.5 mA

VOVP Over-Voltage Protection Threshold 4.3 V

1. Specification over the –40°C to +85°C operating temperature range is assured by design, characterization and correlation with statistical process controls.

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Electrical Characteristics1

VIN = 5V, VBAT = 3.6V, -40°C ≤ TA ≤ +85°C, unless noted otherwise. Typical values are TA = 25°C.

Symbol Description Conditions Min Typ Max Units

Logic Control / Protection (continued)

VOCP Over Current Protection Threshold 105 %VCS

TCConstant Current Mode Time Out

CCT = 100nF, VCHGIN = 5V

3 Hours

TKTrickle Charge Time Out TC/8 Hours

TVConstant Voltage Mode Time Out 3 Hours

ITS Current Source from TS Pin 71 75 79 μA

TS1TS Hot Temperature Fault Falling Threshold 318 331 346 mV

Hysteresis 25

TS2TS Cold Temperature Fault Rising Threshold 2.30 2.39 2.48 V

Hysteresis 25 mV

TLOOP_IN Thermal Loop Entering Threshold 115 °C

TLOOP_OUT Thermal Loop Exiting Threshold 85 °C

TREG Thermal Loop Regulation 100 °C

Step-Down Buck Converter (Core)

VOUTBUCK Output Voltage Accuracy IOUTBUCK = 0 ~ 300mA; VIN = 2.7V ~ 5.5V 1.71 1.80 1.89 V

ILIMOUTBUCK P-Channel Current Limit 0.8 A

RDS(ON)L High Side Switch On-Resistance 0.8 Ω

RDS(ON)H Low Side Switch On-Resistance 0.8 Ω

FOSC Oscillator Frequency TA = 25°C 1.5 MHz

TSStart-Up Time From Enable to Regulation; COUTBUCK =

4.7μF, C NOISE = On 100 μs

LDO1 (PowerDigital)

VOUT1 Output Voltage Accuracy IOUT1 = 0~300mA -3 +3 %

IOUT1 Output Current 300 mA

ILIM1 Output Current Limit 1000 mA

VDO1 Dropout Voltage IOUT1 = 300mA 160 320 mV

ΔVOUT1(VOUT1ΔVIN1) Line Regulation IOUT1 = 100mA 0.07 %/V

ΔVOUT1 Load Regulation IOUT1 = 0.5mA ~ 150mA 40 mV

PSRR Power Supply Rejection Ratio IOUT1 = 10mA, COUT1=22μF, 100Hz ~ 10KHz 60 dB

TSStart Up Time From Enable to Regulation; C OUT1 = 22μF,

CNOISE = On 175 μs

1. Specification over the –40°C to +85°C operating temperature range is assured by design, characterization and correlation with statistical process controls.

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Electrical Characteristics1

VIN = 5V, VBAT = 3.6V, -40°C ≤ TA ≤ +85°C, unless noted otherwise. Typical values are TA = 25°C.

Symbol Description Conditions Min Typ Max Units

LDO2 (PowerAnalog)

VOUT2 Output Voltage Accuracy IOUT2 = 0 ~ 150mA -3 +3 %

IOUT2 Output Current 150 mA

ILIM2 Output Current Limit 1000 mA

VDO2 Dropout Voltage IOUT2 = 150mA 165 mV

ΔVOUT2/

(VOUT2ΔVIN2)Line Regulation IOUT2 = 100mA 0.07 %/V

ΔVOUT2 Load Regulation Load: 0.5mA~150mA 40 mV

PSRR Power Supply Rejection Ratio IOUT2 = 10mA, COUT2 = 4.7μF, 10 ~ 10KHz 60 dB

Ts Start Up Time From Enable to Regulation; COUT2 = 4.7μF,

CNOISE = On 65 μs

LDO3 (TCXO), LDO4 (TX) and LDO5 (RX)

VOUTx Output Voltage Accuracy IOUTX = 0 ~ 150mA -3 +3 %

IOUTx Output Current 150 mA

ILIMx Output Current Limit 1000 mA

VDOx Dropout Voltage IOUTX = 150mA 165 mV

ΔVOUTx/

(VOUTxΔVINx)Line Regulation IOUTX = 100mA 0.07 %/V

ΔVOUTx Load Regulation IOUTX = 0.5mA ~ 150mA 40 mV

PSRR Power Supply Rejection Ratio IOUTX = 10mA, COUTx = 4.7μF, 10 ~ 10KHz 60 dB

eNOutput Noise Voltage

IOUTX = 10mA, Power BW: 10kHz ~ 100KHz

40 μVrms

Ts Start Up Time From Enable to Regulation; COUTX = 4.7μF,

CNOISE = On 65 μs

Logic Control

VIH Enable Pin Logic High Level For EN2, EN3, EN4 and EN5 1.4 V

VIL Enable Pin Logic Low Level 0.4 V

Thermal

TSD Over Temperature Shutdown Threshold 140 ˚C

THYS Over Temperature Shutdown Hysteresis 15 ˚C

SCL, SDA (I2C Interface)

FSCL Clock Frequency 0 400 KHz

TLOW Clock Low Period 1.3 μs

THIGH Clock High Period 0.6 μs

THD_STA Hold Time START Condition 0.6 μs

TSU_STA Setup Time for Repeat START 0.6 μs

TSU_DTA Data Setup Time 100 ns

TSU_STO Setup Time for STOP Condition 0.6 μs

TBUF

Bus Free Time Between STOP and

START Condition 1.3 μs

VIL Input Threshold Low 2.7V ≤ VIN ≤ 5.5V 0.4 V

VIH Input Threshold High 2.7V ≤ VIN ≤ 5.5V 1.4 - V

IIInput Current -1.0 1.0 μA

VOL Output Logic Low (SDA) IPULLUP = 3mA 0.4 V

1. Specification over the –40°C to +85°C operating temperature range is assured by design, characterization and correlation with statistical process controls.

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Basic I2C Timing Diagram

SU_STO

SU_STA

HD_STA

HIGH

LOW

SU_DAT

HD_DAT

SDA

SCL

BUF

HD_STA

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Typical Characteristics—Charger

Preconditioning Threshold Voltage

vs. Temperature

Temperature (°C)

VMIN (V)

2.790

2.792

2.794

2.796

2.798

2.800

2.802

2.804

2.806

2.808

2.810

-50 -25 0 25 50 75 100

VCHGIN = 6.0V

VCHGIN = 5.5V

VCHGIN = 5.0V VCHGIN = 4.5V

Preconditioning Charge Current vs. Temperature

(VBAT = 2.5V, RSET = 1.24kΩ)

Temperature (°C)

ICH_PRE (mA)

100

105

110

115

-50 -25 0 25 50 75 10

VCHGIN = 6.0V

VCHGIN = 5.5V

VCHGIN = 5.0V

VCHGIN = 4.5V

Recharge Voltage Threshold vs. Temperature

(VRCH set to 4.0V)

Temperature (°C)

VRCH (V)

3.96

3.97

3.98

3.99

4.00

4.01

4.02

4.03

4.04

4.05

4.06

-50 -25 0 25 50 75 100

VCHGIN = 6.0V

VCHGIN = 5.5V

VCHGIN = 5.0V

VCHGIN = 4.5V

Output Charge Voltage Regulation vs. Temperatur

(End of Charge Voltage)

Temperature (°C)

VBAT_REG (V)

4.16

4.17

4.18

4.19

4.20

4.21

4.22

4.23

4.24

4.25

-50 -25 0 25 50 75 100

VCHGIN = 6.0V

VCHGIN = 5.5V

VCHGIN = 5.0V VCHGIN = 4.5V

Charge Termination Threshold Current

vs. Temperature

Temperature (°C)

ICH_TERM (mA)

100

-50 -25 0 25 50 75 100

VCHGIN = 6.0V

VCHGIN = 5.5V

VCHGIN = 5.0V VCHGIN = 4.5V

Charging Current vs. Battery Voltage

(RISET = 1.24kΩ

)

Battery Voltage (V)

ICH (mA)

100

200

300

400

500

600

700

800

900

2.5 2.9 3.3 3.7 4.1 4.5

VCHGIN = 6.0V

VCHGIN = 5.5V

VCHGIN = 5.0V

VCHGIN = 4.5V

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Typical Characteristics—Charger (continued)

Constant Current Mode Charge Current

vs. Temperature

(VBAT = 3.6V; RISET = 1.24kΩ

)

Temperature (°C)

ICH_CC (mA)

300

400

500

600

700

800

900

-50 -25 0 25 50 75 100

VCHGIN = 6.0V

VCHGIN = 5.5V

VCHGIN = 5.0V

VCHGIN = 4.5V

Constant Current Mode Charge Current

vs. Input Voltage

(RSET = 1.24kΩ

)

CHGIN Voltage (V)

ICH_CC (mA)

700

720

740

760

780

800

820

840

860

880

900

4.5 4.75 5 5.25 5.5 5.75 6

VBAT = 3.3V

VBAT = 3.6V

VBAT = 4.1V

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Typical Characteristics—Step-Down Buck Converter

Step-Down Buck Efficiency vs. Output Current

(VOUT = 1.8V; L = 3.3µH)

Output Current (mA)

Efficiency (%)

100

1 10 100 1000

VBAT = 2.7V

VBAT = 4.2V

VCHGIN = 4.5V

VCHGIN = 5.0V

VCHGIN = 6.0V

VCHGIN = 5.5V

VBAT = 3.6V

Step-Down Buck Load Regulation

vs. Output Current

(VOUT = 1.8V; L = 3.3µH)

Output Current (mA)

Load Regulation (%)

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

1 10 100 1000

VBAT = 2.7V

VBAT = 4.2V

VCHGIN = 4.5V

VCHGIN = 5.0V

VCHGIN = 6.0V

VCHGIN = 5.5V

VBAT = 3.6V

Step-Down Buck Line Regulation

vs. CHGIN and Battery Input Voltage

(VOUT = 1.8V; L = 3.3µH)

Input VBAT, VCHGIN (V)

Line Regulation (%)

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

2.5 3 3.5 4 4.5 5 5.5 6

4.2

IOUT = 1mA

IOUT = 0.01mA

IOUT = 10mA

IOUT = 300mA

IOUT = 200mA

IOUT = 100mA

VBAT VCHGIN

IOUT = 50mA

Step-Down Buck Output Voltage vs. Temperature

(IOUT = 10mA)

Temperature (°C)

VOUT (V)

1.780

1.785

1.790

1.795

1.800

1.805

1.810

1.815

1.820

1.825

-50 -25 0 25 50 75 100

VCHGIN = 6.0V VBAT = 2.7V

VBAT = 3.6V

VBAT = 4.2V

VCHGIN = 4.5V

VCHGIN = 5.5V

VCHGIN = 5.0V

VBAT Line Transient Response Step-Down Buck

(VBAT = 3.5V to 4.2V; IOUT = 300mA; VOUT = 1.8V; COUT = 4.7µF)

Time (100µs/div)

Output Voltage (top) (V)

Input Voltage (bottom) (V)

1.76

1.80

1.84

1.88

1.92

3.0

3.5

4.0

4.5

VBAT

VCHGIN Line Transient Response Step-Down Buck

(VCHGIN = 4.5V to 5.5V; IOUT = 300mA; VOUT = 1.8V; COUT = 4.7µF)

Time (100µs/div)

Output Voltage (top) (V)

Input Voltage (bottom) (V)

1.76

1.78

1.80

1.82

1.84

1.86

4.0

4.5

5.0

5.5

6.0

CHGIN

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Typical Characteristics—Step-Down Buck Converter (continued)

Load Transient Response Step-Down Buck

(IOUTBUCK = 10mA to 100mA; VBAT = 3.6V;

VOUTBUCK = 1.8V; COUT = 4.7µF)

Time (100µs/div)

Output Voltage (top) (V)

Output Current

(bottom) (mA)

1.60

1.70

1.80

1.90

2.00

100

Load Transient Response Step-Down Buck

(IOUTBUCK = 100mA to 300mA; VBAT = 3.6V;

VOUTBUCK = 1.8V; COUT = 4.7µF)

Time (100µs/div)

Output Voltage (top) (V)

Output Current

(bottom) (mA)

1.60

1.70

1.80

1.90

2.00

100

200

300

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Typical Characteristics—LDO1

LDO1 Load Regulation vs. Output Current

(VOUT1 = 3.0V)

Output Current (mA)

Load Regulation (%)

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0.1 1 10 100 1000

VBAT = 4.2V

VBAT = 3.6V

VBAT = 3.3V

LDO1 Line Regulation vs. Battery

and CHGIN Input Voltage

(VOUT1 = 3.0V)

Input Voltage VBAT, VCHGIN (V)

Line Regulation (%)

-0.15

-0.13

-0.11

-0.09

-0.07

-0.05

-0.03

-0.01

0.01

0.03

0.05

3 3.5 4 4.5 5 5.5 6

IOUT = 0.01mA

IOUT = 1mA

IOUT = 10mA

IOUT = 50mA

IOUT = 100mA

IOUT = 200mA

IOUT = 300mA

4.2

VBAT VCHGIN

LDO1 Output Voltage vs. Temperature

(IOUT1 = 10mA)

Temperature (°C)

Output Voltage VOUT1 (V)

2.992

2.994

2.996

2.998

3.000

3.002

3.004

-50 -25 0 25 50 75 100

VCHGIN = 6.0V

VCHGIN = 5.5V

VCHGIN = 5.0V

VCHGIN = 4.5V

VBAT = 4.2V

VBAT = 3.6V

VBAT = 3.1V

LDO1 Dropout Characteristics vs. Input Voltage

(VOUT1 = 3.0V)

Input Voltage (V)

Output Voltage

VOUT1

(V)

2.80

2.85

2.90

2.95

3.00

3.05

3.10

3.0 3.1 3.2 3.3 3.4 3.5 3.

IOUT = 1mA

IOUT = 50mA

IOUT = 100mA

IOUT = 150mA

IOUT = 200mA

IOUT = 250mA

IOUT = 300mA

LDO1 Dropout Voltage vs. Output Current

(VOUT1 = 3.0V)

Output Current (mA)

Dropout Voltage (mV)

100

120

140

160

180

200

0 50 100 150 200 250 300

-40°C

25°C

85°C

VBAT Line Transient Response LDO1

(VBAT = 3.5V to 4.2V; IOUT1 = 300mA; VOUT1 = 3V)

Time (100µs/div)

Output Voltage (top) (V)

Input Voltage (bottom) (V)

2.98

2.99

3.00

3.01

3.02

3.0

3.5

4.0

4.5

VBAT

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Typical Characteristics—LDO1 (continued)

VCHGIN Line Transient Response LDO1

(VCHGIN = 4.5V to 5.5V; IOUT = 300mA; VOUT = 3V)

Time (100µs/div)

Output Voltage (top) (V)

Input Voltage (bottom) (V)

2.98

2.99

3.00

3.01

3.02

4.0

4.5

5.0

5.5

6.0

VCHGIN

Load Transient Response LDO1

(IOUT1 = 10mA to 100mA; VBAT = 3.6V; VOUT1 = 3V)

Time (100µs/div)

Output Voltage (top) (V)

Output Current

(bottom) (mA)

2.96

2.98

3.00

3.02

3.04

100

Load Transient Response LDO1

(IOUT1 = 100mA to 300mA; VBAT = 3.6V; VOUT1 = 3V)

Time (100µs/div)

Output Voltage (top) (V)

Output Current

(bottom) (mA)

2.96

2.98

3.00

3.02

3.04

100

200

300

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Typical Characteristics—LDO4

LDO4 Load Regulation vs. Output Current

(VOUT4 = 3.0V)

Output Current (mA)

Load Regulation (%)

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0.1 1 10 100 1000

VCHGIN = 4.5V

VCHGIN = 5.0V

VCHGIN = 5.5V

VCHGIN = 6.0V

LDO4 Load Regulation vs. Output Current

(VOUT4 = 3.0V)

Output Current (mA)

Load Regulation (%)

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0.1 1 10 100 100

VBAT = 4.2V

VBAT = 3.6V

VBAT = 3.3V

VBAT = 3.1V

LDO4 Output Voltage vs. Temperature

(IOUT4 = 10mA)

Temperature (°C)

Output Voltage VOUT4 (V)

2.990

2.992

2.994

2.996

2.998

3.000

3.002

3.004

3.006

3.008

-50 -25 0 25 50 75 100

VCHGIN = 6.0V

VCHGIN = 5.5V

VCHGIN = 5.0V

VCHGIN = 4.5V

VBAT = 4.2V

VBAT = 3.6V

VBAT = 3.1V

LDO4 Line Regulation vs. Battery

and CHGIN Input Voltage

(VOUT4 = 3.0V)

Input Voltage VBAT, VCHGIN (V)

Line Regulation (%)

-0.14

-0.12

-0.1

-0.08

-0.06

-0.04

-0.02

0.02

0.04

0.06

3 3.5 4 4.5 5 65.5

4.2

IOUT = 0.01mA

IOUT = 1mA

IOUT = 10mA

IOUT = 50mA

IOUT = 100mA

IOUT = 150mA

VBAT VCHGIN

LDO4 Dropout Characteristics vs. Input Voltage

(VOUT4 = 3.0V)

Input Voltage (V)

Output Voltage (V)

2.80

2.85

2.90

2.95

3.00

3.05

3.10

3.0 3.1 3.2 3.3 3.4 3.5 3.6

IOUT = 1mA

IOUT = 50mA

IOUT = 100mA

IOUT = 150mA

LDO4 Dropout Voltage vs. Output Current

(VOUT4 = 3.0V)

Output Current (mA)

Dropout Voltage (mV)

100

120

140

160

180

200

0 25 50 75 100 125 150

-40°C

25°C

85°C

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Typical Characteristics—LDO4 (continued)

VBAT Line Transient Response LDO4

(VBAT = 3.5V to 4.2V; IOUT4 = 150mA; VOUT4 = 3V)

Time (100µs/div)

Output Voltage (top) (V)

Input Voltage (bottom) (V)

2.98

2.99

3.00

3.01

3.02

3.0

3.5

4.0

4.5

VBAT

VCHGIN Line Transient Response LDO4

(VCHGIN = 4.5V to 5.5V; IOUT4 = 150mA; VOUT4 = 3V)

Time (100µs/div)

Output Voltage (top) (V)

Input Voltage (bottom) (V)

2.98

2.99

3.00

3.01

3.02

4.0

4.5

5.0

5.5

6.0

VCHGIN

Load Transient Response LDO4

(IOUT4 = 10mA to 75mA; VBAT = 3.6V;

VOUT4 = 3V; COUT = 4.7µF)

Time (100µs/div)

Output Voltage (top) (V)

Output Current

(bottom) (mA)

2.96

2.98

3.00

3.02

3.04

100

Load Transient Response LDO4

(IOUT4 = 75mA to 150mA; VBAT = 3.6V;

VOUT4 = 3V; COUT = 4.7µF)

Time (100µs/div)

Output Voltage (top) (V)

Output Current

(bottom) (mA)

2.96

2.98

3.00

3.02

3.04

100

150

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Typical Characteristics—General

Quiescent Current vs. Input Voltage

(VOUT = 1.8V; L = 3.3µH)

Input VBAT, VCHGIN (V)

Quiescent Current (µA)

100

150

200

250

300

350

400

450

500

2.7 3.2 3.7 4.2 4.7 5.2 5.7

-40°C

25°C

85°C

VBAT VCHGIN

Start-up Sequence

(VCHGIN = 5.0V)

Time (50µs/div)

Output Voltage (2V/div)

Buck

LDO1

LDO2

LDO3

LDO4

LDO5

LDO Output Voltage Noise

(No Load; Power BW: 100~100KHz)

Frequency (Hz)

Noise (µVRMS)

0.00

0.60

1.20

1.80

2.40

3.00

3.60

4.20

4.80

5.40

6.00

100 1000 10000 100000

LDO Output Voltage Noise

(IOUT3 = 10mA, Power BW = 100~100KHz)

Frequency (Hz)

Noise (µVRMS)

0.00

0.60

1.20

1.80

2.40

3.00

3.60

4.20

4.80

5.40

6.00

100 1000 10000 100000

LDO Power Supply Rejection Ratio, PSRR

(IOUT3 = 10mA, BW = 100~100KHz)

Frequency (Hz)

Magnitude (dB)

105

120

135

150

100 1000 10000 100000

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Functional Block Diagram

LDO2

Enable

LDO1

Enable

LDO4

LDO5

Enable

LDO3

Enable

BUCK

CHGIN

UVLO

BAT

PGND

PVIN

OUTBUCK

OUT1

OUT2

VIN

OUT3

OUT4

OUT5

REF

AVIN2

EN5

EN4

EN3

EN_TEST

EN_HOLD

RESET

Ref

CNOISE

AGND

AVIN1

VIN

I2C

and

Enable

Control

EN_KEY

ON_KEY

SDA

SCL

ISET

Ref

Charger

Control STAT

ADPP

ENBAT

EN2

Functional Description

The AAT3603 is a complete power management solution.

It seamlessly integrates an intelligent, stand-alone CC/

CV (Constant Current/Constant Voltage), linear-mode

single-cell battery charger with one step-down Buck con-

verter and five low-dropout (LDO) regulators to provide

power from either a wall adapter or a single-cell Lithium

Ion/Polymer battery.

If only the battery is available, then the voltage regula-

tors and converter are powered directly from the battery.

(The charger is put into sleep mode and draws less than

1μA quiescent current.)

Typical Power Up Sequence

The AAT3603 supports a variety of push-button or

enable/disable schemes. A typical startup and shutdown

process proceeds as follows (referring to Figures 1 and

2): System startup is initiated whenever one of the fol-

lowing conditions occurs:

1) A push-button is used to assert EN_KEY low.

2) A valid supply (>CHGIN UVLO) is connected to the

charger input CHGIN.

3) A hands free device or headset is connected, assert-

ing EN_TEST high.

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The startup sequence for the AAT3603 core (Buck and

LDO1) is typically initiated by pulling the EN_KEY pin low

with a pushbutton switch, see Figure 1. The Buck (Core)

is the first block to be turned on. When the output of the

Buck reaches 90% of its final value, then LDO1 is

enabled. When LDO1 (PowerDigital) reaches 90% of its

final value, the 65ms RESET timer is initiated holding the

microprocessor in reset. When the RESET pin goes High,

the μP can begin a power up sequence. After the startup

sequence has commenced, LDO2 (PowerAnalog), LDO3

(TCXO), LDO4 (TX) and LDO5 (RX) can be enabled and

disabled as desired using their independent enable pins,

even while the Buck and LDO1 are still starting up.

However, if they are shut down, then LDO2, LDO3,

LDO4, and LDO5 cannot be enabled. The μP must pull

the EN_HOLD signal high before the EN_KEY signal can

be released by the push-button. This procedure requires

that the push-button be held until the μP assumes con-

trol of EN_HOLD, providing protection against inadver-

tent momentary assertions of the pushbutton. Once

EN_HOLD is high the startup sequence is complete. If

the μP is unable to complete its power-up routine suc-

cessfully before the user lets go of the push-button, the

AAT3603 will automatically shut itself down. (EN_KEY

and EN_HOLD are OR’d internally to enable the two core

converters.)

Alternatively, the startup sequence is automatically

started without the pushbutton switch when the CHGIN

pin rises above its UVLO threshold. The system cannot

be disabled until the voltage at the CHGIN pin drops

below the falling UVLO threshold. Thirdly, the EN_TEST

pin can be used to startup the device for test purposes

or for hands free operation such as when connecting a

headset to the system.

Typical Power Down Sequence

If only the battery is connected and the voltage level is

above the BAT UVLO , then the EN_KEY pin can be held

low in order to power down AAT3603. The user can initi-

ate a shutdown process by pressing the push-button a

second time. Upon detecting a second assertion of EN_

KEY (by depressing the push-button), the AAT3603

asserts ON_KEY to interrupt the microprocessor which

initiates an interrupt service routine that the user

pressed the push-button. If EN_TEST and CHGIN are

both low, the microprocessor then initiates a power-

down routine, the final step of which will be to de-assert

EN_HOLD, disabling LDO2, LDO3, LDO4, and LDO5.

When the voltage at the CHGIN pin is above the CHGIN

UVLO, the device cannot be powered down. If the voltage

at the CHGIN pin is below the CHGIN UVLO, both the

EN_KEY and EN_HOLD pins must be held low in order to

power down AAT3603. If LDO2, LDO3, LDO4, and LDO5

have not been disabled individually prior to global power

down, then they will be turned off simultaneously with the

Buck. The outputs of LDO4 and LDO5 are internally pulled

to ground with 10k during shutdown to discharge the out-

put capacitors and ensure a fast turn-off response time.

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BAT

CHGIN

EN_KEY

UVLO

Micro

Processor

μP

ON_KEY

OUT1

EN_ HOLD

Automatic

Tester or

Handsfree

Operation

EN_TEST

Enable

for BAT

Regulators

EN_BAT

Enable for

Battery Charger

Debounce

Push-button

On Switch

Figure 1: Enable Function Detailed Schematic.

EN_KEY

EN_HOLD

OUTBuck

(Core)

RESET

65ms

300ms

debounce

delay

OUT1

(PowerDigital)

90% Regulation

EN_HOLD must be held high

before EN _KEY can be released .

Power Up Sequence

ON_KEY

90% Regulation

Power Down Sequence

Figure 2: Typical Power Up/Down Sequence.

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Battery Charger

Figure 3 illustrates the entire battery charging profile

which consists of three phases.

1. Preconditioning Current Mode (Trickle) Charge

2. Constant Current Mode Charge

3. Constant Voltage Mode Charge

Preconditioning Trickle Charge

Battery charging commences only after the AAT3603

battery charger checks several conditions in order to

maintain a safe charging environment. The system

operation flow chart for the battery charger operation is

shown in Figure 4. The input supply must be above the

minimum operating voltage (UVLO) and the enable pin

(ENBAT) must be low (it is internally pulled down). When

the battery is connected to the BAT pin, the battery

charger checks the condition of the battery and deter-

mines which charging mode to apply.

Preconditioning Current Mode

Charge Current

If the battery voltage is below the preconditioning volt-

age threshold VMIN, then the battery charger initiates

precondition trickle charge mode and charges the bat-

tery at 12% of the programmed constant-current mag-

nitude. For example, if the programmed current is

500mA, then the trickle charge current will be 60mA.

Trickle charge is a safety precaution for a deeply dis-

charged cell. It also reduces the power dissipation in the

internal series pass MOSFET when the input-output volt-

age differential is at its highest.

Constant Current Mode Charge Current

Trickle charge continues until the battery voltage reach-

es VMIN. At this point the battery charger begins con-

stant-current charging. The current level default for this

mode is programmed using a resistor from the ISET pin

to ground. Once that resistor has been selected for the

default charge current, then the current can be adjusted

through I2C from a range of 40% to 180% of the pro-

grammed default charge current. Programmed current

can be set at a minimum of 100mA and up to a maxi-

mum of 1A. When the ADPP signal goes high, the default

I2C setting of 100% is reset.

Constant Voltage Mode Charge

Constant current charging will continue until the battery

voltage reaches the Output Charge Voltage Regulation

point VBAT_REG. When the battery voltage reaches the regu-

lation voltage (VBAT_REG), the battery charger will transition

to constant-voltage mode. VBAT_REG is factory programmed

to 4.2V (nominal). Charging in constant-voltage mode will

continue until the charge current has reduced to the end

of charge termination current programmed using the I2C

interface (5%, 10%, 15%, or 20%).

Constant Current

Charge Phase

Constant Voltage

Charge Phase

Preconditioning

Trickle Charge

Phase

I (mA) V (V)

Preconditioning Threshold

Voltage (VMiN)

Charge Termination

Threshold Current

(ICH_TERM)

T (s)

Battery End of Charge

Voltage Regulation (VBAT_REG)

FAST-CHARGE to

TOP-OFF Charge

Threshold

Trickle Charge

Timeout

(TK)

Constant-Current Mode

Charge Current (ICH_CC)

Preconditioning Charge

Current (ICH_PRE)

Charge Current

Charge Voltage

Constant Current Timeout

(TC)

Constant Voltage Timeout

(TV)

Figure 3: Current vs. Voltage and Charger Time Profile.

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Power On Reset

Power Input

Voltage

CHGIN

> V

UVLO

Fault

Conditions Monitoring

OV, OT,

TS1

< < V

TS2

Preconditioning

Test

MIN

< V

BAT

Current Phase Test

BAT

< V

BAT_REG

Voltage Phase Test

> I

CH_TERM

Yes

Preconditioning

(Trickle Charge)

Constant

Current Charge

Mode

Constant

Voltage Charge

Mode

Yes

Charge Completed

Charge Timer

Control

Recharge Test

RCH

< V

BAT

Yes

Shut Down Yes

Enable

Yes

Device Thermal

Loop Monitor

> 115°C

Thermal Loop

Current

Reduction in ADP

Charging Mode

Thermal Loop

Current

Reduction in

C.C. Mode

Enable

Expired

Yes

Figure 4: System Operation Flow Chart for the Battery Charger.

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Power Saving Mode

After the charge cycle is complete, the battery charger

turns off the series pass device and automatically goes into

a power saving sleep mode. During this time, the series

pass device will block current in both directions to prevent

the battery from discharging through the battery charger.

The battery charger will remain in sleep mode even if the

charger source is disconnected. It will come out of sleep

mode if either the battery terminal voltage drops below

the VRCH threshold, the charger EN pin is recycled, or the

charging source is reconnected. In all cases, the battery

charger will monitor all parameters and resume charging

in the most appropriate mode.

Temperature Sense (TS)

The TS pin is available to monitor the battery tempera-

ture. Connect a 10k NTC resistor from the TS pin to

ground. The TS pin outputs a 75μA constant current into

the resistor and monitors the voltage to ensure that the

battery temperature does not fall outside the limits

depending on the temperature coefficient of the resistor

used. When the voltage goes above 2.39V or goes below

0.331V, the charging current will be suspended.

Charge Safety Timer (CT)

While monitoring the charge cycle, the AAT3603 utilizes a

charge safety timer to help identify damaged cells and to

ensure that the cell is charged safely. Operation is as fol-

lows: upon initiating a charging cycle, the AAT3603 charg-

es the cell at 12% of the programmed maximum charge

until VBAT >2.8V. If the cell voltage fails to reach the pre-

conditioning threshold of 2.8V (typ) before the safety

timer expires, the cell is assumed to be damaged and the

charge cycle terminates. If the cell voltage exceeds 2.8V

prior to the expiration of the timer, the charge cycle pro-

ceeds into fast charge. There are three timeout periods: 1

hour for Trickle Charge mode, 3 hours for Constant

Current mode, and 3 hours for Constant Voltage mode.

The CT pin is driven by a constant current source and will

provide a linear response to increases in the timing

capacitor value. Thus, if the timing capacitor were to be

doubled from the nominal 0.1μF value, the time-out

periods would be doubled. If the programmable watch-

dog timer function is not needed, it can be disabled by

terminating the CT pin to ground. The CT pin should not

be left floating or unterminated, as this will cause errors

in the internal timing control circuit. The constant cur-

rent provided to charge the timing capacitor is very

small, and this pin is susceptible to noise and changes in

capacitance value. Therefore, the timing capacitor should

be physically located on the printed circuit board layout

as close as possible to the CT pin. Since the accuracy of

the internal timer is dominated by the capacitance value,

a 10% tolerance or better ceramic capacitor is recom-

mended. Ceramic capacitor materials, such as X7R and

X5R types, are a good choice for this application.

Programming Charge Current (ISET)

At initial power-on, the charge current is always set to

100mA. The constant current mode charge level is user

programmed with the I2C interface and a set resistor

placed between the ISET pin and ground. The accuracy of

the constant charge current, as well as the precondition-

ing trickle charge current, is dominated by the tolerance

of the set resistor. For this reason, a 1% tolerance metal

film resistor is recommended for the set resistor function.

The programmable constant charge current levels from

100mA to 1A may be set by selecting the appropriate

resistor value from Table 1, Figure 5, and Table 3. The

ISET pin current to charging current ratio is 1 to 800. It

is regulated to 1.25V during constant current mode

unless changed using I2C commands. It can be used as a

charging current monitor, based on the equation:

= 800

⋅

⎛

⎝⎞

⎠

ISET

During preconditioning charge, the ISET pin is regulated

to 12% of the fast charge current ISET voltage level

(Figure 5), but the equation stays the same. During con-

stant voltage charge mode, the ISET pin voltage will

slew down and be directly proportional to the battery

current at all times.

Constant Charging

Current ICH_CC (mA) Set Resistor

Value (kΩ)

100 10

200 4.99

300 3.32

400 2.49

500 2

600 1.65

700 1.43

800 1.24

900 1.1

1000 1

Table 1: Constant Current Charge vs.

ISET Resistor Value.

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Reverse Battery Leakage

The AAT3603 includes internal circuitry that eliminates

the need for series blocking diodes, reducing solution

size and cost as well as dropout voltage relative to con-

ventional battery chargers. When the input supply is

removed or when CHGIN goes below the AAT3603’s

under voltage-lockout (UVLO) voltage, or when CHGIN

drops below VBAT

, the AAT3603 automatically reconfig-

ures its power switches to minimize current drain from

the battery.

Adapter Power Indicator (ADPP)

This is an open drain output which will pull low when

VCHGIN > 4.5V. When this happens the charge current will

be reset to the default ISET values or I2C programmed

values.

Charge Status Output (STAT)

The AAT3603 provides battery charging status via a sta-

tus pin. This pin is a buffered output with a supply level

up to the LDO1 output (PowerDigital). The status pin can

indicate the following conditions:

Event Description STAT

No battery charging activity Low (to GND)

Battery charging High (to VOUT1)

Charging completed Low (to GND)

Table 2: Charge Status Output (STAT).

CHGIN Bypass Capacitor Selection

CHGIN is the power input for the AAT3603 battery char-

ger. The battery charger is automatically enabled when-

ever a valid voltage is present on CHGIN. In most appli-

cations, CHGIN is connected to either a wall adapter or

USB port. Under normal operation, the input of the char-

ger will often be “hot-plugged” directly to a powered USB

or wall adapter cable, and supply voltage ringing and

overshoot may appear at the CHGIN pin. A high quality

capacitor connected from CHGIN to G, placed as close as

possible to the IC, is sufficient to absorb the energy.

Wall-adapter powered applications provide flexibility in

input capacitor selection, but the USB specification pres-

ents limitations to input capacitance selection. In order

to meet both the USB 2.0 and USB OTG (On The Go)

specifications while avoiding USB supply under-voltage

conditions resulting from the current limit slew rate

(100mA/μs) limitations of the USB bus, the CHGIN

bypass capacitance value must be between 1μF and

4.7μF. Ceramic capacitors are often preferred for bypass-

ing due to their small size and good surge current rat-

ings, but care must be taken in applications that can

encounter hot plug conditions as their very low ESR, in

combination with the inductance of the cable, can create

a high-Q filter that induces excessive ringing at the

CHGIN pin. This ringing can couple to the output and be

mistaken as loop instability, or the ringing may be large

enough to damage the input itself. Although the CHGIN

pin is designed for maximum robustness and an absolute

Constant Current Mode Charge Current

vs. ISET Resistor

(VIN = 5V; VBAT = 3.6V)

ISET Resistor (kΩ

)

ICH_CC (mA)

200

400

600

800

1000

1200

1400

0.1 1 10 100

ISET Voltage vs. Battery Voltage

(CHGIN = 5.0V, RISET = 1.24kΩ

)

Battery Voltage (V)

VISET (V)

0.2

0.4

0.6

0.8

1.2

1.4

2.5 2.9 3.3 3.7 4.1 4.5

Figure 5: Constant Current Mode Charge ICH_CC Setting vs. ISET Resistor

and ISET Voltage vs. Battery Voltage.

AAT3603178

Total Power Solution for Portable Applications

PRODUCT DATASHEET

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maximum voltage rating of +6.5V for transients, atten-

tion must be given to bypass techniques to ensure safe

operation. As a result, design of the CHGIN bypass must

take care to “de-Q” the filter. This can be accomplished

by connecting a 1Ω resistor in series with a ceramic

capacitor (as shown in Figure 6A), or by bypassing with

a tantalum or electrolytic capacitor to utilize its higher

ESR to dampen the ringing (as shown in Figure 6A). For

additional protection, Zener diodes with 6V clamp volt-

ages may also be used. In any case, it is always critical

to evaluate voltage transients at the CHGIN pin with an

oscilloscope to ensure safe operation.

Thermal Considerations

The actual maximum charging current is a function of

charge adapter input voltage, the state of charge of the

battery at the moment of charge, and the ambient tem-

perature and the thermal impedance of the package and

printed circuit board. The maximum programmable cur-

rent may not be achievable under all operating parame-

ters. One issue to consider is the amount of current being

sourced to the supply channels while the battery is being

charged.

The AAT3603 is offered in a TQFN55-36 package which

can provide up to 4W of power dissipation when it is

properly bonded to a printed circuit board and has a

maximum thermal resistance of 25°C/W. Many consider-

ations should be taken into account when designing the

printed circuit board layout, as well as the placement of

the charger IC package in proximity to other heat gen-

erating devices in a given application design. The ambi-

ent temperature around the charger IC will also have an

effect on the thermal limits of a battery charging applica-

tion. The maximum limits that can be expected for a

given ambient condition can be estimated by the follow-

ing discussion. First, the maximum power dissipation for

a given situation should be calculated:

J(MAX) -

)

D(MAX)

= θ

Where:

PD(MAX) = Maximum Power Dissipation (W)

θJA = Package Thermal Resistance (°C/W)

TJ(MAX) = Maximum Device Junction Temperature (°C)

[150°C]

TA = Ambient Temperature (°C)

To USB Port or

Wall Adapter To USB Port or

Wall Adapter

1μF Ceramic

(XR5/XR7)

4.7μF

ESR > 1Ω

1Ω

CHGIN

(A) (B)

Figure 6: Hot Plug Requirements.

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Next, the power dissipation for the charger can be cal-

culated by the following equation:

PD = (VCHGIN - VBAT) · ICH_CC + (VCHGIN · IOP) + (VCHGIN - VBAT) · IBAT

+ (VBAT - VOUT1) · IOUT1 + (VBAT - VOUT2) · IOUT2

+ (VBAT - VOUT3) · IOUT3 + (VBAT - VOUT4) · IOUT4

+ (VBAT - VOUT5) · IOUT5

+ IOUTBUCK2 · RDS(ON)L · + RDS(ON)H · [VBAT - VOUTBUCK]

VBAT

VOUTBUCK

VBAT

Where:

PD = Total Power Dissipation by the Device

VCHGIN = CHGIN Input Voltage

VBAT = Battery Voltage at the BAT Pin

ICH_CC = Constant Charge Current Programmed for the

Application

IOP = Quiescent Current Consumed by the IC for Normal

Operation [0.5mA]

VBAT = Load current from the BAT pin for the system

LDOs and step-down converter

RDS(ON)H and RDS(ON)L = On-resistance of step-down high

and low side MOSFETs [0.8Ω each]

VOUTX and IOUTX = Output voltage and load currents for

the LDOs and step-down converter [3V out for each

LDO]

By substitution, we can derive the maximum charge cur-

rent before reaching the thermal limit condition (TREG =

100°C, Thermal Loop Regulation). The maximum charge

current is the key factor when designing battery charger

applications.

ICH_CC(MAX) =

- [(VBAT - VOUT1) · IOUT1] - (VBAT - VOUT2) · IOUT2

- [(VBAT - VOUT3) · IOUT3] - (VBAT - VOUT4) · IOUT4

- (VBAT - VOUT5) · IOUT5

VCHGIN - VBAT

- IOUTBUCK

2 · RDS(ON)L · + RDS(ON)H · (VBAT - VOUTBUCK)

VBAT

VOUTBUCK

VBAT

(TREG

TA)

θJA

- (VCHGIN · IOP) - (VCHGIN - VBAT) · IBAT

In general, the worst condition is when there is the

greatest voltage drop across the charger, when battery

voltage is charged up to just past the preconditioning

voltage threshold and the LDOs and step-down con-

verter are sourcing full output current.

For example, if 977mA is being sourced from the BAT pin

to the LDOs and Buck channels (300mA to LDO1, 100mA

to LDO2-5, and 277mA to the Buck; see buck efficiency

graph for 300mA output current) with a CHGIN supply of

5V, and the battery is being charged at 3.0V with 800mA

charge current, then the power dissipated will be 3.64W.

A reduction in the charge current (through I2C) may be

necessary in addition to the reduction provided by the

internal thermal loop of the charger itself.

For the above example at TA = 30°C, the ICH_CC(MAX) =

386mA.

Thermal Overload Protection

The AAT3603 integrates thermal overload protection

circuitry to prevent damage resulting from excessive

thermal stress that may be encountered under fault con-

ditions, for example. This circuitry disables all regulators

if the AAT3603 die temperature exceeds 140°C, and

prevents the regulators from being enable until the die

temperature drops by 15°C (typ).

Synchronous Step-Down

Converter (Buck)

The AAT3603 contains a high performance 300mA,

1.5MHz synchronous step-down converter. The step-

down converter operates to ensure high efficiency per-

formance over all load conditions. It requires only three

external power components (CIN, COUT

, and L). A high DC

gain error amplifier with internal compensation controls

the output. It provides excellent transient response and

load/line regulation. Transient response time is typically

less than 20μs. The converter has soft start control to

limit inrush current and transitions to 100% duty cycle

at drop out.

The step-down converter input pin PVIN should be con-

nected to the BAT output pin. The output voltage is

internally fixed at 1.8V. Power devices are sized for

300mA current capability while maintaining over 90%

efficiency at full load.

AAT3603178

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Input/Output Capacitor and Inductor

Apart from the input capacitor that is shared with the LDO

inputs, only a small L-C filter is required at the output side

for the step-down converter to operate properly. Typically,

a 3.3μH inductor such as the Sumida CDRH2D11NP-

3R3NC and a 4.7μF ceramic output capacitor are recom-

mended for low output voltage ripple and small compo-

nent size. Ceramic capacitors with X5R or X7R dielectrics

are highly recommended because of their low ESR and

small temperature coefficients. A 10μF ceramic input

capacitor is sufficient for most applications.

Control Loop

The converter is a peak current mode step-down con-

verter. The inner, wide bandwidth loop controls the

inductor peak current. The inductor current is sensed

through the P-channel MOSFET (high side) which is also

used for short circuit and overload protection. A fixed

slope compensation signal is added to the sensed cur-

rent to maintain stability for duty cycles greater than

50%. The peak current mode loop appears as a voltage

programmed current source in parallel with the output

capacitor.

The output of the voltage error amplifier programs the

current mode loop for the necessary peak inductor cur-

rent to force a constant output voltage for all load and

line conditions. The voltage feedback resistive divider is

internal and the error amplifier reference voltage is

0.45V. The voltage loop has a high DC gain making for

excellent DC load and line regulation. The internal volt-

age loop compensation is located at the output of the

transconductance voltage error amplifier.

Soft Start

Soft start slowly increases the internal reference voltage

when the input voltage or enable input is initially applied.

It limits the current surge seen at the input and elimi-

nates output voltage overshoot.

Current Limit and

Over-Temperature Protection

For overload conditions the peak input current is limited.

As load impedance decreases and the output voltage

falls closer to zero, more power is dissipated internally,

raising the device temperature. Thermal protection com-

pletely disables switching when internal dissipation

becomes excessive, protecting the device from damage.

The junction over-temperature threshold is 140°C with

15°C of hysteresis.

Linear LDO Regulators (OUT1-5)

The advanced circuit design of the linear regulators has

been specifically optimized for very fast start-up and

shutdown timing. These proprietary LDOs are tailored for

superior transient response characteristics. These traits

are particularly important for applications which require

fast power supply timing.

There are two LDO input pins, AVIN1/2, which should be

connected to the BAT output pin. All LDO outputs are

initially fixed at 3.0V. The user can program the output

voltages for the LDOs to 2.8V, 2.85V, or 2.9V using I2C.

The high-speed turn-on capability is enabled through the

implementation of a fast start control circuit, which

accelerates the power up behavior of fundamental con-

trol and feedback circuits within the LDO regulator. For

LDO4 and LDO5, fast turn-off time response is achieved

by an active output pull down circuit, which is enabled

when the LDO regulator is placed in the shutdown mode.

This active fast shutdown circuit has no adverse effect on

normal device operation.

Input/Output Capacitors

The LDO regulator output has been specifically optimized

to function with low cost, low ESR ceramic capacitors.

However, the design will allow for operation over a wide

range of capacitor types. The input capacitor is shared

with all LDO inputs and the step-down converter. A 10μF

is sufficient. A 4.7μF ceramic output capacitor is recom-

mended for LDO2-5 and a 22μF output capacitor for

LDO1.

Current Limit and

Over-Temperature Protection

The regulator comes with complete short circuit and

thermal protection. The combination of these two internal

protection circuits gives a comprehensive safety system

to guard against extreme adverse operating conditions.

AAT3603178

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I2C Serial Interface

and Programmability

Serial Interface

Many of the features of the AAT3603 can be controlled via

the I2C serial interface. The I2C serial interface is a wide-

ly used interface where it requires a master to initiate all

the communications with the slave devices. The I2C pro-

tocol consists of 2 active wire SDA (serial data line) and

SCL (serial clock line). Both wires are open drain and

require an external pull up resistor to VCC (BAT may be

used as VCC). The SDA pin serves I/O function, and the

SCL pin controls and references the I2C bus. I2C protocol

is a bidirectional bus which allows both read and write

actions to take place, but the AAT3603 supports the write

protocol only. Since the protocol has a dedicated bit for

Read or Write access (R/W), when communicating with

AAT3603, this bit must be set to “0”.

The timing diagram in Figure 7 depicts the transmission

protocol.

START and STOP Conditions

START and STOP conditions are always generated by the

master. Prior to initiating a START condition, both the

SDA and SCL pin are idle mode (idle mode is when there

is no activity on the bus and SDA and SCL are pulled to

VCC via external resistor). As depicted in Figure 7, a

START condition is defined to be when the master pulls

the SDA line low and after a short period pulls the SCL

line low. A START condition acts as a signal to all IC’s

that something is about to be transmitted on the BUS.

A STOP condition, also shown in Figure 7, is when the

master releases the bus and SCL changes from low to

high followed by SDA low to high transition. The master

does not issue an ACKNOWLEGE and releases the SCL

and SDA pins.

ACK from slave ACK from slave ACK from slave

START

SCL

SDA

including R/W bit,

Chip Address = 0x98

STOP

ACK

Data

LSB

MSB

LSB

Chip

Address

MSB

LSB

Address

MSB

Figure 7: I2C Timing Diagram.

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Transferring Data

Every byte on the bus must be 8 bits long. A byte is

always sent with a most significant bit first (see Figure

8).

R/W

MSB LSB

Figure 8: Bit Order.

The address is embedded in the first seven bits of the

byte. The eighth bit is reserved for the direction of the

information flow for the next byte of information. For

the AAT3603, this bit must be set to “0”. The full 8-bit

address including the R/W bit is 0x98 (hex) or

10011000 in binary.

Acknowledge Bit

The acknowledge bit is the ninth bit of data. It is used

to send back a confirmation to the master that the

data has been received properly. For acknowledge to

take place, the MASTER must first release the SDA

line, then the SLAVE will pull the data line low as

shown in Figure 7.

Serial Programming Code

After sending the chip address, the master should send

an 8-bit data stream to select which register to program

and then the codes that the user wishes to enter.

Timer RCHG1RCHG0CHG2CHG1CHG0Term1Term0

Not used Not used Not used Not used Not used SYS LDO11LDO10

LDO51LDO50LDO41LDO40LDO31LDO30LDO21LDO20

Figure 9: Serial Programming Register Codes.

CHG2CHG1CHG0

Constant Current Charge

ICH_CC

Constant Current Charge

as % of ISET Current

000 100mA

(ﬁ xed internally) (default)

0 0 1 640mA 80%

0 1 0 480mA 60%

0 1 1 320mA 40%

1 0 0 960mA 120%

1 0 1 1120mA 140%

1 1 0 1280mA 160%

1 1 1 1440mA 180%

Table 3: CHG Bit Setting for the Constant Current Charge Level

(assuming ISET resistor is set to default 800mA charge current).

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Notes concerning the operation of the CHG2, CHG1 and

CHG0 bits or ISET code:

• Once the part is turned on using the EN_KEY pin (and

there is a BAT and/or CHGIN supply), and data is sent

through I2C, the I2C codes in the registers will always

be preserved until the part is shut down using the

EN_HOLD (going low) or if the BAT and CHGIN supply

are removed.

• If the part is turned on by connecting supply CHGIN

(and not through EN_KEY), then when the CHGIN is

removed, the part will shut down and all I2C registers

will be cleared.

•

ISET Code 000 in Register 0x00, bits 2,3,4 = 100mA.

• If the part has been turned on by EN_KEY and CHGIN

is disconnected then reconnected, the ISET code will

be forced to 000 and the current will be set to

100mA.

• The next time any I2C register is programmed (even if

it is not for the ISET code), the ISET code will revert

back to what it was before. For example, if the ISET

code is set to 010 and the part was turned on with

EN_KEY, then when CHGIN is disconnected then

reconnected, the charger will be set to 100mA. Then

if any other command is sent, the ISET code will

remain 010.

Term1Term0Termination Current (as % of Constant Current Charge)

0 0 5% (default)

0 1 10%

1 0 15%

1 1 20%

Table 4: Term Bit Setting for the Termination Current Level.

RCHG1RCHG0Recharge Threshold

0 0 4.00V (default)

0 1 4.05V

1 0 4.10V

1 1 4.15V

Table 5: RCHG Bit Setting for the Battery Charger Recharge Voltage Level.

Timer Charger Watchdog Timer

0 ON (default)

1 OFF (and reset to zero)

Table 6: Timer Bit Setting for the Charger Watchdog Timer.

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LDO11LDO10LDO1 Output Voltage

0 0 3.00V (default)

0 1 2.90V

1 0 2.85V

1 1 2.80V

LDO21LDO20LDO2 Output Voltage

0 0 3.00V (default)

0 1 2.90V

1 0 2.85V

1 1 2.80V

LDO31LDO30LDO3 Output Voltage

0 0 3.00V (default)

0 1 2.90V

1 0 2.85V

1 1 2.80V

LDO41LDO40LDO4 Output Voltage

0 0 3.00V (default)

0 1 2.90V

1 0 2.85V

1 1 2.80V

LDO51LDO50LDO5 Output Voltage

0 0 3.00V (default)

0 1 2.90V

1 0 2.85V

1 1 2.80V

Table 7: LDO Bit Setting for

LDO Output Voltage Level.

Layout Guidance

Figure 10 is the schematic for the evaluation board. The

evaluation board has extra components for easy evalua-

tion; the actual BOM need for a system is shown in Table

9. When laying out the PC board, the following layout

guideline should be followed to ensure proper operation

of the AAT3603:

1. The exposed pad EP must be reliably soldered to

PGND/AGND and multilayer GND. The exposed ther-

mal pad should be connected to board ground plane

and pins 2 and 16. The ground plane should include

a large exposed copper pad under the package with

VIAs to all board layers for thermal dissipation.

2. The power traces, including GND traces, the LX

traces and the VIN trace should be kept short, direct

and wide to allow large current flow. The L1 connec-

tion to the LX pins should be as short as possible.

Use several via pads when routing between layers.

3. The input capacitors (C1 and C2) should be con-

nected as close as possible to CHGIN (Pin 28) and

PGND (Pin 2) to get good power filtering.

4. Keep the switching node LX away from the sensitive

OUTBUCK feedback node.

5. The feedback trace for the OUTBUCK pin should be

separate from any power trace and connected as

closely as possible to the load point. Sensing along a

high current load trace will degrade DC load regula-

tion.

6. The output capacitor C4 and L1 should be connected

as close as possible and there should not be any

signal lines under the inductor.

7. The resistance of the trace from the load return to

the PGND (Pin 2) should be kept to a minimum. This

will help to minimize any error in DC regulation due

to differences in the potential of the internal signal

ground and the power ground.

Quantity Value Designator Footprint Description

510μF C1, C2, C3, C14, C15 0603 Capacitor, Ceramic, X5R, 6.3V, ±20%

222μF C9 0805 Capacitor, Ceramic, 20%, 6.3V, X5R

4 4.7μF C4, C5, C6, C7, C8 0603 Capacitor, Ceramic, 20%, 6.3V, X5R

3 0.1μF C10, C11, C12 0402 Capacitor, Ceramic, 16V, 10%, X5R

1 0.01μF C13 0402 Capacitor, Ceramic, 16V, 10%, X7R

1 3.3μH L1 CDRH2D Inductor, Sumida CDRH2D11NP-3R3NC

9 100K R5, R8, R20, R21, R22, R23, R25, R26, R27 0402 Resistor, 5%

8 10K R17, R19, R24, R29, R31, R32, R33, R37 0402 Resistor, 5%

1 1.24K R18 0402 Resistor, 1%

Table 8: Minimum AAT3603 Bill of Materials.

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1 2

3 4

5 6

7 8

910

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

Header 13X2H

1 2

3 4

5 6

7 8

910

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

Header 13X2H

EN_TEST

1EN_HOLD

2EN_KEY

ON-KEY 4

EN2

EN3

EN4

EN5

OUT5 9

OUT4 10

AVIN2 11

OUT3 12

OUT2 13

AVIN1 14

OUT1 15

AGND 16

CNOISE 17

RESET 18

ADPP 19

LX 20

PGND 21

PVIN 22

OUTBUCK 23

N/C 24

N/C 25

BAT 26

BAT 27

CHGIN

ENBAT

ISET

STAT 34

SDA

SCL

GND_SLUG 37

J11

VBUS/VCHG

BUCK

OUT5

OUT4

OUT 3

OUT2

OUT1

VBAT

BAT VDIG VDIG VDIG VDIG

CHGINVDIGBAT

PWR_ON RX_EN

STAT

BAT_ID

VANA

VTCXO

VCORE

ACOK_N

RESET_N

BAT_I D

VDIG

PON_N

CHG_EN

TP2

CHGIN

TP1

VBAT

TP3

ACOK_N

TP4

PON_N

TP5

RESET_N

TP6

STAT

TP7

GND

TP8

GND

SDA

SCL

SDA

SCL

GND

J10

DATA HEADER

VBATT

PWR_HOLD

HF_PWR

PWR_ON

VDIG

VRX

VTX

ANA_EN

TX_EN

RX_EN

VBATT

TCXO_EN

VBUS

VCHG

VBAT

L1 3.3μH

ACOK_N

PON_N

RESET_N

STAT

VCORE VRX VTX VTCXO VANA VDIG

J13

RX_EN

J14

TX_EN

J15

TCXO_EN

J16

ANA_EN

J20

CHG_EN

J18

PWR_HOLD

J17

HF_PWR

CMPT3904

buckout

CHGIN

OUT1

OUT2

OUT3

OUT4

OUT5

BAT

TP9 LX

VDIG

R34 0

R35 0

R36 0

SW1

PWR_ON

R30

NP1K

STAT

R31

10K

R33

10K

J1 2

INT/EXT PWR

TP11

EXT PWR

VCORE

R2 0

R4 0

R6 0

R9 0

R10 0

R12 0

R14 0

R7 DNP

R11 0

R13 0

R15 0

R16 0

R29

10K

R37

10K

R17

10K

R28

4.75K

100K

R24

10K

R19

10K

R20

100K

R21

100K

R22

100K

R23

100K

R25

100K

R27

100K

BAT

10μF

C10

0.1μF

C11

0.1μF

C12

0.1μF

R18

1.24K

C13

0.01μF

4.7μF 4.7μF 4.7μF 4.7μF 4.7μF

22μF

C6 C7 C8

22μF

R1 0

R32 NP 10k

TP12

GND

C1 5

22μF

C16

0.001μF

C17

0.001μF

R380

R390

AAT3603

Figure 10: AAT3603 Evaluation Kit Schematic.

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Ordering Information

Package Part Marking1Part Number (Tape and Reel)2

TQFN55-36 3YXYY AAT3603IIH-T1

All AnalogicTech products are offered in Pb-free packaging. The term “Pb-free” means semiconductor

products that are in compliance with current RoHS standards, including the requirement that lead not exceed

0.1% by weight in homogeneous materials. For more information, please visit our website at

http://www.analogictech.com/about/quality.aspx.

Packaging Information

TQFN55-36

0.750 ± 0.050

0.000 + 0.050

- 0.000

0.203 REF

0.200 ± 0.050

0.450 ± 0.050

0.40 BSC

5.000 ± 0.050

3.600 ± 0.050

Detail "A"

3.600 ± 0.050

Top View

Side View

Detail "A"

Bottom View

Index Area

(D/2 x E/2)

R = 0.1

C = 0.3

All dimensions in millimeters.

1. XYY = assembly and date code.

2. Sample stock is generally held on part numbers listed in BOLD.

3. The leadless package family, which includes QFN, TQFN, DFN, TDFN and STDFN, has exposed copper (unplated) at the end of the lead terminals due to the manufacturing

process. A solder fillet at the exposed copper edge cannot be guaranteed and is not required to ensure a proper bottom solder connection.

AAT3603178

Total Power Solution for Portable Applications

PRODUCT DATASHEET

3603.2008.06.1.0 35

www.analogictech.com

AAT3603178

Total Power Solution for Portable Applications

PRODUCT DATASHEET

3603.2008.06.1.0 35

www.analogictech.com

Advanced Analogic Technologies, Inc.

3230 Scott Boulevard, Santa Clara, CA 95054

Phone (408) 737-4600

Fax (408) 737-4611

AnalogicTech cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in an AnalogicTech product. No circuit patent licenses, copyrights, mask work rights, or other intellectual

property rights are implied. AnalogicTech reserves the right to make changes to their products or speciﬁ cations or to discontinue any product or service without notice. Except as provided in AnalogicTech’s terms and

conditions of sale, AnalogicTech assumes no liability whatsoever, and AnalogicTech disclaims any express or implied warranty relating to the sale and/or use of AnalogicTech products including liability or warranties

relating to ﬁ tness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. In order to minimize risks associated with the customer’s applications, adequate

design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. Testing and other quality control techniques are utilized to the extent AnalogicTech deems necessary to

support this warranty. Speciﬁ c testing of all parameters of each device is not necessarily performed. AnalogicTech and the AnalogicTech logo are trademarks of Advanced Analogic Technologies Incorporated. All other

brand and product names appearing in this document are registered trademarks or trademarks of their respective holders.