Order Now Product Folder Support & Community Tools & Software Technical Documents PCA9555 SCPS131G - AUGUST 2005 - REVISED MARCH 2018 PCA9555 Remote 16-Bit I2C and SMBus I/O Expander With Interrupt Output and Configuration Registers 1 Features 3 Description * * * * * * * This 16-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 2.3-V to 5.5-V VCC operation. It provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock (SCL), serial data (SDA)]. 1 * * * * Low Standby-Current Consumption of 1 A Max I2C to Parallel Port Expander Open-Drain Active-Low Interrupt Output 5-V Tolerant I/O Ports Compatible With Most Microcontrollers 400-kHz Fast I2C Bus Address by Three Hardware Address Pins for Use of up to Eight Devices Polarity Inversion Register Latched Outputs With High-Current Drive Capability for Directly Driving LEDs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) The PCA9555 consists of two 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity Inversion (active high or active low operation) registers. At power on, the I/Os are configured as inputs. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master. Device Information(1) PART NUMBER PCA9555 2 Applications * * * * * * PACKAGE BODY SIZE (NOM) SSOP (16) 6.20 mm x 5.30 mm VQFN (16) 4.00 mm x 4.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Servers Routers (Telecom Switching Equipment) Personal Computers Personal Electronics Industrial Automation Equipment Products with GPIO-Limited Processors Block Diagram INT A0 A1 A2 SCL SDA PCA9555 1 Interrupt Logic LP Filter 21 2 P07-P00 3 22 23 Input Filter I2C Bus Control Shift Register 16 Bits I/O Port P17-P10 Write Pulse VCC GND 24 12 Read Pulse Power-On Reset 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. PCA9555 SCPS131G - AUGUST 2005 - REVISED MARCH 2018 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 4 4 4 5 5 6 6 7 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... I2C Interface Timing Requirements........................... Switching Characteristics .......................................... Typical Characteristics .............................................. Parameter Measurement Information ................ 10 Detailed Description ............................................ 12 8.1 Overview ................................................................. 12 8.2 Functional Block Diagram ....................................... 12 8.3 Device Features ...................................................... 13 8.4 Device Functional Modes........................................ 14 8.5 Programming........................................................... 15 9 Application and Implementation ........................ 22 9.1 Application Information............................................ 22 9.2 Typical Application ................................................. 22 10 Power Supply Recommendations ..................... 24 10.1 Power-On Reset Errata......................................... 24 11 Layout................................................................... 25 11.1 Layout Guidelines ................................................. 25 11.2 Layout Example .................................................... 25 12 Device and Documentation Support ................. 26 12.1 12.2 12.3 12.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 26 26 26 26 13 Mechanical, Packaging, and Orderable Information ........................................................... 26 4 Revision History Changes from Revision F (June 2014) to Revision G Page * Added the Applications list .................................................................................................................................................... 1 * Removed the Thermal Information from the Absolute Maximum Ratings.............................................................................. 4 * Added Storage temperature range to the Absolute Maximum Ratings.................................................................................. 4 * Changed the Handling Ratings table to the ESD Ratings table ............................................................................................. 4 * Added the Thermal Information table .................................................................................................................................... 5 * Changed From: "VCC must be lowered to below 0.2 V" To: VCC must be lowered to 0 V" in the Power-On Reset section. 13 * Added the Design Requirements section ............................................................................................................................ 23 * Added the Application Curves section ................................................................................................................................. 24 * Added the Layout section .................................................................................................................................................... 25 Changes from Revision E (May 2008) to Revision F Page * Added Interrupt Errata section.............................................................................................................................................. 14 * Added Power-On Reset Errata section. ............................................................................................................................... 24 2 Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 PCA9555 www.ti.com SCPS131G - AUGUST 2005 - REVISED MARCH 2018 5 Pin Configuration and Functions DB, DBQ, DGV, DW or PW Package 24 Pin (SOP) (Top View) P02 6 19 P16 7 18 P15 P04 8 17 P14 P05 9 16 P13 P06 10 15 P12 P07 11 14 P11 GND 12 13 P10 SDA SCL 20 19 P17 P02 3 16 P16 P03 4 15 P15 P04 5 14 P14 P05 6 13 P13 Thermal Pad P06 7 P03 A0 17 12 P17 18 2 11 20 1 P01 P12 5 P00 P11 P01 VCC A0 21 21 10 4 P10 P00 INT SCL A1 SDA 22 22 23 3 23 2 A2 9 A1 8 VCC P07 24 GND 1 A2 INT 24 RGE Package 24 Pin (QFN) (Top View) Not to scale Not to scale Pin Functions PIN NAME SSOP (DB), QSOP (DBQ), TSSOP (PW), AND TVSOP (DGV) QFN (RGE) INT 1 22 Interrupt output. Connect to VCC through a pullup resistor. A1 2 23 Address input 1. Connect directly to VCC or ground. A2 3 24 Address input 2. Connect directly to VCC or ground. P00 4 1 P-port input/output. Push-pull design structure. P01 5 2 P-port input/output. Push-pull design structure. P02 6 3 P-port input/output. Push-pull design structure. P03 7 4 P-port input/output. Push-pull design structure. P04 8 5 P-port input/output. Push-pull design structure. P05 9 6 P-port input/output. Push-pull design structure. P06 10 7 P-port input/output. Push-pull design structure. P07 11 8 P-port input/output. Push-pull design structure. GND 12 9 Ground P10 13 10 P-port input/output. Push-pull design structure. P11 14 11 P-port input/output. Push-pull design structure. P12 15 12 P-port input/output. Push-pull design structure. P13 16 13 P-port input/output. Push-pull design structure. P14 17 14 P-port input/output. Push-pull design structure. P15 18 15 P-port input/output. Push-pull design structure. P16 19 16 P-port input/output. Push-pull design structure. P17 20 17 P-port input/output. Push-pull design structure. DESCRIPTION A0 21 18 Address input 0. Connect directly to VCC or ground. SCL 22 19 Serial clock bus. Connect to VCC through a pullup resistor. SDA 23 20 Serial data bus. Connect to VCC through a pullup resistor. VCC 24 21 Supply voltage Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 3 PCA9555 SCPS131G - AUGUST 2005 - REVISED MARCH 2018 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range -0.5 6 V VI Input voltage range (2) -0.5 6 V (2) VO Output voltage range IIK Input clamp current VI < 0 -20 mA IOK Output clamp current VO < 0 -20 mA IIOK Input/output clamp current VO < 0 or VO > VCC 20 mA IOL Continuous output low current VO = 0 to VCC 50 mA IOH Continuous output high current VO = 0 to VCC -50 mA ICC Tstg (1) (2) -0.5 6 UNIT Continuous current through GND -250 Continuous current through VCC 160 Storage temperature range -65 150 V mA C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 6.2 ESD Ratings MIN V(ESD) (1) (2) Electrostatic discharge MAX UNIT Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 0 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 0 1000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions VCC MIN MAX 2.3 5.5 SCL, SDA 0.7 x VCC 5.5 A2-A0, P07-P00, P17-P10 0.7 x VCC 5.5 SCL, SDA -0.5 0.3 x VCC A2-A0, P07-P00, P17-P10 -0.5 0.3 x VCC Supply voltage UNIT V VIH High-level input voltage VIL Low-level input voltage IOH High-level output current P07-P00, P17-P10 -10 mA IOL Low-level output current P07-P00, P17-P10 25 mA TA Operating free-air temperature 85 C 4 -40 Submit Documentation Feedback V V Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 PCA9555 www.ti.com SCPS131G - AUGUST 2005 - REVISED MARCH 2018 6.4 Thermal Information PCA9555 THERMAL METRIC (1) DB (SSOP) DBQ (QSOP) DGV (TVSOP) PW (TSSOP) RGE (QFN) 24 PINS 24 PINS 24 PINS 24 PINS 24 PINS UNIT RJA Junction-to-ambient thermal resistance 81.1 81.8 105.4 91.0 43.6 C/W RJC(top) Junction-to-case (top) thermal resistance 41.5 39.3 36.7 35.5 37.8 C/W RJB Junction-to-board thermal resistance 40.0 36.0 50.8 46.1 21.0 C/W JT Junction-to-top characterization parameter 9.9 7.6 2.4 2.8 0.9 C/W JB Junction-to-board characterization parameter 39.6 35.6 50.3 45.7 21.0 C/W RJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a 5.4 C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK Input diode clamp voltage II = -18 mA VPOR Power-on reset voltage VI = VCC or GND, IO = 0 IOH = -8 mA VOH P-port high-level output voltage (2) IOH = -10 mA VCC MIN 2.3 V to 5.5 V -1.2 VPOR 2.3 V 1.8 3V 2.6 4.75 V 4.1 2.3 V 1.7 3V 2.5 4.75 V SDA IOL P port (3) VOL = 0.7 V INT II A2-A0 1.5 1.65 UNIT V V V 3 2.3 V to 5.5 V VOL = 0.4 V SCL, SDA MAX 4 VOL = 0.4 V VOL = 0.5 V TYP (1) 8 20 10 24 mA 3 VI = VCC or GND 2.3 V to 5.5 V 1 1 A IIH P port VI = VCC 2.3 V to 5.5 V 1 A IIL P port VI = GND 2.3 V to 5.5 V -100 A VI = VCC or GND, IO = 0, I/O = inputs, fSCL = 400 kHz, No load Operating mode ICC Low inputs VI = GND, IO = 0, I/O = inputs, fSCL = 0 kHz, No load Standby mode High inputs VI = VCC, IO = 0, I/O = inputs, fSCL = 0 kHz, No load ICC Additional current in standby mode One input at VCC - 0.6 V, Other inputs at VCC or GND CI SCL VI = VCC or GND Cio (1) (2) (3) SDA P port VIO = VCC or GND 5.5 V 100 200 3.6 V 30 75 2.7 V 20 50 5.5 V 1.1 1.5 3.6 V 0.7 1.3 2.7 V 0.5 1 5.5 V 0.5 1 3.6 V 0.4 0.9 2.7 V 0.25 0.8 2.3 V to 5.5 V 2.3 V to 5.5 V 2.3 V to 5.5 V A mA A 1.5 mA 3 7 pF 3 7 3.7 9.5 pF All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25C. Each I/O must be externally limited to a maximum of 25 mA, and each octal (P07-P00 and P17-P10) must be limited to a maximum current of 100 mA, for a device total of 200 mA. The total current sourced by all I/Os must be limited to 160 mA (80 mA for P07-P00 and 80 mA for P17-P10). Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 5 PCA9555 SCPS131G - AUGUST 2005 - REVISED MARCH 2018 www.ti.com 6.6 I2C Interface Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 14) MIN MAX UNIT 0 400 kHz 2 fscl I C clock frequency tsch I2C clock high time 0.6 tscl I2C clock low time 1.3 tsp I2C spike time tsds I2C serial-data setup time tsdh I2C serial-data hold time ticr I2C input rise time I C input fall time tocf I2C output fall time tbuf I2C bus free time between Stop and Start s 50 100 10-pF to 400-pF bus 2 ns ns 0 2 ticf s ns 20 + 0.1Cb (1) 300 ns 20 + 0.1Cb (1) 300 ns 20 + 0.1Cb (1) 300 ns 1.3 s tsts I C Start or repeated Start condition setup 0.6 s tsth I2C Start or repeated Start condition hold 0.6 s tsps I2C Stop condition setup 0.6 s tvd(Data) Valid-data time SCL low to SDA output valid 50 ns tvd(ack) Valid-data time of ACK condition ACK signal from SCL low to SDA (out) low 0.1 Cb I2C bus capacitive load (1) 0.9 s 400 pF Cb = total capacitance of one bus line in pF. 6.7 Switching Characteristics over recommended operating free-air temperature range, CL 100 pF (unless otherwise noted) (see Figure 14 and Figure 15) PARAMETER FROM (INPUT) TO (OUTPUT) P port INT MIN MAX tiv Interrupt valid time tir Interrupt reset delay time SCL INT tpv Output data valid SCL P port tps Input data setup time P port SCL 150 ns tph Input data hold time P port SCL 1 s 6 Submit Documentation Feedback 4 UNIT s 4 s 200 ns Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 PCA9555 www.ti.com SCPS131G - AUGUST 2005 - REVISED MARCH 2018 6.8 Typical Characteristics TA = 25C (unless otherwise noted) 55 30 SCL = V CC 50 V CC = 5 V 25 ICC - Supply Current - nA ICC - Supply Current - A 45 40 f SCL = 400 kHz I/Os Unloaded 35 30 25 V CC = 3.3 V 20 15 10 20 V CC = 5 V 15 V CC = 3.3 V 10 0 -50 -25 0 25 50 75 0 -50 100 TA - Free-Air Tem perature - C -25 0 25 50 75 100 TA - Free-Air Tem perature - C Figure 1. Supply Current vs Temperature Figure 2. Standby Supply Current vs Temperature 30 70 V CC = 2.5 V f SCL = 400 kHz I/Os Unloaded 25 ISINK - I/O Sink Current - mA 60 ICC - Supply Current - A V CC = 2.5 V 5 V CC = 2.5 V 5 50 40 30 20 10 TA = -40C 20 TA = 25C 15 10 TA = 125C 5 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 0 0.0 V CC - Supply Voltage - V 0.1 0.2 0.3 0.4 0.5 0.6 V OL - Output Low Voltage - V Figure 3. Supply Current vs Supply Voltage Figure 4. I/O Sink Current vs Output Low Voltage 50 40 V CC = 3.3 V TA = -40C TA = -40C 40 30 ISINK - I/O Sink Current - mA ISINK - I/O Sink Current - mA V CC = 5 V 45 35 25 TA = 25C 20 15 10 TA = 125C 35 TA = 25C 30 25 20 15 10 5 TA = 125C 5 0 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.0 V OL - Output Low Voltage - V 0.1 0.2 0.3 0.4 0.5 0.6 V OL - Output Low Voltage - V Figure 5. I/O Sink Current vs Output Low Voltage Figure 6. I/O Sink Current vs Output Low Voltage Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 7 PCA9555 SCPS131G - AUGUST 2005 - REVISED MARCH 2018 www.ti.com Typical Characteristics (continued) TA = 25C (unless otherwise noted) 300 35 V CC = 2.5 V, ISINK = 10 m A 275 V CC = 2.5 V ISOURCE - I/O Source Current - mA V OL - Output Low Voltage - mV 250 225 200 175 V CC = 5 V, ISINK = 10 m A 150 125 100 75 V CC = 2.5 V, ISINK = 1 m A 50 30 TA = -40C 25 TA = 25C 20 15 10 TA = 125C 5 V CC = 5 V, ISINK = 1 m A 25 0 0.0 0 -50 -25 0 25 50 75 0.1 0.2 100 0.3 0.4 0.5 0.6 0.7 (V CC - V OH) - V TA - Free-Air Tem perature - C Figure 8. I/O Source Current vs Output High Voltage Figure 7. I/O Output Low Voltage vs Temperature 50 TA = -40C 40 35 ISOURCE - I/O Source Current - mA ISOURCE - I/O Source Current - mA 75 70 65 V CC = 3.3 V 45 TA = 25C 30 25 20 15 10 TA = 125C 5 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 V CC = 5 V TA = -40C 60 55 50 45 40 TA = 25C 35 30 25 20 15 TA = 125C 10 5 0 0.7 0.0 0.1 (V CC - V OH) - V 1200 275 1100 250 1000 V CC = 2.5 V, IOL = 10 m A 225 ICC - Supply Current - A V OH - Output High Voltage - mV 8 0.4 0.5 0.6 0.7 Figure 10. I/O Source Current vs Output High Voltage 300 200 175 150 V CC = 5 V, IOL = 10 m A 100 75 V CC = 5 V TA = -40C 900 800 700 600 TA = 25C 500 400 300 50 200 25 100 0 -50 0.3 (V CC - V OH) - V Figure 9. I/O Source Current vs Output High Voltage 125 0.2 TA = 125C 0 -25 0 25 50 75 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 100 TA - Free-Air Tem perature - C Num ber of I/Os Held Low Figure 11. I/O High Voltage vs Temperature Figure 12. Supply Current vs Number Of I/Os Held Low Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 PCA9555 www.ti.com SCPS131G - AUGUST 2005 - REVISED MARCH 2018 Typical Characteristics (continued) TA = 25C (unless otherwise noted) 6 V OH - Output High Voltage - V TA = 25C 5 4 IOH = -8 m A 3 IOH = -10 m A 2 1 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 V CC - Supply Voltage - V Figure 13. Output High Voltage vs Supply Voltage Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 9 PCA9555 SCPS131G - AUGUST 2005 - REVISED MARCH 2018 www.ti.com 7 Parameter Measurement Information VCC RL = 1 kW SDA DUT CL = 50 pF SDA LOAD CONFIGURA TION Three Bytes for Complete Device Programming Stop Condition (P) Start Condition (S) Address Address Bit 7 Bit 6 (MSB) Address Bit 1 t scl R/W Bit 0 (LSB) ACK (A) Data Bit 07 (MSB) Data Bit 10 (LSB) Stop Condition (P) t sch 0.7 x VCC SCL 0.3 x VCC t icr t icf t buf t sts t PHL t PLH t sp 0.7 x VCC SDA 0.3 x VCC t icf t icr t sth t sdh t sds Start or Repeat Start Condition t sps Repeat Start Condition Stop Condition VOLTAGE WAVEFORMS BYTE DESCRIPTION 1 I2C address 2, 3 P-port data A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 14. I2C Interface Load Circuit And Voltage Waveforms 10 Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 PCA9555 www.ti.com SCPS131G - AUGUST 2005 - REVISED MARCH 2018 Parameter Measurement Information (continued) DUT Pn CL = 100 pF GND P-PORT LOAD CONFIGURATION SCL 0.7 x VCC P00 A P17 0.3 x VCC Slave ACK SDA tpv (see Note A) Pn Unstable Data Last Stable Bit WRITE MODE (R/W = 0) SCL 0.7 x VCC P00 A tps P17 0.3 x VCC tph 0.7 x VCC Pn 0.3 x VCC READ MODE (R/W = 1) A. CL includes probe and jig capacitance. B. tpv is measured from 0.7 x VCC on SCL to 50% I/O (Pn) output. C. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 15. P-Port Load Circuit And Voltage Waveforms Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 11 PCA9555 SCPS131G - AUGUST 2005 - REVISED MARCH 2018 www.ti.com 8 Detailed Description 8.1 Overview The system master can reset the PCA9555 in the event of a timeout or other improper operation by utilizing the power-on reset feature, which puts the registers in their default state and initializes the I2C/SMBus state machine. The PCA9555 open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the PCA9555 can remain a simple slave device. The device outputs (latched) have high-current drive capability for directly driving LEDs. Although pin-to-pin and I2C-address is compatible with the PCF8575, software changes are required due to the enhancements. The PCA9555 is identical to the PCA9535, except for the inclusion of the internal I/O pullup resistor, which pulls the I/O to a default high when configured as an input and undriven. Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address and allow up to eight devices to share the same I2C bus or SMBus. The fixed I2C address of the PCA9555 is the same as the PCF8575, PCF8575C, and PCF8574, allowing up to eight of these devices in any combination to share the same I2C bus or SMBus. 8.2 Functional Block Diagram INT A0 A1 A2 SCL SDA PCA9555 1 Interrupt Logic LP Filter 21 2 P07-P00 3 22 23 Input Filter I2C Bus Control Shift Register 16 Bits I/O Port P17-P10 Write Pulse VCC GND 24 12 Read Pulse Power-On Reset A. Pin numbers shown are for DB, DBQ, DGV, DW, and PW packages. B. All I/Os are set to inputs at reset. Figure 16. Logic Diagram 12 Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 PCA9555 www.ti.com SCPS131G - AUGUST 2005 - REVISED MARCH 2018 Functional Block Diagram (continued) Data From Shift Register Output Port Register Data Configuration Register Data From Shift Register D Q 100 k FF Write Configuration Pulse VCC Q1 D CLK Q Q FF I/O Pin CLK Q Write Pulse Output Port Register Q2 Input Port Register D GND Q Input Port Register Data FF Read Pulse CLK Q To INT Data From Shift Register D Polarity Register Data Q FF Write Polarity Pulse CLK Q Polarity Inversion Register (1) At power-on reset, all registers return to default values. Figure 17. Simplified Schematic Of P-Port I/Os 8.3 Device Features 8.3.1 Power-On Reset When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9555 in a reset condition until VCC has reached VPOR. At that point, the reset condition is released and the PCA9555 registers and I2C/SMBus state machine initialize to their default states. After that, VCC must be lowered to 0 V and then back up to the operating voltage for a power-reset cycle. Refer to the Power-On Reset Errata section. Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 13 PCA9555 SCPS131G - AUGUST 2005 - REVISED MARCH 2018 www.ti.com Device Features (continued) 8.3.2 I/O Port When an I/O is configured as an input, FETs Q1 and Q2 (in Figure 17) are off, creating a high-impedance input. The input voltage may be raised above VCC to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register. In this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation. 8.4 Device Functional Modes 8.4.1 Interrupt (INT) Output An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting, data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the Input Port register. Because each 8-pin port is read independently, the interrupt caused by port 0 is not cleared by a read of port 1 or vice versa. The INT output has an open-drain structure and requires pullup resistor to VCC. 8.4.1.1 Interrupt Errata 8.4.1.1.1 INT Description The INT will be improperly de-asserted if the following two conditions occur: i. The last I2C command byte (register pointer) written to the device was 00h. NOTE This generally means the last operation with the device was a Read of the input register. However, the command byte may have been written with 00h without ever going on to read the input register. After reading from the device, if no other command byte written, it will remain 00h. ii. Any other slave device on the I2C bus acknowledges an address byte with the R/W bit set high 8.4.1.1.2 System Impact Can cause improper interrupt handling as the Master will see the interrupt as being cleared. 8.4.1.1.3 System Workaround Minor software change: User must change command byte to something besides 00h after a Read operation to the PCA9555 device or before reading from another slave device. NOTE Software change will be compatible with other versions (competition and TI redesigns) of this device. 14 Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 PCA9555 www.ti.com SCPS131G - AUGUST 2005 - REVISED MARCH 2018 8.5 Programming 8.5.1 I2C Interface The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on the SDA input/output while the SCL input is high (see Figure 18). After the Start condition, the device address byte is sent, MSB first, including the data direction bit (R/W). This device does not respond to the general call address. After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output during the high of the ACK-related clock pulse. The address inputs (A0-A2) of the slave device must not be changed between the Start and Stop conditions. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (Start or Stop) (see Figure 19). A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master (see Figure 18). Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 20). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to ensure proper operation. A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition. SDA SCL S P Start Condition Stop Condition Figure 18. Definition Of Start And Stop Conditions SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 19. Bit Transfer Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 15 PCA9555 SCPS131G - AUGUST 2005 - REVISED MARCH 2018 www.ti.com Programming (continued) Data Output by Transmitter NACK Data Output by Receiver ACK SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgment Start Condition Figure 20. Acknowledgment On I2C Bus 8.5.2 Register Map Table 1. Interface Definition BYTE 16 BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) I2C slave address L H L L A2 A1 A0 R/W P0x I/O data bus P07 P06 P05 P04 P03 P02 P01 P00 P1x I/O data bus P17 P16 P15 P14 P13 P12 P11 P10 Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 PCA9555 www.ti.com SCPS131G - AUGUST 2005 - REVISED MARCH 2018 8.5.2.1 Device Address Figure 21 shows the address byte of the PCA9555. R/W Slave Address 0 1 0 Fixed 0 A2 A1 A0 Programmable Figure 21. PCA9555 Address Table 2. Address Reference INPUTS I2C BUS SLAVE ADDRESS A2 A1 A0 L L L 32 (decimal), 20 (hexadecimal) L L H 33 (decimal), 21 (hexadecimal) L H L 34 (decimal), 22 (hexadecimal) L H H 35 (decimal), 23 (hexadecimal) H L L 36 (decimal), 24 (hexadecimal) H L H 37 (decimal), 25 (hexadecimal) H H L 38 (decimal), 26 (hexadecimal) H H H 39 (decimal), 27 (hexadecimal) The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read operation, while a low (0) selects a write operation. 8.5.2.2 Control Register And Command Byte Following the successful acknowledgment of the address byte, the bus master sends a command byte that is stored in the control register in the PCA9555. Three bits of this data byte state the operation (read or write) and the internal register (input, output, polarity inversion, or configuration) that will be affected. This register can be written or read through the I2C bus. The command byte is sent only during a write transmission. Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent. Figure 22. Control Register Bits 7 0 6 0 5 0 4 0 3 0 2 B2 1 B1 0 B0 Table 3. Command Byte CONTROL REGISTER BITS B2 B1 B0 COMMAND BYTE (HEX) REGISTER PROTOCOL POWER-UP DEFAULT 0 0 0 0x00 Input Port 0 Read byte xxxx xxxx 0 0 1 0x01 Input Port 1 Read byte xxxx xxxx 0 1 0 0x02 Output Port 0 Read/write byte 1111 1111 0 1 1 0x03 Output Port 1 Read/write byte 1111 1111 1 0 0 0x04 Polarity Inversion Port 0 Read/write byte 0000 0000 1 0 1 0x05 Polarity Inversion Port 1 Read/write byte 0000 0000 1 1 0 0x06 Configuration Port 0 Read/write byte 1111 1111 1 1 1 0x07 Configuration Port 1 Read/write byte 1111 1111 Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 17 PCA9555 SCPS131G - AUGUST 2005 - REVISED MARCH 2018 www.ti.com 8.5.2.3 Register Descriptions The Input Port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these registers have no effect. The default value, X, is determined by the externally applied logic level. Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input Port register will be accessed next. Table 4. Registers 0 And 1 (Input Port Registers) Bit Default Bit Default I0.7 I0.6 I0.5 I0.4 I0.3 I0.2 I0.1 I0.0 X X X X X X X X I1.7 I1.6 I1.5 I1.4 I1.3 I1.2 I1.1 I1.0 X X X X X X X X The Output Port registers (registers 2 and 3) show the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. Table 5. Registers 2 And 3 (Output Port Registers) Bit Default Bit Default O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0 1 1 1 1 1 1 1 1 O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0 1 1 1 1 1 1 1 1 The Polarity Inversion registers (registers 4 and 5) allow polarity inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original polarity is retained. Table 6. Registers 4 And 5 (Polarity Inversion Registers) Bit Default Bit Default N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 0 0 0 0 0 0 0 N0.0 0 N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0 0 0 0 0 0 0 0 0 The Configuration registers (registers 6 and 7) configure the directions of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. Table 7. Registers 6 And 7 (Configuration Registers) Bit Default Bit Default 18 C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 1 1 1 1 1 1 1 1 C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0 1 1 1 1 1 1 1 1 Submit Documentation Feedback C0.0 Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 PCA9555 www.ti.com SCPS131G - AUGUST 2005 - REVISED MARCH 2018 8.5.2.4 Bus Transactions Data is exchanged between the master and the PCA9555 through write and read commands. 8.5.2.4.1 Writes Data is transmitted to the PCA9555 by sending the device address and setting the least-significant bit to a logic 0 (see Figure 21 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. The eight registers within the PCA9555 are configured to operate as four register pairs. The four pairs are input ports, output ports, polarity inversion ports, and configuration ports. After sending data to one register, the next data byte is sent to the other register in the pair (see Figure 23 and Figure 24). For example, if the first byte is sent to output port (register 3), the next byte is stored in Output Port 0 (register 2). There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register may be updated independently of the other registers. 1 SCL 2 3 4 5 6 7 8 9 Command Byte Slave Address SDA S 0 1 0 0 A2 A1 A0 Start Condition 0 0 A 0 0 0 0 Data to Port 0 0 1 0 0.7 A Data to Port 1 0.0 Data 0 Acknowledge From Slave R/W Acknowledge From Slave 1.7 A 1.0 Data 1 A P Acknowledge From Slave Write to Port Data Out from Port 0 tpv Data Valid Data Out from Port 1 tpv Figure 23. Write To Output Port Registers 1 SCL 2 3 4 5 6 7 8 9 1 2 3 Slave Address SDA S 0 1 Start Condition 0 0 A2 A1 A0 4 5 6 7 8 9 1 2 R/W A 0 0 Acknowledge From Slave 0 0 0 1 4 5 6 7 8 9 1 2 Data to Register Command Byte 0 3 1 0 A MSB Data 0 3 4 5 Data to Register LSB Acknowledge From Slave A MSB Data 1 LSB A P Acknowledge From Slave Figure 24. Write To Configuration Registers 8.5.2.4.2 Reads The bus master first must send the PCA9555 address with the least-significant bit set to a logic 0 (see Figure 21 for device address). The command byte is sent after the address and determines which register is accessed. After a restart, the device address is sent again, but this time, the least-significant bit is set to a logic 1. Data from the register defined by the command byte then is sent by the PCA9555 (see Figure 25 through Figure 27). After a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but the data now reflect the information in the other register in the pair. For example, if Input Port 1 is read, the next byte read is Input Port 0. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data. Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 19 PCA9555 SCPS131G - AUGUST 2005 - REVISED MARCH 2018 0 1 0 0 Acknowledge From Slave Acknowledge From Slave Slave Address S www.ti.com A2 A1 A0 0 Command Byte A A S Slave Address 0 1 0 0 A2 A1 A0 1 Acknowledge From Master Data A MSB LSB A First Byte At this moment, master transmitter becomes master receiver , and slave-receiver becomes slave-transmitter. R/W Data From Lower or Upper Byte of Register Acknowledge From Slave R/W Data From Upper or Lower Byte of Register MSB No Acknowledge From Master LSB NA Data P Last Byte Figure 25. Read From Register 1 SCL 2 3 4 5 6 7 8 9 I0.x SDA S 0 1 0 0 A2 A1 A0 1 R/W A 7 6 5 Acknowledge From Slave 4 3 I1.x 2 1 0 A 7 6 Acknowledge From Master 5 4 3 I0.x 2 1 0 A 7 6 5 4 3 I1.x 2 1 0 A 7 6 5 4 3 2 Acknowledge From Master Acknowledge From Master 1 0 1 P No Acknowledge From Master Read From Port 0 Data Into Port 0 Read From Port 1 Data Into Port 1 INT t iv t ir A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read Input Port register). B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from the P port (see Figure 25 for these details). Figure 26. Read Input Port Register, Scenario 1 20 Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 PCA9555 www.ti.com 1 SCL SCPS131G - AUGUST 2005 - REVISED MARCH 2018 2 3 4 5 6 7 8 9 I0.x SDA S 0 1 0 0 A2 A1 A0 1 R/W A 00 I1.x A 10 A I1.x 03 Acknowledge From Master Acknowledge From Master Acknowledge From Slave I0.x A P No Acknowledge From Master tps tph 1 12 Acknowledge From Master Read From Port 0 Data Into Port 0 Data 00 Data 01 Data 02 Data 03 tph Read From Port 1 Data 10 Data Into Port 1 tps Data 11 Data 12 INT t iv t ir A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read Input Port register). B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from the P port (see Figure 25 for these details). Figure 27. Read Input Port Register, Scenario 2 Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 21 PCA9555 SCPS131G - AUGUST 2005 - REVISED MARCH 2018 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.2 Typical Application Figure 28 shows an application in which the PCA9555 can be used. Subsystem 1 (e.g., Temperature Sensor) INT VCC (5 V) VCC Master Controller 10 k 10 k 10 k 24 10 k 22 SCL 23 SDA 1 INT Subsystem 2 (e.g., Counter) 2k VCC SCL SDA INT P00 P01 P02 P03 GND P04 P05 RESET 4 5 A 6 7 ENABLE 8 9 B PCA9555 VCC P06 P07 3 A2 P10 P11 2 A1 P12 P13 21 A0 P14 P15 P16 GND P17 12 A. Device address is configured as 0100100 for this example. B. P00, P02, and P03 are configured as outputs. C. P01, P04-P07, and P10-P17 are configured as inputs. D. Pin numbers shown are for DB, DBQ, DGV, DW, and PW packages. 10 11 13 14 15 16 17 18 19 20 Controlled Switch (e.g., CBT Device) ALARM Keypad Subsystem 3 (e.g., Alarm) Figure 28. Typical Application 22 Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 PCA9555 www.ti.com SCPS131G - AUGUST 2005 - REVISED MARCH 2018 Typical Application (continued) 9.2.1 Design Requirements For this design example, use the parameters shown in Table 8. Table 8. Design Parameters DESIGN PARAMETER EXAMPLE VALUE 2 I C and Subsystem Voltage (VCC) 5V Output current rating, P-port sinking (IOL) 25 mA I2C bus clock (SCL) speed 400 kHz 9.2.2 Design Requirements 9.2.2.1 Minimizing ICC When I/O Is Used To Control Led When an I/O is used to control an LED, normally it is connected to VCC through a resistor as shown in Figure 28. Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ICC parameter in Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC. For batterypowered applications, it is essential that the voltage of I/O pins is greater than or equal to VCC when the LED is off to minimize current consumption. Figure 29 shows a high-value resistor in parallel with the LED. Figure 30 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevent additional supply current consumption when the LED is off. VCC LED 100 k VCC Pn Figure 29. High-Value Resistor In Parallel With Led 3.3 V VCC 5V LED Pn Figure 30. Device Supplied By Lower Voltage Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 23 PCA9555 SCPS131G - AUGUST 2005 - REVISED MARCH 2018 www.ti.com 9.2.3 Application Curves 1.8 Standard-Mode Fast-Mode Minimum Pull-Up Resistance (k:) Maximum Pull-Up Resistance (k:) 25 20 15 10 5 VDPUX > 2 V VDUPX </= 2 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 0 50 100 150 200 250 300 Bus Capacitance (pF) 350 400 450 0 0.5 D008 1 1.5 2 2.5 3 3.5 4 Pull-Up Reference Voltage (V) 4.5 5 5.5 D009 VOL = 0.2 x VCC, IOL = 2 mA when VCC 2 V VOL = 0.4 V, IOL = 3 mA when VCC > 2 V Standard-mode: fSCL = 100 kHz, tr = 1 s Fast-mode: fSCL = 400 kHz, tr = 300 ns Figure 31. Maximum Pull-Up Resistance (Rp(max)) vs Bus Capacitance (Cb) Figure 32. Minimum Pull-Up Resistance (Rp(min)) vs Pull-up Reference Voltage (VCC) 10 Power Supply Recommendations 10.1 Power-On Reset Errata A power-on reset condition can be missed if the VCC ramps are outside specification listed below. 10.1.1 System Impact If ramp conditions are outside timing allowances above, POR condition can be missed, causing the device to lock up. 24 Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 PCA9555 www.ti.com SCPS131G - AUGUST 2005 - REVISED MARCH 2018 11 Layout 11.1 Layout Guidelines For printed circuit board (PCB) layout of the PCA9555, common PCB layout practices must be followed, but additional concerns related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C signal speeds. In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller capacitor to filter out highfrequency ripple. These capacitors must be placed as close to the PCA9555 as possible. These best practices are shown in the Layout Example. For the layout example provided in the Layout Example, it is possible to fabricate a PCB with only 2 layers by using the top layer for signal routing and the bottom layer as a split plane for power (VCC) and ground (GND). However, a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other internal layer to a power plane. In a board layout using planes or split planes for power and ground, vias are placed directly next to the surface mount component pad which needs to attach to VCC, or GND and the via is connected electrically to the internal layer or the other side of the board. Vias are also used when a signal trace needs to be routed to the opposite side of the board, but this technique is not demonstrated in the Layout Example. 11.2 Layout Example Figure 33. PCA9555 Example Layout Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 25 PCA9555 SCPS131G - AUGUST 2005 - REVISED MARCH 2018 www.ti.com 12 Device and Documentation Support 12.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.2 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.4 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 26 Submit Documentation Feedback Copyright (c) 2005-2018, Texas Instruments Incorporated Product Folder Links: PCA9555 PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) PCA9555DB ACTIVE SSOP DB 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD9555 PCA9555DBQR ACTIVE SSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PCA9555 PCA9555DBR ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD9555 PCA9555DGVR ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD9555 PCA9555DW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9555 PCA9555DWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9555 PCA9555DWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9555 PCA9555DWT NRND SOIC DW 24 TBD Call TI Call TI -40 to 85 PCA9555N NRND PDIP N 24 TBD Call TI Call TI -40 to 85 PCA9555PW ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD9555 PCA9555PWE4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD9555 PCA9555PWR NRND TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD9555 PCA9555PWRG4 NRND TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD9555 PCA9555PWT NRND TSSOP PW 24 TBD Call TI Call TI -40 to 85 PCA9555RGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PD9555 PCA9555RGERG4 ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PD9555 PCA9555RHLR NRND VQFN RHL 24 TBD Call TI Call TI -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 27-Feb-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCA9555DBQR Package Package Pins Type Drawing SSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PCA9555DBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 PCA9555DGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PCA9555DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 PCA9555PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 PCA9555RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 27-Feb-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCA9555DBQR SSOP DBQ 24 2500 367.0 367.0 38.0 PCA9555DBR SSOP DB 24 2000 367.0 367.0 38.0 PCA9555DGVR TVSOP DGV 24 2000 367.0 367.0 35.0 PCA9555DWR SOIC DW 24 2000 367.0 367.0 45.0 PCA9555PWR TSSOP PW 24 2000 367.0 367.0 38.0 PCA9555RGER VQFN RGE 24 3000 367.0 367.0 35.0 Pack Materials-Page 2 GENERIC PACKAGE VIEW RGE 24 VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4204104/H PACKAGE OUTLINE VQFN - 1 mm max height RGE0024C PLASTIC QUAD FLATPACK- NO LEAD A 4.1 3.9 B 4.1 3.9 PIN 1 INDEX AREA 1 MAX C SEATING PLANE 0.05 0.00 0.08 C 2X 2.5 2.10.1 (0.2) TYP 12 7 20X 0.5 6 13 25 2X 2.5 SYMM 1 PIN 1 ID (OPTIONAL) 18 24X 0.30 0.18 24 19 SYMM 24X 0.50 0.30 0.1 0.05 C A B C 4224376 / A 07/2018 NOTES: 1. 2. 3. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. This drawing is subject to change without notice. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT VQFN - 1 mm max height RGE0024C PLASTIC QUAD FLATPACK- NO LEAD (3.8) ( 2.1) 19 24 24X (0.6) 24X (0.24) 1 18 20X (0.5) 25 SYMM (3.8) 2X (0.8) (O0.2) VIA TYP 6 13 (R0.05) 12 7 2X(0.8) SYMM LAND PATTERN EXAMPLE SCALE: 20X 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND METAL SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) METAL UNDER SOLDER MASK SOLDER MASK DEFINED SOLDER MASK DETAILS 4224376 / A 07/2018 NOTES: (continued) 4. 5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN VQFN - 1 mm max height RGE0024C PLASTIC QUAD FLATPACK- NO LEAD (0.19) 4X ( 0.94) 19 24 24X (0.58) 24X (0.24) 1 18 20X (0.5) SYMM (3.8) (0.57) TYP 6 13 (R0.05) TYP METAL TYP 25 7 SYMM 12 (0.57) TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 80% PRINTED COVERAGE BY AREA SCALE: 20X 4224376 / A 07/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.. www.ti.com MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI's published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyers and others who are developing systems that incorporate TI products (collectively, "Designers") understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers' applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications. TI's provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, "TI Resources") are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer's company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. TI's provision of TI Resources does not expand or otherwise alter TI's applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED "AS IS" AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers' own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer's noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2018, Texas Instruments Incorporated Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: PCA9555DB PCA9555DBQR PCA9555DBR PCA9555DGVR PCA9555DW PCA9555DWR PCA9555PW PCA9555PWE4 PCA9555PWR PCA9555PWRE4 PCA9555RGER PCA9555DBQRG4 PCA9555DWG4 PCA9555DWRG4 PCA9555PWG4 PCA9555PWRG4 PCA9555RGERG4