PCA9555DB - Texas Instruments

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Port

P17−P10

Shift

LP Filter

Interrupt

Logic

Input

Filter

Power-On

Reset

Read Pulse

Write Pulse

PCA9555

GND

VCC

SDA

SCL

INT

I2C Bus

Control

P07−P00

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

PCA9555

SCPS131G –AUGUST 2005–REVISED MARCH 2018

PCA9555 Remote 16-Bit I

C and SMBus I/O Expander With Interrupt Output and

Configuration Registers

1 Features

1• Low Standby-Current Consumption of 1 μA Max

• I2C to Parallel Port Expander

• Open-Drain Active-Low Interrupt Output

• 5-V Tolerant I/O Ports

• Compatible With Most Microcontrollers

• 400-kHz Fast I2C Bus

• Address by Three Hardware Address Pins for Use

of up to Eight Devices

• Polarity Inversion Register

• Latched Outputs With High-Current Drive

Capability for Directly Driving LEDs

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

2 Applications

• Servers

• Routers (Telecom Switching Equipment)

• Personal Computers

• Personal Electronics

• Industrial Automation Equipment

• Products with GPIO-Limited Processors

3 Description

This 16-bit I/O expander for the two-line bidirectional

bus (I2C) is designed for 2.3-V to 5.5-V VCC

operation. It provides general-purpose remote I/O

expansion for most microcontroller families via the I2C

interface [serial clock (SCL), serial data (SDA)].

The PCA9555 consists of two 8-bit Configuration

(input or output selection), Input Port, Output Port,

and Polarity Inversion (active high or active low

operation) registers. At power on, the I/Os are

configured as inputs. The system master can enable

the I/Os as either inputs or outputs by writing to the

I/O configuration bits. The data for each input or

output is kept in the corresponding Input or Output

inverted with the Polarity Inversion register. All

registers can be read by the system master.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

PCA9555 SSOP (16) 6.20 mm × 5.30 mm

VQFN (16) 4.00 mm × 4.00 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Block Diagram

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ..................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 I2C Interface Timing Requirements........................... 6

6.7 Switching Characteristics.......................................... 6

6.8 Typical Characteristics.............................................. 7

7 Parameter Measurement Information ................ 10

8 Detailed Description............................................ 12

8.1 Overview................................................................. 12

8.2 Functional Block Diagram....................................... 12

8.3 Device Features...................................................... 13

8.4 Device Functional Modes........................................ 14

8.5 Programming........................................................... 15

9 Application and Implementation ........................ 22

9.1 Application Information............................................ 22

9.2 Typical Application ................................................. 22

10 Power Supply Recommendations ..................... 24

10.1 Power-On Reset Errata......................................... 24

11 Layout................................................................... 25

11.1 Layout Guidelines ................................................. 25

11.2 Layout Example .................................................... 25

12 Device and Documentation Support................. 26

12.1 Community Resources.......................................... 26

12.2 Trademarks........................................................... 26

12.3 Electrostatic Discharge Caution............................ 26

12.4 Glossary................................................................ 26

13 Mechanical, Packaging, and Orderable

Information........................................................... 26

4 Revision History

Changes from Revision F (June 2014) to Revision G Page

• Added the Applications list .................................................................................................................................................... 1

• Removed the Thermal Information from the Absolute Maximum Ratings.............................................................................. 4

• Added Storage temperature range to the Absolute Maximum Ratings.................................................................................. 4

• Changed the Handling Ratings table to the ESD Ratings table............................................................................................. 4

• Added the Thermal Information table .................................................................................................................................... 5

• Changed From: "VCC must be lowered to below 0.2 V" To: VCC must be lowered to 0 V" in the Power-On Reset section. 13

• Added the Design Requirements section ............................................................................................................................ 23

• Added the Application Curves section ................................................................................................................................. 24

• Added the Layout section .................................................................................................................................................... 25

Changes from Revision E (May 2008) to Revision F Page

• Added Interrupt Errata section.............................................................................................................................................. 14

• Added Power-On Reset Errata section................................................................................................................................ 24

1INT 24 VCC

2A1 23 SDA

3A2 22 SCL

4P00 21 A0

5P01 20 P17

6P02 19 P16

7P03 18 P15

8P04 17 P14

9P05 16 P13

10P06 15 P12

11P07 14 P11

12GND 13 P10

Not to scale

24 A27P06

1P00 18 A0

23 A18P07

2P01 17 P17

22 INT9GND

3P02 16 P16

21 VCC 10P10

4P03 15 P15

20 SDA11P11

5P04 14 P14

19 SCL12P12

6P05 13 P13

Not to scale

Thermal

Pad

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5 Pin Configuration and Functions

DB, DBQ, DGV, DW or PW Package

24 Pin (SOP)

(Top View) RGE Package

24 Pin (QFN)

(Top View)

Pin Functions

DESCRIPTION

NAME

SSOP (DB),

QSOP (DBQ),

TSSOP (PW), AND

TVSOP (DGV)

QFN (RGE)

INT 1 22 Interrupt output. Connect to VCC through a pullup resistor.

A1 2 23 Address input 1. Connect directly to VCC or ground.

A2 3 24 Address input 2. Connect directly to VCC or ground.

P00 4 1 P-port input/output. Push-pull design structure.

P01 5 2 P-port input/output. Push-pull design structure.

P02 6 3 P-port input/output. Push-pull design structure.

P03 7 4 P-port input/output. Push-pull design structure.

P04 8 5 P-port input/output. Push-pull design structure.

P05 9 6 P-port input/output. Push-pull design structure.

P06 10 7 P-port input/output. Push-pull design structure.

P07 11 8 P-port input/output. Push-pull design structure.

GND 12 9 Ground

P10 13 10 P-port input/output. Push-pull design structure.

P11 14 11 P-port input/output. Push-pull design structure.

P12 15 12 P-port input/output. Push-pull design structure.

P13 16 13 P-port input/output. Push-pull design structure.

P14 17 14 P-port input/output. Push-pull design structure.

P15 18 15 P-port input/output. Push-pull design structure.

P16 19 16 P-port input/output. Push-pull design structure.

P17 20 17 P-port input/output. Push-pull design structure.

A0 21 18 Address input 0. Connect directly to VCC or ground.

SCL 22 19 Serial clock bus. Connect to VCC through a pullup resistor.

SDA 23 20 Serial data bus. Connect to VCC through a pullup resistor.

VCC 24 21 Supply voltage

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6 Specifications

6.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

VCC Supply voltage range –0.5 6 V

VIInput voltage range(2) –0.5 6 V

VOOutput voltage range(2) –0.5 6 V

IIK Input clamp current VI< 0 –20 mA

IOK Output clamp current VO< 0 –20 mA

IIOK Input/output clamp current VO< 0 or VO> VCC ±20 mA

IOL Continuous output low current VO= 0 to VCC 50 mA

IOH Continuous output high current VO= 0 to VCC –50 mA

ICC Continuous current through GND –250 mA

Continuous current through VCC 160

Tstg Storage temperature range –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings MIN MAX UNIT

V(ESD) Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins(1) 0 2000 V

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins(2) 0 1000

6.3 Recommended Operating Conditions MIN MAX UNIT

VCC Supply voltage 2.3 5.5 V

VIH High-level input voltage SCL, SDA 0.7 × VCC 5.5 V

A2–A0, P07–P00, P17–P10 0.7 × VCC 5.5

VIL Low-level input voltage SCL, SDA –0.5 0.3 × VCC V

A2–A0, P07–P00, P17–P10 –0.5 0.3 × VCC

IOH High-level output current P07–P00, P17–P10 –10 mA

IOL Low-level output current P07–P00, P17–P10 25 mA

TAOperating free-air temperature –40 85 °C

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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.4 Thermal Information

THERMAL METRIC(1)

PCA9555

UNITDB (SSOP) DBQ (QSOP) DGV (TVSOP) PW (TSSOP) RGE (QFN)

24 PINS 24 PINS 24 PINS 24 PINS 24 PINS

RθJA Junction-to-ambient thermal resistance 81.1 81.8 105.4 91.0 43.6 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 41.5 39.3 36.7 35.5 37.8 °C/W

RθJB Junction-to-board thermal resistance 40.0 36.0 50.8 46.1 21.0 °C/W

ψJT Junction-to-top characterization parameter 9.9 7.6 2.4 2.8 0.9 °C/W

ψJB Junction-to-board characterization parameter 39.6 35.6 50.3 45.7 21.0 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a 5.4 °C/W

(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA= 25°C.

(2) Each I/O must be externally limited to a maximum of 25 mA, and each octal (P07–P00 and P17–P10) must be limited to a maximum

current of 100 mA, for a device total of 200 mA.

(3) The total current sourced by all I/Os must be limited to 160 mA (80 mA for P07–P00 and 80 mA for P17–P10).

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT

VIK Input diode clamp voltage II= –18 mA 2.3 V to 5.5 V –1.2 V

VPOR Power-on reset voltage VI= VCC or GND, IO= 0 VPOR 1.5 1.65 V

VOH P-port high-level output voltage(2)

IOH = –8 mA

2.3 V 1.8

3 V 2.6

4.75 V 4.1

IOH = –10 mA

2.3 V 1.7

3 V 2.5

4.75 V 4

IOL

SDA VOL = 0.4 V

2.3 V to 5.5 V

mAP port(3) VOL = 0.5 V 8 20

VOL = 0.7 V 10 24

INT VOL = 0.4 V 3

IISCL, SDA VI= VCC or GND 2.3 V to 5.5 V ±1 μA

A2–A0 ±1

IIH P port VI= VCC 2.3 V to 5.5 V 1 μA

IIL P port VI= GND 2.3 V to 5.5 V –100 μA

ICC

Operating mode VI= VCC or GND, IO= 0,

I/O = inputs, fSCL = 400 kHz, No load

5.5 V 100 200

μA3.6 V 30 75

2.7 V 20 50

Standby mode

Low inputs VI= GND, IO= 0, I/O = inputs,

fSCL = 0 kHz, No load

5.5 V 1.1 1.5

mA3.6 V 0.7 1.3

2.7 V 0.5 1

High inputs VI= VCC, IO= 0, I/O = inputs,

fSCL = 0 kHz, No load

5.5 V 0.5 1

μA3.6 V 0.4 0.9

2.7 V 0.25 0.8

ΔICC Additional current in standby mode One input at VCC – 0.6 V,

Other inputs at VCC or GND 2.3 V to 5.5 V 1.5 mA

CISCL VI= VCC or GND 2.3 V to 5.5 V 3 7 pF

Cio SDA VIO = VCC or GND 2.3 V to 5.5 V 3 7 pF

P port 3.7 9.5

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(1) Cb= total capacitance of one bus line in pF.

6.6 I2C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 14)MIN MAX UNIT

fscl I2C clock frequency 0 400 kHz

tsch I2C clock high time 0.6 μs

tscl I2C clock low time 1.3 μs

tsp I2C spike time 50 ns

tsds I2C serial-data setup time 100 ns

tsdh I2C serial-data hold time 0 ns

ticr I2C input rise time 20 + 0.1Cb(1) 300 ns

ticf I2C input fall time 20 + 0.1Cb(1) 300 ns

tocf I2C output fall time 10-pF to 400-pF bus 20 + 0.1Cb(1) 300 ns

tbuf I2C bus free time between Stop and Start 1.3 μs

tsts I2C Start or repeated Start condition setup 0.6 μs

tsth I2C Start or repeated Start condition hold 0.6 μs

tsps I2C Stop condition setup 0.6 μs

tvd(Data) Valid-data time SCL low to SDA output valid 50 ns

tvd(ack) Valid-data time of ACK condition ACK signal from SCL low to SDA (out) low 0.1 0.9 μs

CbI2C bus capacitive load 400 pF

6.7 Switching Characteristics

over recommended operating free-air temperature range, CL≤100 pF (unless otherwise noted) (see Figure 14 and Figure 15)

PARAMETER FROM

(INPUT) TO

(OUTPUT) MIN MAX UNIT

tiv Interrupt valid time P port INT 4 μs

tir Interrupt reset delay time SCL INT 4 μs

tpv Output data valid SCL P port 200 ns

tps Input data setup time P port SCL 150 ns

tph Input data hold time P port SCL 1 μs

0.0 0.1 0.2 0.3 0.4 0.5 0.6

VOL – Output Low Voltage – V

ISINK – I/O Sink Current – mA

TA= –40°C

VCC = 3.3 V

TA= 25°C

TA= 125°C

0.0 0.1 0.2 0.3 0.4 0.5 0.6

VOL – Output Low Voltage – V

ISINK – I/O Sink Current – mA

TA= –40°C

VCC = 5 V

TA= 25°C

TA= 125°C

0.0 0.1 0.2 0.3 0.4 0.5 0.6

VOL – Output Low Voltage – V

ISINK – I/O Sink Current – mA

TA= –40°C

VCC = 2.5 V

TA= 25°C

TA= 125°C

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

VCC – Supply Voltage – V

ICC – Supply Current – µA

fSCL = 400 kHz

I/Os Unloaded

-50 -25 0 25 50 75 100

TA– Free-Air Tem perature – °C

ICC – Supply Current – nA

VCC = 2.5 V

VCC = 3.3 V

VCC = 5 V

SCL = VCC

-50 -25 0 25 50 75 100

TA– Free-Air Tem perature – °C

ICC – Supply Current – µA

VCC = 2.5 V

VCC = 3.3 V

VCC = 5 V

fSCL = 400 kHz

I/Os Unloaded

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6.8 Typical Characteristics

TA= 25°C (unless otherwise noted)

Figure 1. Supply Current vs Temperature Figure 2. Standby Supply Current vs Temperature

Figure 3. Supply Current vs Supply Voltage Figure 4. I/O Sink Current vs Output Low Voltage

Figure 5. I/O Sink Current vs Output Low Voltage Figure 6. I/O Sink Current vs Output Low Voltage

100

125

150

175

200

225

250

275

300

-50 -25 0 25 50 75 100

TA– Free-Air Tem perature – °C

VOH – Output High Voltage – mV

VCC = 5 V, IOL = 10 mA

VCC = 2.5 V, IOL = 10 mA

100

200

300

400

500

600

700

800

900

1000

1100

1200

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Num ber of I/Os Held Low

ICC – Supply Current – µA

TA= –40°C

VCC = 5 V

TA= 25°C

TA= 125°C

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

(VCC – VOH) – V

ISOURCE – I/O Source Current – mA

TA= –40°C

VCC = 5 V

TA= 25°C

TA= 125°C

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

(VCC – VOH) – V

ISOURCE – I/O Source Current – mA

TA= –40°C

VCC = 3.3 V

TA= 25°C

TA= 125°C

100

125

150

175

200

225

250

275

300

-50 -25 0 25 50 75 100

TA– Free-Air Tem perature – °C

VOL – Output Low Voltage – mV

VCC = 5 V, ISINK = 10 mA

VCC = 2.5 V, ISINK = 10 m A

VCC = 2.5 V, ISINK = 1 m A

VCC = 5 V, ISINK = 1 mA

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

(VCC – VOH) – V

ISOURCE – I/O Source Current – mA

TA= –40°C

VCC = 2.5 V

TA= 25°C

TA= 125°C

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Typical Characteristics (continued)

TA= 25°C (unless otherwise noted)

Figure 7. I/O Output Low Voltage vs Temperature Figure 8. I/O Source Current vs Output High Voltage

Figure 9. I/O Source Current vs Output High Voltage Figure 10. I/O Source Current vs Output High Voltage

Figure 11. I/O High Voltage vs Temperature Figure 12. Supply Current vs Number Of I/Os Held Low

2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

VCC – Supply Voltage – V

VOH – Output High Voltage – V

IOH = –10 m A

IOH = –8 m A

TA= 25°C

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Typical Characteristics (continued)

TA= 25°C (unless otherwise noted)

Figure 13. Output High Voltage vs Supply Voltage

RL= 1 kW

VCC

CL= 50 pF

tbuf

ticr

tsth tsds

tsdh

ticf

ticr

tscl tsch

tsts

tPHL

tPLH

0.3 ×VCC

Stop

Condition

tsps

Repeat

Start

Condition

Start or

Repeat

Start

Condition

SCL

SDA

Start

Condition

(S)

Address

Bit 7

(MSB)

Data

Bit 10

(LSB)

Stop

Condition

(P)

Three Bytes for Complete

Device Programming

SDA LOAD CONFIGURA TION

VOLTAGE WAVEFORMS

ticf

Stop

Condition

(P)

tsp

DUT SDA

0.7 ×VCC

0.3 ×VCC

0.7 ×VCC

R/W

Bit 0

(LSB)

ACK

(A)

Data

Bit 07

(MSB)

Address

Bit 1

Address

Bit 6

BYTE DESCRIPTION

1 I2C address

2, 3 P-port data

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7 Parameter Measurement Information

A. CLincludes probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.

C. All parameters and waveforms are not applicable to all devices.

Figure 14. I2C Interface Load Circuit And Voltage Waveforms

P00 A

0.7 ×VCC

0.3 ×VCC

SCL P17

tpv

(see Note A)

Slave

ACK

Unstable

Data

Last Stable Bit

SDA

WRITE MODE (R/W = 0)

P00 A

0.7 ×VCC

0.3 ×VCC

SCL P17

0.7 ×VCC

0.3 ×VCC

tps tph

READ MODE (R/W = 1)

DUT

GND

CL= 100 pF

P-PORT LOAD CONFIGURATION

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Parameter Measurement Information (continued)

A. CLincludes probe and jig capacitance.

B. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.

C. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.

D. The outputs are measured one at a time, with one transition per measurement.

E. All parameters and waveforms are not applicable to all devices.

Figure 15. P-Port Load Circuit And Voltage Waveforms

I/O

Port

P17−P10

Shift

LP Filter

Interrupt

Logic

Input

Filter

Power-On

Reset

Read Pulse

Write Pulse

PCA9555

GND

VCC

SDA

SCL

INT

I2C Bus

Control

P07−P00

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8 Detailed Description

8.1 Overview

The system master can reset the PCA9555 in the event of a timeout or other improper operation by utilizing the

power-on reset feature, which puts the registers in their default state and initializes the I2C/SMBus state machine.

The PCA9555 open-drain interrupt (INT) output is activated when any input state differs from its corresponding

Input Port register state and is used to indicate to the system master that an input state has changed.

INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the

remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via

the I2C bus. Thus, the PCA9555 can remain a simple slave device.

The device outputs (latched) have high-current drive capability for directly driving LEDs.

Although pin-to-pin and I2C-address is compatible with the PCF8575, software changes are required due to the

enhancements.

The PCA9555 is identical to the PCA9535, except for the inclusion of the internal I/O pullup resistor, which pulls

the I/O to a default high when configured as an input and undriven.

Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address and allow up to eight

devices to share the same I2C bus or SMBus. The fixed I2C address of the PCA9555 is the same as the

PCF8575, PCF8575C, and PCF8574, allowing up to eight of these devices in any combination to share the same

I2C bus or SMBus.

8.2 Functional Block Diagram

A. Pin numbers shown are for DB, DBQ, DGV, DW, and PW packages.

B. All I/Os are set to inputs at reset.

Figure 16. Logic Diagram

VCC

CLK

D Q

Conﬁguration

Data From

Shift Register

Data From

Shift Register

Write Conﬁguration

Pulse

CLK

D Q

Write Pulse

Output Port

100 k

GND

I/O Pin

Output Port

CLK

D Q

Input Port

Read Pulse

CLK

D Q

Polarity Inversion

Write Polarity

Pulse

Input Port

Polarity

To INT

Data From

Shift Register

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Functional Block Diagram (continued)

(1) At power-on reset, all registers return to default values.

Figure 17. Simplified Schematic Of P-Port I/Os

8.3 Device Features

8.3.1 Power-On Reset

When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9555 in a reset condition until

VCC has reached VPOR. At that point, the reset condition is released and the PCA9555 registers and I2C/SMBus

state machine initialize to their default states. After that, VCC must be lowered to 0 V and then back up to the

operating voltage for a power-reset cycle.

Refer to the Power-On Reset Errata section.

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Device Features (continued)

8.3.2 I/O Port

When an I/O is configured as an input, FETs Q1 and Q2 (in Figure 17) are off, creating a high-impedance input.

The input voltage may be raised above VCC to a maximum of 5.5 V.

If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register. In

this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage

applied to this I/O pin should not exceed the recommended levels for proper operation.

8.4 Device Functional Modes

8.4.1 Interrupt (INT) Output

An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the

signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original

setting, data is read from the port that generated the interrupt. Resetting occurs in the read mode at the

acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal.

Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of

the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.

Writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an

interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin

does not match the contents of the Input Port register. Because each 8-pin port is read independently, the

interrupt caused by port 0 is not cleared by a read of port 1 or vice versa.

The INT output has an open-drain structure and requires pullup resistor to VCC.

8.4.1.1 Interrupt Errata

8.4.1.1.1 INT Description

The INT will be improperly de-asserted if the following two conditions occur:

i. The last I2C command byte (register pointer) written to the device was 00h.

NOTE

This generally means the last operation with the device was a Read of the input

going on to read the input register. After reading from the device, if no other command

byte written, it will remain 00h.

ii. Any other slave device on the I2C bus acknowledges an address byte with the R/W bit set high

8.4.1.1.2 System Impact

Can cause improper interrupt handling as the Master will see the interrupt as being cleared.

8.4.1.1.3 System Workaround

Minor software change: User must change command byte to something besides 00h after a Read operation to

the PCA9555 device or before reading from another slave device.

NOTE

Software change will be compatible with other versions (competition and TI redesigns) of

this device.

SDA

SCL

Data Line

Stable;

Data Valid

Change

of Data

Allowed

SDA

SCL

Start Condition

Stop Condition

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8.5 Programming

8.5.1 I2C Interface

The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be

connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on

the SDA input/output while the SCL input is high (see Figure 18). After the Start condition, the device address

byte is sent, MSB first, including the data direction bit (R/W). This device does not respond to the general call

address.

After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output during

the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must not be changed

between the Start and Stop conditions.

On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (Start or Stop) (see Figure 19).

A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 18).

Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see

Figure 20). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,

the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold

times must be met to ensure proper operation.

A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after

the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.

In this event, the transmitter must release the data line to enable the master to generate a Stop condition.

Figure 18. Definition Of Start And Stop Conditions

Figure 19. Bit Transfer

Data Output

by Transmitter

SCL From

Master

Start

Condition

1 2 8 9

Data Output

by Receiver

Clock Pulse for

Acknowledgment

NACK

ACK

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Programming (continued)

Figure 20. Acknowledgment On I2C Bus

8.5.2 Register Map

Table 1. Interface Definition

BYTE BIT

7 (MSB) 6 5 4 3 2 1 0 (LSB)

I2C slave address L H L L A2 A1 A0 R/W

P0x I/O data bus P07 P06 P05 P04 P03 P02 P01 P00

P1x I/O data bus P17 P16 P15 P14 P13 P12 P11 P10

0 1 0 0 A1A2 A0

Slave Address

R/W

Fixed Programmable

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8.5.2.1 Device Address

Figure 21 shows the address byte of the PCA9555.

Figure 21. PCA9555 Address

Table 2. Address Reference

INPUTS I2C BUS SLAVE ADDRESS

A2 A1 A0

L L L 32 (decimal), 20 (hexadecimal)

L L H 33 (decimal), 21 (hexadecimal)

L H L 34 (decimal), 22 (hexadecimal)

L H H 35 (decimal), 23 (hexadecimal)

H L L 36 (decimal), 24 (hexadecimal)

H L H 37 (decimal), 25 (hexadecimal)

H H L 38 (decimal), 26 (hexadecimal)

H H H 39 (decimal), 27 (hexadecimal)

The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read

operation, while a low (0) selects a write operation.

8.5.2.2 Control Register And Command Byte

Following the successful acknowledgment of the address byte, the bus master sends a command byte that is

stored in the control register in the PCA9555. Three bits of this data byte state the operation (read or write) and

the internal register (input, output, polarity inversion, or configuration) that will be affected. This register can be

written or read through the I2C bus. The command byte is sent only during a write transmission.

Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a

new command byte has been sent.

Figure 22. Control Register Bits

76543210

0 0 0 0 0 B2 B1 B0

Table 3. Command Byte

CONTROL REGISTER BITS COMMAND

BYTE (HEX) REGISTER PROTOCOL POWER-UP

DEFAULT

B2 B1 B0

0 0 0 0x00 Input Port 0 Read byte xxxx xxxx

0 0 1 0x01 Input Port 1 Read byte xxxx xxxx

0 1 0 0x02 Output Port 0 Read/write byte 1111 1111

0 1 1 0x03 Output Port 1 Read/write byte 1111 1111

1 0 0 0x04 Polarity Inversion Port 0 Read/write byte 0000 0000

1 0 1 0x05 Polarity Inversion Port 1 Read/write byte 0000 0000

1 1 0 0x06 Configuration Port 0 Read/write byte 1111 1111

1 1 1 0x07 Configuration Port 1 Read/write byte 1111 1111

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8.5.2.3 Register Descriptions

The Input Port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the

pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to

these registers have no effect. The default value, X, is determined by the externally applied logic level.

Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the

Input Port register will be accessed next.

Table 4. Registers 0 And 1 (Input Port Registers)

Bit I0.7 I0.6 I0.5 I0.4 I0.3 I0.2 I0.1 I0.0

Default XXXXXXXX

Bit I1.7 I1.6 I1.5 I1.4 I1.3 I1.2 I1.1 I1.0

Default XXXXXXXX

The Output Port registers (registers 2 and 3) show the outgoing logic levels of the pins defined as outputs by the

Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this

Table 5. Registers 2 And 3 (Output Port Registers)

Bit O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0

Default 11111111

Bit O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0

Default 11111111

The Polarity Inversion registers (registers 4 and 5) allow polarity inversion of pins defined as inputs by the

Configuration register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is

inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original polarity is

retained.

Table 6. Registers 4 And 5 (Polarity Inversion Registers)

Bit N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0

Default 00000000

Bit N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0

Default 00000000

The Configuration registers (registers 6 and 7) configure the directions of the I/O pins. If a bit in this register is

set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this

Table 7. Registers 6 And 7 (Configuration Registers)

Bit C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0

Default 11111111

Bit C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0

Default 11111111

1 2

SCL 3 4 5 6 7 8

SDA A A A

Data 0

Data to Register

R/W

00 0 0 0 0 1 1 MSB LSB Data 1MSB LSB A

Data to Register

S 0 1 0 0 A2 A1 A0 0

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5

Acknowledge

From Slave

Acknowledge

From Slave

Start Condition

Command ByteSlave Address

Acknowledge

From Slave

1 2

SCL 3 4 5 6 7 8

SDA A A A

Data 0

R/W

tpv

00 0 0 0 0 0 1 0.7 0.0 Data 1

1.7 1.0 A

S 0 1 0 0 A2 A1 A0 0

tpv

Slave Address Command Byte Data to Port 0 Data to Port 1

Start Condition Acknowledge

From Slave

Write to Port

Data Out from Port 1

Data Out from Port 0

Data Valid

Acknowledge

From Slave

Acknowledge

From Slave

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8.5.2.4 Bus Transactions

Data is exchanged between the master and the PCA9555 through write and read commands.

8.5.2.4.1 Writes

Data is transmitted to the PCA9555 by sending the device address and setting the least-significant bit to a logic 0

(see Figure 21 for device address). The command byte is sent after the address and determines which register

receives the data that follows the command byte.

The eight registers within the PCA9555 are configured to operate as four register pairs. The four pairs are input

ports, output ports, polarity inversion ports, and configuration ports. After sending data to one register, the next

data byte is sent to the other register in the pair (see Figure 23 and Figure 24). For example, if the first byte is

sent to output port (register 3), the next byte is stored in Output Port 0 (register 2).

There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register

may be updated independently of the other registers.

Figure 23. Write To Output Port Registers

Figure 24. Write To Configuration Registers

8.5.2.4.2 Reads

The bus master first must send the PCA9555 address with the least-significant bit set to a logic 0 (see Figure 21

for device address). The command byte is sent after the address and determines which register is accessed.

After a restart, the device address is sent again, but this time, the least-significant bit is set to a logic 1. Data

from the register defined by the command byte then is sent by the PCA9555 (see Figure 25 through Figure 27).

After a restart, the value of the register defined by the command byte matches the register being accessed when

the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart

occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original

command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the

the data now reflect the information in the other register in the pair. For example, if Input Port 1 is read, the next

byte read is Input Port 0.

Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number

of data bytes received in one read transmission, but when the final byte is received, the bus master must not

acknowledge the data.

1 2 3 4 5 6 7 8 9

S 0 1 0 0 A2 A1 A0 1 A 7 6 5 4 3 2 1 0 A

I0.x

7 6 5 4 3 2 1 0 A

I1.x

7 6 5 4 3 2 1 0 A

I0.x

7 6 5 4 3 2 1 0 1

I1.x

R/W

SCL

SDA

INT

Read From Port 0

Data Into Port 0

Read From Port 1

Data Into Port 1

Acknowledge

From Master

Acknowledge

From Slave Acknowledge

From Master

Acknowledge

From Master

No Acknowledge

From Master

tiv tir

0 0 A2 A1 A00 10 0 A2 A1 A00 1S 0 A A A

R/W

PNA

R/W

1MSB LSB

MSB LSB

Slave Address

Acknowledge

From Slave

Command Byte

Data From Upper

or Lower Byte

of Register

Last Byte

Data

Acknowledge

From Slave

Acknowledge

From Slave

Slave Address

Data From Lower

or Upper Byte

of Register

First Byte

Data

No Acknowledge

From Master

Acknowledge

From Master

At this moment, master transmitter

becomes master receiver , and

slave-receiver becomes

slave-transmitter.

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Figure 25. Read From Register

A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest

acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read

Input Port register).

B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address

call and actual data transfer from the P port (see Figure 25 for these details).

Figure 26. Read Input Port Register, Scenario 1

1 2 3 4 5 6 7 8 9

S 0 1 0 0 A2 A1 A0 1 A A

I0.x

I1.x

I0.x

I1.x

R/W

SCL

SDA

INT

tph

00 10 03 12

tps

tph tps

11 12

Read From Port 0

Data Into Port 0

Read From Port 1

Data Into Port 1

Data 02Data 01Data 00 Data 03

DataDataData 10

Acknowledge

From Slave

Acknowledge

From Master

Acknowledge

From Master

Acknowledge

From Master

No Acknowledge

From Master

tiv tir

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A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest

acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read

Input Port register).

B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address

call and actual data transfer from the P port (see Figure 25 for these details).

Figure 27. Read Input Port Register, Scenario 2

P00

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

P15

P16

P17

VCC

(5 V)

Controlled Switch

(e.g., CBT Device)

GND

INT

SDA

SCL

10 k 10 k 10 k 10 k 2 k

INT

Subsystem 1

(e.g., Temperature

Sensor)

Subsystem 2

(e.g., Counter)

PCA9555

SDA

SCL

INT

GND

Keypad

ALARM

RESET

ENABLE

Subsystem 3

(e.g., Alarm)

Master

Controller

VCC

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.2 Typical Application

Figure 28 shows an application in which the PCA9555 can be used.

A. Device address is configured as 0100100 for this example.

B. P00, P02, and P03 are configured as outputs.

C. P01, P04–P07, and P10–P17 are configured as inputs.

D. Pin numbers shown are for DB, DBQ, DGV, DW, and PW packages.

Figure 28. Typical Application

VCC

3.3 V 5 V

LED

VCC

100 k

LED

VCC

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Typical Application (continued)

9.2.1 Design Requirements

For this design example, use the parameters shown in Table 8.

Table 8. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE

I2C and Subsystem Voltage (VCC) 5 V

Output current rating, P-port sinking (IOL) 25 mA

I2C bus clock (SCL) speed 400 kHz

9.2.2 Design Requirements

9.2.2.1 Minimizing ICC When I/O Is Used To Control Led

When an I/O is used to control an LED, normally it is connected to VCC through a resistor as shown in Figure 28.

Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ΔICC

parameter in Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC. For battery-

powered applications, it is essential that the voltage of I/O pins is greater than or equal to VCC when the LED is

off to minimize current consumption.

Figure 29 shows a high-value resistor in parallel with the LED. Figure 30 shows VCC less than the LED supply

voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevent additional

supply current consumption when the LED is off.

Figure 29. High-Value Resistor In Parallel With Led

Figure 30. Device Supplied By Lower Voltage

Bus Capacitance (pF)

Maximum Pull-Up Resistance (k:)

0 50 100 150 200 250 300 350 400 450

D008

Standard-Mode

Fast-Mode

Pull-Up Reference Voltage (V)

Minimum Pull-Up Resistance (k:)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

D009

VDPUX > 2 V

VDUPX </= 2

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9.2.3 Application Curves

Standard-mode: fSCL = 100 kHz, tr= 1 µs

Fast-mode: fSCL = 400 kHz, tr= 300 ns

Figure 31. Maximum Pull-Up Resistance (Rp(max)) vs Bus

Capacitance (Cb)

VOL = 0.2 × VCC, IOL = 2 mA when VCC ≤2 V

VOL = 0.4 V, IOL = 3 mA when VCC > 2 V

Figure 32. Minimum Pull-Up Resistance (Rp(min)) vs Pull-up

Reference Voltage (VCC)

10 Power Supply Recommendations

10.1 Power-On Reset Errata

A power-on reset condition can be missed if the VCC ramps are outside specification listed below.

10.1.1 System Impact

If ramp conditions are outside timing allowances above, POR condition can be missed, causing the device to lock

up.

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11 Layout

11.1 Layout Guidelines

For printed circuit board (PCB) layout of the PCA9555, common PCB layout practices must be followed, but

additional concerns related to high-speed data transfer such as matched impedances and differential pairs

are not a concern for I2C signal speeds.

In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away

from each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry

higher amounts of current that commonly pass through power and ground traces. By-pass and de-coupling

capacitors are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide

additional power in the event of a short power supply glitch and a smaller capacitor to filter out high-

frequency ripple. These capacitors must be placed as close to the PCA9555 as possible. These best

practices are shown in the Layout Example.

For the layout example provided in the Layout Example, it is possible to fabricate a PCB with only 2 layers by

using the top layer for signal routing and the bottom layer as a split plane for power (VCC) and ground (GND).

However, a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is

common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and

dedicate the other internal layer to a power plane. In a board layout using planes or split planes for power

and ground, vias are placed directly next to the surface mount component pad which needs to attach to VCC,

or GND and the via is connected electrically to the internal layer or the other side of the board. Vias are also

used when a signal trace needs to be routed to the opposite side of the board, but this technique is not

demonstrated in the Layout Example.

11.2 Layout Example

Figure 33. PCA9555 Example Layout

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12 Device and Documentation Support

12.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.2 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.4 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

PCA9555DB ACTIVE SSOP DB 24 60 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD9555

PCA9555DBQR ACTIVE SSOP DBQ 24 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PCA9555

PCA9555DBR ACTIVE SSOP DB 24 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD9555

PCA9555DGVR ACTIVE TVSOP DGV 24 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD9555

PCA9555DW ACTIVE SOIC DW 24 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9555

PCA9555DWR ACTIVE SOIC DW 24 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9555

PCA9555DWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9555

PCA9555DWT NRND SOIC DW 24 TBD Call TI Call TI -40 to 85

PCA9555N NRND PDIP N 24 TBD Call TI Call TI -40 to 85

PCA9555PW ACTIVE TSSOP PW 24 60 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD9555

PCA9555PWE4 ACTIVE TSSOP PW 24 60 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD9555

PCA9555PWR NRND TSSOP PW 24 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD9555

PCA9555PWRG4 NRND TSSOP PW 24 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD9555

PCA9555PWT NRND TSSOP PW 24 TBD Call TI Call TI -40 to 85

PCA9555RGER ACTIVE VQFN RGE 24 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PD9555

PCA9555RGERG4 ACTIVE VQFN RGE 24 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PD9555

PCA9555RHLR NRND VQFN RHL 24 TBD Call TI Call TI -40 to 85

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

Addendum-Page 2

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

PCA9555DBQR SSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

PCA9555DBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1

PCA9555DGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PCA9555DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1

PCA9555PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1

PCA9555RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 27-Feb-2018

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

PCA9555DBQR SSOP DBQ 24 2500 367.0 367.0 38.0

PCA9555DBR SSOP DB 24 2000 367.0 367.0 38.0

PCA9555DGVR TVSOP DGV 24 2000 367.0 367.0 35.0

PCA9555DWR SOIC DW 24 2000 367.0 367.0 45.0

PCA9555PWR TSSOP PW 24 2000 367.0 367.0 38.0

PCA9555RGER VQFN RGE 24 3000 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 27-Feb-2018

Pack Materials-Page 2

GENERIC PACKAGE VIEW

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

RGE 24 VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4204104/H

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

PACKAGE OUTLINE

www.ti.com

4224376 / A 07/2018

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK- NO LEAD

RGE0024C

0.08 C

0.1 C A B

0.05 C

SYMM

4.1

3.9

4.1

3.9

PIN 1 INDEX AREA

1 MAX

0.05

0.00

SEATING PLANE

2X 2.5

2.1±0.1

2.5

20X 0.5

712

24X 0.30

0.18

24X 0.50

0.30

(0.2) TYP

PIN 1 ID

(OPTIONAL)

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments

literature number SLUA271 (www.ti.com/lit/slua271).

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

EXAMPLE BOARD LAYOUT

4224376 / A 07/2018

www.ti.com

VQFN - 1 mm max height

RGE0024C

PLASTIC QUAD FLATPACK- NO LEAD

SYMM

LAND PATTERN EXAMPLE

SCALE: 20X

(0.8)

2X(0.8)

(3.8)

( 2.1)

712

24X (0.6)

24X (0.24)

20X (0.5)

(R0.05)

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

(Ø0.2) VIA

TYP

(3.8)

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations..

EXAMPLE STENCIL DESIGN

4224376 / A 07/2018

www.ti.com

VQFN - 1 mm max height

RGE0024C

PLASTIC QUAD FLATPACK- NO LEAD

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

80% PRINTED COVERAGE BY AREA

SCALE: 20X

(3.8)

(0.57)

TYP

(0.57)

TYP

4X ( 0.94)

712

24X (0.24)

24X (0.58)

20X (0.5)

(R0.05) TYP

METAL

TYP

(0.19)

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

4040065 /E 12/01

28 PINS SHOWN

Gage Plane

8,20

7,40

0,55

0,95

0,25

12,90

12,30

10,50

8,50

Seating Plane

9,907,90

10,50

9,90

0,38

5,60

5,00

0,22

2016

6,50

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65 M

0,15

0°–ā8°

0,10

0,09

0,25

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

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Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Texas Instruments:

PCA9555DB PCA9555DBQR PCA9555DBR PCA9555DGVR PCA9555DW PCA9555DWR PCA9555PW

PCA9555PWE4 PCA9555PWR PCA9555PWRE4 PCA9555RGER PCA9555DBQRG4 PCA9555DWG4

PCA9555DWRG4 PCA9555PWG4 PCA9555PWRG4 PCA9555RGERG4