SAMSUNG ELECTRONICS INC bE D MM 7564142 00168286 871 MESNGK KM93C56/KM93C66 CMOS EEPROM 2K/4K Bit Serial Electrically Erasable PROM FEATURES GENERAL DESCRIPTION * Single 5 volt supply The KM93C56/66 is a 5V only 2K/4K bits serial VO + Low power consumption EEPROM and |s fabricated with the well defined float- Active: 3 mA (TTL) ing gate CMOS technology using Flower Nordheim tun- Standby: 250 yA (TTL) nating for erasing and programming. Memory organization: 128 x 16 bits for KM93C56 The KM93C56/66 can be organized as 128/256 256 = 16 bits for KM93C66 registers of 16 bits each, which can be read/written System Clock Frequency: 1 MHz (max.) serially by a microprocessor. Self timed write cycle Automatic erase before write The KM93C56/66 is designed for applications up to RIB statue signal during programming 100,000 erase/write cycles per word and over 10 years * Reliable CMOS floating-gate technology of data retention. Endurance : 100,000 cycle Data retention: 10 years FUNCTIONAL BLOCK DIAGRAM [sx /}______] Clock/Vpp J GENERATOR csT]o FB] Vee ncto TT N.C. Vee iT] GND sk [2] P7}NC CONTROL || x aY GORE es Ho 90 [os + toaie []pec |] 388%18 0 [3 INC gk oy 1 bi KM83C56G/66G oo[| }s].aN0 (SC56/66) KMOSCESIEG DATA OUTPUT cso HO Vee tT REGISTER CONTROL sk NC | Dl INSTRUCTION om TO NC. T 00 | Doma [7] @ND INSTRUCTION KM83C56GD/66GD DECODER (C56D/66D) Pin Name Pin Function cs Chip Select SK Serial Data Clock DI Serial Data Input DO Serial Data Output GND Ground N.C. No Connection Veco Power Supply <> ELECTRONICSSAMSUNG ELECTRONICS INC B7E D MM 7964342 0016429 708 MSMGK KM93C56/KM93C66 CMOS EEPROM ABSOLUTE MAXIMUM RATINGS* Item Symbol Rating Unit Voltage on any pin relative to Vss - Vin 0.3 to +7.0 Vv Temperature Under Bias Tras 10 to +125 C Storage Temperature Tstg -65 to +150 C * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to ab- solute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to Vss, Ta=OC to 70C) Item Symbol Min Typ Max Unit Supply Voltage Voc 45 5.0 55 Vv Supply Voltage Vss 0 0 0 Vv DC OPERATING CHARACTERISTICS (Vcc = 4.5V to 5.5V unless otherwise specified) Parameter Symbol Test Condition Min Max Unit Operating Voltage Voc 45 5.5 Vv DC Iee1 CS=Vin, SK= Vin - 1 mA Operating Current AC loca CS =Vin, SK = 1.0MHz _ 3 mA TTL Ise1 Veco = 5.5V, CS = Vit _ 250 uA Standby Current CMOS Ise2 Voc = 5.5V, cs = Ves _ 100 pA Input Low Voltage Levels Vin -0.3 0.8 v Input High Voltage Levels Vin 2.0 Vec+0.3 v Vor lol = 2.1MA _ 0.4 Vv Output Voltage Levels Vou low = 400nA 2.4 _ Vv Input Leakage Current Iie Vin = 5.5V -2.5 2.5 pA Output Leakage Current lot Vour = 5.5V, CS =0V -2.5 2.5 BA INSTRUCTION SET FOR MODE SELECTION Instruction | SB | OP Code Address Data Comment READ 1 10 ATABASA4A3A2A1 AO Dout Read register at specified address WRITE 1 01 A7AGASA4A3A2A1 AO Dis5-Do | Write the data at specified address ERASE 1 11 ATABASA4A3A2A1A0 _ Erase the data at specified address EWEN 1 00 1 1XXXXXX > Erase/Write enable Ewods 1 00 OOXXXXXX - Erase/Write disable WRAL 1 00 O1XXXXXX Dis-Do | Write all registers ERAL 1 00 1OXXXXXX - Erase ail registers Note: 1. A? is a dont care address for KM93C56. <= ELECTRONICSSAMSUNG ELECTRONICS INC BPE D MM 7964142 0016830 42T MESMNGK KM93C56/KM93C66 CMOS EEPROM A.C. TEST CONDITIONS PARAMETER VALUE Input Pulse Level 0.45V to 2.4V Input Rise and Fail Time 20ns Output Load 1 TTL Gate and CL=100pF AC OPERATING CHARACTERISTICS (Vcc=4.5V to 5.5V unless otherwise specified} Limits Parameter Symbol Test Conditions Unit Min. Max. Maximum clock frequency foik _ - 1.0 MHz SK High Time tsKH (Note 1) 500 - ns SK Low Time _ tsKL (Note 1) 250 - ns Minimum CS Low Time tes (Note 2) 250 - ns [L CS Setup Time tess Relative to SK 50 ns DI Setup Time tois Relative to SK 50 _ ns CS Hold Time : tesH Relative to SK 0 _ ns DI Hold Time toi Relative to SK 100 _- ns Output delay to data 1 tpp1 > - 500 ns Output Delay to Data 'O tpoo - > 500 ns CS to Status Valid tsv _ _ 500 ns CS to DO in High-Z tor _ - 100 ns Write Cycle Time teyw _ _ 10 ms Falling Edge of CS to Dout High-Z tou, tin _ _- 100 ns Note 1: The SK spec. specifies a minimum SK clock period of 1 us, therefore in a SK clock cycle tsk. +tskH must be equal or greater than to 1 ys. e.g., if tsxL=250 ns then the minimum tskH=750 ns in order to meet the SK frequency specification. Note 2. The CS must be brought low for a minimum 250 ns (tcs) between consecutive instruction cycles. TIMING DIAGRAMS SYNCHRONOUS DATA TIMING Vin cs Vi Vin SK Va Vin DI Vit Vi DO OH Vor ein : ELECTRONICSSAMSUNG ELECTRONICS INC B7E D MM 7964342 0016831 3bb MBSNGK KM93C56/KM93C66 CMOS EEPROM TIMING DIAGRAMS continued INSTRUCTION TIMING {f READ cst ot et \_ 2 LE XR KEKE KE po Hiah2 * Note: A; Is a don't care address for KM93C56 0 = nyo 4 f) P=tcs pa \ CHECK NSTANOBY WRITE os STATUS oS \ 2 EXEXEXG KEEN TS HIGH-Z tw tH DO off BUSY READY * Note: Ap is a don't care address for KM93C56 tew HIGH.Z FULL LL LLL Le 8 EWEN ~<j EWDS S og / ~\ STANDBY ENABLE = 11 DISABLE = 00 sk FU Uy UU erase< cg / r tos Saeon STANDBY STATUS lo he 55 HIGH-Z tay {tH HIGH.Z po ff BUSY READY * Note A; Is a dont care address for KM93C56 be tem x LULL LL, ALLL LL ERAL jS ts \'cs CHECK STANDBY ce STATUS bl 1\o of 1\o0 se ap HIGH:2 tay | Busy fot HIGHZ St jaf READY me LE STANDBY CHECK WRAL STATUS tin READY <> ELECTRONICSSAMSUNG ELECTRONICS INC KM93C56/KM93C66 b7E D MM 7964142 0016832 2Te MSMGK CMOS EEPROM INTRODUCTION The KM93C56/66 is a 2K/4K bit CMOS serial I/O EEPROM used with microcontrollers for non-volatile memory applications The on chip programming voltage generator allows user to use a single 5.0V power supply. The write cycle of the KM93C56/66 is self tim- ed with the ready/busy status of chip indicated at the DO pin. All the operations of the chip are preceded by two OP code bits, facilitating inherent protection against false writes. The DO pin is a high-Z except for the read period and the ready/busy indication period to eliminate bus contention. It is possible to connect the DI and DO pins together as a common WO to futher simplify the interface. However, with this configuration it is possible for a bus conflict to occur during the dummy zero that precedes the read operation, if AO is a logic high level. Under such a condition the voltage level seen at DO is undefined and will depend upon the relative impedances of DO and the signal source driving AO. The higher the current sourcing capability of AO, the higher the voltage at the DO pin. DEVICE OPERATION READ After a read instruction and address set is received, low to high transition of the SK clock produces output data at DO pin. A dummy bit (logical 0) proceeds the 16 bit data output string. EWEN/EWDS The KM93C66/56 is at the write disable (EWDS) state during the power-up period to protect against acciden- tal disturbance. After the power-up period, the write operation must be preceded by an write enable (EWEN) operation. The write enable (EWEN) mode is maintained until a EWDS operation is executed or Vcc is removed from the part. Execution of the read operation is indepen- dent of both EWEN and EWDS instructions. WRITE The write operation is started by sequentially loading its instruction, address and data set. After the last bit of data is input on the DI pin, CS must be brought low before the rising edge of the SK clock. This falling edge of CS initiates the self-timed write cycle with auto erase. The chip's ready/busy status is indicated at the DO pin by bringing CS high during write cycle. ERASE The erase operation is started by sequentially loading its instruction, address. After the last bit of data is input on the DI pin, CS must be brought low before the rising edge of the SK clock. This falling edge of CS initiates the self- timed erase cycle. The chips ready/busy status is in- dicated at the DO pin by bringing CS high during erase cycle. WRAL The WRAL instruction is started by sequentially loading its instruction and data set. After the last bit of data is input on the DO pin, CS must be brought low before the rising edge of the SK clock. This falling edge of CS in- itiates the self-timed write cycle with auto chip erase. All ceils are written simultaneously with given data. ERAL The ERAL instruction is started by sequentially loading its instruction. After the last bit of data is input on the DO pin, CS must be brought low before the rising edge of the SK clock. This falling edge of CS initiates the seif- timed write cycle. All cells are erased simultaneously. a ELECTRONICS 93SAMSUNG ELECTRONICS INC B7E D MM 7964442 0616833 139 MESMGK KM93C56/KM93C66 CMOS EEPROM PACKAGE DIMENSIONS 8 PIN PLASTIC DUAL IN LINE PACKAGE unit; inches (millimeters) 0.352(8.92) 0.372(9.45) JL O~10 CL Ty) ma 0 240(6 09) 0 290(7 37) 0 260(6 60) 0 310(7 87} Oo LJ LILI U L _| = 0 040(1 02) /~ 0 060(1 52) 0 008(0.20) 0 012{0 30) LO 0 159(4 05) 0 179(4 65) 0 115(2 92) 0 138(3.42) 0 100(2 54) TYP /- 0 020(0 51) 0 040(1.02) 0.014(0 36) 0 022(0.56) 8 PIN PLASTIC SMALL OUT LINE PACKAGE 0.012 (0.30) ROBE 7] 0.148 (3.73) 0.224 (6.70) 0.163 (4.15) 0.002 (0.05) 0.248 (6.30) 0.006 (0.20) 0.012 (0.31) 0,006 (0.153) 0.020 (0.51) 0.012 (0.303) 0.194 (4.92) 0.202 (5.12) 0.055 (1.40) 0.077 (1.95) ELECTRONICSSAMSUNG ELECTRONICS INC b?7E D MM 7964142 0016834 O75 MESNGK PRELIMINARY KM93C56V/KM93C66V CMOS EEPROM 2K/4K Bit Serial Electrically Erasable PROM FEATURES GENERAL DESCRIPTION * Enhanced extended operating voltage: 3.0V~5.5V The KM93C56V/66V is a extended voltage 2K/4K bits * Low power consumption serial /O EEPROM and is fabricated with the well de- Active: 3 mA (TTL) fined floating gate CMOS technology using Flower Standby: 250A (TTL) Nordheim tunneling for erasing and programming. e Memory organization: 128 16 bits for kM@acs6V registers of 16 bits each, which can be readhtten ser: 256 x 16 bits for KM93C66 V I by a mi , System Clock Frequency: 1 MHz (max.) ally by Croprocessor. * Self timed write cycle The KM93C56V/66V is designed for applications up to Automatic erase before write 100,000 erase/write cycles per word and over 10 years RIB status signal during programming of data retention. * Reliable CMOS floating-gate technology Endurance: 100,000 cycle Data retention: 10 years FUNCTIONAL BLOCK DIAGRAM SK Clock/Vpp W/ [si | GENERATOR cs[T]o 3] Vee nc(Wo TO NC Voce C4 fl GND sk [2] [7]NC CORE cs] iT] DO CONTROL |_| x & CSF Logic ]oec fo) 3BBxI8 oi [3] OLess DI oo [4] Biles KM93C56VG/66VG , (C56 V/66V) KMS93C56V/66V DATA OUTPUT cso Ho Vee [ REGISTER CONTROL sK cy LONG DI INSTRUCTION oc TIN C REGISTER T Do | pol] TT] GND INSTRUCTION KM93C56VGD/E6VGD DECODER ( 56VD/66VD) Pin Name Pin Function cs Chip Select SK | Sernal Data Clock DI Senal Data Input DO Serial Data Qutput GND Ground N.C. No Connection _ | Voc | Power Supply <I ELECTRONICSSAMSUNG ELECTRONICS INC b7E D MM 796434e 0016635 TOL MESNGK PRELIMINARY KM93C56V/KM93CE6V CMOS EEPROM ABSOLUTE MAXIMUM RATINGS* Item Symbol Rating Unit Voitage-on any pin relative to Vss Vin -0.3 to +7.0 Vv Temperature Under Bias Toias 10 to +125 C Storage Temperature Tstg 65 to +150 C * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to ab- solute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voitage reference to Vss, Ta=O0C to 70C) Item Symbol Min Typ Max Unit Supply Voltage Voc 3.0 _- 5.5 Vv Supply Valtage Vss 0 0 0 Vv DC OPERATING CHARACTERISTICS (Vcc =3.0V to 5.5V unless otherwise specified) Parameter Symbol Test Condition Vi Voc Operating Current Standby Current Voltage Levels 5<Voo< <Vec<4 INSTRUCTION SET FOR MODE SELECTION instruction | SB | OP Code Address Data Comment READ 1 10 A7ABAS5SA4A3A2A1 AO Dout Read register at specified address WRITE 1 01 A7AGASA4A3A2A1A0 | Dis-Do | Write the data at specified address ERASE 1 11 A7ABA5SA4A3A2A1 AO _ Erase the data at specified address EWEN 1 00 11 XXXXXX _ Erase/Write enable EWDS 1 00 OOXXXXXX - Erase/Write disable WRAL 1 00 O1XXXXXX Di5-Do | Write all registers ERAL 1 00 1 OXXXXXX - Erase all registers Note: 1. A7 is a don't care address for KM93C56V, <> ELECTRONICSSAMSUNG ELECTRONICS INC B7E D MM 7564142 0016836 948 MSMGK PRELIMINARY KM93C56V/KM93CE6V CMOS EEPROM AC TEST CONDITIONS Parameter Value Input Pulse Levels 0.2V to 2.6V Input Rise and Fall Times 20ns Timing Measurement Reference Level 0.8V and 2.0V Output Load 1 TTL GATE and CL = 100pF AC OPERATING CHARACTERISTICS (vc:=30v to 5.5V unless otherwise specified) Limits Parameter Symbol Test Conditions Unit Min. Max. Maximum clock frequency fork _ - 1.0 MHz SK High Time tskH (Note 1) 500 - ns SK Low Time tsk (Note 1) 250 - ns - Minimum CS Low Time tes (Note 2) 250 ~ ns CS Setup Time tess Relative to SK 50 _ ns DI Setup Time tois Relative to SK 50 - ns CS Hold Time tosH Relative to SK 0 - ns Dt Hold Time toln Relative to SK 100 - ns Output delay to data 1 tpp1 - - 500 ns Output Delay to Data 0 tepo - - 500 ns CS to Status Valid tsv - _ 500 ns CS to DO in High-Z tor _ - 100 ns Write Cycle Time tesw - - 10 ms Falling Edge of CS to Dout High-Z tou, tix - _ 100 ns Note 1: The SK spec. specifies a minimum SK clock period of 1 us, therefore in a SK clock cycle tsk. +tskH must be equal or greater than to 1 us. e.g., if tex,=250 ns then the minimum tsxH=750 ns in order to meet the SK frequency specification. Note 2: The CS must be brought low for a minimum 250 ns (ics) between consecutive instruction cycles. TIMING DIAGRAMS SYNCHRONOUS DATA TIMING Vie cs Vi. Via SK Vu Vow Ol Vi bo Vou Vou <> ELECTRONICSSAMSUNG ELECTRONICS INC b7E D MM 7964142 0016837 884 MESNGK PRELIMINARY KM93CS56V/KM93C66V CMOS EEPROM TIMING DIAGRAMS 6 continue INSTRUCTION TIMING reared cs cs 1 STANOBY of + 1\ 2 LAK KAK IX Be 4 | HIGH-Z 4b oo ton. tH $$-\_0 ADI5XO14K EX 11K DOKKX) HIGH.2 Note A; 1s a dont care address for KM93C56V x LULL ULL LPL LL, st ii tes pth u \ STANDBY JS CHECK write SCS STATUS _ on S 1 \ 2/1 XEXEXEXG XEN XE HIGH-Z tsv ee tin DO j- +- BUSY READY * Note A; ts a don't care address for KM93C56V tew HIGH-Z cwen fox S LULL LLLP LLL {$ EWDS le S ~\, STANDBY , ENABLE = 11 DISABLE = 00 oe SLL LL, PL yo rr saad cs f csp Sra STANDBY STATUS ii HIGH- It . DO : y. svi Peusy READY a Fy * Note Az ts a dont care address for KM93C56V h~ ten J UU, FLL Lr Si + tes les ERAL< og / " NOS CHECK STANDBY STATUS ot 1 Q 0 1 0 $4. po tlch2 te Feusy tin HIGH.Z i) Le tew ox LOLLY, LPL Li 4d Sh if Sh Nts ip \ STANDBY wraL< co STATUS READYS=HIGH.2 4h tev Fausy tt id tew-4 <= ELECTRONICSSAMSUNG ELECTRONICS INC KM93C56V/KM93C66V b7E D MM 79641342 0016438 710 MESMNGK PRELIMINARY CMOS EEPROM INTRODUCTION The KM93C56V/66V is a 2K/4K bit CMOS serial I/O EEPROM used with microcontrollers for non-volatile memory applications. The on chip programming voltage generator allows user to use a3.0V to 5.5V single power supply. The write cycle of the KM93C56V/66V is self tim- ed with the ready/busy status of chip indicated at the DO pin. All the operations of the chip are preceded by two OP code bits, facilitating innerent protection against false writes. The DO pin is a high-Z except for the read period and the ready/busy indication period to eliminate bus contention. It is possible to connect the DI and DO pins together as a common I/O to futher simplify the interface. However, with this configuration it is possible for a bus conflict to occur during the dummy zero that precedes the read operation, if AO is a logic high level. Under such a condition the voltage level seen at DO is undefined and will depend upon the relative impedances of DO and the signa! source driving AO. The higher the current sourcing capability of AO, the higher the voltage at the DO pin. DEVICE OPERATION READ After a read instruction and address set is received, low to high transition of the SK clock produces output data at DO pin. A dummy bit (logical Q) proceeds the 16 bit data output string. EWEN/EWDS The KM93C56V/66V is at the write disable(EWDS) state during the power-up period to protect against acci- dental! distubance. After the power-up period, the write operation must be preceded by an write enable(EWEN) operation. The write enable (EWEN) mode is maintained until a EWDS operation is executed or Vcc is removed from the part. Execution of the read operation is indepen- dent of both EWEN and EWDS instructions. WRITE The write operation is started by sequentially loading its instruction, address and data set. After the last bit of data is input on the DI pin, CS must be brought low before the rising edge of the SK clock. This falling edge of CS initiates the self-timed write cycle with auto erase. The chips ready/busy status is indicated at the DO pin by bringing CS high during write cycle. ERASE The erase operation is started by sequentially loading its instruction, address. After the last bit of data is input on the DI pin, CS must be brought low before the rising edge of the SK clock. This falling edge of CS initiates the self- timed erase cycle. The chips ready/busy status is in- dicated at the DO pin by bringing CS high during erase cycle. WRAL The WRAL instruction is started by sequentially loading its instruction and data set. After the last bit of data is input on the DO pin, CS must be brought low before the rising edge of the SK clock. This falling edge of CS in- itiates the self-timed write cycle with auto chip erase. All cells are written simultaneously with given data. ERAL The ERAL instruction is started by sequentially loading tts instruction. After the last bit of data is input on the 00 pin, CS must be brought low before the rising edge of the SK clock. This falling edge of CS initiates the self- timed write cycle. All cells are erased simultaneously. ex ELECTRONICS 99SAMSUNG ELECTRONICS INC b7E D MB 7964442 0036839 657 MESNGK PRELIMINARY KM93C56V/KM93C66V CMOS EEPROM PACKAGE DIMENSIONS 8 PIN PLASTIC DUAL IN LINE PACKAGE unit; inches (millimeters) 0 352(8.92) 0.372(9 45) _\ 010 Or C1 Tv 0 240(6 09) 0 290(7 37) 0 260(6 60) 0 310(7 87) Oo LI te WI L _ = 0.040(1.02) 0 060(1 52) 0 008{0 20) 0012(0 30) 0.189(4 05) 0.179(4 55) 0 115(2.92) 0 135(3 42) 0 100(2 54) TYP /- 0 020(0 51) 0 040(1 02) 0.014{0 36) 0.022(0.56) 8 PIN PLASTIC SMALL OUT LINE PACKAGE 0.012 (0.30) ne: rT 0.148 (3.73) 0.224 (5.70) 0.163 (4.15) 0.002 (0.05) 0.248 (6.30) 0.008 (0.20) I 0.012 0.31) 0.006 (0.153) 0.020 (0.51) 0.012 (0.303) 0.194 (4.92) 0.202 (6.12) 0.055 (1.40) ir! 0.077 (1.95) 0.050 (1.27) TYP <= . ELECTRONICS