ANALOG DEVICES Low-Cost Sample-and-Hold Amplifier AD582 FEATURES Suitable for 12-Bit Applications High Sample/Hold Current Ratio: 10 Low Acquisition Time: Ens to 0.1% Low Charge Transfer: <2pC High Input impedance in Sample-and-Hold Modes Connect in Any Op Amp Configuration Differential Logic Inputs MIL-STD-883 Compilant Versions Available PRODUCT DESCRIPTION The ADS8Z is a low-cost integrated circuit sample-and-hold amplifier consisting of 3 high performance operational ampli- fier, 2 low leakage analog switch and a JFET integrating ampli- fier all fabricated on 2 single monolithic chip. An external holding capacitor, connected to the device, completes the sample-and-hold function. With the analog switch closed, the ADS82 functions like 2 stan- dard op amp; any feedback network may be connected around the device to control gain and frequency response. With the switch open, the capacitor holds the output at its last level, regardless of input voltage. Typical applications for the ADS82 include sampled data sys- tems, D/A degtitchers, analog de-multiplexers, auto null systems, strobed measurement systems and A/D speed enhancement. The device is available in two versions: the K specified for operation over the 0 to +70C commercial temperature range and the S specified over the extended temperature range, 55C wo +125C. All versions may be obtained in either the hermetic scaled, TO-100 can or the TO-116 DIP. PRODUCT HIGHLIGHTS 1. The specially designed input stage presents 2 high impedance to the signal source in both sample and hold modes (up to 12V). Even with signal levels up to tVg, no undesirable signal inversion, peaking or loss of hold voltage occurs. 2. The AD582 may be connected in any standard op amp con- figuration to control gain or frequency response and provide signal inversion, etc. . REV. A information furnished by Anslog Oevices is believed to be eccurete end reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third perties which may result from its use. No license is granted by implica- tion or otherwise under any patent or patent rights of Anslag Devices. PIN CONFIGURATIONS 10-Pin TO-100 TOP VIEW 14-Pin DIP TO-116 3. The ADS582 offers a high, sample-to-hold current ratio: 10. The ratio of the available charging current to the holding leakage current is often used as a figure of merit for a sam- ple and hold circuit. 4. The ADS82 has a typical charge transfer less than 2pC. A low charge transfer produces less offset error and permits the use of smaller hold capacitors for faster signal acquisition. 5. The AD582 provides separate analog and digital grounds, thus improving the device's immunity to ground and switch- ing transients. 6. The AD582 is available in versions compliant with MIL- STD-883. Refer to the Analog Devices Military Products Databook or current AD582/883B data sheet for detailed specifications. One Technology Wey, P.O. Sox $106, Norwoed, MA 02062-6166, U.S.A. Tel: 617/328-4700 Fax: 617/326-8703 Twx: 710/984-0677 Telex: 824481 Cable: ANALOG NORWOODMASS POAD582SPECIFICATIONS topics c +200, y= 157 and C,= Mot A= +1 wes steric saci ~~ MODEL ' ADS82K ADS828 - SAMPLE/MOLD CHARACTERISTICS Acquisition Time, 10V Step ro 0.1%, Cy + 100pF &s , Acquisition Time, 10V Step to 0.01%, . Cy 1000pF 2Sus . Aperture Deisy, 20V p-p input, Hold 0V 200ns e Aperture Jitter, 20V p-p Input, Hold OV 15ns . Settling Time, 20V p-p input, Hold OV, to 0.01% 0.5ys . Droop Current, Steady State, 10V out 100pA max . Droop Current, Tay 10 Trex inA 1S0nA max Charge Transfer SpC max (1.5pC typ) Sampte to Hold Offset O.5mV Feedthrough Capacitance 20V p-p, 10kHz Input O0SpF , TRANSPER CHARACTERISTICS Open Loop Gain Vout = 20V p-p, Ry = 2k 25% min (50k typ) . Common Mode Rejection Yeu * 20 $0dB min (7008 typ) . Smail Signal Gain Bandwideh Vour * 100mV p-p, Cy = 100pF 1.SMHz . Full Power Bandwidth Vout = 20V p-p, Cy = 100pP 70kHz . Slew Rate Vout = 20V p-p. Cu = 100pF 3Vips . Qutput Resistance Hold Mode, lout = 25mA a , Vout = 20V pp, Ry = 2k 10.01% * Output Short Circuit Current t25mA . ANALOG INPUT CHARACTERISTICS Offeet Voltage 6reV max (2mV typ) . Offeet Voltage, Tai 10 Tnax 4mnV SmV max (SmV typ) Bias Current SpA max (1.5MA typ) . Offect Current 300nA max {75nA typ) . Offset Current, Tai tO Tay 1000A 400nA max (100nA typ) Input Capacitance, f - IMHz ipF . input Resistance, Sample or Hold 20V pp Input, A +1 30M82 Absolute Max Diff Input Volrage 30V . Absolute Max Input Voltage, Either input aVs . DIGITAL INPUT CHARACTERISTICS +Logic Input Voltage Hold Mode, Tas 10 Trg, Logic @ OV +2 min , Sample Modes Pig (0 Tazy, Logic @ OV +0.8V man +Logie lnpur Current Hold Mode, +Logic @ +5V, -Logic @ OV 1.SpA . Semple Mode, sLogic @ OV, -Lagic @ OV inA . Logic [npuc Current Hold Mode, +Logic @ #SV, -Logic @ OV 24a . Mode, *Logic @ OV, -Logic @ OV 4uA * Absolute Max Diff Input Voltage, L to -L +15Vl-6V e Absoluee Max Input Voltage. Either Input 2V5 . POWER SUPPLY CHARACTERISTICS Operating Voltage Range t9V to 18V 29V wo 22V Supply Cerrent, Ry =~ 4.5mA max (3mA typ) . Power Sepply Rejection, . AVg = SV, Sample Mode (sec next page) 60dB min (75d8 typ) . TEMPERATURE RANGE Specified Performance 010 470C 258C to #1258C Opesating 28C co 485C * =$8C to 4128C Storage -6$C wo +150C . Lead Temperature (Soldering, 15 sec} +300C . PACKAGE OFTION"? TO-100 (H-10A) ADSB2KH ADS82SH TO-116 (D-14) ADS82KD ADS82SD NOTES Specifications same as ADSB2K. 1) Coramie DIP, H = Hermetic Metal Can. For outtine information see Package Information section. FPoe ADSE2/083R specifications, refer to Analog Devices Military Products Datebook. Specifications subject to change without notice. -2- REV. A PtApplying the AD582 APPLYING THE ADS82 In the hold mode, the output voltage will follow any change - Both the inverting and non-inverting inputs are brought out to _in the -Vg supply. Consequently, this supply should be well allow op amp type versatility in connecting and using the regulated and filtered. ADS82. Figure 1 shows the basic non-inverting unity gain con- nection requiring only an external hold capacitor and the usual Biasing the +Logic Input anywhere between -6V to +0.8V with tespect to the -Logic will set the sample mode. The hold mode power supply bypass capacitors. An offset null por can be added for ee Pitical applications. pe will result from any bias between +2.0V and (+V5 - 3V). The sample and hold modes will be controlled differentially with the absolute voltage at either logic input ranging from -Vg to within 3V of +Vgs (Vg - 3V). Figure 3 illustrates some examples of the flexibility of this feature. AIVSEY COSMOS on ww Tun + LOGIC _Vour *a10 rc y-- 7 A> A0582 LOGIC ca Figure 3A. Standard Logic Connection eater +3Vie1ZV COMOROS Figure 1. Sample and Hold with A = +1 Figure 2 shows 2 non-inverting configuration where voltage gain, Ay, is set by a pair of external resistors. Frequency shap- ing or non-linear networks can also be used for special applica- tions. Figure 38. Inverted Logic Sense Connection + LOGIC << | AD582 - Logic orev MTL vy s q $ s Figure 3C. High Threshold Logie Connection VOLYAOe ows DEFINITION OF TERMS Figure 4 illustrates various dynamic characteristics of the ADS82. Veo Pan | TF Aner Ww - Zz Figure 2. Sample and Hold with A= (1+ Rp/R)} The hold capacitor, Cy, should be a high quality polystyrenc (for temperatures below +85C) or Teflon type with low dielectric absorption. For high speed, limited accuracy applica- tions, capacitors as small as 100pF may be used. Larger values are required for accuracies of 12 bits and above in order to minimize feedthrough, sample to hold offset and droop errors (see Figure 6). Care should be taken in the circuit layout to minimize coupling between the hold capacitor and the digital or signal inputs. Figure 4, Pictorial Showing Various S/H Characteristics 4. REV. A -3- PtAD582 Aperture Delay is the time required after the hold command until the switch is fully open and produces a delsy in the effec- tive sample timing. Figure 5 is plot giving the maximum fre- quency at which the ADS82 can sample an input with a given accuracy (lower curve). Aperture Jitter is the uncertainty in Aperture Time. The Aperture Time can be eliminated by advancing the sample- to-hold command 200ns with respect to the input signa). The Aperture Jitter now determines the maximum sampling fre- quency (upper curve of Figure 5). Acquisition Time is the time required by the device to reach its final value within a given error band after the sample command has been given. This includes switch delay time, slewing time and settling time for a given output voltage change. Droop is the change in the output voltage from the held value a a result of device leakage. In the AD5S82, droop can be in either the positive or negative direction. Droop rate may be calculated from droop current using the following formula: AY Volte/sec) s pA) A) ar Cy (pF) (See also Figure 5.) ws ww a CONVERSION RESOLUTION ~ Sra id n m ig wx wa: wa SHOUBOIDAL HEPUT FREQUENCY Hz Figure 5. Maximum Frequency of Input Signa! for #LSB8 Sampling Accuracy 108900 ame 198 we 1 .20teF Oar OtsF ed Ca VALUE Figure 6. Sempie-end-Hold Performance as 8 Function of Hold Capacitance Feedthrough is chat component of the outpuc which follows the input signal after the switch is open. As a percentage of the input, feedthrough is determined as the ratio of the feed- through capacitance to the hold capacitance (Cp /Cyy). -4- a Sample-to-Hold Offset is an output shift or step caused by charge injection into the hold capscitor ss the device is switched from sample to hold. The charge transfer generates asample-to-hold offset where: Charge (pC) S/H Offset (V) = 7 (V) Cu (PF) This offset also has a dc component as shown in Figure 6. TEMPERATURE " Ne w rg to a DROOP CURRENT pA Figure 7. Droop Current vs. Tempereture OUTLINE DIMENSIONS Dimendous shown in inches snd (mm). TO-100 H TO-116 D" bw 0.490 moan peven pat 0.290 361 090 1742) 777 20.28) | luncown - 8.006 (2.49 0.700 20.000 - 7-78 20.28) 2898 36.090) ot a Rm [esas seg see tt | Ronse O70 We .a0t (900338) REV. A C638c-6~6/85 PRINTED IN U.S.A.