Synchronous Buck Controller with Constant
On-Time and Valley Current Mode
Data Sheet
ADP1874/ADP1875
Rev. A
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FEATURES
Power input voltage range: 2.95 V to 20 V
On-board bias regulator
Minimum output voltage: 0.6 V
0.6 V reference voltage with ±1.0% accuracy
Supports all N-channel MOSFET power stages
Available in 300 kHz, 600 kHz, and 1.0 MHz options
No current-sense resistor required
Power saving mode (PSM) for light loads (ADP1875 only)
Resistor programmable current limit
Power good with internal pull-up resistor
Externally programmable soft start
Thermal overload protection
Short-circuit protection
Standalone precision enable input
Integrated bootstrap diode for high-side drive
Starts into a precharged output
Available in a 16-lead QSOP package
APPLICATIONS
Telecom and networking systems
Mid- to high-end servers
Set-top boxes
DSP core power supplies
GENERAL DESCRIPTION
The ADP1874/ADP1875 are versatile current mode, synchronous
step-down controllers. They provide superior transient response,
optimal stability, and current-limit protection by using a constant
on-time, pseudo fixed frequency with a programmable current
limit, current control scheme. In addition, these devices offer
optimum performance at low duty cycles by using a valley, current
mode control architecture. This allows the ADP1874/ADP1875
to drive all N-channel power stages to regulate output voltages
to as low as 0.6 V.
The ADP1875 is the power saving mode (PSM) version of
the device and is capable of pulse skipping to maintain output
regulation while achieving improved system efficiency at light
loads (see the ADP1875 Power Saving Mode (PSM) section for
more information).
Available in three frequency options (300 kHz, 600 kHz, and
1.0 MHz, plus the PSM option), the ADP1874/ADP1875 are well
suited for a wide range of applications that require a single-input
power supply range from 2.95 V to 20 V. Low voltage biasing is
supplied via a 5 V internal low dropout regulator (LDO).
TYPICAL APPLICATIONS CIRCUIT
COMP BST
FB
DRVH
GND
SW
VREG
VREG_IN
RES
DRVL
SS CSS
PGND
VIN
CC
CVREG
CVREG2
CC2
RC
RBOT
RTOP
VOUT
EN
10kΩ
VREG Q1
Q2
L
COUT
VOUT
CBST
LOAD
CIN
VIN = 2.95V T O 20V
ADP1874/
ADP1875
RRES
RTRK1
PGOOD RPGD VEXT
TRACK RTRK2 VMASTER
09347-001
Figure 1. Typical Applications Circuit
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
2510 100 1k 10k 100k
EF FICIENCY ( %)
LOAD CURRENT ( mA)
T
A
= 25° C
V
OUT
= 1.8V
f
SW
= 300kHz
WÜRTH INDUCTOR:
744325120, L = 1.2µH, DCR = 1.8mΩ
INFINEON FETs:
BSC042N03MS G (UPP E R/LOWE R)
V
IN
= 5V (PSM)
V
IN
= 13V (PSM)
V
IN
= 16.5V (PSM)
VIN = 13V
VIN = 16.5V
09347-102
Figure 2. ADP1874/ADP1875 Efficiency vs. Load Current (VOUT = 1.8 V, 300 kHz)
In addition, soft start programmability is included to limit input
in-rush current from the input supply during startup and to
provide reverse current protection during precharged output
conditions. The low-side current sense, current gain scheme, and
integration of a boost diode, along with the PSM/forced pulse-
width modulation (PWM) option, reduce the external part count
and improve efficiency.
The ADP1874/ADP1875 operate over the −40°C to +125°C
junction temperature range and are available in a 16-lead QSOP
package.
ADP1874/ADP1875 Data Sheet
Rev. A | Page 2 of 44
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Typical Applications Circuit ............................................................ 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
Boundary Condition .................................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
ADP1874/ADP1875 Block Digram ............................................... 18
Theory of Operation ...................................................................... 19
Startup .......................................................................................... 19
Soft Start ...................................................................................... 19
Precision Enable Circuitry ........................................................ 19
Undervoltage Lockout ............................................................... 19
On-Board Low Dropout Regulator .......................................... 20
Thermal Shutdown ..................................................................... 20
Programming Resistor (RES) Detect Circuit .......................... 20
Valley Current-Limit Setting .................................................... 20
Hiccup Mode During Short Circuit ......................................... 22
Synchronous Rectifier ................................................................ 22
ADP1875 Power Saving Mode (PSM) ...................................... 22
Timer Operation ........................................................................ 23
Pseudo-Fixed Frequency ........................................................... 24
Power Good Monitoring ........................................................... 24
Voltage Tracking ......................................................................... 25
Applications Information .............................................................. 27
Feedback Resistor Divider ........................................................ 27
Inductor Selection ...................................................................... 27
Output Ripple Voltage (ΔVRR) .................................................. 27
Output Capacitor Selection....................................................... 27
Compensation Network ............................................................ 28
Efficiency Consideration ........................................................... 29
Input Capacitor Selection .......................................................... 30
Thermal Considerations ............................................................ 31
Design Example .......................................................................... 32
External Component Recommendations .................................... 34
Layout Considerations ................................................................... 36
IC Section (Left Side of Evaluation Board) ............................. 38
Power Section ............................................................................. 38
Differential Sensing .................................................................... 39
Typical Application Circuits ......................................................... 40
12 A, 300 kHz High Current Application Circuit .................. 40
5.5 V Input, 600 kHz Application Circuit ............................... 40
300 kHz High Current Application Circuit ............................ 41
Outline Dimensions ....................................................................... 42
Ordering Guide .......................................................................... 42
REVISION HISTORY
7/12—Rev. 0 to Rev. A
Changes to Table 7 .......................................................................... 21
3/11—Revision 0: Initial Version
Data Sheet ADP1874/ADP1875
Rev. A | Page 3 of 44
SPECIFICATIONS
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VREG = 5 V,
BST − SW = VREG − VRECT_DROP (see Figure 40 to Figure 42). VIN = 12 V. The specifications are valid for TJ = −40°C to +125°C,
unless otherwise specified.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY CHARACTERISTICS
High Input Voltage Range VIN C
VIN
= 22 µF(25 V rating) to PGND (at Pin 1)
ADP1874ARQZ-0.3/ADP1875ARQZ-0.3 (300 kHz) 2.95 12 20 V
ADP1874ARQZ-0.6/ADP1875ARQZ-0.6 (600 kHz) 2.95 12 20 V
ADP1874ARQZ-1.0/ADP1875ARQZ-1.0 (1.0 MHz) 3.25 12 20 V
Quiescent Current I
Q_REG
+ I
Q_BST
FB = 1.5 V, no switching 1.1 mA
Shutdown Current I
REG,SD
+ I
BST,SD
EN < 600 mV 140 225 µA
Undervoltage Lockout UVLO Rising V
IN
(see Figure 35 for temperature variation) 2.65 V
UVLO Hysteresis Falling V
IN
from operational state 190 mV
INTERNAL REGULATOR
CHARACTERISTICS
VREG and VREG_IN tied together and should not be
loaded externally because they are intended to only
bias internal circuitry
VREG Operational Output Voltage VREG C
VREG
= 4.7 µF to PGND, 0.22 µF to GND, V
IN
= 2.95 V to 20 V
ADP1874ARQZ-0.3/ADP1875ARQZ-0.3 (300 kHz) 2.75 5 5.5 V
ADP1874ARQZ-0.6/ADP1875ARQZ-0.6 (600 kHz) 2.75 5 5.5 V
ADP1874ARQZ-1.0/ADP1875ARQZ-1.0 (1.0 MHz) 3.05 5 5.5 V
VREG Output in Regulation V
IN
= 7 V, 100 mA 4.82 4.981 5.16 V
V
IN
= 12 V, 100 mA 4.83 4.982 5.16 V
Load Regulation 0 mA to 100 mA, V
IN
= 7 V 32 mV
0 mA to 100 mA, VIN = 20 V
34
mV
Line Regulation V
IN
= 7 V to 20 V, 20 mA 2.5 mV
V
IN
= 7 V to 20 V, 100 mA 2 mV
VIN to VREG Dropout Voltage 100 mA out of VREG, V
IN
≤ 5 V 300 415 mV
Short VREG to PGND V
IN
= 20 V 229 320 mA
SOFT START
Soft Start Period Calculation Connect external capacitor from SS pin to GND,
C
SS
= 10 nF/ms
10 nF/ms
ERROR AMPLIFER
FB Regulation Voltage V
FB
T
J
= 25°C 600 mV
T
J
= −40°C to +85°C 596 600 604 mV
T
J
= −40°C to +125°C 594.2 600 605.8 mV
Transconductance G
m
320 496 670 µS
FB Input Leakage Current I
FB, LEAK
FB = 0.6 V, EN = VREG 1 50 nA
CURRENT-SENSE AMPLIFIER GAIN
Programming Resistor (RES)
Value from RES to PGND
RES = 47 kΩ ± 1% 2.7 3 3.3 V/V
RES = 22 kΩ ± 1% 5.5 6 6.5 V/V
RES = none 11 12 13 V/V
RES = 100 kΩ ± 1%
22
24
26
V/V
SWITCHING FREQUENCY Typical values measured at 50% time points with
0 nF at DRVH and DRVL; maximum values are
guaranteed by bench evaluation1
ADP1874ARQZ-0.3/
ADP1875ARQZ-0.3 (300 kHz)
300 kHz
On-Time VIN = 5 V, V
OUT
= 2 V, T
J
= 25°C 1120 1200 1280 ns
Minimum On-Time VIN = 20 V 145 190 ns
Minimum Off-Time 84% duty cycle (maximum) 340 400 ns
ADP1874/ADP1875 Data Sheet
Rev. A | Page 4 of 44
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
ADP1874ARQZ-0.6/
ADP1875ARQZ-0.6 (600 kHz)
600 kHz
On-Time VIN = 5 V, V
OUT
= 2 V, T
J
= 25°C 500 540 580 ns
Minimum On-Time VIN = 20 V, V
OUT
= 0.8 V 82 110 ns
Minimum Off-Time 65% duty cycle (maximum) 340 400 ns
ADP1874ARQZ-1.0/
ADP1875ARQZ-1.0 (1.0 MHz)
1.0 MHz
On-Time VIN = 5 V, V
OUT
= 2 V, T
J
= 25°C 285 312 340 ns
Minimum On-Time VIN = 20 V 52 85 ns
Minimum Off-Time 45% duty cycle (maximum) 340 400 ns
OUTPUT DRIVER CHARACTERISTICS
High-Side Driver
Output Source Resistance2 I
SOURCE
= 1.5 A, 100 ns, positive pulse (0 V to 5 V) 2.25 3.5 Ω
Output Sink Resistance2 I
SINK
= 1.5 A, 100 ns, negative pulse (5 V to 0 V) 0.70 1 Ω
Rise Time3 t
r, DRVH
BST − SW = 4.4 V, C
IN
= 4.3 nF (see Figure 59) 25 ns
Fall Time3 t
f, DRVH
BST − SW = 4.4 V, C
IN
= 4.3 nF (see Figure 60) 11 ns
Low-Side Driver
Output Source Resistance
2
I
SOURCE
= 1.5 A, 100 ns, positive pulse (0 V to 5 V) 1.6 2.4 Ω
Output Sink Resistance
2
I
SINK
= 1.5 A, 100 ns, negative pulse (5 V to 0 V) 0.7 1 Ω
Rise Time3 t
r,DRVL
VREG = 5.0 V, C
IN
= 4.3 nF (see Figure 60) 18 ns
Fall Time3 t
f,DRVL
VREG = 5.0 V, C
IN
= 4.3 nF (see Figure 59) 16 ns
Propagation Delays
DRVL Fall to DRVH Rise
3
t
tpdhDRVH
BST − SW = 4.4 V (see Figure 59) 15.4 ns
DRVH Fall to DRVL Rise
3
t
tpdhDRVL
BST − SW = 4.4 V (see Figure 60) 18 ns
SW Leakage Current I
SWLEAK
BST = 25 V, SW = 20 V, VREG = 5 V 110 µA
Integrated Rectifier
Channel Impedance I
SINK
= 10 mA 22 Ω
PRECISION ENABLE THRESHOLD
Logic High Level VIN = 2.9 V to 20 V, VREG = 2.75 V to 5.5 V 570 630 680 mV
Enable Hysteresis VIN = 2.9 V to 20 V, VREG = 2.75 V to 5.5 V 31 mV
COMP VOLTAGE
COMP Clamp Low Voltage VCOMP(LOW) Tie EN pin to VREG to enable device
(2.75 V ≤ VREG ≤ 5.5 V)
0.47 V
COMP Clamp High Voltage V
COMP(HIGH)
(2.75 V ≤ VREG ≤ 5.5 V) 2.55 V
COMP Zero Current Threshold V
COMP_ZCT
(2.75 V ≤ VREG ≤ 5.5 V) 1.15 V
THERMAL SHUTDOWN T
TMSD
Thermal Shutdown Threshold Rising temperature 155 °C
Thermal Shutdown Hysteresis 15 °C
CURRENT LIMIT
Hiccup Current Limit Timing COMP = 2.4 V 6 ms
OVERVOLTAGE AND POWER GOOD
THRESHOLDS
PGOOD
FB Power Good Threshold FB
PGD
V
FB
rising during system power-up 542 568 mV
FB Power Good Hysteresis 30 mV
FB Overvoltage Threshold FB
OV
V
FB
rising during overvoltage event, I
PGOOD
= 1 mA 691 710 mV
FB Overvoltage Hysteresis 30 mV
PGOOD Low Voltage During Sink V
PGOOD
I
PGOOD
= 1 mA 143 200 mV
PGOOD Leakage Current PGOOD = 5 V 1 400 nA
Data Sheet ADP1874/ADP1875
Rev. A | Page 5 of 44
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
TRACKING
Track Input Voltage Range 0 5 V
FB-to-Tracking Offset Voltage 0.5 V < TRACK < 0.6 V, offset = V
FB
− V
TRACK
63 mV
Leakage Current V
TRACK
= 5 V 1 50 nA
1 The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 59 and Figure 60), CGATE = 4.3 nF, and the upper side and lower
side MOSFETs being Infineon BSC042N03MS G.
2 Guaranteed by design.
3 Not automatic test equipment (ATE) tested.
ADP1874/ADP1875 Data Sheet
Rev. A | Page 6 of 44
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VREG, VREG_IN, TRACK to PGND, GND −0.3 V to +6 V
VIN, EN, PGOOD to PGND
−0.3 V to +28 V
FB, COMP, RES, SS to GND −0.3 V to (VREG + 0.3 V)
DRVL to PGND −0.3 V to (VREG + 0.3 V)
SW to PGND −2.0 V to +28 V
BST to SW −0.6 V to (VREG + 0.3 V)
BST to PGND −0.3 V to +28 V
DRVH to SW −0.3 V to VREG
PGND to GND ±0.3 V
PGOOD Input Current 20 mA
θ
JA
(16-Lead QSOP)
4-Layer Board 104°C/W
Operating Junction Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Soldering Conditions JEDEC J-STD-020
Maximum Soldering Lead Temperature
(10 sec)
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages
are referenced to PGND.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θ
JA
Unit
θ
JA
(16-Lead QSOP)
4-Layer Board
104°
°C/W
BOUNDARY CONDITION
In determining the values given in Table 2 and Table 3, natural
convection is used to transfer heat to a 4-layer evaluation board.
ESD CAUTION
Data Sheet ADP1874/ADP1875
Rev. A | Page 7 of 44
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIN 1
COMP 2
EN 3
FB 4
BST
16
SW
15
DRVH
14
PGND
13
GND 5DRVL
12
RES 6PGOOD
11
VREG 7SS
10
VREG_IN 8TRACK
9
ADP1874/
ADP1875
TOP VIEW
(Not t o Scale)
09347-003
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin
No. Mnemonic Description
1 VIN High-Side Input Voltage. Connect VIN to the drain of the upper side MOSFET.
2 COMP Output of the Error Amplifier. Connect the compensation network between this pin and AGND to achieve stability (see the
Compensation Network section).
3 EN Connect to VREG to Enable IC. When pulled down to AGND externally, disables the IC.
4 FB Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected.
5 GND Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground plane
(see the Layout Considerations section).
6 RES Current Sense Gain Resistor (External). Connect a resistor between the RES pin and GND (Pin 5).
7 VREG Internal Regulator Supply Bias Voltage for the ADP1874/ADP1875 Controller (Includes the Output Gate Drivers). A
bypass capacitor of 1 µF directly from this pin to PGND and a 0.1 µF across VREG and GND are recommended.
8 VREG_IN Input to the Internal LDO. Tie this pin directly to Pin 7 (VREG).
9 TRACK Tracking Input. If the tracking function is not used, it is recommended to connect TRACK to VREG through a resistor
higher than 1 MΩ or simply connect TRACK between 0.7 V and 2 V to reduce the bias current going into the pin.
10 SS Soft Start Input. Connect an external capacitor to GND to program the soft start period. Capacitance value of 10 nF for
every 1 ms of soft start delay.
11
PGOOD
Open-Drain Power Good Output. Sinks current when FB is out of regulation or during thermal shutdown. Connect a
3 kΩ resistor between PGOOD and VREG. Leave unconnected if not used.
12 DRVL Drive Output for the External Lower Side, N-Channel MOSFET. This pin also serves as the current-sense gain setting pin (see
Figure 69).
13 PGND Power GND. Ground for the lower side gate driver and lower side, N-channel MOSFET.
14
DRVH
Drive Output for the External Upper Side, N-Channel MOSFET.
15 SW Switch Node Connection.
16 BST Bootstrap for the Upper Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected between VREG and
BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected between VREG and BST for
increased gate drive capability.
ADP1874/ADP1875 Data Sheet
Rev. A | Page 8 of 44
TYPICAL PERFORMANCE CHARACTERISTICS
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
010 100 1k 10k 100k
EF FICIENCY ( %)
LOAD CURRENT ( mA)
TA = 25° C
VOUT = 0.8V
fSW = 300kHz
WÜRTH INDUCTOR:
744325072, L = 0.72µH, DCR = 1.3mΩ
INFINEON FETs:
BSC042N03MS G (UPP E R/LOWE R)
VIN = 13V (PSM)
VIN = 16.5V (PSM)
VIN = 13V
VIN = 16.5V
09347-104
Figure 4. Efficiency—300 kHz, VOUT = 0.8 V
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
010 100 1k 10k 100k
EF FICIENCY ( %)
LOAD CURRENT ( mA)
TA = 25° C
VOUT = 1.8V
fSW = 300kHz
WÜRTH INDUCTOR:
744325120, L = 1.2µH, DCR = 1.8mΩ
INFINEON FETs:
BSC042N03MS G (UPP E R/LOWE R)
VIN = 5V (PSM)
VIN = 13V (PSM)
VIN = 16.5V (PSM)
VIN = 13V
VIN = 16.5V
09347-105
Figure 5. Efficiency—300 kHz, VOUT = 1.8 V
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
010 100 1k 10k 100k
EF FICIENCY ( %)
LOAD CURRENT ( mA)
TA = 25° C
VOUT = 7V
fSW = 300kHz
WÜRTH INDUCTOR:
7443551200, L = 2.0µH, DCR = 2.6mΩ
INFINEON FETs:
BSC042N03MS G (UPP E R/LOWE R)
VIN = 13V (PSM)
VIN = 16.5V (PSM)
VIN = 13V
VIN = 16.5V
09347-106
Figure 6. Efficiency—300 kHz, VOUT = 7 V
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
010 100 1k 10k 100k
EF FICIENCY ( %)
LOAD CURRENT ( mA)
TA = 25° C
VOUT = 0.8V
fSW = 600kHz
WÜRTH INDUCTOR:
744355147, L = 0.47µH, DCR = 0.67mΩ
INFINEON FETs:
BSC042N03MS G (UPP E R/LOWE R)
VIN = 13V (PSM)
VIN = 16.5V
(PSM)
VIN = 13V
VIN = 16.5V
09347-107
Figure 7. Efficiency—600 kHz, VOUT = 0.8 V
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
010 100 1k 10k 100k
EF FICIENCY ( %)
LOAD CURRENT ( mA)
TA = 25° C
VOUT = 1.8V
fSW = 600kHz
WÜRTH INDUCTOR:
744325072, L = 0.72µH, DCR = 1.3mΩ
INFINEON FETs:
BSC042N03MS G (UPP E R/LOWE R)
VIN = 13V (PSM)
VIN = 16.5V (PSM)
VIN = 13V
VIN = 16.5V
09347-108
Figure 8. Efficiency—600 kHz, VOUT = 1.8 V
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
010 100 1k 10k 100k
EF FICIENCY ( %)
LOAD CURRENT ( mA)
TA = 25° C
VOUT = 5V
fSW = 600kHz
WÜRTH INDUCTOR:
744318180, L = 1.4µH, DCR = 3.2mΩ
INFINEON FETs:
BSC042N03MS G (UPP E R/LOWE R)
VIN = 20V (PSM)
VIN = 13V (PSM)
VIN = 16.5V (PSM)
VIN = 20V
VIN = 16.5V
09347-109
Figure 9. Efficiency—600 kHz, VOUT = 5 V
Data Sheet ADP1874/ADP1875
Rev. A | Page 9 of 44
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
010 100 1k 10k 100k
EF FICIENCY ( %)
LOAD CURRENT ( mA)
TA = 25° C
VOUT = 0.8V
fSW = 1.0MHz
WÜRTH INDUCTOR:
744303012, L = 0.12µH, DCR = 0.33mΩ
INFINEON FETs:
BSC042N03MS G (UPP E R/LOWE R)
VIN = 13V (PSM)
VIN = 16.5V (PSM)
VIN = 13V
VIN = 16.5V
09347-110
Figure 10. Efficiency—1.0 MHz, VOUT = 0.8 V
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
010 100 1k 10k 100k
EF FICIENCY ( %)
LOAD CURRENT ( mA)
TA = 25° C
VOUT = 1.8V
fSW = 1.0MHz
WÜRTH INDUCTOR:
744303022, L = 0.22µH, DCR = 0.33mΩ
INFINEON FETs:
BSC042N03MS G (UPP E R/LOWE R)
VIN = 13V (PSM)
VIN = 16.5V (PSM)
VIN = 13V
VIN = 16.5V
09347-111
Figure 11. Efficiency—1.0 MHz, VOUT = 1.8 V
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
010 100 1k 10k 100k
EF FICIENCY ( %)
LOAD CURRENT ( mA)
TA = 25° C
VOUT = 5V
fSW = 1.0MHz
WÜRTH INDUCTOR:
744355090, L = 0.9µH, DCR = 1.6mΩ
INFINEON FETs:
BSC042N03MS G (UPP E R/LOWE R)
VIN = 13V (PSM)
VIN = 16.5V (PSM) VIN = 13V
VIN = 16.5V
09347-112
Figure 12. Efficiency—1.0 MHz, VOUT = 5 V
0.807
0.806
0.805
0.804
0.803
0.802
0.801
0.800
0.799
0.798
0.797
0.796
0.795
0.794
0.793
0.792 02000 4000 6000 8000 10,000
OUTPUT VOLTAGE (V)
LOAD CURRENT ( mA)
+125°C
+25°C
–40°C
V
IN
= 13V +125°C
+25°C
–40°C
V
IN
= 16.5V
09347-013
Figure 13. Output Voltage Accuracy—300 kHz, VOUT = 0.8 V
1.821
1.816
1.811
1.806
1.801
1.796
1.791
1.786 01500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000
OUTPUT VOLTAGE (V)
LOAD CURRENT ( mA)
+125°C
+25°C
–40°C
VIN = 5.5V +125°C
+25°C
–40°C
VIN = 13V +125°C
+25°C
–40°C
VIN = 16.5V
09347-014
Figure 14. Output Voltage Accuracy—300 kHz, VOUT = 1.8 V
7.100
7.095
7.090
7.085
7.080
7.075
7.070
7.065
7.060
7.055
7.050
7.045
7.040
7.035
7.030
7.025
7.020
7.015
7.010
7.005
7.000 01000 2000 3000 4000 5000 6000 7000 8000 9000
OUTPUT VOLTAGE (V)
LOAD CURRENT ( mA)
+125°C
+25°C
–40°C
VIN = 13V
VIN = 16.5V
09347-015
Figure 15. Output Voltage Accuracy—300 kHz, VOUT = 7 V
ADP1874/ADP1875 Data Sheet
Rev. A | Page 10 of 44
0.808
0.792
0.794
0.796
0.798
0.800
0.802
0.804
0.806
01000 2000 3000 4000 5000 6000 7000 8000 10,0009000
FRE QUENCY ( kHz )
LOAD CURRENT ( mA)
+125°C
+25°C
–40°C
V
IN
= 13V
V
IN
= 16.5V
09347-115
Figure 16. Output Voltage Accuracy—600 kHz, VOUT = 0.8 V
1.818
1.770
1.772
1.774
1.776
1.778
1.780
1.782
1.784
1.786
1.788
1.790
1.792
1.794
1.796
1.798
1.800
1.802
1.804
1.806
1.808
1.810
1.812
1.814
1.816
012,00010,500900075006000450030001500
OUTPUT VOLTAGE (V)
LOAD CURRENT ( mA)
+125°C
+25°C
–40°C
V
IN
= 13V +125°C
+25°C
–40°C
V
IN
= 16.5V
09347-016
Figure 17. Output Voltage Accuracy—600 kHz, VOUT = 1.8 V
5.030
5.025
5.005
5.010
5.015
5.020
5.000
4.995
4.990
4.985
4.980
4.975
4.970 01000 2000 3000 4000 5000 6000 7000 8000 9000 10,000
OUTPUT VOLTAGE (V)
LOAD CURRENT ( mA)
+125°C
+25°C
–40°C
VIN = 13V
VIN = 16.5V
VIN = 20V
09347-017
Figure 18. Output Voltage Accuracy—600 kHz, VOUT = 5 V
02000 4000 6000 8000 10,000
OUTPUT VOLTAGE (V)
LOAD CURRENT ( mA)
+125°C
+25°C
–40°C
V
IN
= 13V +125°C
+25°C
–40°C
V
IN
= 16.5V
0.787
0.789
0.791
0.793
0.795
0.797
0.799
0.801
0.803
0.805
0.807
09347-118
Figure 19. Output Voltage Accuracy—1.0 MHz, VOUT = 0.8 V
1.820
1.815
1.810
1.805
1.800
1.795
1.790
0
10,00001000 2000 3000 4000 5000 6000 7000 8000 9000
OUTPUT VOLTAGE (V)
LOAD CURRENT ( mA)
+125°C
+25°C
–40°C
V
IN
= 13V +125°C
+25°C
–40°C
V
IN
= 16.5V
09347-019
Figure 20. Output Voltage Accuracy—1.0 MHz, VOUT = 1.8 V
72006400
560048004000
24001600 3200096008800
8000800
5.04
4.90
4.91
4.92
4.93
4.94
4.95
4.96
4.97
4.98
4.99
5.00
5.01
5.02
5.03
OUTPUT VOLTAGE (V)
LOAD CURRENT ( mA)
+125°C
+25°C
–40°C
V
IN
= 13V +125°C
+25°C
–40°C
V
IN
= 16.5V
09347-020
Figure 21. Output Voltage Accuracy—1.0 MHz, VOUT =5 V
Data Sheet ADP1874/ADP1875
Rev. A | Page 11 of 44
601.0
600.5
600.0
599.5
599.0
598.5
598.0
597.5
597.0
–40.0 –7.5 25.0 57.5 90.0 122.5
FE E DBACK V OLTAGE ( V )
TEMPERATURE (°C)
VREG = 5V, V
IN
= 13V
VREG = 5V, V
IN
= 20V
09347-121
Figure 22. Feedback Voltage vs. Temperature
325
315
305
295
285
275
265
255
10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2
SW ITCHING FREQ UE NCY ( kHz )
VIN (V)
+125°C
+25°C
–40°C
NO LOAD
09347-022
Figure 23. Switching Frequency vs. High Input Voltage, 300 kHz, ±10% of 12 V
650
600
550
500
450
400
13.0 13.4 13.8 14.2 14.6 15.0 15.4 15.8 16.2 16.5
SW ITCHING FREQ UE NCY ( kHz )
VIN (V)
+125°C
+25°C
–40°C
NO LOAD
09347-123
Figure 24. Switching Frequency vs. High Input Voltage, 600 kHz, VOUT = 1.8 V,
VIN Range = 13 V to 16.5 V
900
880
860
840
820
800
780
760
740
720
700
13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
SW ITCHING FREQ UE NCY ( kHz )
V
IN
(V)
+125°C
+25°C
–40°C
09347-124
Figure 25. Switching Frequency vs. High Input Voltage, 1.0 MHz,
VIN Range = 13 V to 16.5 V
280
190
205
220
235
250
265
010,0008000600040002000
FRE QUENCY ( kHz )
LOAD CURRENT ( mA)
V
IN
= 13V
V
IN
= 20V
V
IN
= 16.5V
+125°C
+25°C
–40°C
09347-025
Figure 26. Frequency vs. Load Current, 300 kHz, VOUT = 0.8 V
330
240
250
260
270
280
290
300
310
320
015,00012,000 13,500
10,500900075006000450030001500
FRE QUENCY ( kHz )
LOAD CURRENT ( mA)
V
IN
= 20V
V
IN
= 13V
V
IN
= 16.5V
+125°C
+25°C
–40°C
09347-026
Figure 27. Frequency vs. Load Current, 300 kHz, VOUT = 1.8 V
ADP1874/ADP1875 Data Sheet
Rev. A | Page 12 of 44
338
298
302
306
310
314
318
322
326
330
334
06400 7200 8000 8800560048004000320024001600800
FRE QUENCY ( kHz )
LOAD CURRENT ( mA)
V
IN
= 13V
V
IN
= 16.5V +125°C
+25°C
–40°C
09347-027
Figure 28. Frequency vs. Load Current, 300 kHz, VOUT = 7 V
300
330
360
390
420
450
480
510
540
012,0001200 2400 3600 4800 6000 7200 8400 9600 10,800
FRE QUENCY ( kHz )
LOAD CURRENT ( mA)
V
IN
= 16.5V
V
IN
= 13V +125°C
+25°C
–40°C
09347-028
Figure 29. Frequency vs. Load Current, 600 kHz, VOUT = 0.8 V
675
495
515
535
555
575
595
615
635
655
01000 2000 3000 4000 5000 6000 7000 8000 9000 10,000
FRE QUENCY ( kHz )
LOAD CURRENT ( mA)
V
IN
= 16.5V
V
IN
= 13V
+125°C
+25°C
–40°C
09347-029
Figure 30. Frequency vs. Load Current, 600 kHz, VOUT = 1.8 V
740
621
628
635
642
649
656
663
670
677
684
691
698
705
712
719
726
733
096008800800072006400560048004000320024001600800
FRE QUENCY ( kHz )
LOAD CURRENT ( mA)
V
IN
= 13V
V
IN
= 16.5V +125°C
+25°C
–40°C
09347-030
Figure 31. Frequency vs. Load Current, 600 kHz, VOUT = 5 V
850
775
700
625
550
475
400 012,00010,0008000600040002000
FRE QUENCY ( kHz )
LOAD CURRENT ( mA)
VIN = 16.5V
VIN = 13V +125°C
+25°C
–40°C
09347-031
Figure 32. Frequency vs. Load Current, VOUT = 1.0 MHz, 0.8 V
550
625
700
775
850
925
1000
1075
1150
1225
012,0009600 10,8008400720060004800360024001200
FRE QUENCY ( kHz )
LOAD CURRENT ( mA)
VIN = 16.5V
VIN = 13V +125°C
+25°C
–40°C
09347-032
Figure 33. Frequency vs. Load Current, 1.0 MHz, VOUT = 1.8 V
Data Sheet ADP1874/ADP1875
Rev. A | Page 13 of 44
1000
1450
1400
1350
1300
1250
1200
1150
1100
1050
08000800 1600 2400 3200 4000 4800 5600 6400 7200
FRE QUENCY ( kHz )
LOAD CURRENT ( mA)
V
IN
= 16.5V
V
IN
= 13V +125°C
+25°C
–40°C
09347-033
Figure 34. Frequency vs. Load Current, 1.0 MHz, VOUT = 5 V
2.649
2.658
2.657
2.656
2.655
2.654
2.653
2.652
2.651
2.650
–40 120100806040200–20
UVLO (V)
TEMPERATURE (°C)
09347-034
Figure 35. UVLO vs. Temperature
55
60
65
70
75
80
85
90
95
300 400 500 600 700 800 900 1000
MAXIMUM DUTY CYCLE (%)
FRE QUENCY ( kHz )
+125°C
+25°C
–40°C
09347-035
Figure 36. Maximum Duty Cycle vs. Frequency
62
64
66
68
70
72
74
76
78
80
82
5.5 6.7 7.9 9.1 10.3 11.5 12.7 13.9 15.1 16.3
MAXIMUM DUTY CYCLE (%)
V
IN
(V)
+125°C
+25°C
–40°C
09347-036
Figure 37. Maximum Duty Cycle vs. High Voltage Input (VIN)
180
680
630
580
530
480
430
380
330
280
230
–40 120100806040200–20
MINUMUM OFF-TI ME (n s)
TEMPERATURE (°C)
VREG = 2. 7V
VREG = 5. 5V
VREG = 3. 6V
09347-037
Figure 38. Minimum Off-Time vs. Temperature
180
680
630
580
530
480
430
380
330
280
230
2.7 5.55.14.74.33.93.53.1
MINUMUM OFF-TI ME (n s)
VREG (V)
+125°C
+25°C
–40°C
09347-038
Figure 39. Minimum Off-Time vs. VREG (Low Input Voltage)
ADP1874/ADP1875 Data Sheet
Rev. A | Page 14 of 44
80
800
720
640
560
480
400
320
240
160
300 400 500 600 700 800 900 1000
RECT IFIER DRO P ( mV )
FRE QUENCY ( kHz )
VREG = 2. 7V
VREG = 5. 5V
VREG = 3. 6V +125°C
+25°C
–40°C
09347-039
Figure 40. Internal Rectifier Drop vs. Frequency
80
1280
720
640
560
480
1040
1120
1200
960
880
800
400
320
240
160
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
RECT IFIER DRO P ( mV )
VREG (V)
V
IN
= 5.5V
V
IN
= 16.5V
V
IN
= 13V 1MHz
300kHz T
A
= 25° C
09347-040
Figure 41. Internal Boost Rectifier Drop vs. VREG (Low Input Voltage)
Over VIN Variation
80
720
640
560
480
400
320
240
160
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
RECT IFIER DRO P ( mV )
VREG (V)
1MHz
300kHz +125°C
+25°C
–40°C
09347-041
Figure 42. Internal Boost Rectifier Drop vs. VREG
8
80
64
72
56
48
40
32
24
16
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
BODY DIODE CONDUCTION TIM E ( ns)
VREG (V)
1MHz
300kHz +125°C
+25°C
–40°C
09347-042
Figure 43. Lower Side MOSFET Body Diode Conduction Time vs. VREG
CH1 50mV
BW
CH2 5A Ω
CH3 10V
BW
CH4 5V M400ns A CH2 3.90A
T 35.8%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
09347-043
Figure 44. Power Saving Mode (PSM) Operational Waveform, 100 mA
CH1 50mV
BW
CH2 5A Ω
CH3 10V
BW
CH4 5V M4.0µs A CH2 3.90A
T 35.8%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
09347-044
Figure 45. PSM Waveform at Light Load, 500 mA
Data Sheet ADP1874/ADP1875
Rev. A | Page 15 of 44
CH1 5A Ω
CH3 10V CH4 100mV
BW
M400ns A CH3 2.20V
T 30.6%
1
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
09347-045
Figure 46. CCM Operation at Heavy Load, 12 A
(See Figure 99 for Application Circuit)
CH1 10A Ω CH2 200mV BW
CH3 20V CH4 5V M2ms A CH1 3. 40A
T 75.6%
1
2
3
4
OUTPUT VOLTAGE
12A ST E P
SW NODE
LOW SIDE
09347-046
Figure 47. Load Transient Step—PSM Enabled, 12 A
(See Figure 99 Application Circuit)
CH1 10A Ω CH2 200mV
BW
CH3 20V CH4 5V M20µs A CH1 3.40A
T 30.6%
1
2
3
4
OUTPUT VOLTAGE
12A POSIT I VE ST EP
SW NODE
LOW SIDE
09347-047
Figure 48. Positive Step During Heavy Load Transient Behavior—PSM Enabled,
12 A, VOUT = 1.8 V (See Figure 99 Application Circuit)
CH1 10A Ω CH2 200mV
BW
CH3 20V CH4 5V M20µs A CH1 3.40A
T 48.2%
1
2
3
4
OUTPUT VOLTAGE
12A NEG ATIV E S TEP
SW NODE
LOW SIDE
09347-048
Figure 49. Negative Step During Heavy Load Transient Behavior—PSM Enabled,
12 A (See Figure 99 Application Circuit)
CH1 10A Ω CH2 5V
CH3 20V CH4 200mV
BW
M2ms A CH1 6. 20A
T 15.6%
1
2
3
4
OUTPUT VOLTAGE
12A ST E P
SW NODE
LOW SIDE
09347-049
Figure 50. Load Transient Step—Forced PWM at Light Load, 12 A
(See Figure 99 Application Circuit)
CH1 10A Ω CH2 5V
CH3 20V CH4 200mV
BW
M20µs A CH1 6.20A
T 43.8%
1
2
3
4
OUTPUT VOLTAGE
12A POSIT I VE ST EP
SW NODE
LOW SIDE
09347-050
Figure 51. Positive Step During Heavy Load Transient Behavior—Forced PWM
at Light Load, 12 A, VOUT = 1.8 V (See Figure 99 Application Circuit)
ADP1874/ADP1875 Data Sheet
Rev. A | Page 16 of 44
CH1 10A Ω CH2 200mV
BW
CH3 20V CH4 5V M10µs A CH1 5.60A
T 23.8%
1
2
3
4
OUTPUT VOLTAGE
12A NEG ATIV E S TEP
SW NODE
LOW
SIDE
09347-051
Figure 52. Negative Step During Heavy Load Transient Behavior—Forced PWM
at Light Load, 12 A (See Figure 99 Application Circuit)
CH1 2V
BW
CH2 5A Ω
CH3 10V CH4 5V M4ms A CH1 920mV
T 49.4%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
09347-052
Figure 53. Output Short-Circuit Behavior Leading to Hiccup Mode
CH1 5V
BW
CH2 10A Ω
CH3 10V CH4 5V M10µs A CH2 8.20A
T 36.2%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
09347-053
Figure 54. Magnified Waveform During Hiccup Mode
CH1 2V
BW
CH2 5A Ω
CH3 10V CH4 5V M2ms A CH1 720mV
T 32.8%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
09347-054
Figure 55. Start-Up Behavior at Heavy Load, 12 A, 300 kHz
(See Figure 99 Application Circuit)
CH1 2V
BW
CH2 5A Ω
CH3 10V CH4 5V M4ms A CH1 720mV
T 41.6%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
09347-055
Figure 56. Power-Down Waveform During Heavy Load
CH1 50mV
BW
CH2 5A Ω
CH3 10V
BW
CH4 5V M2µs A CH2 3.90A
T 35.8%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
09347-056
Figure 57. Output Voltage Ripple Waveform During PSM Operation
at Light Load, 2 A
Data Sheet ADP1874/ADP1875
Rev. A | Page 17 of 44
2
CH2 5V
CH3 5V
MAT H 2V 40ns CH4 2V M40ns A CH2 4.20V
T 29.0%
3
M
4
HIGH SI DE
HS MINUS
SW
SW NODE
LOW SIDE T
A
= 25° C
09347-058
Figure 58. Output Drivers and SW Node Waveforms
2
CH2 5V
CH3 5V
MAT H 2V 40ns CH4 2V M40ns A CH2 4.20V
T 29.0%
3
M
4
HIGH SI DE
HS MINUS
SW
SW NODE
LOW SIDE 16n s (
t
f
,DRVL
)
25ns (
t
r
,DRVH
)
22ns (
t
pdh
DRVH
)
T
A
= 25° C
09347-059
Figure 59. Upper Side Driver Rising and Lower Side Falling Edge Waveforms
(CIN = 4.3 nF (Upper Side/Lower Side MOSFET),
QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3))
2
CH2 5V
CH3 5V
MAT H 2V 20ns CH4 2V M20ns A CH2 4.20V
T 39.2%
3
M
4
HIGH SI DE
HS MINUS
SW SW NODE
LOW SIDE
18ns (
t
r
,DRVL
)
24ns (
t
pdh
,DRVL
)
11ns (
t
f
,DRVH
)
T
A
= 25° C
09347-060
Figure 60. Upper Side Driver Falling and Lower Side Rising Edge Waveforms
(CIN = 4.3 nF (Upper Side/Lower Side MOSFET),
QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3))
570
550
530
510
490
470
450
430
–40 –20 120100806040200
TRANS CONDUCTANCE ( µ S )
TEMPERATURE (°C)
VREG = 5. 5V
VREG = 3. 6V
VREG = 2. 7V
09347-061
Figure 61. Transconductance (Gm) vs. Temperature
680
330
380
430
480
530
580
630
2.7 3.0 5.44.8 5.14.54.23.93.63.3
TRANS CONDUCTANCE ( µ s)
VREG (V)
+125°C
+25°C
–40°C
09347-062
Figure 62. Transconductance (Gm) vs. VREG
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.702.7 5.55.14.74.3
–40°C
+25°C
+125°C
3.93.53.1
QUIESCE NT CURRENT ( mA)
VREG (V)
09347-163
Figure 63. Quiescent Current vs. VREG
ADP1874/ADP1875 Data Sheet
Rev. A | Page 18 of 44
ADP1874/ADP1875 BLOCK DIGRAM
09347-063
DRVH
GND
IREV
COMP
ADP1874/ADP1875
C
R (TRIMMED)
VREG
t
ON
TIMER
t
ON
= 2RC(V
OUT
/V
IN
)
I
SW
INFORMATION
SW FILTER
STATE
MACHINE
TON
BG_REF
IN_PSM
IN_SS
PWM
HS_O
HS
SW
LS
LS_O
IREV
LEVEL
SHIFT HS
VREG
LS
VREG
300kΩ
800kΩ
8kΩ
SW
DRVL
PGND
BST
VIN
PSM
REF_ZERO
IN_HICC
SS
COMP
ERROR
AMP
SS_REF
0.6V
LOWER
COMP
CLAMP
REF_ZERO
CS
AMP
PWM
FB
TRACK
COMP
VREG
VREG_IN
I
SS
SS
0.4V
ADC RES DE TECT AND
GAIN SET
CS G AIN SET
BIAS BLOCK
AND REF E RE NCE
REF
LDO
PRECISION
ENABLE
EN_REF
TO ENABL E
ALL BLOCKS
EN
RES
530mV
690mV
FB
600mV
PGOOD
Figure 64. ADP1874/ADP1875 Block Diagram
Data Sheet ADP1874/ADP1875
Rev. A | Page 19 of 44
THEORY OF OPERATION
The ADP1874/ADP1875 are versatile current mode, synchronous
step-down controllers that provide superior transient response,
optimal stability, and current limit protection by using a constant
on-time, pseudo-fixed frequency with a programmable current-
sense gain, current-control scheme. In addition, these devices offer
optimum performance at low duty cycles by using a valley, current
mode control architecture. This allows the ADP1874/ADP1875
to drive all N-channel power stages to regulate output voltages
to as low as 0.6 V.
STARTUP
The ADP1874/ADP1875 have an internal regulator (VREG) for
biasing and supplying power for the integrated MOSFET drivers.
A bypass capacitor should be located directly across the VREG
(Pin 7) and PGND (Pin 13) pins. Included in the power-up
sequence is the biasing of the current-sense amplifier, the current-
sense gain circuit (see the Programming Resistor (RES) Detect
Circuit section), the soft start circuit, and the error amplifier.
The current-sense blocks provide valley current information
(see the Programming Resistor (RES) Detect Circuit section)
and are a variable of the compensation equation for loop stability
(see the Compensation Network section). The valley current
information is extracted by forcing a voltage across the RES and
PGND pins, which generates a current depending on the resistor
value across RES and PGND. The current through the resistor is
used to set the current-sense amplifier gain. This process takes
approximately 800 µs, after which the drive signal pulses appear
at the DRVL and DRVH pins synchronously, and the output
voltage begins to rise in a controlled manner through the soft
start sequence.
The rise time of the output voltage is determined by the soft
start and error amplifier blocks (see the Soft Start section). At
the beginning of a soft start, the error amplifier charges the
external compensation capacitor, causing the COMP pin to
begin to rise (see Figure 66). Tying the VREG pin to the EN pin
via a pull-up resistor causes the voltage at this pin to rise above the
enable threshold of 630 mV to enable the ADP1874/ADP1875.
SOFT START
The ADP1874 employs externally programmable, soft start
circuitry that charges up a capacitor tied to the SS pin to GND.
This prevents input in-rush current through the external MOSFET
from the input supply (VIN). The output tracks the ramping voltage
by producing PWM output pulses to the upper side MOSFET.
The purpose is to limit the in-rush current from the high
voltage input supply (VIN) to the output (VOUT).
PRECISION ENABLE CIRCUITRY
The ADP1874/ADP1875 have precision enable circuitry. The
precision enable threshold is 630 mV with 30 mV of hysteresis
(see Figure 65). Connecting the EN pin to GND disables the
ADP1874/ADP1875, reducing the supply current of the device
to approximately 140 µA.
PRECISION
ENABLE COMP .
TO E NABLE
ALL BLO CKS
EN
630mV
VREG
10kΩ
09347-064
Figure 65. Connecting EN Pin to VREG via a Pull-Up Resistor to Enable the
ADP1874/ADP1875
COMP
2.4V
1.0V
500mV
0V
MAXIMUM CURRE NT (UPP E R CLAMP)
ZE RO CURRENT
USABLE RANG E ONLY AF TER S OFT START
PERI OD I F CONTUNUOUS CO NDUCTIO N
MODE OF OPERATI O N IS SELECTED.
LOWE R CLAMP
09347-065
Figure 66. COMP Voltage Range
UNDERVOLTAGE LOCKOUT
The undervoltage lockout (UVLO) feature prevents the part
from operating both the upper side and lower side MOSFETs at
extremely low or undefined input voltage (VIN) ranges. Operation
at an undefined bias voltage may result in the incorrect propagation
of signals to the high-side power switches. This, in turn, results
in invalid output behavior that can cause damage to the output
devices, ultimately destroying the device tied at the output. The
UVLO level is set at 2.65 V (nominal).
ADP1874/ADP1875 Data Sheet
Rev. A | Page 20 of 44
ON-BOARD LOW DROPOUT REGULATOR
The ADP1874/ADP1875 use an on-board LDO to bias the
internal digital and analog circuitry. Connect the VREG and
VREG_IN pins together for normal LDO operation for low
voltage internal block biasing (see Figure 67).
09347-168
VREG_IN
REF
VREG VIN
ON-BOARD REGULATOR
Figure 67. Connecting VREG and VREG_IN Together
With proper bypass capacitors connected to the VREG pin (output
of the internal LDO), this pin also provides power for the internal
MOSFET drivers. It is recommended to float VREG/VREG_IN
if VIN is used for greater than 5.5 V operation. The minimum
voltage where bias is guaranteed to operate is 2.75 V at VREG.
For applications where VIN is decoupled from VREG, the
minimum voltage at VIN must be 2.9 V. It is recommended to tie
VIN and VREG together if the VIN pin is subjected to a 2.75 V rail.
Table 5. Power Input and LDO Output Configurations
VIN
VREG/VREG_IN
Comments
>5.5 V Float Must use the LDO.
<5.5 V
Connect to VIN
LDO drop voltage is not
realized (that is, if VIN = 2.75 V,
then VREG = 2.75 V).
<5.5 V
Float
LDO drop is realized.
VIN Ranging
Above and
Below 5.5 V
Float
LDO drop is realized,
minimum VIN
recommendation is 2.95 V.
THERMAL SHUTDOWN
The thermal shutdown is a self-protection feature to prevent the
IC from damage due to a very high operating junction temperature.
If the junction temperature of the device exceeds 155°C, the part
enters the thermal shutdown state. In this state, the device shuts off
both the upper side and lower side MOSFETs and disables the entire
controller immediately, thus reducing the power consumption of
the IC. The part resumes operation after the junction temperature
of the part cools to less than 140°C.
PROGRAMMING RESISTOR (RES) DETECT CIRCUIT
Upon startup, one of the first blocks to become active is the RES
detect circuit. This block powers up before soft start begins. It
forces a 0.4 V reference value at the RES pin (see Figure 68) and is
programmed to identify four possible resistor values: 47 kΩ, 22 kΩ,
open, and 100 kΩ.
The RES detect circuit digitizes the value of the resistor at the
RES pin (Pin 6). An internal ADC outputs a 2-bit digital code
that is used to program four separate gain configurations in the
current-sense amplifier (see Figure 69). Each configuration corre-
sponds to a current-sense gain (ACS) of 3 V/V, 6 V/V, 12 V/V, or
24 V/V, respectively (see Table 6 and Table 7). This variable is used
for the valley current-limit setting, which sets up the appropriate
current-sense gain for a given application and sets the compensation
necessary to achieve loop stability (see the Valley Current-Limit
Setting section and the Compensation Network section).
DRVH
DRVL
Q1
SW
Q2
RES CS G AIN
PROGRAMMING
09347-066
Figure 68. Programming Resistor Location
SW
PGND
CS G AIN
SET
CS
AMP
ADC
RES
0.4V
09347-067
Figure 69. RES Detect Circuit for Current-Sense Gain Programming
Table 6. Current-Sense Gain Programming
Resistor A
CS
47 kΩ 3 V/V
22 kΩ 6 V/V
Open 12 V/V
100 kΩ 24 V/V
VALLEY CURRENT-LIMIT SETTING
The architecture of the ADP1874/ADP1875 is based on valley
current-mode control. The current limit is determined by three
components: the RON of the lower side MOSFET, the current-
sense amplifier output voltage swing, and the current-sense gain.
The CS output voltage range is internally fixed at 1.4 V. The
current-sense gain is programmable via an external resistor at
the RES pin (see the Programming Resistor (RES) Detect Circuit
section). The RON of the lower side MOSFET can vary over
temperature and usually has a positive TC (meaning that it
increases with temperature); therefore, it is recommended to
program the current-sense gain resistor based on the rated RON
of the MOSFET at 125°C.
Data Sheet ADP1874/ADP1875
Rev. A | Page 21 of 44
Because the ADP1874/ADP1875 are based on valley current
control, the relationship between ICLIM and ILOAD is
−×= 2
1
I
LOADCLIM
K
II
where:
KI is the ratio between the inductor ripple current and the
desired average load current (see Figure 70).
ICLIM is the desired valley current limit.
ILOAD is the current load.
Establishing KI helps to determine the inductor value (see the
Inductor Selection section), but in most cases KI = 0.33.
LOAD CURRENT
VAL LEY CURRE NT LIMI T
RIP P LE CURRENT = ILOAD
3
09347-068
Figure 70. Valley Current Limit to Average Current Relation
When the desired valley current limit (ICLIM) has been determined,
the current-sense gain can be calculated as follows:
ONCS
CLIM
RA
I×
=V4.1
where:
RON is the channel impedance of the lower side MOSFET.
ACS is the current-sense gain multiplier (see Table 6 and Table 7).
Although the ADP1874/ADP1875 have only four discrete current-
sense gain settings for a given RON variable, Table 7 and Figure 71
outline several available options for the valley current setpoint
based on various RON values.
Table 7. Valley Current Limit Program (See Figure 71)
RON
(mΩ)
Valley Current Level
47 kΩ 22 kΩ Open 100 kΩ
ACS = 3 V/V
ACS = 6 V/V
ACS = 12 V/V
ACS = 24 V/V
1.5 38.9
2 29.2
2.5 23.3
3 39.0 19.5
3.5 33.4 16.7
4.5 26.0 13
5
23.4
11.7
5.5 21.25 10.6
10 23.3 11.7 5.83
15 31.0 15.5 7.75 3.87
18 26.0 13.0 6.5 3.25
12345678910 11 12 13 14 15 16 17 18 19 20
VAL LEY CURRE NT LIMI T (A)
R
ON
(mΩ)
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
RES = 47kΩ
A
CS
= 3V/ V
RES = 22kΩ
A
CS
= 6V/ V
RES = NO RES
A
CS = 12V /V
RES = 100kΩ
ACS = 24V /V
09347-069
Figure 71. Valley Current-Limit Value vs. RON of the Lower Side MOSFET
for Each Programming Resistor (RES)
The valley current limit is programmed as outlined in Table 7
and Figure 71. The inductor chosen must be rated to handle the
peak current, which is equal to the valley current from Table 7
plus the peak-to-peak inductor ripple current (see the Inductor
Selection section). In addition, the peak current value must be
used to compute the worst-case power dissipation in the MOSFETs
(see Figure 72).
INDUCTOR
CURRENT
VAL LEY CURRE NT-L IMI T
THRE S HOLD ( S E T FOR 25A)
ΔI = 33%
OF 30A
CS
AMPLIFIER
OUTPUT
SWING
CS
AMPLIFIER
OUTPUT
2.4V
1V0A
35A 37A
49A
39.5A
ΔI = 45%
OF 32. 25A
ΔI = 65%
OF 37A
MAXIMUM DC LOAD
CURRENT
09347-070
32.25A
30A
Figure 72. Valley Current-Limit Threshold in Relation to Inductor Ripple Current
ADP1874/ADP1875 Data Sheet
Rev. A | Page 22 of 44
HS
CLIM
ZERO
CURRENT
REPE ATED CURRENT-L IMI T
VIOLATION DETECTED
A PREDE TERMINED NUMBE R
OF PULSES IS COUNTED TO
ALLOW THE CONVERTER
TO COOL DOWN
SOFT START IS
REINITIALIZED TO
MONITOR IF THE
VIOLATION
STILL EXISTS
09347-071
Figure 73. Idle Mode Entry Sequence Due to Current-Limit Violation
HICCUP MODE DURING SHORT CIRCUIT
A current-limit violation occurs when the current across the
source and drain of the lower side MOSFET exceeds the current-
limit setpoint. When 16 current-limit violations are detected,
the controller enters idle mode and turns off the MOSFETs for
6 ms, allowing the converter to cool down. Then, the controller
reestablishes soft start and begins to cause the output to ramp up
again (see Figure 73). While the output ramps up, CS amplifier
output is monitored to determine if the violation is still present.
If it is still present, the idle event occurs again, followed by the full
chip, power-down sequence. This cycle continues until the
violation no longer exists. If the violation disappears, the converter
is allowed to switch normally, maintaining regulation.
SYNCHRONOUS RECTIFIER
The ADP1874/ADP1875 employ internal MOSFET drivers for
the external upper side and lower side MOSFETs. The low-side
synchronous rectifier not only improves overall conduction
efficiency but it also ensures proper charging of the bootstrap
capacitor located at the upper side driver input. This is beneficial
during startup to provide sufficient drive signal to the external
upper side MOSFET and to attain fast turn-on response, which is
essential for minimizing switching losses. The integrated upper
side and lower side MOSFET drivers operate in complementary
fashion with built-in anti cross-conduction circuitry to prevent
unwanted shoot-through current that may potentially damage the
MOSFETs or reduce efficiency because of excessive power loss.
ADP1875 POWER SAVING MODE (PSM)
A power saving mode is provided in the ADP1875. The ADP1875
operates in the discontinuous conduction mode (DCM) and
pulse skips at light load to medium load currents. The controller
outputs pulses as necessary to maintain output regulation. Unlike
the continuous conduction mode (CCM), DCM operation
prevents negative current, thus allowing improved system
efficiency at light loads. Current in the reverse direction through
this pathway, however, results in power dissipation and therefore
a decrease in efficiency.
HS
HS AND L S ARE OFF
OR IN IDLE MODE
LS
0A
I
LOAD
AS T HE INDUCTOR
CURRENT AP P ROACHES
ZE RO CURRENT , THE S TATE
MACHI NE TURNS O FF THE
LOW ER-SIDE MOSF ET .
t
ON
t
OFF
09347-072
Figure 74. Discontinuous Mode of Operation (DCM)
To minimize the chance of negative inductor current buildup,
an on-board zero-cross comparator turns off all upper side and
lower side switching activities when the inductor current
approaches the zero current line, causing the system to enter
idle mode, where the upper side and lower side MOSFETs are
turned off. To ensure idle mode entry, a 10 mV offset, connected in
series at the SW node, is implemented (see Figure 75).
10mV
ZERO-CROSS
COMPARATOR
Q2
LS
SW I
Q2
09347-073
Figure 75. Zero-Cross Comparator with 10 mV of Offset
Data Sheet ADP1874/ADP1875
Rev. A | Page 23 of 44
As soon as the forward current through the lower side MOSFET
decreases to a level where
10 mV = IQ2 × RON(Q2)
the zero-cross comparator (or IREV comparator) emits a signal to
turn off the lower side MOSFE T. From this point, the slope of the
inductor current ramping down becomes steeper (see Figure 76)
as the body diode of the lower side MOSFET begins to conduct
current and continues conducting current until the remaining
energy stored in the inductor has been depleted.
HS AND L S
IN IDLE MODE
10mV = R
ON
× I
LOAD
ZE RO-CRO S S COMPARATOR
DET E CTS 10mV OFFSET AND
TURNS OFF LS
SW
LS
0A
I
LOAD
tON
ANOTHER
tON
EDGE IS
TRIGGERED WHEN V
OUT
FALLS BELOW REGULATION
09347-074
Figure 76. 10 mV Offset to Ensure Prevention of Negative Inductor Current
The system remains in idle mode until the output voltage drops
below regulation. A PWM pulse is then produced, turning on the
upper side MOSFET to maintain system regulation. The ADP1875
does not have an internal clock, so it switches purely as a hysteretic
controller as described in this section.
TIMER OPERATION
The ADP1874/ADP1875 employ a constant on-time architecture,
which provides a variety of benefits, including improved load
and line transient response when compared with a constant
(fixed) frequency current-mode control loop of comparable
loop design. The constant on-time timer, or tON timer, senses
the high-side input voltage (VIN) and the output voltage (VOUT)
using SW waveform information to produce an adjustable one-
shot PWM pulse. The pulse varies the on-time of the upper side
MOSFET in response to dynamic changes in input voltage,
output voltage, and load current conditions to maintain output
regulation. The timer generates an on-time (tON) pulse that is
inversely proportional to VIN.
IN
OUT
ON
V
V
Kt ×=
where K is a constant that is trimmed using an RC timer product
for the 300 kHz, 600 kHz, and 1.0 MHz frequency options.
C
R(TRIMMED)
VREG
t
ON
V
IN
I
SW
INFORMATION
09347-075
Figure 77. Constant On-Time Time
The constant on-time (tON) is not strictly constant because it
varies with VIN and VOUT. However, this variation occurs in such
a way as to keep the switching frequency virtually independent
of VIN and VOUT.
The tON timer uses a feedforward technique, which when applied
to the constant on-time control loop makes it a pseudo-fixed
frequency to a first-order approximation. Second-order effects,
such as dc losses in the external power MOSFETs (see the
Efficiency Consideration section), cause some variation in
frequency vs. load current and line voltage. These effects are
shown in Figure 23 to Figure 34. The variations in frequency
are much reduced compared with the variations generated if
the feedforward technique is not used.
The feedforward technique establishes the following relationship:
K
fSW
1
=
where fSW is the controller switching frequency (300 kHz,
600 kHz, and 1.0 MHz).
The tON timer senses VIN and VOUT to minimize frequency variation
as previously explained. This provides pseudo-fixed frequency
as explained in the Pseudo-Fixed Frequency section. To allow
headroom for VIN and VOUT sensing, adhere to the following
equations:
VREG ≥ VIN/8 + 1.5
VREG ≥ VOUT/4
For typical applications where VREG is 5 V, these equations are not
relevant; however, care may be required for lower VREG/VIN
inputs.
ADP1874/ADP1875 Data Sheet
Rev. A | Page 24 of 44
PSEUDO-FIXED FREQUENCY
The ADP1874/ADP1875 employ a constant on-time control
scheme. During steady state operation, the switching frequency
stays relatively constant, or pseudo-fixed. This is due to the one-
shot tON timer that produces a high-side PWM pulse with a fixed
duration, given that external conditions such as input voltage,
output voltage, and load current are also at steady state. During
load transients, the frequency momentarily changes for the
duration of the transient event so that the output comes back
within regulation more quickly than if the frequency were fixed
or if it were to remain unchanged. After the transient event is
complete, the frequency returns to a pseudo-fixed value.
To illustrate this feature more clearly, this section describes
one such load transient event—a positive load step—in detail.
During load transient events, the high-side driver output pulse-
width stays relatively consistent from cycle to cycle; however,
the off-time (DRVL on-time) dynamically adjusts according to
the instantaneous changes in the external conditions mentioned.
When a positive load step occurs, the error amplifier (out of phase
with the output, VOUT) produces new voltage information at its
output (COMP). In addition, the current-sense amplifier senses
new inductor current information during this positive load
transient event. The error amplifier’s output voltage reaction is
compared with the new inductor current information that sets
the start of the next switching cycle. Because current information
is produced from valley current sensing, it is sensed at the down
ramp of the inductor current, whereas the voltage loop information
is sensed through the counter action upswing of the error
amplifier’s output (COMP).
The result is a convergence of these two signals (see Figure 78),
which allows an instantaneous increase in switching frequency
during the positive load transient event. In summary, a positive
load step causes VOUT to transient down, which causes COMP to
transient up and, therefore, shortens the off time. This resulting
increase in frequency during a positive load transient helps to
quickly bring VOUT back up in value and within the regulation
window.
Similarly, a negative load step causes the off time to lengthen in
response to VOUT rising. This effectively increases the inductor
demagnetizing phase, helping to bring VOUT within regulation.
In this case, the switching frequency decreases, or experiences a
foldback, to help facilitate output voltage recovery.
Because the ADP1874/ADP1875 have the ability to respond rapidly
to sudden changes in load demand, the recovery period in which
the output voltage settles back to its original steady state operating
point is much quicker than it would be for a fixed-frequency
equivalent. Therefore, using a pseudo-fixed frequency results in
significantly better load-transient performance compared to
using a fixed frequency.
VALLEY
TRIP POINTS
LO AD CURRENT
DEMAND
ERROR AMP
OUTPUT
PWM OUTPUT
fSW
>
fSW
CS AMP
OUTPUT
09347-076
Figure 78. Load Transient Response Operation
POWER GOOD MONITORING
The ADP1874/ADP1875 power good circuitry monitors the
output voltage via the FB pin. The PGOOD pin is an open-drain
output that can be pulled up by an external resistor to a voltage
rail that does not necessarily have to be VREG. When the internal
NMOS switch is in high impedance (off state), this means that
the PGOOD pin is logic high, and the output voltage via the FB
pin is within the specified regulation window. When the internal
switch is turned on, PGOOD is internally pulled low when the
output voltage via the FB pin is outside this regulation window.
The power good window is defined with a typical upper
specification of +90 mV and a lower specification of −70 mV
below the FB voltage of 600 mV. When an overvoltage event occurs
at the output, there is a typical propagation delay of 12 µs prior
to the PGOOD pin deassertion (logic low). When the output
voltage re-enters the regulation window, there is a propagation
delay of 12 µs prior to PGOOD reasserting back to a logic high
state. When the output is outside the regulation window, the
PGOOD open drain switch is capable of sinking 1mA of current
and provides 140 mV of drop across this switch. The user is free
to tie the external pull-up resistor (RRES) to any voltage rail up to
20 V. The following equation provides the proper external pull-up
resistor value:
mA1
mV140−
=EXT
PGD
V
R
where:
RPGD is the PGOOD external resistor.
VEXT is a user-chosen voltage rail.
09347-180
530mV
690mV
FB
600mV
PGOOD
1mA
–
140mV
+
V
EXT
R
PGD
Figure 79. Power Good, Output Voltage Monitoring Circuit
Data Sheet ADP1874/ADP1875
Rev. A | Page 25 of 44
09347-181
690mV
640mV
600mV
530mV
FB
HYSTERESIS ( 5 0mV)
OUT PUT OVERVOLTAGE
PGOO D DEASSERT
PGOOD
REASSERT
PGOOD
ASSERTION
AT PO W ER-UP PGOOD
DEASSERTION
AT PO W ER DOW N
SOFT-START
VEXT
PGOOD
0V
0V
t
PGD
t
PGD
t
PGD
t
PGD
Figure 80. Power Good Timing Diagram, tPGD = 12 µs (Diagram May Look Disproportionate for Illustration Purposes.)
09347-182
SLAVE
R
TRK2
1kΩ
R
TRK1
1kΩ
R
PGD
V
EXT
C
SS
10kΩ
R
TOP2
1kΩ R
BOT2
1kΩ
VREG
1.2V V
OUT2 ( SLAVE)
EN
FB
GND
PGOOD
SS
TRACK
PGND
MASTER
10kΩ
R
TOP1
R
BOT1
VREG
1.8V V
OUT 1 (M AST ER)
EN
FB
GND
PGND
0.9V
Figure 81. Coincident Tracking Circuit Implementation
09347-184
SLAVE
R
TRK2
500Ω
R
TRK1
1kΩ
R
PGD
V
EXT
C
SS
10kΩ
R
TOP2
1kΩ R
BOT2
1kΩ
VREG
1.2V V
OUT2 ( SLAVE)
EN
FB
GND
PGOOD
SS
TRACK
PGND
MASTER
10kΩ
R
TOP1
R
BOT1
VREG
2.5V V
OUT 1 (M AST ER)
EN
FB
GND
PGND
1.7V
Figure 82. Ratiometric Tracking Circuit Implementation
VOLTAGE TRACKING
The ADP1874/ADP1875 feature a voltage-tracking function that
facilitates proper power-up sequencing in applications that require
tracking a master voltage. In this manner, the user is free to
impose a master voltage that typically comes with a selectable
or programmable ramp rate on slave or secondary power rails.
To impose any voltage tracking relationship, the master voltage
rise time must be longer than the slave voltage soft start period.
This is particularly important in applications such as I/O voltage
sequencing and core voltage applications where specific power
sequencing is required.
Tracking is made possible by four inputs to the error amplifier,
three of which are input pins to the IC. The TRACK and SS pins
are positive inputs, and the FB pin provides the negative feedback
from the output voltage via the divider network. The fourth input
to the amplifier is the reference voltage of 0.6 V. The negative
feedback pin (FB pin) regulates the output voltage to the lowest
of the three positive inputs (TRACK, SS, and 0.6 V reference).
In all tracking configurations, the slave output can be set to as
low as 0.6 V for a given operating condition. The master voltage
must have a longer rise time than the slaves programmed soft start
period; otherwise, the tracking relationship will not be observed
at the slave output.
Coincident and ratiometric tracking are two possible tracking
configuration options offered by the ADP1874/ADP1875.
Coincident tracking is the most commonly used tracking
technique. It is primarily used in core and I/O sequencing
applications. The ramp rate of the master voltage is fully
imposed onto the ramp rate of the slave output voltage until it
has reached its regulation setpoint. Connecting the TRACK pin,
by differentially tapping onto the master voltage via a resistive
divider of similar ratio to the slave feedback divider network,
is depicted in Figure 83.
09347-083
MASTER VOLTAGE
SLAVE VOLTAGE
TIME (ms)
OUTPUT VOLTAGE (V)
Figure 83. Coincident Tracking: Master Voltage—Slave Voltage Tracking
Relationship
ADP1874/ADP1875 Data Sheet
Rev. A | Page 26 of 44
The slave output tracks the master output dv/dt until the slave
output regulation point is reached. Any influence by the master
voltage thereafter will no longer be in effect. Ensure that the voltage
forced on the slave TRACK pin is above 0.7 V at the end of TRACK
phase. Voltages imposed on the TRACK pin below 0.7 V, once
that tracking period has expired (steady state), may result in
regulation inaccuracies due to the internal offsets of the error
amplifier between TRACK and FB. Ratiometric tracking can be
achieved by assigning the slave output to rise more quickly than
the master voltage. The simplest way to perform ratiometric
tracking is to differentially connect the slave TRACK pin to the
FB pin of the master voltage IC. The slave output, however, must
be limited to a fraction of the master voltage. In this tracking
configuration, it is not recommended for the slave TRACK pin
to terminate at a voltage lower than 0.6 V due to inaccuracies
between the TRACK and FB inputs previously mentioned. It is
not recommended to force any voltage on the slave TRACK pin
lower than 0.6 V. Figure 84 illustrates a circuit with a ratiometric
tracking configuration. Setting RTRK1 > RTRK2 ensures that the
slave TRACK voltage will rise up more quickly (to the regulation
point) than the master voltage.
09347-085
MASTER VOLTAGE
SLAVE VOLTAGE
TIME (ms)
OUTPUT VOLTAGE (V)
Figure 84. Ratiometric Tracking: Master Voltage—Slave Voltage Tracking
Relationship
Data Sheet ADP1874/ADP1875
Rev. A | Page 27 of 44
APPLICATIONS INFORMATION
FEEDBACK RESISTOR DIVIDER
The required resistor divider network can be determined for a
given VOUT value because the internal band gap reference (VREF)
is fixed at 0.6 V. Selecting values for RT and RB determines the
minimum output load current of the converter. Therefore, for
a given value of RB, the RT value can be determined through the
following expression:
V6.0
V)6.0( −
×=
OUT
B
T
V
RR
INDUCTOR SELECTION
The inductor value is inversely proportional to the inductor
ripple current. The peak-to-peak ripple current is given by
3
LOAD
LOAD
IL
I
IKI ≈×=∆
where KI is typically 0.33.
The equation for the inductor value is given by
IN
OUT
SW
L
OUT
IN
V
V
fI
VV
L×
×∆
−
=)(
where:
VIN is the high voltage input.
VOUT is the desired output voltage.
fSW is the controller switching frequency (300 kHz, 600 kHz,
or 1.0 MHz).
When selecting the inductor, choose an inductor saturation
rating that is above the peak current level, and then calculate
the inductor current ripple (see the Valley Current-Limit
Setting section and Figure 85).
52
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
6 8 10 12 14 16 18 20 22 24 26 28 30
PEAK INDUCTOR CURRENT ( A)
VAL LEY CURRE NT LIMI T (A)
ΔI = 50%
ΔI = 40%
ΔI = 33%
09347-077
Figure 85. Peak Inductor Current vs. Valley Current Limit for 33%, 40%, and
50% of Inductor Ripple Current
Table 8. Recommended Inductors
L
(µH)
DCR
(mΩ)
I
SAT
(A)
Dimensions
(mm) Manufacturer
Model
Number
0.12 0.33 55 10.2 × 7 Würth Elek. 744303012
0.22 0.33 30 10.2 × 7 Würth Elek. 744303022
0.47 0.8 50 14.2 × 12.8 Würth Elek. 744355147
0.72
1.65
35
10.5 × 10.2
Würth Elek.
744325072
0.9
1.6
32
14 × 12.8
Würth Elek.
744318120
1.2 1.8 25 10.5 × 10.2 Würth Elek. 744325120
1.0 3.8 16 10.2 × 10.2 Würth Elek. 7443552100
1.4 3.2 24 14 × 12.8 Würth Elek. 744318180
2.0 2.0 23 10.2 × 10.2 Würth Elek. 7443551200
0.8 27.5 Sumida CEP125U-0R8
OUTPUT RIPPLE VOLTAGE (ΔVRR)
The output ripple voltage is the ac component of the dc output
voltage during steady state. For a ripple error of 1.0%, the output
capacitor value needed to achieve this tolerance can be determined
using the following equation. (Note that an accuracy of 1.0% is
only possible during steady state conditions, not during load
transients.)
ΔVRR = (0.01) × VOUT
OUTPUT CAPACITOR SELECTION
The primary objective of the output capacitor is to facilitate the
reduction of the output voltage ripple; however, the output capacitor
also assists in the output voltage recovery during load transient
events. For a given load current step, the output voltage ripple
generated during this step event is inversely proportional to the
value chosen for the output capacitor. The speed at which the
output voltage settles during this recovery period depends on
where the crossover frequency (loop bandwidth) is set. This
crossover frequency is determined by the output capacitor, the
equivalent series resistance (ESR) of the capacitor, and the
compensation network.
To c alculate the small signal voltage ripple (output ripple voltage) at
the steady state operating point, use the following equation:
[ ]
×∆−∆××
×∆= )(8
1
ESRIV
f
IC
LRIPPLE
SW
L
OUT
where ESR is the equivalent series resistance of the output
capacitors.
To calculate the output load step, use the following equation:
))((
2ESRIVf
I
C
LOADDROOPSW
LOAD
OUT ×∆−∆×
∆
×=
where ΔVDROOP is the amount that VOUT is allowed to deviate for
a given positive load current step (ΔILOAD).
ADP1874/ADP1875 Data Sheet
Rev. A | Page 28 of 44
Ceramic capacitors are known to have low ESR. However, there
is a trade-off in using the popular X5R capacitor technology
because up to 80% of its capacitance may be lost due to derating
as the voltage applied across the capacitor is increased (see
Figure 86). Although X7R series capacitors can also be used, the
available selection is limited to 22 µF maximum.
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100 0 5 10 15 20 25
30
CAPACI TANCE CHARG E ( %)
DC VOLTAGE (V
DC
)
X7R (50V )
X5R (25V )
X5R (16V )
10µF TDK 25V, X 7R, 1210 C3225X7R1E106M
22µF M URATA 25V, X 7R, 1210 GRM 32E R71E 226KE 15L
47µF M URATA 16V, X 5R, 1210 GRM 32E R61C476KE 15L
09347-078
Figure 86. Capacitance vs. DC Voltage Characteristics for Ceramic Capacitors
Electrolytic capacitors satisfy the bulk capacitance requirements
for most high current applications. However, because the ESR
of electrolytic capacitors is much higher than that of ceramic
capacitors, several MLCCs should be mounted in parallel with
the electrolytic capacitors to reduce the overall series resistance.
COMPENSATION NETWORK
Due to its current-mode architecture, the ADP1874/ADP1875
require Type II compensation. To determine the component
values needed for compensation (resistance and capacitance
values), it is necessary to examine the converter’s overall loop
gain (H) at the unity gain frequency (fSW/10) when H = 1 V/V.
FILT
COMP
OUT
REF
CS
M
ZZ
V
V
GGH ××××== V/V1
Examining each variable at high frequency enables the unity-
gain transfer function to be simplified to provide expressions
for the RCOMP and CCOMP component values.
Output Filter Impedance (ZFILT)
Examining the filter’s transfer function at high frequencies
simplifies to
OUT
L
OUT
L
FILTER
CESRRs
CESRs
RZ )(1
1
++
××+
×=
at the crossover frequency (s = 2πfCROSS). ESR is the equivalent
series resistance of the output capacitors.
Error Amplifier Output Impedance (ZCOMP)
Assuming that CC2 is significantly smaller than CCOMP, CC2 can
be omitted from the output impedance equation of the error
amplifier. The transfer function simplifies to
22
ZERO
CROSS
CROSS
COMP
COMP
ff
f
R
Z+×=
and
SWCROSS
ff ×= 12
1
where fZERO, the zero frequency, is set to be 1/4 the crossover
frequency for the ADP1874.
Error Amplifier Gain (Gm)
The error amplifier gain (transconductance) is
Gm = 500 µA/V (µs)
Current-Sense Loop Gain (GCS)
The current-sense loop-gain is
ONCS
CS
RA
G×
=1
(A/V)
where:
ACS (V/V) is programmable for 3 V/V, 6 V/V, 12 V / V, and 24 V/V
(see the Programming Resistor (RES) Detect Circuit and Valley
Current-Limit Setting sections).
RON is the channel impedance of the lower side MOSFET.
Crossover Frequency
The crossover frequency is the frequency at which the overall
loop (system) gain is 0 dB (H = 1 V/V). It is recommended for
current-mode converters, such as the ADP1874, that the user
set the crossover frequency between 1/10 and 1/15 the
switching frequency.
SWCROSS
ff 12
1
=
The relationship between CCOMP and fZERO (zero frequency) is as
follows:
COMPCOMP
ZERO
CR
f××π
=2
1
The zero frequency is set to 1/4 the crossover frequency.
Combining all of the above parameters results in
( )
( )
CS
MREF
OUT
L
OUT
OUT
L
ZERO
CROSS
CROSS
COMP
GGV
V
R
CESRs
CESRRs
ff
f
R
11
1
)(1
2
2
2
2
22 ×××
××+
++
×
+
=
where ESR is the equivalent series resistance of the output
capacitors.
ZERO
COMP
COMP
fR
C××π×
=2
1
Data Sheet ADP1874/ADP1875
Rev. A | Page 29 of 44
EFFICIENCY CONSIDERATION
One of the important criteria to consider in constructing a dc-to-dc
converter is efficiency. By definition, efficiency is the ratio of the
output power to the input power. For high power applications at
load currents up to 20 A, the following are important MOSFET
parameters that aid in the selection process:
• VGS (TH) is the MOSFET voltage applied between the gate
and the source that starts channel conduction.
• RDS (ON) is the MOSFET on resistance during channel
conduction.
• QG is the total gate charge.
• CN1 is the input capacitance of the upper side switch.
• CN2 is the input capacitance of the lower side switch.
The following are the losses experienced through the external
component during normal switching operation:
• Channel conduction loss (both the MOSFETs)
• MOSFET driver loss
• MOSFET switching loss
• Body diode conduction loss (lower side MOSFET)
• Inductor loss (copper and core loss)
Channel Conduction Loss
During normal operation, the bulk of the loss in efficiency is due
to the power dissipated through MOSFET channel conduction.
Power loss through the upper side MOSFET is directly pro-
portional to the duty-cycle (D) for each switching period, and
the power loss through the lower side MOSFET is directly
proportional to 1 − D for each switching period. The selection
of MOSFETs is governed by the maximum dc load current that
the converter is expected to deliver. In particular, the selection
of the lower side MOSFET is dictated by the maximum load
current because a typical high current application employs duty
cycles of less than 50%. Therefore, the lower side MOSFET is
in the on state for most of the switching period.
( )
[ ]
2
1LOAD
N2(ON)N1(ON)N1,N2(CL) IRDRDP ××−+×=
MOSFET Driver Loss
Other dissipative elements are the MOSFET drivers. The con-
tributing factors are the dc current flowing through a driver
during operation and the QGATE parameter of the external MOSFETs.
( )
[ ]
( )
[ ]
BIASREG
lowerFET
SW
BIAS
DR
upperFET
SW
DR
LOSSDR
IVCfVREG
IVCfVP
+×
++×=
)(
where:
CupperFET is the input gate capacitance of the upper side MOSFET.
ClowerFET is the input gate capacitance of the lower side MOSFET.
IBIAS is the dc current flowing into the upper side and lower side
drivers.
VDR is the driver bias voltage (that is, the low input voltage
(VREG) minus the rectifier drop (see Figure 87)).
VREG is the bias voltage.
800
720
640
560
480
400
320
240
160
80
300 1000900800700600500400
RECT IFIER DRO P ( mV )
SW ITCHING FREQ UE NCY ( kHz )
+125°C
+25°C
–40°C
VREG = 2. 7V
VREG = 3. 6V
VREG = 5. 5V
09347-079
Figure 87. Internal Rectifier Voltage Drop vs. Switching Frequency
Switching Loss
The SW node transitions due to the switching activities of the
upper side and lower side MOSFETs. This causes removal and
replenishing of charge to and from the gate oxide layer of the
MOSFET, as well as to and from the parasitic capacitance
associated with the gate oxide edge overlap and the drain and
source terminals. The current that enters and exits these charge
paths presents additional loss during these transition times.
This can be approximately quantified by using the following
equation, which represents the time in which charge enters and
exits these capacitive regions:
tSW-TRANS = RGATE × CTOTAL
where:
CTOTAL is the CGD + CGS of the external MOSFET.
RGATE is the gate input resistance of the external MOSFET.
The ratio of this time constant to the period of one switching cycle
is the multiplying factor to be used in the following expression:
2
-
)( ×××= IN
LOAD
SW
TRANSSW
LOSSSW VI
t
t
P
or
PSW(LOSS) = fSW × RGATE × CTOTAL × ILOAD × VIN × 2
ADP1874/ADP1875 Data Sheet
Rev. A | Page 30 of 44
Diode Conduction Loss
The ADP1874/ADP1875 employ anti cross-conduction circuitry
that prevents the upper side and lower side MOSFETs from
conducting current simultaneously. This overlap control is
beneficial, avoiding large current flow that may lead to irreparable
damage to the external components of the power stage. However,
this blanking period comes with the trade-off of a diode
conduction loss occurring immediately after the MOSFET
change states and continuing well into idle mode. The amount of
loss through the body diode of the lower side MOSFET during
the anti-overlap state is given by the following expression:
2
)(
)( ×××= F
LOAD
SW
LOSSBODY
LOSSBODY VI
t
t
P
where:
tBODY(LOSS) is the body conduction time (see Figure 88 for dead
time periods).
tSW is the period per switching cycle.
VF is the forward drop of the body diode during conduction.
(See the selected external MOSFET data sheet for more
information about the VF parameter.)
80
72
64
56
48
40
32
24
16
8
2.7 5.54.84.13.4
BODY DIODE CONDUCTION TIM E ( ns)
VREG (V)
+125°C
+25°C
–40°C
1MHz
300kHz
09347-080
Figure 88. Body Diode Conduction Time vs. Low Voltage Input (VREG)
Inductor Loss
During normal conduction mode, further power loss is caused
by the conduction of current through the inductor windings,
which have dc resistance (DCR). Typically, larger sized inductors
have smaller DCR values.
The inductor core loss is a result of the eddy currents generated
within the core material. These eddy currents are induced by the
changing flux, which is produced by the current flowing through
the windings. The amount of inductor core loss depends on the
core material, the flux swing, the frequency, and the core volume.
Ferrite inductors have the lowest core losses, whereas powdered iron
inductors have higher core losses. It is recommended to use shielded
ferrite core material type inductors with the ADP1874/ADP1875
for a high current, dc-to-dc switching application to achieve
minimal loss and negligible electromagnetic interference (EMI).
2
)( LOAD
LOSSDCR
IDCRP×=
+ Core Loss
INPUT CAPACITOR SELECTION
The goal in selecting an input capacitor is to reduce or minimize
input voltage ripple and to reduce the high frequency source
impedance, which is essential for achieving predictable loop
stability and transient performance.
The problem with using bulk capacitors, other than their physical
geometries, is their large equivalent series resistance (ESR) and
large equivalent series inductance (ESL). Aluminum electrolytic
capacitors have such high ESR that they cause undesired input
voltage ripple magnitudes and are generally not effective at high
switching frequencies.
If bulk electrolytic capacitors are used, it is recommended to use
multilayered ceramic capacitors (MLCC) in parallel due to their
low ESR values. This dramatically reduces the input voltage ripple
amplitude as long as the MLCCs are mounted directly across the
drain of the upper side MOSFET and the source terminal of the
lower side MOSFET (see the Layout Considerations section).
Improper placement and mounting of these MLCCs may cancel
their effectiveness due to stray inductance and an increase in
trace impedance.
( )
OUT
OUT
IN
OUT
MAXLOADRMSCIN V
VVV
II −×
×= ,,
The maximum input voltage ripple and maximum input capacitor
rms current occur at the end of the duration of 1 − D while the
upper side MOSFET is in the off state. The input capacitor rms
current reaches its maximum at Time D. When calculating the
maximum input voltage ripple, account for the ESR of the input
capacitor as follows:
VMAX,RIPPLE = VRIPP + (ILOAD,MAX × ESR)
where:
VRIPP is usually 1% of the minimum voltage input.
ILOAD,MAX is the maximum load current.
ESR is the equivalent series resistance rating of the input capacitor.
Inserting VMAX,RIPPLE into the charge balance equation to
calculate the minimum input capacitor requirement gives
SWRIPPLEMAX
MAXLOAD
IN,min f
DD
V
I
C)1(
,
,−
×=
or
RIPPLEMAXSW
MAXLOAD
IN,min Vf
I
C
,
,
4
=
where D = 50%.
Data Sheet ADP1874/ADP1875
Rev. A | Page 31 of 44
THERMAL CONSIDERATIONS
The ADP1874/ADP1875 are used for dc-to-dc, step down, high
current applications that have an on-board controller, an on-board
LDO, and on-board MOSFET drivers. Because applications may
require up to 20 A of load current and be subjected to high ambient
temperature, the selection of external upper side and lower side
MOSFETs must be associated with careful thermal consideration
to not exceed the maximum allowable junction temperature of
125°C. To avoid permanent or irreparable damage, if the junction
temperature reaches or exceeds 155°C, the part enters thermal
shutdown, turning off both external MOSFETs and is not re-
enabled until the junction temperature cools to 140°C (see the
On-Board Low Dropout Regulator section).
In addition, it is important to consider the thermal impedance
of the package. Because the ADP1874/ADP1875 employ an
on-board LDO, the ac current (fxCxV) consumed by the internal
drivers to drive the external MOSFETs, adds another element of
power dissipation across the internal LDO. Equation 3 shows the
power dissipation calculations for the integrated drivers and for
the internal LDO.
Table 9 lists the thermal impedance for the ADP1874/ADP1875,
which are available in a 16-lead QSOP.
Table 9. Thermal Impedance for 16-lead QSOP
Parameter Thermal Impedance
16-Lead QSOP θ
JA
4-Layer Board 104°C/W
Figure 89 specifies the maximum allowable ambient temperature
that can surround the ADP1874/ADP1875 IC for a specified
high input voltage (VIN). Figure 89 illustrates the temperature
derating conditions for each available switching frequency for
low, typical, and high output setpoints for the 16-lead QSOP
package. All temperature derating criteria are based on a
maximum IC junction temperature of 125°C.
150
30
40
50
60
70
80
90
100
110
120
130
140
5.5 19.017.516.014.513.011.510.08.57.0
MAXIMUM ALLOWABLE AMBIENT
TEMPERATURE (°C)
VIN (V)
VOUT = 0.8V
VOUT = 1.8V
VOUT = HIGH SETPOINT
600kHz
300kHz
1MHz
09347-183
Figure 89. Ambient Temperature vs. VIN,
4-Layer EVB, CIN = 4.3 nF (Upper Side/Lower Side MOSFET)
The maximum junction temperature allowed for the ADP1874/
ADP1875 ICs is 125°C. This means that the sum of the ambient
temperature (TA) and the rise in package temperature (TR), which is
caused by the thermal impedance of the package and the internal
power dissipation, should not exceed 125°C, as dictated by the
following expression:
TJ = TR × TA (1)
where:
TJ is the maximum junction temperature.
TR is the rise in package temperature due to the power
dissipated from within.
TA is the ambient temperature.
The rise in package temperature is directly proportional to its
thermal impedance characteristics. The following equation
represents this proportionality relationship:
TR = θJA × PDR(LOSS) (2)
where:
θJA is the thermal resistance of the package from the junction to
the outside surface of the die, where it meets the surrounding air.
PDR(LOSS) is the overall power dissipated by the IC.
The bulk of the power dissipated is due to the gate capacitance of
the external MOSFETs and current running through the on-board
LDO. The power loss equations for the MOSFET drivers and
internal low dropout regulator (see the MOSFET Driver Loss
section and the Efficiency Consideration section) are
PDR(LOSS) = [VDR × (fSWCupperFETVDR + IBIAS)] +
[VREG × (fSWClowerFET VREG + IBIAS)] (3)
where:
CupperFET is the input gate capacitance of the upper side MOSFET.
ClowerFET is the input gate capacitance of the lower side MOSFET.
IBIAS is the dc current (2 mA) flowing into the upper side and
lower side drivers.
VDR is the driver bias voltage (the low input voltage (VREG) minus
the rectifier drop (see Figure 87)).
VREG is the LDO output/bias voltage.
)()(
)(
)(
BIAS
TOTAL
SW
IN
LOSSDR
LDODISS
IVREGCfVREGVP
P
+
×××−+
=
(4)
where:
PDISS(LDO) is the power dissipated through the pass device in the
LDO block across VIN and VREG.
PDR(LOSS) is the MOSFET driver loss.
VIN is the high voltage input.
VREG is the LDO output voltage and bias voltage.
CTOTAL is the CGD + CGS of the external MOSFET.
IBIAS is the dc input bias current.
ADP1874/ADP1875 Data Sheet
Rev. A | Page 32 of 44
For example, if the external MOSFET characteristics are θJA
(16-lead QSOP) = 104° C / W, f SW = 300 kHz, IBIAS = 2 mA, CupperFET =
3.3 nF, ClowerFET = 3.3 nF, VDR = 4.62 V, a nd VREG = 5.0 V, then the
power loss is
( )
[ ]
( )
[ ]
))002.00.5103.310300(0.5(
))002.062.4103.310300(62.4(
93
93
)(
+×××××
++×××××=
+×
++×=
−
−
BIAS
lowerFET
SW
BIAS
DR
upperFET
SW
DR
LOSSDR
IVREGCfVREG
IVCfVP
= 57.12 mW
)002.05103.310300()V5V13(
)()(
9
3
)(
+×××××−=
+×××−=
−
BIAS
total
SW
IN
LDODISS
IVREGCf
VREGVP
= 55.6 mW
mW6.55mW13.77
)()()(
+=
+= LOSSDRLDODISSTOTALDISS PPP
= 132.73 mW
The rise in package temperature (for 16-lead QSOP) is
mW05.132°C104
)(
×=
×θ=
LOSSDR
JA
R
PT
= 13.7°C
Assuming a maximum ambient temperature environment of 85°C,
TJ = TR × TA = 13.7°C + 85°C = 98.7°C
which is below the maximum junction temperature of 125°C.
DESIGN EXAMPLE
The ADP1874/ADP1875 are easy to use, requiring only a few
design criteria. For example, the example outlined in this section
uses only four design criteria: VOUT = 1.8 V, ILOAD = 15 A (pulsing),
VIN = 12 V (typical), and fSW = 300 kHz.
Input Capacitor
The maximum input voltage ripple is usually 1% of the
minimum input voltage (11.8 V × 0.01 = 120 mV).
VRIPP = 120 mV
VMAX,RIPPLE = VRIPP − (ILOAD,MAX × ESR)
= 120 mV − (15 A × 0.001) = 45 mV
mV105103004
A15
4
3
,
,
×××
==
RIPPLEMAXSW
MAXLOAD
IN,min
Vf
I
C
= 120 µF
Choose five 22 µF ceramic capacitors. The overall ESR of five
22 µF ceramic capacitors is less than 1 mΩ.
IRMS = ILOAD/2 = 7.5 A
PCIN = (IRMS)2 × ESR = (7.5 A)2 × 1 mΩ = 56.25 mW
Inductor
Determine inductor ripple current amplitude as follows:
3
LOAD
L
I
I≈∆ = 5 A
Therefore, calculating for the inductor value
V2.13
V8.1
10300V5
)V8.1V2.13(
)(
3
×
××
−
=
×
×∆
−
=
IN,MAX
OUT
SW
L
OUT
IN,MAX
V
V
fI
VV
L
= 1.03 µH
The inductor peak current is approximately
15 A + (5 A × 0.5) = 17.5 A
Therefore, an appropriate inductor selection is 1.0 µH with
DCR = 3.3 mΩ (Würth Elektronik 7443552100) from Table 10
with peak current handling of 20 A.
2
)( L
LOSSDCR
IDCRP×=
= 0.003 × (15 A)2 = 675 mW
Current Limit Programming
The valley current is approximately
15 A − (5 A × 0.5) = 12.5 A
Assuming a lower side MOSFET RON of 4.5 mΩ and 13 A as
the valley current limit from Table 7 and Figure 71 indicates, a
programming resistor (RES) of 100 kΩ corresponds to an ACS
of 24 V / V.
Choose a programmable resistor of RRES = 100 kΩ for a current-
sense gain of 24 V/ V.
Output Capacitor
Assume that a load step of 15 A occurs at the output and no more
than 5% output deviation is allowed from the steady state
operating point. In this case, the ADP1874 advantage is that,
because the frequency is pseudo-fixed, the converter is able to
respond quickly because of the immediate, though temporary,
increase in switching frequency.
ΔVDROOP = 0.05 × 1.8 V = 90 mV
Assuming that the overall ESR of the output capacitor ranges
from 5 mΩ to 10 mΩ,
)mV90(10300
A15
2
)(
2
3××
×=
∆×
∆
×=
DROOPSW
LOAD
OUT Vf
I
C
= 1.11 mF
Therefore, an appropriate inductor selection is five 270 µF
polymer capacitors with a combined ESR of 3.5 mΩ.
Data Sheet ADP1874/ADP1875
Rev. A | Page 33 of 44
Assuming an overshoot of 45 mV, determine if the output
capacitor that was calculated previously is adequate.
( )
( )
22
26
2
2
2
)8.1()mV458.1(
)A15(101
)(
)(
−−
××
=
−∆−
×
=
−
OUTOVSHTOUT
LOAD
OUT VVV
IL
C
= 1.4 mF
Choose five 270 µF polymer capacitors.
The rms current through the output capacitor is
A49.1
V2.13
V8.1
10300μF1
)V8.1V2.13(
3
1
2
1
)(
3
1
2
1
3
,
,
=×
××
−
×=
×
×
−
×=
MAXIN
OUT
SW
OUT
MAXIN
RMS
V
V
fL
VV
I
The power loss dissipated through the ESR of the output
capacitor is
PCOUT = (IRMS)2 × ESR = (1.5 A)2 × 1.4 mΩ = 3.15 mW
Feedback Resistor Network Setup
Choosing RB = 1 kΩ as an example, calculate RT as follows:
kΩ2
V6.0
V)6.0V8.1(
kΩ1 =
−
×=
T
R
Compensation Network
To calculate RCOMP, CCOMP, and CPAR, the transconductance
parameter and the current-sense gain variable are required. The
transconductance parameter (Gm) is 500 µA/V, and the current-
sense loop gain is
A/V33.8
005.024
11 =
×
=
×
=
ONCS
CS
RA
G
where ACS and RON are taken from setting up the current limit
(see the Programming Resistor (RES) Detect Circuit section
and the Valley Current-Limit Setting section).
The crossover frequency is 1/12 the switching frequency.
300 kHz/12 = 25 kHz
The zero frequency is 1/4 the crossover frequency.
25 kHz/4 = 6.25 kHz
( )
( )
CS
MREF
OUT
L
OUT
OUT
L
ZERO
CROSS
CROSS
COMP
GGV
V
R
CESRs
CESRRs
ff
f
R
11
1
)(1
2
2
2
2
22
×××
××+
++
×
+
=
( )
( )
8.1
15
3.810500
1
6.0
8.1
0011.00035.02521
0011.0)0035.0)158.1((2521
25.625
25
6
22
2
2
22
×
××
×
×
×××π+
×+××π+
×
+
=
−
k
k
kk
K
RCOMP
= 60.25 kΩ
ZERO
COMP
COMP fR
Cπ
=2
1
=
33 1025.61025.6014.32
1
×××××
= 423 pF
Loss Calculations
Duty cycle = 1.8/12 V = 0.15
RON (N2) = 5.4 mΩ
tBODY(LOSS) = 20 ns (body conduction time)
VF = 0.84 V (MOSFET forward voltage)
CIN = 3.3 nF (MOSFET gate input capacitance)
QN1,N2 = 17 nC (total MOSFET gate charge)
RGATE = 1.5 Ω (MOSFET gate input resistance)
( )
[ ]
2
1LOAD
N2(ON)N1(ON)N1,N2(CL) IRDRDP ××−+×=
= (0.15 × 0.0054 + 0.85 × 0.0054) × (15 A)2
= 1.215 W
2
)(
)( ×××= F
LOAD
SW
LOSSBODY
LOSSBODY VI
t
t
P
= 20 ns × 300 × 103 × 15 A × 0.84 × 2
= 151.2 mW
PSW(LOSS) = fSW × RGATE × CTOTAL × ILOAD × VIN × 2
= 300 × 103 × 1.5 Ω × 3.3 × 10−9 × 15 A × 12 × 2
= 534.6 mW
( )
[ ]
( )
[ ]
))002.00.5103.310300(0.5(
))002.062.4103.310300(62.4(
93
93
)(
+×××××
++×××××=
+×
++×=
−
−
BIAS
lowerFET
SW
BIAS
DR
upperFET
SW
DR
LOSSDR
IVREGCfVREG
IVCfVP
= 57.12 mW
mW6.55
)002.05103.310300()V5V13(
)()(
93
)(
=
+×××××−=
+×××−=
−
BIAS
total
SW
IN
LDODISS
IVREGCfVREGVP
PCOUT = (IRMS)2 × ESR = (1.5 A)2 × 1.4 mΩ = 3.15 mW
2
)( LOAD
LOSSDCR
IDCRP×=
= 0.003 × (15 A)2 = 675 mW
PCIN = (IRMS)2 × ESR = (7.5 A)2 × 1 mΩ = 56.25 mW
PLOSS = PN1,N2 + PBODY(LOSS) + PSW + PDCR + PDR + PDISS(LDO) +
PCOUT + PCIN
= 1.215 W + 151.2 mW + 534.6 mW + 57.12 mW + 55.6 +
3.15 mW + 675 mW + 56.25 mW
= 2.655 W
ADP1874/ADP1875 Data Sheet
Rev. A | Page 34 of 44
EXTERNAL COMPONENT RECOMMENDATIONS
The configurations listed in Table 10 are with fCROSS = 1/12 × fSW, fZERO = ¼ × fCROSS, RRES = 100 kΩ, RBOT = 1 kΩ, RON = 5.4 mΩ (BSC042N03MS G),
VREG = 5 V (float), and a maximum load current of 14 A.
The ADP1875 models listed in Table 10 are the PSM versions of the device.
Table 10. External Component Values
Marking Code
(First Line/Second Line)
SAP Model ADP1874 ADP1875
VOUT
(V)
VIN
(V)
CIN
(µF) C
OUT
(µF)
L1
(µH)
RC
(kΩ)
CCOMP
(pF)
CPAR
(pF)
RTOP
(kΩ)
ADP1874ARQZ-0.3-R7/ 1874/0.3 1875/0.3 0.8 13 5 × 222 5 × 5603 0.72 56.9 620 62 0.3
ADP1875ARQZ-0.3-R7 1874/0.3 1875/0.3 1.2 13 5 × 222 4 × 5603 1.0 56.9 620 62 1.0
1874/0.3 1875/0.3 1.8 13 4 × 22
2
4 × 270
4
1.2 56.9 470 47 2.0
1874/0.3 1875/0.3 2.5 13 4 × 22
2
3 × 270
4
1.53 57.6 470 47 3.2
1874/0.3 1875/0.3 3.3 13 5 × 22
2
2 × 330
5
2.0 56.9 470 47 4.5
1874/0.3 1875/0.3 5 13 4 × 222 3305 3.27 40.7 680 68 7.3
1874/0.3 1875/0.3 7 13 4 × 222 222 + ( 4 × 476) 3.44 40.7 680 68 10.7
1874/0.3 1875/0.3 1.2 16.5 4 × 222 4 × 5603 1.0 56.9 620 62 1.0
1874/0.3
1875/0.3
1.8
16.5
3 × 222
4 × 2704
1.0
56.9
470
47
2.0
1874/0.3 1875/0.3 2.5 16.5 3 × 22
2
4 × 270
4
1.67 57.6 470 47 3.2
1874/0.3 1875/0.3 3.3 16.5 3 × 22
2
2 × 330
5
2.00 56.9 510 51 4.5
1874/0.3 1875/0.3 5 16.5 3 × 222 2 × 1507 3.84 41.2 680 68 7.3
1874/0.3 1875/0.3 7 16.5 3 × 222 222 + 4 × 476 4.44 40.7 680 68 10.7
ADP1874ARQZ-0.6-R7/ 1874/0.6 1875/0.6 0.8 5.5 5 × 222 4 × 5603 0.22 56.2 300 300 0.3
ADP1875ARQZ-0.6-R7 1874/0.6 1875/0.6 1.2 5.5 5 × 222 4 × 2704 0.47 56.9 270 27 1.0
1874/0.6 1875/0.6 1.8 5.5 5 × 222 3 × 2704 0.47 56.9 220 22 2.0
1874/0.6 1875/0.6 2.5 5.5 5 × 22
2
3 × 180
8
0.47 56.9 220 22 3.2
1874/0.6 1875/0.6 1.2 13 3 × 22
2
5 × 270
4
0.47 56.9 360 36 1.0
1874/0.6 1875/0.6 1.8 13 5 × 10
9
3 × 330
5
0.47 56.2 270 27 2.0
1874/0.6 1875/0.6 2.5 13 5 × 109 3 × 2704 0.90 57.6 240 24 3.2
1874/0.6 1875/0.6 3.3 13 5 × 109 2 × 2704 1.00 57.6 240 24 4.5
1874/0.6 1875/0.6 5 13 5 × 109 1507 1.76 40.7 360 36 7.3
1874/0.6 1875/0.6 1.2 16.5 3 × 10
9
4 × 270
4
0.47 56.9 300 30 1.0
1874/0.6 1875/0.6 1.8 16.5 4 × 10
9
2 × 330
5
0.72 53.6 270 27 2.0
1874/0.6 1875/0.6 2.5 16.5 4 × 109 3 × 2704 0.90 57.6 270 27 3.2
1874/0.6 1875/0.6 3.3 16.5 4 × 109 3305 1.0 53.0 270 27 4.5
1874/0.6 1875/0.6 5 16.5 4 × 109 4 × 476 2.0 41.2 360 36 7.3
1874/0.6
1875/0.6
7
16.5
4 × 109
3 × 476
2.0
40.7
300
30
10.7
Data Sheet ADP1874/ADP1875
Rev. A | Page 35 of 44
Marking Code
(First Line/Second Line)
SAP Model ADP1874 ADP1875
VOUT
(V)
VIN
(V)
CIN
(µF) C
OUT
(µF)
L1
(µH)
RC
(kΩ)
CCOMP
(pF)
CPAR
(pF)
RTOP
(kΩ)
ADP1874ARQZ-1.0-R7/ 1874/1.0 1875/1.0 0.8 5.5 5 × 222 4 × 2704 0.22 54.9 200 20 0.3
ADP1875ARQZ-1.0-R7 1874/1.0 1875/1.0 1.2 5.5 5 × 222 2 × 3305 0.22 49.3 220 22 1.0
1874/1.0 1875/1.0 1.8 5.5 3 × 22
2
3 × 180
8
0.22 56.9 130 13 2.0
1874/1.0 1875/1.0 2.5 5.5 3 × 22
2
270
4
0.22 54.9 130 13 3.2
1874/1.0 1875/1.0 1.2 13 3 × 109 3 × 3305 0.22 53.6 200 20 1.0
1874/1.0 1875/1.0 1.8 13 4 × 109 3 × 2704 0.47 56.9 180 18 2.0
1874/1.0 1875/1.0 2.5 13 4 × 109 2704 0.47 54.9 180 18 3.2
1874/1.0 1875/1.0 3.3 13 5 × 109 2704 0.72 56.2 180 18 4.5
1874/1.0 1875/1.0 5 13 4 × 10
9
3 × 47
6
1.0 40.7 220 22 7.3
1874/1.0 1875/1.0 1.2 16.5 3 × 10
9
4 × 270
4
0.47 56.9 270 27 1.0
1874/1.0 1875/1.0 1.8 16.5 3 × 109 3 × 2704 0.47 56.9 220 22 2.0
1874/1.0 1875/1.0 2.5 16.5 4 × 109 3 × 1808 0.72 56.9 200 20 3.2
1874/1.0 1875/1.0 3.3 16.5 4 × 109 2704 0.72 56.2 180 18 4.5
1874/1.0
1875/1.0
5
16.5
3 × 109
3 × 476
1.2
40.7
220
22
7.3
1874/1.0 1875/1.0 7 16.5 3 × 10
9
22
2
+ 47
6
1.2 40.7 180 18 10.7
1 See the Inductor Selection section and Table 11.
2 22 µF Murata 25 V, X7R, 1210 GRM32ER71E226KE15L (3.2 mm × 2.5 mm × 2.5 mm).
3 560 µF Panasonic (SP-series) 2 V, 7 mΩ, 3.7 A EEFUE0D561LR (4.3 mm × 7.3 mm × 4.2 mm).
4 270 µF Panasonic (SP-series) 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm).
5 330 µF Panasonic (SP-series) 4 V, 12 mΩ, 3.3 A EEFUE0G331R (4.3 mm × 7.3 mm × 4.2 mm).
6 47 µF Murata 16 V, X5R, 1210 GRM32ER61C476KE15L (3.2 mm × 2.5 mm × 2.5 mm).
7 150 µF Panasonic (SP-series) 6.3 V, 10 mΩ, 3.5 A EEFUE0J151XR (4.3 mm × 7.3 mm × 4.2 mm).
8 180 µF Panasonic (SP-series) 4 V, 10 mΩ, 3.5 A EEFUE0G181XR (4.3 mm × 7.3 mm × 4.2 mm).
9 10 µF TDK 25 V, X7R, 1210 C3225X7R1E106M.
Table 11. Recommended Inductors
L (µH) DCR (mΩ) I
SAT
(A) Dimension (mm) Manufacturer Model Number
0.12 0.33 55 10.2 × 7 Würth Elektronik 744303012
0.22 0.33 30 10.2 × 7 Würth Elektronik 744303022
0.47 0.8 50 14.2 × 12.8 Würth Elektronik 744355147
0.72 1.65 35 10.5 × 10.2 Würth Elektronik 744325072
0.9
1.6
32
14 × 12.8
Würth Elektronik
744318120
1.2 1.8 25 10.5 × 10.2 Würth Elektronik 744325120
1.0 3.8 16 10.2 × 10.2 Würth Elektronik 7443552100
1.4 3.2 24 14 × 12.8 Würth Elektronik 744318180
2.0 2.6 23 10.2 × 10.2 Würth Elektronik 7443551200
0.8
27.5
Sumida
CEP125U-0R8
Table 12. Recommended MOSFETs
V
GS
= 4.5 V R
ON
(mΩ) I
D
(A) V
DS
(V) C
IN
(nF) Q
TOTAL
(nC) Package Manufacturer Model Number
Upper Side MOSFET
(Q1/Q2)
5.4 47 30 3.2 20 PG-TDSON8 Infineon BSC042N03MS G
10.2 53 30 1.6 10 PG-TDSON8 Infineon BSC080N03MS G
6.0 19 30 35 SO-8 Vishay Si4842DY
9 14 30 2.4 25 SO-8 International Rectifier IRF7811
Lower Side MOSFET
(Q3/Q4)
5.4 47 30 3.2 20 PG-TDSON8 Infineon BSC042N03MS G
10.2
82
30
1.6
10
PG-TDSON8
Infineon
BSC080N03MS G
6.0 19 30 35 SO-8 Vishay Si4842DY
ADP1874/ADP1875 Data Sheet
Rev. A | Page 36 of 44
LAYOUT CONSIDERATIONS
The performance of a dc-to-dc converter depends highly on how
the voltage and current paths are configured on the printed circuit
board (PCB). Optimizing the placement of sensitive analog and
power components is essential to minimize output ripple, maintain
tight regulation specifications, and reduce PWM jitter and
electromagnetic interference.
Figure 90 shows the schematic of a typical ADP1874/ADP1875
used for a high current application. Blue traces denote high current
pathways. VIN, PGND, and VOUT traces should be wide and
possibly replicated, descending down into the multiple layers.
Vias should populate, mainly around the positive and negative
terminals of the input and output capacitors, alongside the source
of Q1/Q2, the drain of Q3/Q4, and the inductor.
10kΩ VREG
MURAT A: ( HIGH V OLTAGE INPUT CAP ACITORS)
22µF , 25V, X 7R, 1210 GRM 32E R71E 226KE 15L
PANASONIC: ( OUTP UT CAPACI TORS )
270µF, SP-SERIES, 4V, 7mΩ EEFUE0G271LR
INFINEON MOSFETs:
BSC042N03MS G (L OWE R S IDE)
BSC080N03MS G (UPP E R S IDE)
WÜRTH INDUCTORS :
1µH, 3.8mΩ, 16A 7443552100
Q3 Q4
Q1 Q2
HIGH VOLTAGE INPUT
VIN = 12V
CBST
100nF
VOUT = 1.8V , 15A
C3
22µF C4
22µF C5
22µF C6
22µF C7
22µF C8
N/A C9
N/A
C23
270µF +
C22
270µF +
C21
270µF +
C20
270µF +
C27
N/A C14 TO C19
N/A
+
C26
N/A +
C25
N/A +
C24
N/A +
1.0µH
RSNB
2Ω
CSNB
1.5nF
RTOP 2kΩ
R7 10kΩ
RBOT
1kΩ
VOUT
1VIN 16
BST
2COMP 15
SW
3EN 14
DRVH
5GND 12
DRVL
ADP1874/
ADP1875
CC
430pF
CPAR
53pF RC
57kΩ
C1
1µF
CVIN
22µF
C2
0.1µF
JP3
RRES
100kΩ
4FB 13
PGND
6RES 11
PGOOD
7VREG 10
SS
8VREG_IN 9
TRACK
5kΩ VREG
CSS
34nF
VREG
09347-081
Figure 90. ADP1874/ADP1875 High Current Evaluation Board Schematic (Blue Traces Indicate High Current Paths)
09347-092
INP UT CAPACI TORS
ARE MOUNTE D CLOS E
TO DRAIN OF Q1/Q2
AND SO URCE OF Q3/Q4
SEP ARATE ANAL OG
GROUND PL ANE FOR
COM P E NS ATION AND
FE E DBACK RE S IST ORS
SENSITIVE ANALOG
COMPONENTS
LOCATE D FAR
FROM NOISY
POWER SECTIO N
OUTPUT
CAPACITORS
ARE MOUNTE D
AT RIGHTMOST
AREA O F
EVALUATION
BOARD
Figure 91. Overall Layout of the ADP1874/ADP1875 High Current Evaluation Board
Data Sheet ADP1874/ADP1875
Rev. A | Page 37 of 44
09347-093
Figure 92. Layer 2 of ADP1874/ADP1875 Evaluation Board
09347-094
TOP RESISTOR
FE E DBACK TAP
VOUT SENSE TAP LINE
EXTENDI NG BACK TO THE
TOP RESISTOR IN THE
FE E DBACK DIVI DE R
NETWORK. THIS OVERLAPS
WITH P GND SENS E TAP
LINE EXTENDING TO THE
ANALOG GROUND P LANE
Figure 93. Layer 3 of ADP1874/ADP1875 Evaluation Board
ADP1874/ADP1875 Data Sheet
Rev. A | Page 38 of 44
09347-095
BOTTOM
RESISTOR TAP
TO ANALOG
GROUND PL ANE
PGND SENSE TAP FROM
NEGATIVE TERMINALS OF
THE OUTP UT BULK
CAPACI TORS . THIS
TRACK P LACEME NT
SHO ULD BE DI RE CTLY
BELOW T HE VOUT SENSE
LINE OF LAYER 3.
Figure 94. Layer 4 (Bottom Layer) of ADP1874/ADP1875 Evaluation Board
IC SECTION (LEFT SIDE OF EVALUATION BOARD)
A dedicated plane for the analog ground plane (GND) should
be separate from the main power ground plane (PGND). With
the shortest path possible, connect the analog ground plane to
the GND pin (Pin 5). This plane should be on only the top layer
of the evaluation board. To avoid crosstalk interference, there
should not be any other voltage or current pathway directly below
this plane on Layer 2, Layer 3, or Layer 4. Connect the negative
terminals of all sensitive analog components to the analog ground
plane. Examples of such sensitive analog components include
the resistor divider’s bottom resistor, the high frequency bypass
capacitor for biasing (0.1 µF), and the compensation network.
Mount a 1 µF bypass capacitor directly across the VREG pin
(Pin 7) and the PGND pin (Pin 13). In addition, a 0.1 µF should
be tied across the VREG pin (Pin 7) and the GND pin (Pin 5).
POWER SECTION
As shown in Figure 91, an appropriate configuration to localize
large current transfer from the high voltage input (VIN) to the
output (VOUT) and then back to the power ground is to put the
VIN plane on the left, the output plane on the right, and the main
power ground plane in between the two. Current transfers from
the input capacitors to the output capacitors, through Q1/Q2,
during the on state (see Figure 95). The direction of this current
(yellow arrow) is maintained as Q1/Q2 turns off and Q3/Q4 turns
on. When Q3/Q4 turns on, the current direction continues to be
maintained (yellow arrow) as it circles from the bulk capacitor
power ground terminal to the output capacitors, through
Q3/Q4. Arranging the power planes in this manner minimizes
the area in which changes in flux occur if the current through
Q1/Q2 stops abruptly. Sudden changes in flux, usually at the
source terminals of Q1/Q2 and the drain terminal of Q3/Q4,
cause large dv/dt at the SW node.
The SW node is near the top of the evaluation board. The SW
node should use the least amount of area possible and be away
from any sensitive analog circuitry and components. This is
because the SW node is where most sudden changes in flux
density occur. When possible, replicate this pad onto Layer 2
and Layer 3 for thermal relief and eliminate any other voltage and
current pathways directly beneath the SW node plane. Populate
the SW node plane with vias, mainly around the exposed pad of
the inductor terminal and around the perimeter of the source of
Q1/Q2 and the drain of Q3/Q4. The output voltage power plane
(VOUT) is at the rightmost end of the evaluation board. This plane
should be replicated, descending down to multiple layers with
vias surrounding the inductor terminal and the positive terminals
of the output bulk capacitors. Ensure that the negative terminals of
the output capacitors are placed close to the main power ground
(PGND), as previously mentioned. All of these points form a
tight circle (component geometry permitting) that minimizes
the area of flux change as the event switches between D and 1 − D.
09347-086
Figure 95. Primary Current Pathways During the On State of the Upper Side
MOSFET (Left Arrow) and the On State of the Lower Side MOSFET (Right Arrow)
Data Sheet ADP1874/ADP1875
Rev. A | Page 39 of 44
DIFFERENTIAL SENSING
Because the ADP1874/ADP1875 operate in valley current-mode
control, a differential voltage reading is taken across the drain
and source of the lower side MOSFET. The drain of the lower
side MOSFET should be connected as close as possible to the SW
pin (Pin 15) of the IC. Likewise, the source should be connected
as close as possible to the PGND pin (Pin 13) of the IC. When
possible, both of these track lines should be narrow and away
from any other active device or voltage/current path.
09347-087
LAYER 1: SENSE LINE FO R SW
(DRAIN OF LOWER MOSFET) LAYER 1: SENSE L I NE FO R PGND
(SOURCE OF LOWER MOSFET)
PGND
SW
Figure 96. Drain/Source Tracking Tapping of the Lower Side MOSFET for CS
Amp Differential Sensing (Yellow Sense Line on Layer 2).
Differential sensing should also be employed between the
outermost output capacitor and the feedback resistor divider
(see Figure 93 and Figure 94). Connect the positive terminal of
the output capacitor to the top resistor (RT). Connect the negative
terminal of the output capacitor to the negative terminal of the
bottom resistor, which connects to the analog ground plane as
well. Both of these track lines, as previously mentioned, should
be narrow and away from any other active device or voltage/
current path.
ADP1874/ADP1875 Data Sheet
Rev. A | Page 40 of 44
TYPICAL APPLICATION CIRCUITS
12 A, 300 kHz HIGH CURRENT APPLICATION CIRCUIT
10kΩ VREG
MURAT A: ( HIGH V OLTAGE INPUT CAP ACITORS)
22µF , 25V, X 7R, 1210 GRM 32E R71E 226KE 15L
PANASONIC: ( OUTP UT CAPACI TORS )
270µF, SP-SERIES, 4V, 7mΩ EEFUE0G271LR
INFINEON MOSFETs:
BSC042N03MS G (L OWE R S IDE)
BSC080N03MS G (UPP E R S IDE)
WÜRTH INDUCTORS :
1.2µH, 2.00mΩ, 20A 744325120
Q3 Q4
Q1 Q2
HIGH VOLTAGE INPUT
V
IN
= 12V
C
BST
100nF
V
OUT
= 1.8V , 12A
C3
22µF C4
22µF C5
22µF C6
22µF C7
22µF C8
N/A C9
N/A
C23
270µF +
C22
270µF +
C21
270µF +
C20
270µF +
C27
N/A C14 TO C19
N/A
+
C26
N/A +
C25
N/A +
C24
N/A +
1.2µH
R
SNB
2Ω
C
SNB
1.5nF
R
TOP
2kΩ
R7 10kΩ
R
BOT
1kΩ
V
OUT
1
VIN
16
BST
2
COMP
15
SW
3
EN
14
DRVH
5
GND
12
DRVL
ADP1874/
ADP1875
C
C
560pF
C
PAR
56pF R
C
49.3kΩ
C1
1µF
C
VIN
22µF
C2
0.1µF
JP3
R
RES
100kΩ
4
FB
13
PGND
6
RES
11
PGOOD
7
VREG
10
SS
8
VREG_IN
9
TRACK
5kΩ V
REG
C
SS
34nF
V
REG
09347-088
Figure 97. Application Circuit for 12 V Input, 1.8 V Output, 12 A, 300 kHz (Q2/Q4 No Connect)
5.5 V INPUT, 600 kHz APPLICATION CIRCUIT
10kΩ VREG
MURAT A: ( HIGH V OLTAGE INPUT CAP ACITORS)
22µF , 25V, X 7R, 1210 GRM 32E R71E 226KE 15L
PANASONIC: ( OUTP UT CAPACI TORS )
180µF, SP-SERIES, 4V, 10mΩ EEFUE0G181XR
INFINEON MOSFETs:
BSC042N03MS G (L OWE R S IDE)
BSC080N03MS G (UPP E R S IDE)
WÜRTH INDUCTORS :
0.47µH, 0.8mΩ, 30A 744355147
Q3 Q4
Q1 Q2
HIGH VOLTAGE INPUT
VIN = 5.5V
CBST
100nF
VOUT = 2.5V , 12A
C3
22µF C4
22µF C5
22µF C6
22µF C7
22µF C8
N/A C9
N/A
C23
N/A +
C22
180µF +
C21
180µF +
C20
180µF +
C27
N/A C14 TO C19
N/A
+
C26
N/A +
C25
N/A +
C24
N/A +
1.2µH
R
SNB
2Ω
C
SNB
1.5nF
R
TOP
3.2kΩ
R7 10kΩ
R
BOT
1kΩ
V
OUT
1
VIN
16
BST
2
COMP
15
SW
3
EN
14
DRVH
5
GND
12
DRVL
ADP1874/
ADP1875
C
C
220pF
C
F
22pF R
C
56.9kΩ
C1
1µF
C
VIN
22µF
C2
0.1µF
JP3
R
RES
100kΩ
4
FB
13
PGND
6
RES
11
PGOOD
7
VREG
10
SS
8
VREG_IN
9
TRACK
5kΩ V
REG
C
SS
34nF
V
REG
09347-089
Figure 98. Application Circuit for 5.5 V Input, 2.5 V Output, 12 A, 600 kHz (Q2/Q4 No Connect)
Data Sheet ADP1874/ADP1875
Rev. A | Page 41 of 44
300 kHz HIGH CURRENT APPLICATION CIRCUIT
10kΩ V
REG
MURAT A: ( HIGH V OLTAGE INPUT CAP ACITORS)
22µF , 25V, X 7R, 1210 GRM 32E R71E 226KE 15L
PANASONIC: ( OUTP UT CAPACI TORS )
270µF, SP-SERIES, 4V, 7mΩ EEFUE0G271LR
INFINEON MOSFETs:
BSC042N03MS G (L OWE R S IDE)
BSC080N03MS G (UPP E R S IDE)
WÜRTH INDUCTORS :
1.2µH, 2.00mΩ, 20A 744325120
Q3 Q4
Q1 Q2
HIGH VOLTAGE INPUT
V
IN
= 13V
C
BST
100nF
V
OUT
= 1.8V , 12A
C3
22µF C4
22µF C5
22µF C6
22µF C7
22µF C8
N/A C9
N/A
C23
270µF +
C22
270µF +
C21
270µF +
C20
270µF +
C27
N/A C14 TO C19
N/A
+
C26
N/A +
C25
N/A +
C24
N/A +
1.2µH
R
SNB
2Ω
C
SNB
1.5nF
R
TOP
2kΩ
R7 10kΩ
R
BOT
1kΩ
V
OUT
1
VIN
16
BST
2
COMP
15
SW
3
EN
14
DRVH
5
GND
12
DRVL
ADP1874/
ADP1875
C
C
560pF
C
PAR
56pF R
C
49.3kΩ
C1
1µF
C
VIN
22µF
C2
0.1µF
JP3
R
RES
100kΩ
4
FB
13
PGND
6
RES
11
PGOOD
7
VREG
10
SS
8
VREG_IN
9
TRACK
5kΩ V
REG
C
SS
34nF
V
REG
09347-090
Figure 99. Application Circuit for 13 V Input, 1.8 V Output, 12 A, 300 kHz (Q2/Q4 No Connect)
ADP1874/ADP1875 Data Sheet
Rev. A | Page 42 of 44
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-137-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
16 9
8
1
SEATING
PLANE
0.010 (0.25)
0.004 (0.10)
0.012 (0.30)
0.008 (0.20)
0.025 (0.64)
BSC
0.041 (1.04)
REF
0.010 (0.25)
0.006 (0.15)
0.050 (1.27)
0.016 (0.41)
0.020 (0.51)
0.010 (0.25)
8°
0°
COPLANARITY
0.004 (0.10)
0.065 (1.65)
0.049 (1.25) 0.069 (1.75)
0.053 (1.35)
0.197 (5.00)
0.193 (4.90)
0.189 (4.80)
0.158 (4.01)
0.154 (3.91)
0.150 (3.81) 0.244 (6.20)
0.236 (5.99)
0.228 (5.79)
01-28-2008-A
Figure 100. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
Branding (First Line/
Second Line)
ADP1874ARQZ-0.3-R7 −40°C to +125°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 1874/0.3
ADP1874ARQZ-0.6-R7 −40°C to +125°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 1874/0.6
ADP1874ARQZ-1.0-R7 −40°C to +125°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 1874/1.0
ADP1874-0.3-EVALZ
Evaluation Board
ADP1874-0.6-EVALZ Evaluation Board
ADP1874-1.0-EVALZ Evaluation Board
ADP1875ARQZ-0.3-R7 −40°C to +125°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 1875/0.3
ADP1875ARQZ-0.6-R7 −40°C to +125°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 1875/0.6
ADP1875ARQZ-1.0-R7 −40°C to +125°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 1875/1.0
ADP1875-0.3-EVALZ Evaluation Board
ADP1875-0.6-EVALZ Evaluation Board
ADP1875-1.0-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
Data Sheet ADP1874/ADP1875
Rev. A | Page 43 of 44
NOTES
