LTC2633ACTS8-LZ12#TRPBF - Linear Technology Corporation

LTC2633

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Block Diagram

Features Description

Dual 12-/10-/8-Bit I2C

VOUT DACs with

10ppm/°C Reference

The LTC

2633 is a family of dual 12-, 10-, and 8-bit

voltage-output DACs with an integrated, high accuracy,

low drift reference in an 8-lead TSOT-23 package. It has

rail-to-rail output buffers and is guaranteed monotonic.

The LTC2633-L has a full-scale output of 2.5V, and operates

from a single 2.7V to 5.5V supply. The LTC2633-H has a

full-scale output of 4.096V, and operates from a 4.5V to

5.5V supply. Each DAC can also operate with an external

reference, which sets the full-scale output to the external

reference voltage.

These DACs communicate via a 2-wire I2C-compatible

serial interface. The LTC2633 operates in both the standard

mode (clock rate of 100kHz) and the fast mode (clock rate

of 400kHz). The LTC2633 incorporates a power-on reset

circuit. Options are available for reset to zero-scale, reset

to mid-scale in internal reference mode, reset to mid-scale

in external reference mode, or reset with all DAC outputs

in a high impedance state after power-up.

Integral Nonlinearity (LTC2633A-LZ12)

INL Curve

applications

n Integrated Precision Reference

2.5V Full-Scale 10ppm/°C (LTC2633-L)

4.096V Full-Scale 10ppm/°C (LTC2633-H)

n Maximum INL Error: ±1LSB (LTC2633A-12)

n Low Noise: 0.75mVP-P 0.1Hz to 200kHz

n Guaranteed Monotonic Over –40°C to 125°C

Temperature Range

n Selectable Internal or External Reference

n 2.7V to 5.5V Supply Range (LTC2633-L)

n Low Power: 0.4mA at 3V

n Power-on-Reset to Zero-Scale/Mid-Scale/Hi-Z

n Double-Buffered Data Latches

n 8-Lead ThinSOT™ Package

n Mobile Communications

n Process Control and Industrial Automation

n Power Supply Margining

n Portable Equipment

n Automotive

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners. Protected by U.S. Patents including 5396245, 5859606, 6891433,

6937178, 7414561.

CODE

INL (LSB)

–1

–2 1024 3072

2633 TA01

40952048

VCC = 3V

INTERNAL REF.

2633 BD

I2C INTERFACE

I2C

ADDRESS

DECODE

POWER-ON

RESET

CONTROL

DECODE LOGIC

DAC B

DAC A VOUTB

REF

SCL

SDACA0

VOUTA

VCC

GND

INTERNAL

REFERENCE SWITCH

VREF

LTC2633

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pin conFigurationaBsolute maximum ratings

Supply Voltage (VCC) ................................... –0.3V to 6V

SCL, SDA ..................................................... –0.3V to 6V

VOUTA, VOUTB....................–0.3V to Min(VCC + 0.3V, 6V)

CA0 ...................................–0.3V to Min(VCC + 0.3V, 6V)

REF ...................................–0.3V to Min(VCC + 0.3V, 6V)

Operating Temperature Range

LTC2633C ................................................ 0°C to 70°C

LTC2633H (Note 3) ............................ –40°C to 125°C

Maximum Junction Temperature........................... 150°C

Storage Temperature Range ................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec) ..................300°C

(Notes 1, 2)

TOP VIEW

TS8 PACKAGE

8-LEAD PLASTIC TSOT-23

SDA

VCC

VOUTB

VOUTA

SCL

CA0

REF

GND

TJMAX = 150°C (NOTE 6), θJA = 195°C/W

orDer inFormation

LTC2633 A C TS8 –L Z 12 #TRM PBF

LEAD FREE DESIGNATOR

TAPE AND REEL

TR = 2,500-Piece Tape and Reel

TRM = 500-Piece Tape and Reel

RESOLUTION

12 = 12-Bit

10 = 10-Bit

8 = 8-Bit

POWER-ON RESET

I = Reset to Mid-Scale in Internal Reference Mode

X = Reset to Mid-Scale in External Reference Mode (2.5V Full-Scale

Voltage, Internal Reference Mode Option Only)

O = Reset to Mid-Scale in Internal Reference Mode, DACs High Z

(2.5V Full-Scale Voltage, Internal Reference Mode Option Only)

Z = Reset to Zero-Scale in Internal Reference Mode

FULL-SCALE VOLTAGE INTERNAL REFERENCE MODE

L = 2.5V

H = 4.096V

PACKAGE TYPE

TS8 = 8-Lead Plastic TSOT-23

TEMPERATURE GRADE

C = Commercial Temperature Range (0°C to 70°C)

H = Automotive Temperature Range (–40°C to 125°C)

ELECTRICAL GRADE (OPTIONAL)

A = ±1LSB Maximum INL (12-Bit)

PRODUCT PART NUMBER

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

LTC2633

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proDuct selection guiDe

PART NUMBER

PART

MARKING**

VFS WITH INTERNAL

REFERENCE

POWER-ON RESET

TO CODE

POWER-ON

REFERENCE

MODE

RESOLUTION

VCC

MAXIMUM

INL

LTC2633A-LI12

LTC2633A-LX12

LTC2633A-LZ12

LTC2633A-LO12*

LTC2633A-HI12

LTC2633A-HZ12

LTFTC

LTFTB

LTFSZ

LTFTV

LTFTF

LTFTD

2.5V • (4095/4096)

4.096V • (4095/4096)

Mid-Scale

Zero-Scale

High Impedance

Mid-Scale

Zero-Scale

Internal

External

Internal

12-Bit

2.7V to 5.5V

4.5V to 5.5V

±1LSB

LTC2633-LI12

LTC2633-LI10

LTC2633-LI8

LTFTC

LTFTJ

LTFTQ

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

Mid-Scale

Internal

12-Bit

10-Bit

8-Bit

2.7V to 5.5V

±2.5LSB

±1LSB

±0.5LSB

LTC2633-LX12

LTC2633-LX10

LTC2633-LX8

LTFTB

LTFTH

LTFTP

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

Mid-Scale

External

12-Bit

10-Bit

8-Bit

2.7V to 5.5V

±2.5LSB

±1LSB

±0.5LSB

LTC2633-LZ12

LTC2633-LZ10

LTC2633-LZ8

LTFSZ

LTFTG

LTFTN

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

Zero-Scale

Internal

12-Bit

10-Bit

8-Bit

2.7V to 5.5V

±2.5LSB

±1LSB

±0.5LSB

LTC2633-LO12*

LTC2633-LO10*

LTC2633-LO8*

LTFTV

LTFTW

LTFTX

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

High Impedance

Internal

12-Bit

10-Bit

8-Bit

2.7V to 5.5V

±2.5LSB

±1LSB

±0.5LSB

LTC2633-HI12

LTC2633-HI10

LTC2633-HI8

LTFTF

LTFTM

LTFTS

4.096V • (4095/4096)

4.096V • (1023/1024)

4.096V • (255/256)

Mid-Scale

Internal

12-Bit

10-Bit

8-Bit

4.5V to 5.5V

±2.5LSB

±1LSB

±0.5LSB

LTC2633-HZ12

LTC2633-HZ10

LTC2633-HZ8

LTFTD

LTFTK

LTFTR

4.096V • (4095/4096)

4.096V • (1023/1024)

4.096V • (255/256)

Zero-Scale

Internal

12-Bit

10-Bit

8-Bit

4.5V to 5.5V

±2.5LSB

±1LSB

±0.5LSB

* Contact Linear Technology for other Hi-Z options.

**The temperature grade is identified by a label on the shipping container

electrical characteristics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.

SYMBOL PARAMETER CONDITIONS

LTC2633-8 LTC2633-10 LTC2633-12 LTC2633A-12

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX

DC Performance

Resolution l810 12 12 Bits

Monotonicity VCC = 3V, Internal Ref. (Note 4) l810 12 12 Bits

DNL Differential

Nonlinearity

VCC = 3V, Internal Ref. (Note 4) l±0.5 ±0.5 ±1 ±1 LSB

INL Integral Nonlinearity VCC = 3V, Internal Ref. (Note 4) l±0.05 ±0.5 ±0.2 ±1 ±1 ±2.5 ±0.5 ±1 LSB

ZSE Zero Scale Error VCC = 3V, Internal Ref., Code = 0 l0.5 50.5 50.5 50.5 5 mV

VOS Offset Error VCC = 3V, Internal Ref. (Note 5) l±0.5 ±5 ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV

VOSTC VOS Temperature

Coefficient

VCC = 3V, Internal Ref. ±10 ±10 ±10 ±10 µV/°C

GE Gain Error VCC = 3V, Internal Ref. l±0.2 ±0.8 ±0.2 ±0.8 ±0.2 ±0.8 ±0.2 ±0.8 %FSR

LTC2633-LI12/-LI10/-LI8/-LX12/-LX10/-LX8/-LZ12/-LZ10/-LZ8/-LO12/-LO10/-LO8/LTC2633A-LI12/-LX12/-LZ12/-LO12 (VFS = 2.5V)

LTC2633

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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOUT DAC Output Span External Reference

Internal Reference

0 to VREF

0 to 2.5

PSR Power Supply Rejection VCC = 3V ± 10% or 5V ± 10% –80 dB

ISC Short Circuit Output Current (Note 6)

Sinking

Sourcing

VFS = VCC = 5.5V

Zero Scale; VOUT shorted to VCC

Full Scale; VOUT shorted to GND

–28

–48

DAC ISD DAC Output Current in High Impedance

Mode

LO Options Only l0.01 ±0.5 µA

Power Supply

VCC Positive Supply Voltage For Specified Performance l2.7 5.5 V

ICC Supply Current (Note 7) VCC = 3V, VREF = 2.5V, External Reference

VCC = 3V, Internal Reference

VCC = 5V VREF = 2.5V, External Reference

VCC = 5V, Internal Reference

0.3

0.4

0.3

0.4

0.5

0.6

0.5

0.6

ISD Supply Current in Power-Down Mode

(Note 7)

VCC = 5V l0.5 2 µA

Reference Input

Input Voltage Range l1 VCC V

Resistance l120 160 200 kΩ

Capacitance 12 pF

IREF Reference Current, Power Down Mode DAC Powered Down l0.005 5 µA

Reference Output

Output Voltage l1.24 1.25 1.26 V

Reference Temperature Coefficient ±10 ppm/°C

Output Impedance 0.5 kΩ

Capacitive Load Driving 10 µF

Short Circuit Current VCC = 5.5V, REF Shorted to GND 2.5 mA

SYMBOL PARAMETER CONDITIONS

LTC2633-8 LTC2633-10 LTC2633-12 LTC2633A-12

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX

GETC Gain Temperature

Coefficient

VCC = 3V, Internal Ref. (Note 10)

C-Grade

H-Grade

ppm/°C

Load Regulation Internal Ref., Mid-Scale,

VCC = 3V ± 10%,

–5mA ≤ IOUT ≤ 5mA

VCC = 5V ± 10%,

–10mA ≤ IOUT ≤ 10mA

0.009

0.016

0.035

0.064

0.14

0.256

0.14

0.256

LSB/mA

ROUT DC Output

Impedance

Internal Ref., Mid-Scale,

VCC = 3V ± 10%,

–5mA ≤ IOUT ≤ 5mA

VCC = 5V ± 10%,

–10mA ≤ IOUT ≤ 10mA

0.09

0.156

0.09

0.156

0.09

0.156

0.09

0.156

electrical characteristics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.

LTC2633-LI12/-LI10/-LI8/-LX12/-LX10/-LX8/-LZ12/-LZ10/-LZ8/-LO12/-LO10/-LO8/LTC2633A-LI12/-LX12/-LZ12/-LO12 (VFS = 2.5V)

LTC2633

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electrical characteristics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.

LTC2633-LI12/-LI10/-LI8/-LX12/-LX10/-LX8/-LZ12/-LZ10/-LZ8/-LO12/-LO10/-LO8/LTC2633A-LI12/-LX12/-LZ12/-LO12 (VFS = 2.5V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Digital I/O

VIL Low Level Input Voltage

(SDA and SCL)

(Note 14) l–0.5 0.3VCC V

VIH High Level Input Voltage

(SDA and SCL)

(Note 11) l0.7VCC V

VIL(CA0) Low Level Input Voltage on CA0 See Test Circuit 1 l0.15VCC V

VIH(CA0) High Level Input Voltage on CA0 See Test Circuit 1 l0.85VCC V

RINH Resistance from CA0

to VCC to Set CA0 = VCC

See Test Circuit 2 l10 kΩ

RINL Resistance from CA0

to GND to Set CA0 = GND

See Test Circuit 2 l10 kΩ

RINF Resistance from CA0 to VCC or GND to

Set CA0 = Float

See Test Circuit 2 l2 MΩ

VOL Low Level Output Voltage Sink Current = 3mA l0 0.4 V

tOF Output Fall Time VO = VIH(MIN) to VO = VIL(MAX),

CB = 10pF to 400pF (Note 12)

l20 + 0.1CB250 ns

tSP Pulse Width of Spikes Suppressed by

Input Filter

l0 50 ns

IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC l1 µA

CIN I/O Pin Capacitance (Note 8) l8 pF

CBCapacitive Load for Each Bus Line l400 pF

CCA0 External Capacitive Load on Address Pin

CA0

l10 pF

AC Performance

tsSettling Time VCC = 3V (Note 9)

±0.39% (±1LSB at 8 Bits)

±0.098% (±1LSB at 10 Bits)

±0.024% (±1LSB at 12 Bits)

3.4

4.0

4.5

µs

Voltage Output Slew Rate 1.0 V/µs

Capacitive Load Driving 500 pF

Glitch Impulse At Mid-Scale Transition 2.8 nV•s

DAC-to-DAC Crosstalk 1 DAC Held at FS, 1 DAC Switch 0-FS 5.2 nV•s

Multiplying Bandwidth External Reference 320 kHz

enOutput Voltage Noise Density At f = 1kHz, External Reference

At f = 10kHz, External Reference

At f = 1kHz, Internal Reference

At f = 10kHz, Internal Reference

180

160

200

180

nV/√Hz

Output Voltage Noise 0.1Hz to 10Hz, External Reference

0.1Hz to 10Hz, Internal Reference

0.1Hz to 200kHz, External Reference

0.1Hz to 200kHz, Internal Reference

CREF = 0.1µF

680

730

µVP-P

LTC2633

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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fSCL SCL Clock Frequency l0 400 kHz

tHD(STA) Hold Time (Repeated) Start Condition l0.6 µs

tLOW Low Period of the SCL Clock Pin l1.3 µs

tHIGH High Period of the SCL Clock Pin l0.6 µs

tSU(STA) Set-Up Time for a Repeated Start Condition l0.6 µs

tHD(DAT) Data Hold Time l0 0.9 µs

tSU(DAT) Data Set-Up Time l100 ns

trRise Time of Both SDA and SCL Signals (Note 12) l20 + 0.1CB300 ns

tfFall Time of Both SDA and SCL Signals (Note 12) l20 + 0.1CB300 ns

tSU(STO) Set-Up Time for Stop Condition l0.6 µs

tBUF Bus Free Time Between a Stop and Start

Condition

l1.3 µs

timing characteristics

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V. (See Figure 1) (Note 13)

LTC2633-LI12/-LI10/-LI8/-LX12/-LX10/-LX8/-LZ12/-LZ10/-LZ8/-LO12/-LO10/-LO8/LTC2633A-LI12/-LX12/-LZ12/-LO12 (VFS = 2.5V)

electrical characteristics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.

SYMBOL PARAMETER CONDITIONS

LTC2633-8 LTC2633-10 LTC2633-12 LTC2633A-12

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX

DC Performance

Resolution l810 12 12 Bits

Monotonicity VCC = 5V, Internal Ref. (Note 4) l810 12 12 Bits

DNL Differential

Nonlinearity

VCC = 5V, Internal Ref. (Note 4) l±0.5 ±0.5 ±1 ±1 LSB

INL Integral Nonlinearity VCC = 5V, Internal Ref. (Note 4) l±0.05 ±0.5 ±0.2 ±1 ±1 ±2.5 ±0.5 ±1 LSB

ZSE Zero Scale Error VCC = 5V, Internal Ref., Code = 0 l0.5 50.5 50.5 50.5 5 mV

VOS Offset Error VCC = 5V, Internal Ref. (Note 5) l±0.5 ±5 ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV

VOSTC VOS Temperature

Coefficient

VCC = 5V, Internal Ref. ±10 ±10 ±10 ±10 µV/°C

GE Gain Error VCC = 5V, Internal Ref. l±0.2 ±0.8 ±0.2 ±0.8 ±0.2 ±0.8 ±0.2 ±0.8 %FSR

GETC Gain Temperature

Coefficient

VCC = 5V, Internal Ref. (Note 10)

C-Grade

H-Grade

ppm/°C

Load Regulation VCC = 5V ± 10%, Internal Ref.

Mid-Scale, –10mA ≤ IOUT ≤ 10mA

l0.006 0.01 0.022 0.04 0.09 0.16 0.09 0.16 LSB/mA

ROUT DC Output

Impedance

VCC = 5V ± 10%, Internal Ref.

Mid-Scale, –10mA ≤ IOUT ≤ 10mA

l0.09 0.156 0.09 0.156 0.09 0.156 0.09 0.156 Ω

LTC2633-HI12/-HI10/-HI8/-HZ12/-HZ10/-HZ8/LTC2633A-HI12/-HZ12 (VFS = 4.096V)

LTC2633

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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOUT DAC Output Span External Reference

Internal Reference

0 to VREF

0 to 4.096

PSR Power Supply Rejection VCC = 5V ± 10% –80 dB

ISC Short Circuit Output Current (Note 6)

Sinking

Sourcing

VFS = VCC = 5.5V

Zero Scale; VOUT shorted to VCC

Full Scale; VOUT shorted to GND

–28

–48

Power Supply

VCC Positive Supply Voltage For Specified Performance l4.5 5.5 V

ICC Supply Current (Note 7) VCC = 5V, VREF =4.096V, External Reference

VCC = 5V, Internal Reference

0.4

0.5

0.6

0.7

ISD Supply Current in Power-Down Mode

(Note 7)

VCC = 5V l0.5 2 µA

Reference Input

Input Voltage Range l1 VCC V

Resistance l120 160 200 kΩ

Capacitance 12 pF

IREF Reference Current, Power Down Mode DAC Powered Down l0.005 5 µA

Reference Output

Output Voltage l2.032 2.048 2.064 V

Reference Temperature Coefficient ±10 ppm/°C

Output Impedance 0.5 kΩ

Capacitive Load Driving 10 µF

Short Circuit Current VCC = 5.5V, REF Shorted to GND 4 mA

Digital I/O

VIL Low Level Input Voltage

(SDA and SCL)

(Note 14) l–0.5 0.3VCC V

VIH High Level Input Voltage

(SDA and SCL)

(Note 11) l0.7VCC V

VIL(CA0) Low Level Input Voltage on CA0 See Test Circuit 1 l0.15VCC V

VIH(CA0) High Level Input Voltage on CA0 See Test Circuit 1 l0.85VCC V

RINH Resistance from CA0

to VCC to Set CA0 = VCC

See Test Circuit 2 l10 kΩ

RINL Resistance from CA0

to GND to Set CA0 = GND

See Test Circuit 2 l10 kΩ

RINF Resistance from CA0 to VCC or GND to

Set CA0 = Float

See Test Circuit 2 l2 MΩ

VOL Low Level Output Voltage Sink Current = 3mA l0 0.4 V

tOF Output Fall Time VO = VIH(MIN) to VO = VIL(MAX),

CB = 10pF to 400pF (Note 12)

l20 + 0.1CB250 ns

tSP Pulse Width of Spikes Suppressed by

Input Filter

l0 50 ns

IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC l1 µA

electrical characteristics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.

LTC2633-HI12/-HI10/-HI8/-HZ12/-HZ10/-HZ8/LTC2633A-HI12/-HZ12 (VFS = 4.096V)

LTC2633

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electrical characteristics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.

LTC2633-HI12/-HI10/-HI8/-HZ12/-HZ10/-HZ8/LTC2633A-HI12/-HZ12 (VFS = 4.096V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

CIN I/O Pin Capacitance (Note 8) l8 pF

CBCapacitive Load for Each Bus Line l400 pF

CCA0 External Capacitive Load on Address Pin

CA0

l10 pF

AC Performance

tsSettling Time VCC = 5V (Note 9)

±0.39% (±1LSB at 8 Bits)

±0.098% (±1LSB at 10 Bits)

±0.024% (±1LSB at 12 Bits)

3.7

4.0

4.7

µs

Voltage Output Slew Rate 1.0 V/µs

Capacitive Load Driving 500 pF

Glitch Impulse At Mid-Scale Transition 3.0 nV•s

DAC-to-DAC Crosstalk 1 DAC Held at FS, 1 DAC Switch 0-FS 6.7 nV•s

Multiplying Bandwidth External Reference 320 kHz

enOutput Voltage Noise Density At f = 1kHz, External Reference

At f = 10kHz, External Reference

At f = 1kHz, Internal Reference

At f = 10kHz, Internal Reference

180

160

250

230

nV/√Hz

Output Voltage Noise 0.1Hz to 10Hz, External Reference

0.1Hz to 10Hz, Internal Reference

0.1Hz to 200kHz, External Reference

0.1Hz to 200kHz, Internal Reference

CREF = 0.1µF

680

750

µVP-P

LTC2633

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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fSCL SCL Clock Frequency l0 400 kHz

tHD(STA) Hold Time (Repeated) Start Condition l0.6 µs

tLOW Low Period of the SCL Clock Pin l1.3 µs

tHIGH High Period of the SCL Clock Pin l0.6 µs

tSU(STA) Set-Up Time for a Repeated Start Condition l0.6 µs

tHD(DAT) Data Hold Time l0 0.9 µs

tSU(DAT) Data Set-Up Time l100 ns

trRise Time of Both SDA and SCL Signals (Note 12) l20 + 0.1CB300 ns

tfFall Time of Both SDA and SCL Signals (Note 12) l20 + 0.1CB300 ns

tSU(STO) Set-Up Time for Stop Condition l0.6 µs

tBUF Bus Free Time Between a Stop and Start

Condition

l1.3 µs

timing characteristics

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V. (See Figure 1) (Note 13)

LTC2633-HI12/-HI10/-HI8/-HZ12/-HZ10/-HZ8/LTC2633A-HI12/-HZ12 (VFS = 4.096V)

Note 1. Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2. All voltages are with respect to GND

Note 3. High temperatures degrade operating lifetimes. Operating lifetime

is derated at temperatures greater than 105°C.

Note 4. Linearity and monotonicity are defined from code kL to code

2N–1, where N is the resolution and kL is given by kL = 0.016 • (2N/ VFS),

rounded to the nearest whole code. For VFS = 2.5V and N = 12, kL = 26 and

linearity is defined from code 26 to code 4,095. For VFS = 4.096V and

N = 12, kL = 16 and linearity is defined from code 16 to code 4,095.

Note 5. Inferred from measurement at code 16 (LTC2633-12), code 4

(LTC2633-10) or code 1 (LTC2633-8), and at full scale.

Note 6. This IC includes current limiting that is intended to protect the

device during momentary overload conditions. Junction temperature can

exceed the rated maximum during current limiting. Continuous operation

above the specified maximum operating junction temperature may impair

device reliability.

Note 7. Digital inputs at 0V or VCC.

Note 8. Guaranteed by design and not production tested.

Note 9. Internal reference mode. DAC is stepped 1/4 scale to 3/4 scale and

3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 100pF to GND.

Note 10. Temperature coefficient is calculated by dividing the maximum

change in output voltage by the specified temperature range.

Note 11. Maximum VIH = VCC(MAX) + 0.5V

Note 12. CB = capacitance of one bus line in pF

Note 13. All values refer to VIH = VIH(MIN) and VIL = VIL(MAX) levels.

Note 14. Minimum VIL exceeds the absolute maximum rating. This

condition won’t damage the IC, but could degrade performance.

LTC2633

2633fb

typical perFormance characteristics

INL vs Temperature

DNL vs Temperature

Reference Output Voltage vs

Temperature

Settling to ±1LSB Rising Settling to ±1LSB Falling

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

CODE

INL (LSB)

1.0

0.5

–0.5

–1.0 1024 3072

2633 G01

40952048

VCC = 3V

CODE

DNL (LSB)

1.0

0.5

–0.5

–1.0 1024 3072

2633 G02

40952048

VCC = 3V

TEMPERATURE (°C)

–50

INL (LSB)

1.0

0.5

–0.5

–1.0 –25 125100755025

2633 G03

1500

VCC = 3V

INL (POS)

INL (NEG)

TEMPERATURE (°C)

–50

DNL (LSB)

1.0

0.5

–0.5

–1.0 –25 125100755025

2633 G04

1500

VCC = 3V

DNL (POS)

DNL (NEG)

TEMPERATURE (°C)

–50

VREF (V)

1.260

1.255

1.250

1.245

1.240 –25 125100755025

2633 G05

1500

VCC = 3V

TA = 25°C unless otherwise noted.

LTC2633-L12 (Internal Reference, VFS = 2.5V)

SCL

5V/DIV

VOUT

1LSB/DIV

2µs/DIV

2633 G06

9TH CLOCK OF

3RD DATA BYTE

1/4 SCALE TO 3/4 SCALE STEP

VCC = 3V, VFS = 2.5V

RL = 2k, CL = 100pF

AVERAGE OF 256 EVENTS

3.6µs

SCL

5V/DIV

VOUT

1LSB/DIV

2µs/DIV

2633 G07

9TH CLOCK OF

3RD DATA BYTE

3/4 SCALE TO 1/4 SCALE STEP

VCC = 3V, VFS = 2.5V

RL = 2k, CL = 100pF

AVERAGE OF 256 EVENTS

4.5µs

LTC2633

2633fb

typical perFormance characteristics

INL vs Temperature

DNL vs Temperature

Reference Output Voltage vs

Temperature

Settling to ±1LSB Rising Settling to ±1LSB Falling

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

CODE

INL (LSB)

1.0

0.5

–0.5

–1.0 1024 3072

2633 G08

40952048

VCC = 5V

CODE

DNL (LSB)

1.0

0.5

–0.5

–1.0 1024 3072

2633 G09

40952048

VCC = 5V

TEMPERATURE (°C)

–50

INL (LSB)

1.0

0.5

–0.5

–1.0 –25 125100755025

2633 G10

1500

VCC = 5V

INL (POS)

INL (NEG)

TEMPERATURE (°C)

–50

DNL (LSB)

1.0

0.5

–0.5

–1.0 –25 125100755025

2633 G11

1500

VCC = 5V

DNL (POS)

DNL (NEG)

TEMPERATURE (°C)

–50

VREF (V)

2.068

2.058

2.048

2.038

2.028 –25 125100755025

2633 G12

1500

VCC = 5V

TA = 25°C unless otherwise noted.

LTC2633-H12 (Internal Reference, VFS = 4.096V)

SCL

5V/DIV

VOUT

1LSB/DIV

2µs/DIV

2633 G13

9TH CLOCK OF

3RD DATA BYTE

1/4 SCALE TO 3/4 SCALE STEP

VCC = 5V, VFS = 4.095V

RL = 2k, CL = 100pF

AVERAGE OF 256 EVENTS

3.8µs

SCL

5V/DIV

VOUT

1LSB/DIV

2µs/DIV

2633 G14

9TH CLOCK OF

3RD DATA BYTE

3/4 SCALE TO 1/4 SCALE

STEP

VCC = 5V, VFS = 4.095V

RL = 2k, CL = 100pF

AVERAGE OF 256 EVENTS

4.7µs

LTC2633

2633fb

typical perFormance characteristics

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

Load Regulation Current Limiting Offset Error vs Temperature

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

CODE

INL (LSB)

1.0

0.5

–0.5

–1.0 256 768

2633 G15

1023512

VCC = 3V

VFS = 2.5V

INTERNAL REF

CODE

DNL (LSB)

1.0

0.5

–0.5

–1.0 256 768

2633 G16

1023512

VCC = 3V

VFS = 2.5V

INTERNAL REF

CODE

INL (LSB)

0.50

0.25

–0.25

–0.50 64 192

2633 G17

255128

VCC = 3V

VFS = 2.5V

INTERNAL REF

CODE

DNL (LSB)

0.50

0.25

–0.25

–0.50 64 192

2633 G18

255128

VCC = 3V

VFS = 2.5V

INTERNAL REF

IOUT (mA)

–30

∆VOUT (mV)

–4

–2

–8

–6

–10 –20 –10 20

2633 G19

30100

INTERNAL REFERENCE

CODE = MID-SCALE

VCC = 5V (LTC2633-H)

VCC = 5V (LTC2633-L)

VCC = 3V (LTC2633-L)

IOUT (mA)

–30

∆VOUT (V)

0.20

0.15

0.05

0.10

–0.05

–0.15

–0.10

–0.20 –20 –10 20

2633 G20

30100

INTERNAL REFERENCE

CODE = MID-SCALE

VCC = 5V (LTC2633-H)

VCC = 5V (LTC2633-L)

VCC = 3V (LTC2633-L)

TEMPERATURE (°C)

–50

OFFSET ERROR (mV)

–1

–2

–3 –25 125100755025

2633 G21

1500

TA = 25°C unless otherwise noted.

LTC2633-10

LTC2633-8

LTC2633

2633fb

typical perFormance characteristics

Headroom at Rails vs Output

Current Exiting Power-Down to Mid-Scale Power-On Reset to Mid-Scale

Supply Current vs Logic Voltage

Exiting Power-Down for Hi-Z

Option

Large-Signal Response Mid-Scale-Glitch Impulse Power-On Reset Glitch

2µs/DIV

VOUT

0.5V/DIV

2633 G22

VFS = VCC = 5V

1/4 SCALE to 3/4 SCALE

200µs/DIV

VOUT

10mV/DIV

VCC

2V/DIV

2633 G24

LTC2633-L

ZERO-SCALE

IOUT (mA)

VOUT (V)

5.0

4.0

3.0

4.5

3.5

2.5

1.5

2.0

0.5

1.0

021 3 8

2633 G25

106 974 5

5V SOURCING

5V SINKING

3V (LTC2633-L) SOURCING

3V (LTC2633-L) SINKING

TA = 25°C unless otherwise noted.

LTC2633

1.0

0.8

0.6

0.4

1.2

0.2 1 2 3

LOGIC VOLTAGE (V)

4 50

ICC (mA)

2633 G28

VCC = 3V

(LTC2633-L)

SWEEP SDA, SCL

BETWEEN

ON AND VCC

VCC = 5V SCL

5V/DIV

VOUT

500mV/DIV

5µs/DIV

2633 G29

9TH CLOCK OF

3RD DATA BYTE

LTC2633-LO, VCC = 3V

DAC OUTPUT DRIVEN

BY 1V SOURCE

THROUGH 15k

RESISTOR

HIGH-IMPEDANCE

(POWER-DOWN) MODE

DAC OUTPUT SET

TO MID-SCALE

SCL

5V/DIV

VOUTA

0.5V/DIV

5µs/DIV

2633 G26

9TH CLOCK OF

3RD DATA BYTE

LTC2633-H

VCC = 5V

INTERNAL REF.

DAC B IN

POWER-DOWN

MODE

200µs/DIV

VCC

2V/DIV

VOUT

0.5V/DIV

2633 G27

LTC2633-H

LTC2633-L

SCL

5V/DIV

VOUT

2mV/DIV

2µs/DIV

2633 G23

9TH CLOCK OF

3RD DATA BYTE

LTC2633-H12, VCC = 5V

3nV•s TYPICAL

LTC2633-L12, VCC = 3V

2.8nV•s TYPICAL

LTC2633

2633fb

typical perFormance characteristics

Gain Error vs Reference Input

0.1Hz to 10Hz Voltage Noise DAC to DAC Crosstalk (Dynamic) Gain Error vs Temperature

Multiplying Bandwidth Noise Voltage vs Frequency

FREQUENCY (Hz)

–2

–6

–4

–8

–12

–10

–16

–14

–18 100k

2633 G31

1M10k

VCC = 5V

VREF(DC) = 2V

VREF(AC) = 0.2VP-P

CODE = FULL-SCALE

TEMPERATURE (°C)

–50

GAIN ERROR (%FSR)

1.0

0.5

–0.5

–1.0 –25 125100755025

2633 G36

1500

1s/DIV

10µV/DIV

2632 G34

VCC = 5V, VFS = 2.5V

CODE = MID-SCALE

INTERNAL REFERENCE

TA = 25°C unless otherwise noted.

LTC2633

REFERENCE VOLTAGE (V)

1 2.52

GAIN ERROR (%FSR)

0.8

0.4

0.6

0.2

–0.4

–0.6

–0.2

–0.8 4.5

2633 G33

5.53.51.5 4 53

VCC = 5.5V

GAIN ERROR OF 2 CHANNELS

pin Functions

SCL (Pin 1): Serial Clock Input Pin. Data is shifted into the

SDA pin at the rising edges of the clock. This high impedance

pin requires a pull-up resistor or current source to VCC.

CA0 (Pin 2): Chip Address Bit 0. Tie this pin to VCC, GND

or leave it floating to select an I2C slave address for the

part (see Table 1).

REF (Pin 3): Reference Voltage Input or Output. When

external reference mode is selected, REF is an input (1V ≤

VREF ≤ VCC) where the voltage supplied sets the full-scale

DAC output voltage. When internal reference is selected,

the 10ppm/°C 1.25V (LTC2633-L) or 2.048V (LTC2633-H)

internal reference (half full-scale) is available at the pin.

This output may be bypassed to GND with up to 10µF

(0.1µF is recommended) and must be buffered when

driving external DC load current.

GND (Pin 4): Ground.

VOUTA, VOUTB (Pins 5,6): DAC Analog Voltage Output.

VCC (Pin 7): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V

(LTC2633-L) or 4.5V ≤ VCC ≤ 5.5V (LTC2633-H). Bypass

to GND with a 0.1µF capacitor.

SDA (Pin 8): Serial Data Bidirectional Pin. Data is shifted

into the SDA pin and acknowledged by the SDA pin. This

pin is high impedance while data is shifted in. Open drain

N-channel output during acknowledgement. SDA requires

a pull-up resistor or current source to VCC.

FREQUENCY (Hz)

100 1k

NOISE VOLTAGE (nV/√Hz)

500

300

400

100

200

0100k

2633 G32

1M10k

VCC = 5V

CODE = MID-SCALE

INTERNAL REFERENCE

LTC2633-H

LTC2633-L

SCL

5V/DIV

VOUT

2mV/DIV

1 DAC

SWITCH 0-FS

2V/DIV

2µs/DIV

2633 G35

9TH CLOCK OF

3RD DATA BYTE

LTC2633-H12, VCC = 5V

6.7nV•s TYP

LTC2633

2633fb

Block Diagram

test circuit

Test circuits for I2C digital I/O (see Electrical Characteristics)

Test Circuit 1 Test Circuit 2

timing Diagram

Figure 1. I2C Timing

Figure 2. Typical LTC2633 Write Transaction

2633 BD

I2C INTERFACE

I2C

ADDRESS

DECODE

POWER-ON

RESET

CONTROL

DECODE LOGIC

DAC B

DAC A VOUTB

REF

SCL

SDACA0

VOUTA

VCC

GND

INTERNAL

REFERENCE SWITCH

VREF

2633 TC01

CA0

VIH(CA0)/VIL(CA0)

100Ω

2633 TC02

CA0

GND

RINH/RINL/RINF

VDD

SCL

SDA

2633 F01

tLOW

tHD(STA) tHD(DAT)

S S P S

tSU(STA) tSU(STO)

tBUF

tSU(DAT) tHD(STA) tSP

tHIGH

ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS

123456789123456789123456789123456789

SDA A6 A5 A4 A3 A2 A1 A0 C3 C2 C1 C0 A3 A2 A1 A0WACK ACK ACK ACKXXXX

START

SLAVE ADDRESS 1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE

2633 F02

SCL

LTC2633

2633fb

operation

The LTC2633 is a family of dual voltage output DACs in an

8-lead TSOT package. Each DAC can operate rail-to-rail

using an external reference, or with its full-scale voltage

set by an integrated reference. Eighteen combinations of

accuracy (12-, 10-, and 8-bit), power-on reset value (zero-

scale, mid-scale in internal reference mode, or mid-scale

in external reference mode), DAC power-down output load

(high impedance or 200kΩ), and full-scale voltage (2.5V

or 4.096V) are available. The LTC2633 is controlled using

a 2-wire I2C interface.

Power-On Reset

The LTC2633-HZ/LTC2633-LZ clear the output to zero-scale

when power is first applied, making system initialization

consistent and repeatable.

For some applications, downstream circuits are active dur-

ing DAC power-up, and may be sensitive to nonzero outputs

from the DAC during this time. The LTC2633 contains

circuitry to reduce the power-on glitch: the analog output

typically rises less than 10mV above zero scale during

power-on. In general, the glitch amplitude decreases as the

power supply ramp time is increased. See power-on reset

glitch in the Typical Performance Characteristics section.

The LTC2633-HI/LTC2633-LI/LTC2633-LX provide an

alternative reset, setting the output to mid-scale when

power is first applied. The LTC2633-LI/ and LTC2633-HI

power up in internal reference mode, with the output set

to a mid-scale voltage of 1.25V and 2.048V respectively.

The LTC2633-LX power-up in external reference mode, with

the output set to mid-scale of the external reference. The

LTC2633-LO powers up in internal reference mode with

all the DAC channels placed in the high impedance state

(powered down). Input and DAC registers are set to the

mid-scale code, and only the internal reference is powered

up, causing supply current to be typically 180µA upon

power up. Default reference mode selection is described

in the Reference Modes section.

Power Supply Sequencing

The voltage at REF (Pin 3) must be kept within the range

–0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Rat-

ings). Particular care should be taken to observe these

limits during power supply turn-on and turn-off sequences,

when the voltage at VCC is in transition.

Transfer Function

The digital-to-analog transfer function is:

VOUT(IDEAL) =k

2NVREF

where k is the decimal equivalent of the binary DAC input

code, N is the resolution, and VREF is either 2.5V (LTC2633-LI/

LTC2633-LX/LTC2633-LO/LTC2633-LZ) or 4.096V

(LTC2633-HI/LTC2633-HZ) when in internal reference

mode, and the voltage at REF when in external reference

mode.

I2C Serial Interface

The LTC2633 communicates with a host using the stan-

dard 2-wire I2C interface. The Timing Diagram (Figures

1 and 2) show the timing relationship of the signals on

the bus. The two bus lines, SDA and SCL, must be high

when the bus is not in use. External pull-up resistors or

current sources are required on these lines. The value of

these pull-up resistors is dependent on the power supply

and can be obtained from the I2C specifications. For an

I2C bus operating in the fast mode, an active pull-up will

be necessary if the bus capacitance is greater than 200pF.

The LTC2633 is a receive-only (slave) device. The master

can write to the LTC2633. The LTC2633 will not acknowl-

edge (NAK) a read request from the master.

LTC2633

2633fb

operation

START (S) and STOP (P) Conditions

When the bus is not in use, both SCL and SDA must be

high. A bus master signals the beginning of a communica-

tion to a slave device by transmitting a START condition. A

START condition is generated by transitioning SDA from

high to low while SCL is high.

When the master has finished communicating with the

slave, it issues a STOP condition. A STOP condition is

generated by transitioning SDA from low to high while

SCL is high. The bus is then free for communication with

another I2C device.

Acknowledge

The acknowledge (ACK) signal is used for handshaking

between the master and the slave. An ACK generated by the

slave lets the master know that the latest byte of informa-

tion was properly received. The ACK related clock pulse is

generated by the master. The master releases the SDA line

(HIGH) during the ACK clock pulse. The slave-receiver must

pull down the SDA bus line during the ACK clock pulse

so that it remains a stable LOW during the HIGH period

of this clock pulse. The LTC2633 responds to a write by a

master in this manner but does not acknowledge a read

operation; in that case, SDA is retained HIGH during the

period of the ACK clock pulse.

Chip Address

The state of pin CA0 determines the slave address of the

part. This pin can be set to any one of three states: VCC, GND

or float. This results in 3 selectable addresses for the part.

The slave address assignments is shown in Table 1.

Table 1. Slave Address Map

CA0 A6 A5 A4 A3 A2 A1 A0

GND 0 0 1 0 0 0 0

FLOAT 0 0 1 0 0 0 1

VCC 0 0 1 0 0 1 0

GLOBAL ADDR 1 1 1 0 0 1 1

In addition to the address selected by the address pin,

the part also responds to a global address. This address

allows a common write to all LTC2633 parts to be ac-

complished using one 3-byte write transaction on the I2C

bus. The global address, listed at the end of Tables 1, is a

7-bit hardwired address not selectable by CA0. If another

address is required, please consult the factory.

The maximum capacitive load allowed on the address pin

(CA0) is 10pF, as these pins are driven during address

detection to determine if they are floating.

Write Word Protocol

The master initiates communication with the LTC2633

with a START condition and a 7-bit slave address followed

by the write bit (W) = 0. The LTC2633 acknowledges by

pulling the SDA pin low at the 9th clock if the 7-bit slave

address matches the address of the part (set by CA0) or

the global address. The master then transmits three bytes

of data. The LTC2633 acknowledges each byte of data

by pulling the SDA line low at the 9th clock of each data

byte transmission. After receiving three complete bytes

of data, the LTC2633 executes the command specified in

the 24-bit input word.

If more than three data bytes are transmitted after a valid

7-bit slave address, the LTC2633 does not acknowledge the

extra bytes of data (SDA is high during the 9th clock).

LTC2633

2633fb

The format of the three data bytes is shown in Figure

3. The first byte of the input word consists of the 4-bit

command, followed by the 4-bit DAC address. The next

two bytes contain the 16-bit data word, which consists

of the 12-, 10- or 8-bit input code, MSB to LSB, followed

by 4, 6 or 8 don’t-care bits (LTC2633-12, LTC2633-10

and LTC2633-8 respectively). A typical LTC2633 write

transaction is shown in Figure 4.

The command bit assignments (C3-C0) and address (A3-

A0) assignments are shown in Tables 3 and 4. The first

four commands in the table consist of write and update

operations. A write operation loads a 16-bit data word

from the 32-bit shift register into the input register. In an

update operation, the data word is copied from the input

8-bit input code, and is converted to an analog voltage at

the DAC output. Write to and update combines the first

two commands. The update operation also powers up the

DAC if it had been in power-down mode. The data path

and registers are shown in the Block Diagram.

D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X XD11A0A1A2A3C0C1C2C3

2ND DATA BYTE1ST DATA BYTE

INPUT WORD (LTC2633-12)

WRITE WORD PROTOCOL LTC2633

3RD DATA BYTE

2633 F03

A A A PAWS

INPUT WORD

SLAVE ADDRESS 1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE

D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X XD9A0A1A2A3C0C1C2C3

2ND DATA BYTE1ST DATA BYTE

INPUT WORD (LTC2633-10)

3RD DATA BYTE

D6 D5 D4 D3 D2 D1 D0 X X X X X X XD7A0A1A2A3C0C1C2C3

2ND DATA BYTE1ST DATA BYTE

INPUT WORD (LTC2633-8)

3RD DATA BYTE

operation

Figure 3. Command and Data Input Format

Table 3. Command Codes

COMMAND*

C3 C2 C1 C0

0 0 0 0 Write to Input Register n

0 0 0 1 Update (Power-Up) DAC Register n

0 0 1 0 Write to Input Register n, Update (Power-Up) All

0 0 1 1 Write to and Update (Power-Up) DAC Register n

0 1 0 0 Power-Down n

0 1 0 1 Power-Down Chip (All DAC’s and Reference)

0 1 1 0 Select Internal Reference (Power-Up Reference)

0 1 1 1 Select External Reference (Power-Down Internal

Reference)

1 1 1 1 No Operation

*Command codes not shown are reserved and should not be used.

Table 4. Address Codes

ADDRESS (n)*

A3 A2 A1 A0

0 0 0 0 DAC A

0 0 0 1 DAC B

1 1 1 1 All DACs

* Address codes not shown are reserved and should not be used.

LTC2633

2633fb

123456789123456789123456789123456789

SDA A6 A5 A4 A3 A2 A1 A0

A6 A5 A4 A3 A2 A1 A0 WR

C3 C2 C1 C0 A3 A2 A1 A0

C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

ACK ACK ACK ACK

STOP

FULL-SCALE

VOLTAGE

ZERO-SCALE

VOLTAGE

START

SLAVE ADDRESS

SCL

2633 F04

VOUT

X = DON’T CARE

COMMAND MS DATA LS DATA

operation

Figure 4. Typical LTC2633 Input Waveform—Programming DAC Output for Full Scale

LTC2633

2633fb

Reference Modes

For applications where an accurate external reference is

either not available, or not desirable due to limited space,

the LTC2633 has a user-selectable, integrated reference.

The integrated reference voltage is internally amplified

by 2x to provide the full-scale DAC output voltage range.

The LTC2633-LI/LTC2633-LX/LTC2633-LO/LTC2633-LZ

provides a full-scale output of 2.5V. The LTC2633-HI/

LTC2633-HZ provides a full-scale output of 4.096V. The

internal reference can be useful in applications where

the supply voltage is poorly regulated. Internal reference

mode can be selected by using command 0110b, and is

the power-on default for LTC2633-HZ/LTC2633-LZ, as well

as for LTC2633-HI/LTC2633-LI/LTC2633-LO.

The 10ppm/°C, 1.25V (LTC2633-LI/LTC2633-LX/LTC2633-

LO/LTC2633-LZ) or 2.048V (LTC2633-HI/LTC2633-HZ)

internal reference is available at the REF pin. Adding

bypass capacitance to the REF pin will improve noise

performance; 0.1µF is recommended and up to 10µF can

be driven without oscillation. This output must be buffered

when driving an external DC load current.

Alternatively, the DAC can operate in external reference

mode using command 0111b. In this mode, an input voltage

supplied externally to the REF pin provides the reference

(1V ≤ VREF ≤ VCC) and the supply current is reduced. The

external reference voltage supplied sets the full-scale DAC

output voltage. External reference mode is the power-on

default for LTC2633-LX.

The reference mode of LTC2633-HZ/LTC2633-LZ/

LTC2633-HI/LTC2633-LI/LTC2633-LO (internal reference

power-on default), can be changed by software command

after power up. The same is true for LTC2633-LX (external

reference power-on default).

Power-Down Mode

For power-constrained applications, power-down mode can

be used to reduce the supply current whenever less than

two DAC outputs are needed. When in power-down, the

buffer amplifiers, bias circuits, and integrated reference

circuits are disabled, and draw essentially zero current.

The DAC outputs are put into a high impedance state, and

the output pins are passively pulled to ground through

individual 200kΩ resistors (LTC2633-LI/LTC2633-LX/

LTC2633-LO/LTC2633-LZ/LTC2633-HI/LTC2633-HZ). For

the LTC2633-LO options, the output pins are not passively

pulled to ground, but are also placed in a high impedance

state (open-circuited state) during power-down, typically

drawing less than 0.1µA. The LTC2633-LO options power-

up with all DAC outputs in this high impedance state. They

remain that way until given a software update command.

For all LTC2633 options, Input- and DAC-register contents

are not disturbed during power-down.

Any channel or combination of channels can be put into

power-down mode by using command 0100b in combi-

nation with the appropriate DAC address, (n). The supply

current is reduced approximately 30% for each DAC

powered down. The integrated reference is automatically

powered down when external reference is selected using

command 0111b. In addition, all the DAC channels and the

integrated reference together can be put into power-down

mode using Power Down Chip command 0101b. When

the integrated reference is in power-down mode, the REF

pin becomes high impedance (typically > 1GΩ). For all

power-down commands the 16-bit data word is ignored.

Normal operation resumes after executing any command

that includes a DAC update, (as shown in Table 1). The

selected DAC is powered up as its voltage output is up-

dated. When a DAC which is in a powered-down state is

powered up and updated, normal settling is delayed. If

less than two DACs are in a powered-down state prior to

the update command, the power-up delay time is 10µs.

However, if both DACs and the integrated reference are

powered down, then the main bias generation circuit block

has been automatically shut down in addition to the DAC

amplifiers and reference buffers. In this case, the power up

delay time is 12µs. The power-up of the integrated refer-

ence depends on the command that powered it down. If

the reference is powered down using the select external

reference command (0111b), then it can only be powered

back up using select internal reference command (0110b).

However, if the reference was powered down using power

down chip command (0101b), then in addition to select

operation

LTC2633

2633fb

Figure 5. Effects of Rail-to-Rail Operation on a DAC Transfer Curve (Shown for 12 Bits).

(a) Overall Transfer Function

(b) Effect of Negative Offset for Codes Near Zero

2633 F05

INPUT CODE

(b)

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

0V 2,0480 4,095

INPUT CODE

OUTPUT

VOLTAGE

(a)

VREF = VCC

(c)

INPUT CODE

OUTPUT

VOLTAGE

POSITIVE

FSE

operation

internal reference command (0110b), any command in

software that powers up the DACs will also power up the

integrated reference.

Voltage Output

The LTC2633’s integrated rail-to-rail amplifier has guaran-

teed load regulation when sourcing or sinking up to 10mA

at 5V, and 5mA at 3V.

Load regulation is a measure of the amplifier’s ability to

maintain the rated voltage accuracy over a wide range of

load current. The measured change in output voltage per

change in forced load current is expressed in LSB/mA.

DC output impedance is equivalent to load regulation, and

may be derived from it by simply calculating a change

in units from LSB/mA to Ω. The amplifier’s DC output

impedance is 0.1Ω when driving a load well away from

the rails.

When drawing a load current from either rail, the output

voltage headroom with respect to that rail is limited by

the 50Ω typical channel resistance of the output devices

(e.g., when sinking 1mA, the minimum output voltage is

50Ω • 1mA, or 50mV). See the graph Headroom at Rails

vs Output Current in the Typical Performance Character-

istics section.

The amplifier is stable driving capacitive loads of up to

500pF.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is limited

to voltages within the supply range.

Since the analog output of the DAC cannot go below ground,

it may limit for the lowest codes as shown in Figure 5b.

Similarly, limiting can occur near full scale when the REF

pin is tied to VCC. If VREF = VCC and the DAC full-scale error

(FSE) is positive, the output for the highest codes limits

at VCC, as shown in Figure 5c. No full-scale limiting can

occur if VREF is less than VCC–FSE.

Offset and linearity are defined and tested over the region

of the DAC transfer function where no output limiting can

occur.

LTC2633

2633fb

Board Layout

The PC board should have separate areas for the analog and

digital sections of the circuit. A single, solid ground plane

should be used, with analog and digital signals carefully

routed over separate areas of the plane. This keeps digital

signals away from sensitive analog signals and minimizes

the interaction between digital ground currents and the

analog section of the ground plane. The resistance from

the LTC2633 GND pin to the ground plane should be as

low as possible. Resistance here will add directly to the

effective DC output impedance of the device (typically

0.1Ω). Note that the LTC2633 is no more susceptible to

this effect than any other parts of this type; on the con-

trary, it allows layout-based performance improvements

to shine rather than limiting attainable performance with

excessive internal resistance.

Another technique for minimizing errors is to use a sepa-

rate power ground return trace on another board layer.

The trace should run between the point where the power

supply is connected to the board and the DAC ground pin.

Thus the DAC ground pin becomes the common point for

analog ground, digital ground, and power ground. When

the LTC2633 is sinking large currents, this current flows

out the ground pin and directly to the power ground trace

without affecting the analog ground plane voltage.

It is sometimes necessary to interrupt the ground plane

to confine digital ground currents to the digital portion of

the plane. When doing this, make the gap in the plane only

as long as it needs to be to serve its purpose and ensure

that no traces cross over the gap.

operation

package Description

1.50 – 1.75

(NOTE 4)

2.80 BSC

0.22 – 0.36

8 PLCS (NOTE 3)

DATUM ‘A’

0.09 – 0.20

(NOTE 3)

TS8 TSOT-23 0710 REV A

2.90 BSC

(NOTE 4)

0.65 BSC

1.95 BSC

0.80 – 0.90

1.00 MAX 0.01 – 0.10

0.20 BSC

0.30 – 0.50 REF

PIN ONE ID

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

3.85 MAX

0.40

MAX

0.65

REF

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

1.4 MIN

2.62 REF

1.22 REF

TS8 Package

8-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1637 Rev A)

LTC2633

2633fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision history

REV DATE DESCRIPTION PAGE NUMBER

A 3/11 Revised part numbering. 2 to 9, 13, 16,

20, 26

B 3/11 Revised title of Typical Application. 24

LTC2633

2633fb

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2011

LT 0311 REV B • PRINTED IN USA

relateD parts

typical application

Voltage Margining Application with LTC3850 (1.2V ±5%) LTC2633-LO Option Only

PART NUMBER DESCRIPTION COMMENTS

LTC2632 Dual 12-/10-/8-Bit, SPI VOUT DACs with

Internal Reference

2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail

Output, 8-Pin ThinSOT™ Package

LTC2607/LTC2617/

LTC2627

Dual 16-/14-/12-Bit, I2C VOUT DACs with

External Reference

260μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, 16-Lead SSOP Package

LTC2602/LTC2612/

LTC2622

Dual 16-/14-/12-Bit SPI VOUT DACs with

External Reference

300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, 8-Lead MSOP Package

LTC1662 Dual 10-Bit, SPI VOUT DAC with External

Reference

1.5μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, 8-Lead MSOP Package

LTC2630/LTC2631 Single 12-/10-/8-Bit, SPI/ I2C VOUT DACs

with 10ppm/°C Reference

180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, Rail-to-Rail Output,

in SC70 (LTC2630)/ ThinSOT (LTC2631)

LTC2640 Single 12-/10-/8-Bit, SPI VOUT DACs with

10ppm/°C Reference

180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode,

Rail-to-Rail Output, in ThinSOT

LTC2634/LTC2635 Quad 12-/10-/8-Bit SPI/I2C VOUT DACs with

10ppm/°C Reference

±2.5LSB INL, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode,

16-Pin 3mm × 3mm QFN and 10-Lead MSOP Packages

LTC2636/LTC2637 Octal 12-/10-/8-Bit, SPI/I2C VOUT DACs with

10ppm/°C Reference

125μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode,

Rail-to-Rail Output, 14-Lead 4mm × 3mm DFN and 16-Lead MSOP Packages

LTC2654/LTC2655 Quad 16-/12 Bit, SPI/I2C VOUT DACs with

10ppm/°C Max Reference

±4LSB INL Max at 16-Bits and ±2mV Offset Error, Rail-to-Rail Output,

20-Lead 4mm × 4mm QFN and 16-Lead Narrow SSOP Packages

LTC2656/LTC2657 Octal 16-/12 Bit, SPI/I2C VOUT DACs with

10ppm/°C Max Reference

±4LSB INL Max at 16-Bits and ±2mV Offset Error, Rail-to-Rail Output,

20-Lead 4mm × 5mm QFN and 16-Lead TSSOP Packages

SW1

BG1

PGND

ITH1 SENSE1+

MODE/PLLIN RUN1

SENSE1–

VFB1

500kHz

TKSS1

ILM

VIN INTVCC

PGOOD

TG1

0.1µF

1nF

0.1µF

2.2k 100k

10k

SGND

10k

0.008k2.2µH

LTC3850EUF

2633 TA02

FREQ

BOOST1

0.1µF

CMDSH-3

RJK0305DPB

RJK0301DPB

10nF

1nF 3.32k

10k

1nF

10k

100pF

4.7µF

VIN

6.5V

TO 14V

VOUT

1.2V ±5%

20k

15pF 63.4k

TO I2C

BUS

REF VCC

3 7

CA0

SCL GND

SDA

0.1µF

DAC B

DAC A

LTC2633CTS8-L012

0.22µF

10k 15k