ASAHI KASEI [AK4356]
M0072-E-02 2003/09
- 1 -
GENERAL DESCRIPTION
The AK4356 is a high performance six channels DAC corresponding to 96kHz sampling mode of DVD.
Two channels of them can operate up to 192kHz sampling fully correspond to DVD-Audio standards. The
AK4356 introduces the advanced multi-bit architecture for ∆Σ modulator. This new architecture achieves
the wider dynamic range, while keeping much the same superior distortion characteristics as
conventional Single Bit way. In the AK4356, the analog outputs are filtered in the analog domain by
switched-capacitor filter (SCF) with high tolerance to clock jitter. The analog outputs are full differential
output, so the device is suitable for hi-end applications.
FEATURES
o 128x Oversampling
o Sampling Rate up to 192kHz for 2 channels mode,
96kHz for 6 channels mode
o 24Bit 8 times Digital Filter with Slow roll-off option
Ripple: ±0.005dB, Attenuation: 75dB
o THD+N: -94dB
o DR, S/N: 112dB
o High Tolerance to Clock Jitter
o Low Distortion Differential Output
o Channel Independent Digital De-emphasis for 32, 44.1 & 48kHz sampling
o Channel Independent Zero Detect Pin
o Channel Independent Digital Attenuator with soft-transition
o Soft Mute
o 3-wire Serial Interface for Volume Control
o I/F format: MSB justified, LSB justified, I2S
o TTL Level Digital I/F
o Master Clock
Normal Speed: 256fs, 384fs, 512fs or 768fs
Double Speed: 128fs, 192fs, 256fs or 384fs
o Power Supply: 4.75 to 5.25V
o 44pin LQFP Package
o Ta: -40 to 85°C
192kHz 24Bit Six-Channel DAC for DVD-
Audio
AK4356
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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n Block Diagram
SCF
DAC
DATT
DZFL1
LOUT1+
LOUT1-
SCF
DAC
DATT
DZFR1
ROUT1+
ROUT1-
SCF
DAC
DATT
DZFL2
LOUT2+
LOUT2-
SCF
DAC
DATT
DZFR2
ROUT2+
ROUT2-
SCF
DAC
DATT
DZFL3
LOUT3+
LOUT3-
SCF
DAC
DATT
DZFR3
ROUT3+
ROUT3-
Audio
I/F
Control
Register
AK4356
MCLK
LRCK
BICK
MCKO
LRCK
BICK
XTI
XTO
Controller
CS
CCLK
CDTI
LRCK
BICK
AC3
SDTI1
SDTI2
SDTI3
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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n Ordering Guide
AK4356VQ -40∼+85°C 44pin LQFP(0.8mm pitch)
AKD4356 Evaluation Board
n Pin Layout
LOUT1-
ROUT1+
1
LOUT1+
44
2
DZFL2
3
DZFR1
4
DZFL1
5
CAD0
6
CAD1
7
PDN
8
BICK
9
MCLK
10
DVDD
11
ROUT1-
43
LOUT2+
42
LOUT2-
41
ROUT2+
40
ROUT2-
39
LOUT3+
38
LOUT3-
37
ROUT3+
36
ROUT3-
35
AVSS
34
DVSS
12
SDTI1
13
SDTI2
14
SDTI3
15
LRCK
16
SMUTE
17
CCLK
18
CDTI
19
CSN
20
DFS0
21
CKS0
22
33
32
31
30
29
28
27
26
25
24
23
AVDD
VREFH
DZFR2
DZFL3
DZFR3
DZFE
DIF2
DIF1
DIF0
CKS2
CKS1
AK4356VQ
Top View
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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PIN/FUNCTION
No. Pin Name I/O Function
1 LOUT1- O DAC1 Lch Negative Analog Output Pin
2 LOUT1+ O DAC1 Lch Positive Analog Output Pin
3 DZFL2 O DAC2 Lch Zero Input Detect Pin
4 DZFR1 O DAC1 Rch Zero Input Detect Pin
5 DZFL1 O DAC1 Lch Zero Input Detect Pin
6 CAD0 I Chip Address 0 Pin
7 CAD1 I Chip Address 1 Pin
8 PDN I Power-Down & Reset Pin
When “L”, the AK4356 is powered-down and the control registers are reset to
default state. If the state of CAD0-1 changes, then the AK4356 must be reset by PDN.
9 BICK I Audio Serial Data Clock Pin
10 MCLK I Master Clock Input Pin
11 DVDD - Digital Power Supply Pin, +4.75∼+5.25V
12 DVSS - Digital Ground Pin
13 SDTI1 I DAC1 Audio Serial Data Input Pin
14 SDTI2 I DAC2 Audio Serial Data Input Pin
15 SDTI3 I DAC3 Audio Serial Data Input Pin
16 LRCK I Audio Input Channel Clock Pin
17 SMUTE I Soft Mute Pin (Note)
When this pin goes to “H”, soft mute cycle is initialized.
When returning to “L”, the output mute releases.
18 CCLK I Control Data Clock Pin
19 CDTI I Control Data Input Pin
20 CSN I Chip Select Pin
This pin should be held to “H” except for access.
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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No. Pin Name I/O Function
21 DFS0 I Double Speed Sampling Mode 0 Pin (Note)
“L”: Normal Speed, “H”: Double Speed at DFS1 bit = “0”.
22 CKS0 I Input Clock Select 0 Pin (Note)
23 CKS1 I Input Clock Select 1 Pin (Note)
24 CKS2 I Input Clock Select 2 Pin (Note)
25 DIF0 I Audio Data Interface Format 0 Pin (Note)
26 DIF1 I Audio Data Interface Format 1 Pin (Note)
27 DIF2 I Audio Data Interface Format 2 Pin (Note)
28 DZFE I Zero Input Detect Enable Pin (Note)
29 DZFR3 O DAC3 Rch Zero Input Detect Pin
30 DZFL3 O DAC3 Lch Zero Input Detect Pin
31 DZFR2 O DAC2 Rch Zero Input Detect Pin
32 VREFH I Positive Voltage Reference Input Pin, AVDD
33 AVDD - Analog Power Supply Pin
34 AVSS - Analog Ground Pin, +4.75∼+5.25V
35 ROUT3- O DAC3 Rch Negative Analog Output Pin
36 ROUT3+ O DAC3 Rch Positive Analog Output Pin
37 LOUT3- O DAC3 Lch Negative Analog Output Pin
38 LOUT3+ O DAC3 Lch Positive Analog Output Pin
39 ROUT2- O DAC2 Rch Negative Analog Output Pin
40 ROUT2+ O DAC2 Rch Positive Analog Output Pin
41 LOUT2- O DAC2 Lch Negative Analog Output Pin
42 LOUT2+ O DAC2 Lch Positive Analog Output Pin
43 ROUT1- O DAC1 Rch Negative Analog Output Pin
44 ROUT1+ O DAC1 Rch Positive Analog Output Pin
Note: SMUTE, DFS0, CKS0, CKS1, CKS2, DIF0, DIF1, DIF2, DZFE pins are ORed with serial control register.
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 1)
Parameter Symbol min max Units
Power Supplies
Analog
Digital
|AVSS-DVSS| (Note 2)
AVDD
DVDD
∆GND
-0.3
-0.3
-
6.0
6.0
0.3
V
V
V
Input Current (any pins except for supplies) IIN - ±10 mA
Analog Input Voltage VINA -0.3 AVDD+0.3 V
Digital Input Voltage VIND -0.3 DVDD+0.3 V
Ambient Temperature Ta -40 85 °C
Storage Temperature Tstg -65 150 °C
Note: 1. All voltages with respect to ground.
2. AVSS and DVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V; Note 1)
Parameter Symbol min typ max Units
Power Supplies
(Note 3) Analog
Digital AVDD
DVDD 4.75
4.75 5.0
5.0 5.25
5.25 V
V
Note: 1. All voltages with respect to ground.
3. The power up sequence between AVDD and DVDD is not critical.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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ANALOG CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=5V; AVSS, DVSS=0V; VREFH=AVDD; fs=44.1kHz; BICK=64fs;
Signal Frequency =1kHz; 24bit Data; RL≥2kΩ; Measurement Frequency=20Hz∼20kHz at 44.1kHz,
20Hz~40kHz at fs=96kHz, 20Hz~80kHz at fs=192kHz; unless otherwise specified)
Parameter min typ max Units
Dynamic Characteristics (Note 4)
Resolution 24 Bits
S/(N+D)
fs=44.1kHz
fs=96kHz 88
86 94
92
dB
dB
DR (-60dBFS)
fs=44.1kHz, A-weighted
fs=96kHz 106
- 112
105
dB
dB
S/N (Note 5,6)
fs=44.1kHz, A-weighted
fs=96kHz 106
- 112
105
dB
dB
Interchannel Isolation 90 110 dB
DC Accuracy
Interchannel Gain Mismatch 0.2 0.5 dB
Gain Drift (Note 7) 20 - ppm/°C
Output Voltage (AOUT+) - (AOUT-) (Note 8) ±2.55 ±2.75 ±2.95 Vpp
Load Resistance (Note 9) 2 kΩ
Load Capacitance 25 pF
Power Supply Rejection (Note 10) 50 dB
Power Supplies
Power Supply Current
Normal Operation (PDN = “H”)
AVDD
DVDD (fs=44.1kHz)
(fs=96kHz)
(fs=192kHz)
Power-Down-Mode (PDN = “L”)
AVDD+DVDD (Note 11)
60
15
20
15
10
90
30
40
30
100
mA
mA
mA
mA
µA
Note: 4. Measured by UPD(ROHDE & SCHWARZ). Refer to the evaluation board manual.
5. 107dB at CCIR-ARM weighted
6. S/N is independent of input bit length.
7. VREFH is constantly +5.0V.
8. Full scale voltage (0dB). Output voltage scales with the voltage of VREFH pin.
AOUT(typ.@0dB)=(AOUT+)-(AOUT-)=±2.75Vpp*VREFH/5.0
9. AC load
10. PSR is applied to AVDD, DVDD with 1kHz, 100mVpp. VREFH pin is held a constant voltage.
11. All digital input pins including clock pins (MCLK, BICK and LRCK) are connected to DVSS.
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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FILTER CHARACTERISTICS (fs=44.1kHz)
(Ta=25°C; AVDD, DVDD=4.75∼5.25V; fs=44.1kHz; DFS1 = DFS0 = “0”; DEM=OFF)
Parameter Symbol min typ max Units
Digital Filter
Passband (Note 12) ±0.01dB
-6.0dB PB 0
-
22.05 20.0
- kHz
kHz
Stopband (Note 12) SB 24.1 kHz
Passband Ripple PR ±0.005 dB
Stopband Attenuation SA 75 dB
Group Delay (Note 13) GD - 27.2 - 1/fs
Digital Filter + SCF
Frequency Response: 0∼20.0kHz FR - ±0.2 - dB
Note: 12. The passband and stopband frequencies scale with fs.
For example, PB=0.4535*fs(@±0.01dB), SB=0.546*fs.
13. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24bit data
of both channels on the input register to the output of analog signal.
FILTER CHARACTERISTICS (fs=96kHz)
(Ta=25°C; AVDD, DVDD=4.75∼5.25V; fs=96kHz; DFS1 = “0”; DFS0 = “1”; DEM=OFF)
Parameter Symbol min typ max Units
Digital Filter
Passband (Note 14) ±0.01dB
-6.0dB PB 0
-
48.0 43.5
- kHz
kHz
Stopband (Note 14) SB 52.5 kHz
Passband Ripple PR ±0.005 dB
Stopband Attenuation SA 75 dB
Group Delay (Note 13) GD - 27.2 - 1/fs
Digital Filter + SCF
Frequency Response: 0∼40.0kHz FR - ±0.3 - dB
Note: 14. The passband and stopband frequencies scale with fs.
For example, PB=0.4535*fs(@±0.01dB), SB=0.546*fs.
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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FILTER CHARACTERISTICS (fs=192kHz)
(Ta=25°C; AVDD, DVDD=4.75∼5.25V; fs=192kHz; DFS1 = “1”; DFS0 = “0”; DEM=OFF)
Parameter Symbol min typ max Units
Digital Filter
Passband (Note 15) ±0.01dB
-6.0dB PB 0
-
96.0 87.0
- kHz
kHz
Stopband (Note 15) SB 105 kHz
Passband Ripple PR ±0.005 dB
Stopband Attenuation SA 75 dB
Group Delay (Note 13) GD - 27.2 - 1/fs
Digital Filter + SCF
Frequency Response: 0∼80.0kHz FR - ±0.5 - dB
Note: 15. The passband and stopband frequencies scale with fs.
For example, PB=0.4535*fs(@±0.01dB), SB=0.546*fs.
DIGITAL CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=4.75∼5.25V)
Parameter Symbol min typ max Units
High-Level Input Voltage
Low-Level Input Voltage VIH
VIL 2.2
- -
- -
0.8 V
V
Hight-Level Output Voltage (Iout= -100µA)
Low-Level Output Voltage (Iout= 100µA) VOH
VOL DVDD-0.5
- -
- -
0.5 V
V
Input Leakage Current Iin - - ±10 µA
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=4.75∼5.25V; CL=20pF)
Parameter Symbol min typ max Units
Master Clock Timing (Note 16)
Frequency
Duty
fCLK
Duty
8.192
40
36.864
60
MHz
%
LRCK frequency (Note 17)
Normal Speed Mode (DFS1-0 = “00”)
Double Speed Mode (DFS1-0 = “01”)
4 times Speed Mode (DFS1-0 = “10”)
Duty Cycle
fsn
fsd
fsq
Duty
32
64
128
45
48
96
192
55
kHz
kHz
kHz
%
Serial Interface Timing
BICK Period
Normal Speed Mode
Double Speed Mode
4 times Speed Mode
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge (Note 18)
LRCK Edge to BICK “↑” (Note 18)
SDTI Hold Time
SDTI Setup Time
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fs
1/64fs
1/64fs
33
33
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Rise Time of CSN
Fall Time of CSN
Rise Time of CCLK
Fall Time of CCLK
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tR1
tF1
tR2
tF2
200
80
80
40
40
150
50
50
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Power-down/Reset Timing
PDN Pulse Width (Note 19)
tPDW
150
ns
Note: 16. For Double and 4 times Speed modes please see Appendix A for relationship of MCLK and BCLK/LRCK.
17. If sampling speed mode (DFS0-1) changes, please reset by PDN pin or RSTN bit.
18. BICK rising edge must not occur at the same time as LRCK edge.
19. The AK4356 can be reset by PDN pin “L” upon power up.
If CKS0-2 or DFS0-1 changes, the AK4356 should be reset by PDN pin or RSTN bit.
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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n Timing Diagram
VIH
MCLK VIL
tCLK
VIH
LRCK VIL
1/fs
tBCK
tBCKL
VIH
tBCKH
BICK VIL
Clock Timing
For Double and 4 times Speed modes timing please see Appendix A for relationship of MCLK and BCLK/LRCK.
tLRB
LRCK
VIH
BICK VIL
tSDS
VIH
SDTI VIL
tSDH
VIH
VIL
tBLR
Audio Interface Timing
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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tCSS
CSN
VIH
CCLK VIL
VIH
CDTI VIL
VIH
VIL
C1 C0 R/W A4
tCCKL tCCKH
tCDS tCDH
WRITE Command Input Timing
CSN
VIH
CCLK VIL
VIH
CDTI VIL
VIH
VIL
D3 D2 D1 D0
tCSW
tCSH
WRITE Data Input Timing
tPDW
VIL
PDN
Power-down & Reset Timing
ASAHI KASEI [AK 435 6]
M0072-E-02 2003/09
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OPERATION OVERVIEW
S yste m Clock I nput
The ext ernal clo c k s which are require d to o p e rate t he AK4 356 are MC LK , L RC K and BICK . The master clo c k ( MCL K )
should be syn chr onized with sampling clock (LRCK) but the phase is not critical. However, in Double and 4 times
Speed Modes, the phase relationship between MCLK and LRCK/BICK is limited. (Refer to Appendix A). MCLK
is used to operate th e digita l i nt er polat ion filter a nd the delta -sigma modula tor. T h e frequency of MCLK can be set by
CKS0-2, and can be selected to normal, double or 4 times speed mode by DFS0-1 (See Table 1). 4 times speed mode can
be used fo r only DAC1. If DAC1 is in 4 times speed mode, DAC2 and DAC3 are automatically po wered do wn. When the
st ates of SLOW, D IF2-0, DFS1- 0 or CKS2-0 changes, the AK4356 should be reset by PDN pin or RSTN bit.
All external clocks (MCLK, BICK and LRCK) should always be pr esent whenever the AK4356 is in normal operation
mode (PD N = “ H ”). If these c lo c ks are no t provide d, the AK4 356 may draw e xc es s c urrent and may not po ss ib l y op e rate
properly because the device utilizes dynamic refreshed lo gic internally . If the external clo cks are not present, the AK4356
should be in the power-down m ode (PDN = “L” or a ll DACs are set in the power-down mode by PW1-3 bits) or in t he
reset mode (RSTN = “ 0”). Af ter exiting reset at pow e r-up etc., the AK4356 is in the powe r-dow n mode until MCLK and
LRCK ar e in p ut .
DFS1-0
Mode
CKS2
CKS1
CKS0 “00”
(Nor m a l Speed ) “01”
( Doubl e Sp eed ) “10”
( 4 tim es Speed)
0 0 0 0 256fs 128fs N/A default (DFS1-0 = “00”)
1 0 0 1 256fs 256fs N/A
2 0 1 0 384fs 192fs N/A
3 0 1 1 384fs 384fs N/A
4 1 0 0 512fs 256fs 128fs
5 1 0 1 512fs N/A N/A
6 1 1 0 768fs 384fs 192fs
7 1 1 1 768fs N/A N/A
Table 1. System Clock (DFS1-0 = “11”: reserved)
fs [kHz] Mode 128fs 192fs 256fs 384fs 512fs 768fs
32
64
128
Normal
Double
4 times
-
8.1920
16.3840
-
12.2880
24.5760
8.1920
16.3840
-
12.2880
24.5760
-
16.3840
-
-
24.5760
-
-
44.1
88.2
176.4
Normal
Double
4 times
-
11.2896
22.5792
-
16.9344
33.8688
11.2896
22.5792
-
16.9344
33.8688
-
22.5792
-
-
33.8688
-
-
48
96
192
Normal
Double
4 times
-
12.2880
24.5760
-
18.4320
36.8640
12.2880
24.5760
-
18.4320
36.8640
-
24.5760
-
-
36.8640
-
-
Table 2. E xample of System Cl ock [MHz]
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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n Audio Serial Interface Format
Audio data is input to the AK4356 via the SDTI1-3 pins using BICK and LRCK inputs. 5 serial data formats are supported
and selected by DIF2-0 pins or DIF2-0 bits (See Table 3, compatible with the AK4324/4393). In all modes the serial data
is MSB-first, 2’s compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 20 and 16 MSB
justified formats by zeroing the unused LSBs.
Mode DIF2 DIF1 DIF0 SDTI L/R BICK Figure
0 0 0 0 16bit, LSB justified H/L ≥32fs Figure 1 default
1 0 0 1 20bit, LSB justified H/L ≥40fs Figure 2
2 0 1 0 24bit, MSB justified H/L ≥48fs Figure 3
3 0 1 1 I2S L/H 32fs or ≥48fs Figure 4
4 1 0 0 24bit, LSB justified H/L ≥48fs Figure 2
Table 3. Audio data format
SDTI
BICK
LRCK
SDTI
15 14 6 5 4
BICK
0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1
3 2 1 0 15 14
(32fs)
(64fs)
014
115 16 17 31 0 1 14 15 16 17 31 0 1
15 14 015 14 0
Mode 0
Don’t care Don’t care
15:MSB, 0:LSB
Mode 0
15 14 6 5 4 3 2 1 0
Lch Data Rch Data
Figure 1. Mode 0 Timing
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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SDTI
LRCK
BICK
(64fs)
0 91 10 11 12 31 0 1 9 10 11 12 31 0 1
19 019 0
Mode 1
Don’t care Don’t care
19:MSB, 0:LSB
SDTI
Mode 4
23:MSB, 0:LSB
20 19 020 19 0
Don’t care Don’t care
22 21 22 21
Lch Data Rch Data
8
23 23
8
Figure 2. Mode 1,4 Timing
LRCK
BICK
(64fs)
SDTI
0221 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 1 0 Don’t care23
Lch Data Rch Data
23 30 2222423 30
22 10Don’t care
23 2223
Figure 3. Mode 2 Timing
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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LRCK
BICK
(64fs)
SDTI
0 31 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 10Don’t care
23
Lch Data Rch Data
23 25 32 2423 25
22 1 0 Don’t care23
BICK
(32fs)
SDTI
0 31 2 12 15 0 1 0 1
23 22 138
11 14 2
12 11 10 9
13 312 1511 1413
23 22 13812 11 10 9238
23
Figure 4. Mode 3 Timing
n
Output Volume
The AK4356 includes channel independent digital output volumes (ATT) with 256 levels at 0.5dB steps including MUTE.
These volumes are in front of the DAC and can attenuate the input data from 0dB to –127dB and mute. When changing
levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions.
n
De-emphasis filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc=50/15µs). It can be set for DAC1
(SDTI1), DAC2 (SDTI2) and DAC3 (SDTI3) independently. It is enabled or disabled with the control register data of
DEM1-0 and DFS1-0. The de -emphasis filter is disabled at double or 4 times sampling mode (except for DFS0 = DFS1 =
“0”).
DEM1 DEM0 De-emphasis
0 0 44.1kHz
0 1 OFF default
1 0 48kHz
1 1 32kHz
Table 4. De-emphasis filter control with DEM1-0 (DFS1-0 = “00”)
DFS1 DFS0 De-emphasis
0 0 See Table 4. default
0 1 OFF
1 0 OFF
1 1 OFF
Table 5. De-emphasis filter control with DFS1-0
ASAHI KASEI [AK4356]
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n Zero detection
The AK4356 has channel-independent zeros detect function. When the input data at each channel is continuously zero for
8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input data
of each channel is not zero after going DZF “H”. If RSTN bit is “0”, DZF pins of all channels go to “H”. DZF pins of all
channels go to “L” 4/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, DZF pins of all channels go to “H” only
when the input data at all channels are continuously zeros for 8192 LRCK cycles. Zero detect function can be disabled by
DZFE bit. In this case, DZF pins of all channels are always “L” (except for the case of RSTN = “0”).
n Soft mute operation
Soft mute operation is performed at digital domain. When the SMUTE pin goes to “H”, the output signal is attenuated by
-∞ during 1024 LRCK cycles. When the SMUTE pin is returned to “L”, the mute is cancelled and the output attenuation
gradually changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK cycles after starting
the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source
without stopping the signal transmission.
SMUTE
Attenuation
DZF
1024/fs
0dB
-∞
AOUT
1024/fs
8192/fs
GD GD
(1)
(2)
(3)
(4)
Notes:
(1) The output signal is attenuated by -∞ during 1024 LRCK cycles (1024/fs).
(2) Analog output corresponding to digital input have the group delay (GD).
(3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to
“H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”.
Figure 5. Soft mute and zero detection
n System Reset
The AK4356 should be reset once by bringing PDN = “L” upon power-up. The AK4356 is powered up and the internal
timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4356 is in the power-down
mode until MCLK and LRCK are input.
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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n Power-down
All DACs are placed in the power-down mode by bringing PDN pin “L” and each digital filter is also reset at the same time.
The internal register values are initialized by PDN “L”. This reset should always be done after power-up. Because some
click noise occurs at the edge of PDN, the analog output should be muted externally if the click noise influences system
application. Figure 6 shows the power-down/up sequence.
Each DAC can be powered down by each power-down bit (PW1-3) “0”. In this case, the internal register values are not
initialized and the analog output is Hi-Z. Because some click noise occurs, the analog output should be muted externally if
the click noise influences system application.
If DAC1 is in 4 times speed mode (DFS1=1, DFS0=0), DAC2 and DAC3 are automatically powered down. Both analog
outputs go to analog common voltage (AVDD/2).
Normal Operation
Internal
State
PDN
Power-down Normal Operation
GD GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK, LRCK, BICK
(1) (3)
(6)
DZF
External
MUTE
(5)
(3) (1)
Mute ON
(2)
(4)
Don’t care
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
(6) DZF pins of all channels are “L” in the power-down mode (PDN = “L”).
Figure 6. Power-down/up sequence example
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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n Reset Function
When RSTN=0, all DACs are powered down but the internal register values are not initialized. The analog outputs go to
VCOM voltage and DZF pins of all channels go to “H”. Figure 7 shows the sequence of reset by RSTN bit.
Internal
State
RSTN bit
Digital Block Power-down Normal Operation
GD GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK,LRCK,BICK
(1) (3)
DZFL/DZFR
(3) (1)
(2)
Normal Operation
2/fs(5)
Internal
RSTN bit
2~3/fs (6)
Don’t care
(4)
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs go to VCOM voltage.
(3) Click noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0” data is
input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = “L”).
(5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 4~5/fs after RSTN bit becomes “1”.
(6) There is a delay, 2~3/fs from RSTN bit “1” to the internal RSTN “1”.
Figure 7. Reset sequence example
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
- 20 -
n Serial Control Interface
The AK4356 can control its functions via both pins and registers. CKS2-0, DIF2-0, DFS0, DZFE and SMUTE pins are
ORed with their registers.
Internal registers may be written to the 3 wire uP interface pins: CSN, CCLK & CDTI. The data on this interface consists
of Chip address (2bits, CAD0/1), Read/Write (1bit), Register address (MSB first, 5bits) and Control data (MSB first,
8bits). Address and data is clocked in on the rising edge of CCLK. Data is latched after a low-to-high transition of CSN.
The clock speed of CCLK is 5MHz(max). The CSN pin should be held to “H” except for access.
The chip address is determined by the state of the CAD0 and CAD1 inputs. PDN = “L” initializes the registers to their
default values. Writing “0” to the RSTN bit can initialize the internal timing circuit. But in this case, the register data is not
be initialized.
CDTI
CCLK
CSN
C1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0
D0
D1
D2
D3
C1-C0: Chip Address (C1=CAD1, C0=CAD0)
R/W: Read/Write (Fixed to “1” : Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 7. Control I/F Timing
Function Pin set-up Register set-up
Double Speed O O
4 times Speed X O
De-emphasis X O
DZFE O O
DZFM X O
SMUTE O O
Attenuator X O
Slow roll-off response X O
Table 6. Function Table (O: Supported, X: Not supported)
Note: Writing to control register is inhibited when PDN = “L” or the MCLK is not fed.
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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n Mapping of Program Registers
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 0 SLOW DZFM DZFE DIF2 DIF1 DIF0 RSTN
01H Control 2 0 0 0 CKS2 CKS1 CKS0 SMUTE RSTN
02H Speed & Power Down Control 0 0 DFS1 DFS0 PW3 PW2 PW1 RSTN
03H De-emphasis Control 0 0 DEMC1 DEMC0 DEMB1 DEMB0 DEMA1 DEMA0
04H LOUT1 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
05H ROUT1 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
06H LOUT2 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
07H ROUT2 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
08H LOUT3 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
09H ROUT3 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
0AH Test Mode 0 0 0 TEST4 TEST3 TEST2 TEST1 TEST0
Note: For addresses from 0BH to 1FH, data is not written.
When PDN goes to “L”, the registers are initialized to their default values.
When RSTN bit goes to “0”, the internal timing is reset, DZF pins of all channels go to “H” but registers are not
initialized to their default values.
DZFE, DIF2-0, CKS2-0, SMUTE and DFS0 are ORed with pins.
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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n Register Definitions
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 0 SLOW DZFM DZFE DIF2 DIF1 DIF0 RSTN
Default 0 0 0 0 0 0 0 1
RSTN: Internal timing reset
0: Reset. DZF pins of all channels go to “H” and registers are not initialized.
1: Normal operation
When the states of SLOW, DIF2-0, CKS2-0 or DFS0-1 changes, the AK4356 should be reset
by PDN pin or RSTN bit. Some click noise occurs at that timing.
DIF2-0: Audio data interface modes (See Table 3.)
Initial: “000”, Mode 0
Register bits of DIF2-0 are ORed with the DFS2-0 pins.
DZFE: Data Zero Detect Enable
0: Disable
1: Enable
Zero detect function can be disabled by DZFE bit. In this case, the DZF pins of all channels
are always “L”. Register bit of DZFE is ORed with the DZFE pin.
DZFM: Data Zero Detect Mode
0: Channel Separated Mode
1: Channel ANDed Mode
If the DZFM bit is set to “1”, the DZF pins of all channels go to “H” only when the input data
at all channels are continuously zeros for 8192 LRCK cycles.
SLOW: Slow roll-off response enable
0: Disable
1: Enable
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
01H Control 2 0 0 0 CKS2 CKS1 CKS0 SMUTE RSTN
Default 0 0 0 0 0 0 0 1
RSTN: Internal timing reset
0: Reset. DZF pins of all channels go to “H” and registers are not initialized.
1: Normal operation
When the states of SLOW, DIF2-0, CKS2-0 or DFS0-1 changes, the AK4356 should be reset
by PDN pin or RSTN bit. Some click noise occurs at that timing.
SMUTE: Soft Mute Enable
0: Normal operation
1: All DAC outputs soft-muted
Register bit of SMUTE is ORed with the SMUTE pin.
CKS2-0: Master Clock Frequency Select (See Table 2.)
Initial: “000”, Mode 0
Register bits of CKS2-0 are ORed with the CKS2-0 pins.
ASAHI KASEI [AK4356]
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H Speed & Power Down Control 0 0 DFS1 DFS0 PW3 PW2 PW1 RSTN
Default 0 0 0 0 1 1 1 1
RSTN: Internal timing reset
0: Reset. DZF pins of all channels go to “H” and registers are not initialized.
1: Normal operation
When the states of SLOW, DIF2-0, CKS2-0 or DFS0-1 changes, the AK4356 should be reset
by PDN pin or RSTN bit. Some click noise occurs at that timing.
PW3-1: Power-down control (0: Power-down, 1: Power-up)
PW1: Power down control of DAC1
PW2: Power down control of DAC2
PW3: Power down control of DAC3
All sections are powered-down by PW1=PW2=PW3=0.
DFS1-0: Sampling speed control (See Table 1.)
00: Normal speed
01: Double speed
10: 4 times speed (DAC2 and DAC3 are automatically powered down.)
Register bit of DFS0 is ORed with the DFS0 pin.
When sampling speed mode is changed between normal and double/4 times speed mode, DFS1-0 bit
should be changed after changing MCLK frequency (figure below). Some click noise occurs at this
timing.
Sampling
speed
MCLK
normal
4 times
/double normal
When sampling speed mode is changed between double and 4 times speed mode, sampling mode should
be changed to normal speed mode after changing MCLK frequency, and then it should be changed to
double/4 times speed mode (figure below). Some click noise occurs at those changing timing.
Sampling
speed
MCLK
double/
4 times normal
4 times
/double
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
03H De-emphasis Control 0 0 DEMC1 DEMC0 DEMB1 DEMB0 DEMA1 DEMA0
Default 0 0 0 1 0 1 0 1
DEMA1-0: De-emphasis response control for DAC1 data on SDTI1 (See Table 4,5.)
Initial: “01”, OFF
DEMB1-0: De-emphasis response control for DAC2 data on SDTI2 (See Table 4,5.)
Initial: “01”, OFF
DEMC1-0: De-emphasis response control for DAC3 data on SDTI3 (See Table 4,5.)
Initial: “01”, OFF
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
04H LOUT1 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
05H ROUT1 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
06H LOUT2 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
07H ROUT2 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
08H LOUT3 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
09H ROUT3 ATT Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
Default 1 1 1 1 1 1 1 1
ATT7-0: Attenuation Level
256 levels, 0.5dB step
ATT7-0 Attenuation
FFH 0dB
FEH -0.5dB
FDH -1.0dB
: :
: :
02H -126.5dB
01H -127.0dB
00H MUTE (-∞)
The transition between set values is soft transition of 7425 levels. It takes 7424/fs (168ms@fs=44.1kHz) from
FFH(0dB) to 00H(MUTE).
If PDN pin goes to “L”, the ATTs are initialized to FFH.
The ATTs are FFH when RSTN = “0”. When RSTN return to “1”, the ATTs fade to their current value.
Digital attenuator is independent of soft mute function.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0AH Test Mode 0 0 0 TEST4 TEST3 TEST2 TEST1 TEST0
Default 0 0 0 0 0 0 0 0
TEST4-0: Test mode
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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SYSTEM DESIGN
Figure 8 shows the system connection diagram. An evaluation board is available which demonstrates application circuits,
the optimum layout, power supply arrangements and measurement results.
Condition: Chip Address=”00”
DVSS
DVDD
12
SDTI1
11
13
SDTI214
SDTI315
LRCK16
SMUTE17
CCLK18
CDTI19
CSN20
DFS021
CKS022
MCLK
10
BICK
9
PDN
8
CAD1
7
CAD0
6
DZFL1
5
DZFR1
4
DZFL2
3
LOUT1+
2
LOUT1-
1
CKS1
23
CKS2
24
DIF0
25
DIF1
26
DIF2
27
DZFE
28
DZFR3
29
DZFL3
30
DZFR2
31
VREFH
32
AVDD
33
44
43
42
41
40
39
38
37
36
35
34
ROUT1+
ROUT1-
LOUT2+
LOUT2-
ROUT2+
ROUT2-
LOUT3+
LOUT3-
ROUT3+
ROUT3-
AVSS
AK4356
Top View
DIR
DSP
uP
+
Mode Control
R3ch
LPF
L3ch
LPF
R2ch
LPF
L2ch
LPF
R1ch
LPF
L1ch
LPF L1ch MUTE L1ch
OUT
R1ch MUTE R1ch
OUT
L2ch MUTE L2ch
OUT
R2ch MUTE R2ch
OUT
L3ch MUTE L3ch
OUT
R3ch MUTE R3ch
OUT
+Analog 5V
Digital 5V
System Ground Analog Ground
Reset
10u 0.1u
0.1u 10u
Figure 8. Typical Connection Diagram
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
- 26 -
Analog GroundDigital Ground
System
Controller
DVSS
DVDD
12
SDTI1
11
13
SDTI2
14
SDTI3
15
LRCK
16
SMUTE
17
CCLK
18
CDTI
19
CSN
20
DFS0
21
CKS0
22
CKS1
23
44
ROUT1+
AK4356
24
25
26
27
28
29
30
31
32
33
CKS2
DIF0
DIF1
DIF2
DZFE
DZFR3
DZFL3
DZFR2
VREFH
AVDD
43
ROUT1-
42
LOUT2+
41
LOUT2-
40
ROUT2+
39
ROUT2-
38
LOUT3+
37
LOUT3-
36
ROUT3+
35
ROUT3-
34
AVSS
MCLK 10
BICK 9
PDN
8
CAD1
7
CAD0 6
DZFL1
5
DZFR1
4
DZFL2 3
LOUT1+
2
LOUT1-
1
Figure 9. Ground Layout
Note: AVSS and DVSS must be connected to the same analog ground plane.
1. Grounding and Power Supply Decoupling
The AK4356 requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually
supplied from analog supply in system. Alternatively if AVDD and DVDD are supplied separately, the power up sequence
is not critical. AVSS and DVSS of the AK4356 must be connected to analog ground plane. System analog ground and
digital ground should be connected together near to where the supplies are brought onto the printed circuit board.
Decoupling capacitors should be near to the AK4356 as possible, with the small value ceramic capacitors being the nearest.
2. Voltage Reference Inputs
VREFH sets the analog output range. VREFH pin is normally connected to AVDD with a 0.1µF ceramic capacitor. All
signals, especially clocks, should be kept away from the VREFH pin in order to avoid unwanted coupling into the AK4356.
3. Analog Outputs
The analog outputs are full-differential outputs and 0.55 x VREFH Vpp (typ) centered around the internal common voltage
(about AVDD/2). The differential outputs are summed externally, VAOUT=(AOUT+)-(AOUT-) between AOUT+ and
AOUT-. If the summing gain is 1, the output range is 5.5Vpp (typ @VREFH=5V). The bias voltage of the external
summing circuit is supplied externally. The input data format is 2’s complement. The output voltage(VAOUT) is a positive
full scale for 7FFFFF(@24bit) and a negative full scale for 800000H(@24bit). The ideal VAOUT is 0V for
000000H(@24bit).
The internal switched-capacitor filter and external low pass filter attenuate the noise generated by the delta-sigma
modulator beyond the audio passband.
DC offset on AOUT+/- is eliminated without AC coupling since the analog outputs are differential. Figure 10 and 11 show
the example of external op-amp circuit summing the differential outputs.
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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4.7k 4.7k
R1
4.7k R1
4.7k 470p
Vop
470p
Vop
1k
1k47u
0.1u
BIAS
AOUT-
AOUT+
3300p
When R1=200Ω
When R1=180Ω
fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz
fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
Analog
Out
Figure 10. External 2nd order LPF Circuit Example (using op-amp with single power supply)
4.7k 4.7k
R1
4.7k R1
4.7k 470p
+Vop
470p
-Vop
AOUT-
AOUT+
3300p
When R1=200Ω
When R1=180Ω
fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz
fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
Analog
Out
Figure 11. External 2nd order LPF Circuit Example (using op-amp with dual power supplies)
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
- 28 -
PACKAGE
0.15
0.17±0.05
0.37±0.10
10.00
1.70max
1
11
23
33
44pin LQFP (Unit: mm)
10.00
12.80±0.30
34
44
0.80
22
12
12.80±0.30
0∼0.2
0°∼10°
0.60±0.20
n Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder plate
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
- 29 -
MARKING
AKM
AK4356VQ
XXXXXXX
JAPAN
1
1) Pin #1 indication
2) Date Code: XXXXXXX(7 digits)
3) Marking Code: AK4356VQ
4) Country of Origin
5) Asahi Kasei Logo
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any
use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or
other official approval under the law and regulations of the country of export pertaining to customs and
tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the express written consent of the Representative Director of AKM. As used
here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and
hold AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.
ASAHI KASEI [AK4356]
M0072-E-02 2003/09
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Appendix A
In Double and 4 times Speed Modes, the phase relationship between MCLK and LRCK/BICK is limited (Table 7). If the
phase relationship happens during this prohibited period, it is possible to occur the inverse of output channel. The phase
relationship must be set to avoid the prohibited period when the AK4356 operates at Double Speed Mode or 4 times Speed
Mode. The prohibited period is specified by the combination of digital power supply voltage (DVDD), MCLK frequency
and audio data format (Table 3). When the audio data formats are 16/20/24bit LSB Justified (Mode 0,1,4) and 24bit MSB
Justified (Mode 2), the phase relationship (tLRM: Figure 12) between the rising edge of LRCK and the rising edge of
MCLK has the prohibited period of min to max in Table 7. In case of I2S Compatible (Mode 3), the relationship between
the falling edge of BICK and the rising edge of MCLK has the prohibited period (tBCM: Figure 13)
Mode Setting Prohibited Period Sampling
Mode Digital Power
Supply, DVDD MCLK
Frequency CKS2 CKS1 CKS0 DFS1 DFS0 min max
Units
Double Speed 4.75 to 5.25V 128fs 0 0 0 0 1 0.1 0.6 ns
Double Speed 4.75 to 5.25V 192fs 0 1 0 0 1 -0.6 -0.1 ns
Double Speed 4.75 to 5.25V 256fs 0 0 1 0 1 -0.7 -0.2 ns
Double Speed 4.75 to 5.25V 256fs 1 0 0 0 1 -0.7 -0.2 ns
Double Speed 4.75 to 5.25V 384fs 0 1 1 0 1 -1.4 -0.9 ns
Double Speed 4.75 to 5.25V 384fs 1 1 0 0 1 -1.4 -0.9 ns
4 times Speed 4.75 to 5.25V 128fs 1 0 0 1 0 -0.7 -0.2 ns
4 times Speed 4.75 to 5.25V 192fs 1 1 0 1 0 -1.4 -0.9 ns
Table 7. Prohibited Period
tLRM
LRCK
MCLK
1.5V
1.5V
Figure 12. 16/20/24bit LSB Justified, 24bit MSB Justified
tBCM
BICK
MCLK
1.5V
1.5V
Figure 13. I2S Compatible