SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
Family
D
State-of-the-Art
EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
D
Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’ABT16646 devices consist of
bus-transceiver circuits, D-type flip-flops, and
control circuitry arranged for multiplexed
transmission of data directly from the input bus or
from the internal registers.
These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. Data on the
A or B bus is clocked into the registers on the
low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
can be performed with the ’ABT16646 devices.
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The
select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry
used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition
between stored and real-time data. The direction control (DIR) determines which bus receives data when OE
is low . In the isolation mode (OE high), A data can be stored in one register and/or B data can be stored in the
other register.
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
SN54ABT16646 . . . WD PACKAGE
SN74ABT16646 . . . DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1DIR
1CLKAB
1SAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2SAB
2CLKAB
2DIR
1OE
1CLKBA
1SBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2SBA
2CLKBA
2OE
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The SN54ABT16646 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16646 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS DATA I/O†
OPERATION OR FUNCTION
OE DIR CLKAB CLKBA SAB SBA A1–A8 B1–B8
OPERATION
OR
FUNCTION
X X ↑X X X Input Unspecified Store A, B unspecified
{
XXX ↑X X Unspecified Input Store B, A unspecified
{
H X ↑ ↑ X X Input Input Store A and B data
HX H or L H or L X X Input disabled Input disabled Isolation, hold storage
L L X X X L Output Input Real-time B data to A bus
LL X H or L X H Output Input Stored B data to A bus
L H X X L X Input Output Real-time A data to B Bus
L H H or L X H X Input Output Stored A data to bus
†The data-output functions can be enabled or disabled by various signals at OE or DIR. Data-input functions always are enabled, i.e., data at the
bus terminals is stored on every low-to-high transition of the clock inputs.
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
LDIR
LCLKAB
XCLKBA
XSAB
XSBA
L
REAL-TIME TRANSFER
BUS B TO BUS A
LDIR
HCLKAB
XCLKBA
XSAB
LSBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
XDIR
XCLKAB CLKBA
XSAB
XSBA
X
STORAGE FROM
A, B, OR A AND B
LDIR
LCLKAB
XCLKBA
H or L SAB
XSBA
H
TRANSFER STORED DATA
TO A AND/OR B
X
HX
XXX
XX
XL H H or L X H X
↑↑
↑↑
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OE OE
OEOE
Figure 1. Bus-Management Functions
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol†
1A2 6
1A3 8
1A4 9
1A5 10
1A6 12
1A7 13
1A8 14
2A2 16
2A3 17
2A4 19
2A5 20
2A6 21
2A7 23
2A8 24
5
1A1
1B6
45
1B7
44
1B8
43
1B2
51
1B3
49
1B4
48
1B5
47
1B1
52
4D
1
2
G12
31
2SBA
30
2CLKBA
10 EN8 [BA]
28
2DIR
G10
29
2B6
36
2B7
34
2B8
33
2B2
41
2B3
40
2B4
38
2B5
37
2OE
10 EN9 [AB]
≥1
1
5
5
≥1
1
7
7
15
2A1 8
9
≥1
1
12
12
≥1
1
14
14
13D
2B1
42
11D
C11
G14
26
2SAB
27
2CLKAB C13
G5
54
1SBA
55
1CLKBA
3 EN1 [BA]
1
1DIR
G3
56
1OE
3 EN2 [AB]
C4
G7
3
1SAB
2
1CLKAB C6
6D
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1A1 1B1
1D
C1
1D
C1
One of Eight Channels
52
5
3
2
54
55
56
1
1SAB
1CLKAB
1SBA
1CLKBA
1DIR
1OE
To Seven Other Channels
2A1 2B1
1D
C1
1D
C1
One of Eight Channels
42
15
26
27
31
30
29
28
2SAB
2CLKAB
2SBA
2CLKBA
2DIR
2OE
To Seven Other Channels
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABT16646 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT16646 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
SN54ABT16646 SN74ABT16646
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 0 VCC 0 VCC V
IOH High-level output current –24 –32 mA
IOL Low-level output current 48 64 mA
∆t/∆vInput transition rise or fall rate Outputs enabled 10 10 ns/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C SN54ABT16646 SN74ABT16646
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN MAX MIN MAX
UNIT
VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VOH
VCC = 5 V, IOH = –3 mA 3 3 3
V
V
OH
VCC =45V
IOH = –24 mA 2 2
V
V
CC =
4
.
5
V
IOH = –32 mA 2* 2
VOL
VCC =45V
IOL = 48 mA 0.55 0.55
V
V
OL
V
CC =
4
.
5
V
IOL = 64 mA 0.55* 0.55
V
Vhys 100 mV
I
I
Control
inputs V
CC
= 5.5 V, V
I
= V
CC
or GND ±1±1±1
µ
A
I
A or B ports
CC ,ICC
±20 ±20 ±20
µ
IOZH‡VCC = 5.5 V, VO = 2.7 V 10 10 10 µA
IOZL‡VCC = 5.5 V, VO = 0.5 V –10 –10 –10 µA
Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
ICEX VCC = 5.5 V,
VO = 5.5 V Outputs high 50 50 50 µA
IO§VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
VCC
=
5.5 V,
Outputs high 2 2 2
ICC A or B ports
VCC
=
5
.
5
V
,
IO = 0, Outputs low 32 32 32 mA
VI = VCC or GND Outputs disabled 2 2 2
Data in
p
uts
VCC = 5.5 V,
One input at 3.4 V, Outputs enabled 50 50 50
∆ICC
Data
inp
u
ts
,
Other inputs at
VCC or GND Outputs disabled 50 50 50 µA
Control
inputs VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND 50 50 50
CiControl
inputs VI = 2.5 V or 0.5 V 4 pF
Cio A or B ports VO = 2.5 V or 0.5 V 8 pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†All typical values are at VCC = 5 V.
‡The parameters IOZH and IOZL include the input leakage current.
§Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN54ABT16646
VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN MAX
fclock Clock frequency 125 125 MHz
twPulse duration, CLK high or low 4.3 4.3 ns
tsu Setup time, A or B before CLKAB↑ or CLKBA↑3.5 4 ns
thHold time, A or B after CLKAB↑ or CLKBA↑0.5 0.5 ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN74ABT16646
VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN MAX
fclock Clock frequency 125 125 MHz
twPulse duration, CLK high or low 4.3 4.3 ns
tsu Setup time, A or B before CLKAB↑ or CLKBA↑3 3 ns
thHold time, A or B after CLKAB↑ or CLKBA↑0 0 ns
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 2)
SN54ABT16646
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN TYP MAX
fmax 125 125 MHz
tPLH
CLKBA or CLKAB
AorB
1.5 3.1 4 1 5
ns
tPHL
CLKBA
or
CLKAB
A
or
B
1.5 3.2 4.1 1 5
ns
tPLH
AorB
BorA
1 2.3 3.2 0.6 4
ns
tPHL
A
or
B
B
or
A
1 3 4.1 0.6 4.9
ns
tPLH
SAB or SBA†
BorA
1 2.9 4.3 0.6 5.3
ns
tPHL
SAB
or
SBA†
B
or
A
1 3.1 4.3 0.6 5.3
ns
tPZH
OE
AorB
1 3.4 4.6 0.6 5.9
ns
tPZL
OE
A
or
B
1.5 3.5 5.3 1 6
ns
tPHZ
OE
AorB
1.5 3.9 5.6 1 6.4
ns
tPLZ
OE
A
or
B
1.5 3.1 4.4 1 4.7
ns
tPZH
DIR
AorB
1 3.2 4.5 0.6 5.8
ns
tPZL
DIR
A
or
B
1.5 3.4 5.1 1 6.7
ns
tPHZ
DIR
AorB
2 4.2 5.9 1.2 7.1
ns
tPLZ
DIR
A
or
B
1.5 3.6 5.1 1 6.2
ns
†These parameters are measured with the internal output state of the storage register opposite that of the bus input.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 2)
SN74ABT16646
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN TYP MAX
fmax 125 125 MHz
tPLH
CLKBA or CLKAB
AorB
1.5 3.1 4 1.5 4.9
ns
tPHL
CLKBA
or
CLKAB
A
or
B
1.5 3.2 4.1 1.5 4.7
ns
tPLH
AorB
BorA
1 2.3 3.2 1 3.9
ns
tPHL
A
or
B
B
or
A
1 3 4.1 1 4.6
ns
tPLH
SAB or SBA†
BorA
1 2.9 4.3 1 5
ns
tPHL
SAB
or
SBA†
B
or
A
1 3.1 4.3 1 5
ns
tPZH
OE
AorB
1 3.4 4.6 1 5.5
ns
tPZL
OE
A
or
B
1.5 3.5 4.9 1.5 5.7
ns
tPHZ
OE
AorB
1.5 3.9 4.9 1.5 5.4
ns
tPLZ
OE
A
or
B
1.5 3.1 4.1 1.5 4.5
ns
tPZH
DIR
AorB
1 3.2 4.5 1 5.4
ns
tPZL
DIR
A
or
B
1.5 3.4 4.8 1.5 5.6
ns
tPHZ
DIR
AorB
2 4.2 5.7 2 6.7
ns
tPLZ
DIR
A
or
B
1.5 3.6 5.1 1.5 5.9
ns
†These parameters are measured with the internal output state of the storage register opposite that of the bus input.
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input 1.5 V 3 V
0 V
1.5 V 1.5 V
3 V
0 V
3 V
0 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V 1.5 V 3 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
W aveform 1
S1 at 7 V
(see Note B)
Output
W aveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
3.5 V
0 V
1.5 V VOL + 0.3 V
1.5 V VOH – 0.3 V
≈ 0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST S1
Output
Control
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
Figure 2. Load Circuit and Voltage Waveforms
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74ABT16646DGGR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1
SN74ABT16646DLR SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ABT16646DGGR TSSOP DGG 56 2000 367.0 367.0 45.0
SN74ABT16646DLR SSOP DL 56 1000 367.0 367.0 55.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
WD (R-GDFP-F**) CERAMIC DUAL FLATPACK
4040176/D 10/97
48 LEADS SHOWN
48
48
25
56
0.610
(18,80)
0.710
(18,03)
0.7400.640
0.390 (9,91)
0.370 (9,40)
0.870 (22,10)
1.130 (28,70)
1
A
0.120 (3,05)
0.075 (1,91)
LEADS**
24
NO. OF
A MIN
A MAX (16,26)
(15,49)
0.025 (0,635)
0.009 (0,23)
0.004 (0,10)
0.370 (9,40)
0.250 (6,35)
0.370 (9,40)
0.250 (6,35)
0.014 (0,36)
0.008 (0,20)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only
E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA
GDFP1-F56 and JEDEC MO-146AB
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040048/E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
4828
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0°–ā8°
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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