HSDP2114S - OSRAM Opto Semiconductors

Lead (Pb) Free Product - RoHS Compliant

Red HSDP2110S

Yellow HSDP2111S

High Efficiency Red HSDP2112S

Green HSDP2113S

High Efficiency Green HSDP2114S

Soft Orange HSDP2115S

0.200" 8-Character 5x7 Dot Matrix Parallel Input

Alphanumeric Intelligent Di splay® Devices

2006-01-23 1

DESCRIPTION

The HDSP2110S (Red), HDSP2111S (Yellow),

HDSP2112S (High Efficiency Red), HDSP2113S

(Green), HDSP2114S (High Effi ciency Green), and

HDSP2115S (Soft Orange) are eight digit, 5 x 7 dot

matrix, alphanumeric Intelligent Display devices. The

0.20 inch high digits are pac kaged in a rugged, high qual-

ity, optically transparent, 0.6 inch lead spacing, 28 pin

plastic DIP.

The on-board CMOS has a built-in 128 character ROM.

The HDSP211XS also has a user definable character

(UDC) fea ture, which uses a RAM that permits storage of

16 arbitrary characters, symbols or icons that are soft-

ware-defi nable b y the user. The character ROM itself is

mask programmab le and easily modified by the man uf a c-

turer to provide specif ied custom characters.

The HDSP211XS is designed for standard

microprocessor interface techniques, and is fully TTL

compatible . The Clock I/O and Cloc k Select pins allow the

user to cascade multiple display modules.

ESD Warning: Standard precautions for CMOS

handling should be observed.

FEATURES

• Eight 0.200" Dot Matrix Characters in Red, Yellow,

High Efficiency Red , Green, High Ef fici ency Green, or

Soft Orange

• Built-in 128 Character ROM,

Mask Programmable for Custom Fonts

• Readable from 8 Feet (2.5 meters)

• Built-in Decoders, Multiplexers and Drivers

• Wide Viewing Angle, X Axis ± 55°, Y Axis ± 65°

• Programmable Features:

– Individual Flashing Character

– Full Display Blinking

– Multi-Level Dimming and Blanking

– Clear Function

– Self Test

• Internal or External Clock

• End Stackable Dual-In-Line Plastic Package

• Read/Write Capability

• 16 User D efinable Charac te r s

2006-01-23 2

HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

Package Outlines Dimensions in inch (mm)

Enlarged Character Font Dimensions in inch (mm)

Ordering Information

Type Color of Emission Character Height

[inch] ([mm]) Ordering Code

HSDP2110S red

0.200 (5.10)

Q68000A8560

HSDP2111S yellow Q68000A8561

HSDP2112S high efficiency red Q68000A8562

HSDP2113S green Q68000A8563

HSDP2114S high efficiency green Q68000A8564

HSDP2115S soft orange Q68000A8907

IDOD5019

19.58 (0.771)

5.34 (0.210)

42.67 (1.680) max.

2.67 (0.105)

4.81 (0.189)

9.8 (0.386)

Pin 1

Indicator

5.31 (0.209)

15.24 (0.600)

0.3 (0.012) typ.

2.19 (0.086)

4.79 (0.189) 2.54 (0.100) typ. 0.46 (0.018) typ.

4.06 (0.160)±0.5 (0.020)

HDSP211X Z

OSRAM YYWW V Y

Part Number Code

EIA Date Intensity

Code Color Bin

IDOD5201

C1 C2 C3 C4 C5 R1

2.85 (0.112)

0.76 (0.030) typ.0.254 (0.010)

0.65 (0.026) typ.

4.81 (0.189)

HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

2006-01-23 3

Maximum Ratings at 25°C

Parameter Symbol Value Unit

Operating temperature range Top – 40 … + 85 °C

Storage temperature range Tstg – 40 … + 100 °C

DC Supply Voltage, VCC to GND

(max. voltage with no LEDs on) VCC -0.3 to + 7.0 V

Input Voltage Levels

All inputs -0.3 to VCC +0.3 V

Operating Voltage, VCC to GND

(max. voltage with 20 dots/digits on) + 5.5 V

Solder temperature 063“ (1.59 mm)

below seating plane, t < 5.0 s TS260 °C

Relative Humidity at 85°C (non-condensing) 85 %

ESD (100 pF, 1.5 kΩ), each pin VZ4.0 kV

Optical Characteristics at 25°C

(VLL=VCC=5.0 V at 100% brightness level, viewing angle: X axis ± 55°, Y axis ± 65°)

Description Symbol Values Unit

Red

HSDP2110S

Yellow

HSDP2111S

High Efficiency Red

HSDP2112S

Green

HSDP2113S

High Efficiency Green

HSDP2114S

Soft Orange

HSDP2115S

Peak Luminous Intensity (min.)

(typ.) IVpeak 70

90 130

210 150

330 150

260 200

510 150

270 µcd/dot

µcd/dot

Peak Wavelength (typ.) λpeak 660 583 630 565 568 610 nm

Dominant Wavelength (typ.) λdom 639 585 620 570 574 604 nm

Note:

1) Peak luminous intensity is measured at TA=TJ=25°C. No time is allowed for the device to warm up prior to measurement.

2006-01-23 4

HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

Write Cycle Timing Diagram (Input pulse levels –0.6 V to 2.4 V)

Read Cycle Timing Diagram

Switching Specifications

(over operating temperature range and VCC=4.5 V)

Symbol Description Min. Units Symbol Description Min. Units

Tacc Display Access Time—Write 210 ns Tdh Data Write Time 20 ns

Tacc Display Access Time—Read 230 ns TrChip Enable Active Prior to Valid Data 160 ns

Tacs Address Setup Time to CE 10 ns Trd Read Active Prior to V alid Data 95 µs

Tce Chip Enable Active Time—Write 140 ns Tdf Read Data Float Delay 10 ns

Tce Chip Enable Active Time—Read 160 ns Trc Reset Active Time 300 ns

Tach Address Hold Time to CE 20 ns TwWrite Active Time 100 ns

Tces Chip Enable Active Prior to

Rising Edge—Write 140 ns Twd Data Valid Prior to

Rising Edge of Write Signal 50 ns

Tces Chip Enable Active Prior to

Rising Edge—Read 160 ns Tceh Chip Enable Hold to Rising Edge of

Read/Write Signal 0ns

Tcer Chip Enable Recovery Time 60 ns

Tacc

Twd Tdh

Tces

Tcer

Tceh

Tacs Tach Tacs

0-A3

Tce

0-D7

nput pulse levels —0.6 V to 2.4 v

Tacc

Trd Tdf

TrTces

Tcer

Tceh

Tacs Tach Tacs

0-A3

Tce

0-D7

HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

2006-01-23 5

Cascading Displays

The HDSP211XS oscillator is designed to drive up to 16 other HDSP211XSs with input loading of 15 pF each.

The following are the general requirements for cascading 16 displays together:

• Determine the correct address for each display.

• Use CE from an address decoder to select the correct display.

• Select one of the Displays to pro vide the clock for the other displays. Connect CLKSEL to VCC for this display.

• Tie CLKSEL to ground on other displays.

• Use RTS to synchronize the blinking between the displays.

Cascading Diagram

IDCD5031

RD WR FL CLK CLK

Display

D0-D7 A0-A4 CE

Up to 14 more

displays in between

I/O SEL

Display

D0-D7 A0-A4

Data I/O

Address

Decoder

Address Address Decode Chip 1 to 14

RST

RSTRD WR FL CLK

SEL

CLK

I/O

2006-01-23 6

HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

Electrical Characteristics at 25°C

Parameters Limits Conditions

Min. Typ. Max. Units

VCC 4.5 5.0 5.5 V —

ICC Blank —0.65 1.0 mA VCC=5.0 V, VIN=5.0 V

ICC 12 dots/digit on (1) (2) —185 255 mA VCC=5.0 V, “V” in all 8 digits

ICC 20 dots/digit on (1) (2) —284 370 mA VCC=5.0 V, “#” in all 8 digits

IILP (with pull-up)

Input Leakage –18 –11 –5.0 µA VCC=5.0 V, VIN=0 V to VCC,

(WR, CE, FL, RST, RD, CLKSEL)

IIL (no pull-up)

Input Leakage –1.0 —+1.0 µA VCC=5.0 V, VIN=0–5 V,

(CLK, A0–A3, D0–D7)

VIH

Input Voltage High 2.0 —VCC

+0.3 VVCC=4.5 V to 5.5 V

VIL

Input Voltage Low GND

–0.3 ——V VCC=4.5 V to 5.5 V

VOL (D0–D7), Output Voltage Low — — 0.4 VVCC=4.5 V, IOL=1.6 mA

VOL (CLK), Output Voltage Low — — 0.4 VVCC=4.5 V, IOL= 40 µA

VOH Output Voltage High 2.4 ——V VCC=4.5 V, IOH= –40 µA

θJC Thermal Resistance,

Junction to Case —25 — °C/W —

Clock I/O Frequency 28 57.34 81.14 kHz VCC=4.5 to 5.5 V

FM, Digit Multiplex Frequency 125 256 362.5 Hz VCC=4.5 to 5.5 V

Blinking Rate 0.98 2.0 2.83 Hz —

Clock I/O Buss Loading — — 2.40 pF —

Clock Out Rise Time — — 500 nsec VCC=4.5 V, VOH=2.4 V

Clock Out Fall Time — — 500 nsec VCC=4.5 V, VOH=0.4 V

Notes:

1) ICC is an average value.

2) ICC is measured with the display at full brightness. Peak ICC= 28/15 ICC average (#displayed).

Recommended Operating Conditions (TA=–40°C to +85°C)

Parameter Symbol Min. Max. Units

Supply Voltage VCC 4.5 5.5 V

Input Voltage Low VIL —0.8 V

Input Voltage High VIH 2.0 — V

Output Voltage Low VOL —0.4 V

Output Voltage High VOH 2.4 — V

HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

2006-01-23 7

Top View

Pin Assignment

IDPA5114

01234567

Digit

Pins1

28 Pins 15

Pin Function Definition Pin Function Definition

1RST Used to initialize a displa y and sychroniz e

blinking for multiple displays 15 GND supply Analog Ground for LED drivers

2FL Low input accesses the Flash RAM 16 GND logic Digital Ground for internal drivers

3A0 Address input LSB 17 CE Enables access to the display

4A1 Address input 18 RD A low will r ead data from the display if CE

is low. If read from display is not required,

5A2 Address input MSB 19 D0 Data input LSB

6A3 Mode selector 20 D1 Data input

7VCC Optional connection to positive

power supply input.

21 No pin —

8VCC 22 No pin —

9VCC 23 D2 Data input

10 A4 Mode Selector 24 D3 Data input

11 CLKSEL Selects internal/high clock source 25 D4 Data input

12 CLK I/O Outputs master clock or inputs

external clock 26 D5 Data input

13 WR A low will write data into the display if CE

is low 27 D6 Data input

14 VCC Positive power supply input 28 D7 Data input MSB, selects ROM,

page 1 or 2

2006-01-23 8

HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

Character Set

Notes:

1. Upon power up, the device will initialize in a random state.

2. X=don’t care.

IDCS5086

ASCII

CODE

HEX

D4D5D7

LLL

HLL

LHL

LHH

LLL

LLH

LHL

LHH

HXXX

8UDC

0UDC

1UDC

2UDC

3UDC

4UDC

5UDC

6UDC

7UDC

8UDC

9UDC

10 UDC

11 UDC

12 UDC

14 UDC

1513

UDC

HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

2006-01-23 9

Block Diagram

Functional Description

The display' s user interface is org anized into fiv e memory

areas. The y are accessed using the Fl ash Input, FL , and

address lines, A3 and A4. All the listed RAMs and Regis-

ters may be read or written through the data bus. See

Table „Memory Selection“. Each input pin is described in

Pin Definitions.

RST can be used to initialize display operation upon

power up or du ring normal operation. When activated,

RST will clear the Flash RAM and Control Word Register

(00H) and reset the internal counter. All eight display

memory locations will be set to 20H to show blanks in all

digits.

FL pin enables access to the Flash RAM. The Flash

RAM will set (D0=1) or reset (D0=0) flashing of the char-

acter addressed by A0– A2.

The 1 x 8 bit Control Word Register is loaded with

attribute data if A3=0.

The Control Word Logic decodes attribute data for

proper implementation.

Character ROM is designed for 128 ASCII characters.

The ROM is Mask Programmable for custom fonts.

The Clock Source could either be the internal oscillator

(CLKSEL=1) of the device or an external clock

(CLKSEL=0) could be an input from another HDSP211X

display for the synch ronization of blinking for multiple dis-

plays.

The Display Multiplexer controls the Row Drivers so no

additional logic is required for a display system.

The Display has eight digits. Each digit has 35 LEDs

cluste re d in to a 5 x 7 do t m a trix.

IDBD5064

OSC

Counter Counter

8 Digit Display

Drivers

Counter

128

Counter

Decode

RAM

Character

RAM

D Latch

Holding

Word

ROM

for Display

Decode

Character

(Read/Write)

Character

Decode

Address

UDC

Bus

Row

ROM

4RAM

16 UDC

Column

Latch

Master

Slave

5 25

and

Controls

Cursor

Display

MUX

Word

Control

Test

Self Flash

RAM

Drivers

Column

Data

Five Basic Memory Areas

Character RAM Stores either ASCII (Katakana)

character data or an UDC RAM

address

Flash RAM 1 x 8 RAM whic h stores Flash data

User-Defined

Character RAM

(UDC RAM)

Stores dot pattern for custom

characters

User-Defined Address

Provides address to UDC RAM

when user is writing or reading

custom character

Control Word

brightnes s, flash indivi dual

characters, blink, self test or clearing

the display

HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

2006-01-23 10

Theory of operation

The HDSP211XS Programmable Display is designed to work with

all major microprocessors. Data entry is via an eight bit parallel

bus. Three bits of address route the data to the proper digit loca-

tion in the RAM. Standard control signals like WR and CE allow

the data to be written into the display.

D0–D7 data bits are used for both Character RAM and control

word data input. A3 acts as the mode selector.

If A3=1, character RAM is selected. Then input data bit D7 will

determine whether input data bits D0–D6 is ASCII coded data

(D7=0) or UDC data (D7=1). See section on UDC Address Regis-

ter and RAM.

For normal operation FL pin should be held high. When FL is held

low, Flash RAM is accessed to set character blinking.

The seven bit ASCII code is de coded by the Character ROM to

generate Column data. Twenty columns worth of data is sent out

each display cycle , and it tak es f ourteen display cycles to write into

eight digits.

The rows are multiplexed in two sets of seven rows each. The

internal timing and control logic s ynchronizes the tur n ing on of

rows and presentation of column data to assure proper display

operation.

Power Up Sequence

Upon power up display will come on at random. Thus the display

should be reset on power-up. The reset will clear the Flash RAM,

Control Word Register and reset the internal counter. All the dig-

its will show blanks and display brightness level will be 100%.

The display must not be accessed until three clock pulses

(110 µseconds minimum using the internal clock) after the rising

edge of the reset line.

Microprocessor interface

The interface to a microprocessor is through the 8-bit data bus

(D0–D7), the 4- bi t a ddr e ss bus (A0–A3) an d co ntr o l l in es FL , CE

and WR.

To write data (ASCII/Control Word) into the display CE should be

held low, address and data signals stable and WR should be

brought low. The data is written on the low to high transition of

WR.

The Control Word is decoded by the Control Word Decode Logic.

Each code has a different function. The code for display brightness

changes the duty cycle for the column drivers. The peak LED cur-

rent stays the same but the average LED current diminishes

depending on the intensity level.

The character Flash Enable causes 2.0 Hz coming out of the

counter to be ANDED with column drive signal and makes the col-

umn driver t o cycle a t 2. 0 Hz. Th us th e ch ar a ct er fla shes at 2 .0 Hz .

The display Blink works the same way as the Flash Enable but

causes all twen ty column driv ers to cycle at 2.0 Hz th ereb y making

all eight digits to blink at 2.0 Hz.

The Self Test function of the IC consists of two internal routines

which exercise major por tions of the IC and illuminates all the

LEDs.

Clear bit clears the character RAM and writes a blank into the dis-

play memory. It however does not clear the control word.

ASCII Data or Control Word Data can be written into the display at

this point. For multiple displa y operation, CLK I/O must be properly

selected. CLK I/O will output the internal clock if CLKSEL=1, or will

allow input from an external clock if CLKSEL=0.

Character RAM

The Character RAM is selected when FL, A4 and A3 are set to

1,1,1 during a read or write cycle. The Character RAM is a 8 by 8

bit RAM with each of the eight locations corresponding to a digit on

the displa y. Digit 0 is on the left side of the display and digit 7 is on

the right side of the display. Address lines, A2–A0 select the digit

address with A2 being the most significant bit and A0 being the

least significant bit. The two types of data stored in the Character

RAM are the ASCII coded data and the UDC Address Data. The

type of data stored in th e Character R AM is determined b y data bit,

D7. If D7 is low, then ASCII coded data is stored in data bits D6–

D0. If D7 is high, then UDC Address Data is stored in data bit D3–

D0.

The ASCII coded data is a 7 bit code used to select one of 128

ASCII characters permanently stored in the ASCII ROM.

The UDC Address data is a 4 bit code us ed to select on e of the

UDC characters in the UDC RAM. There are up to 16 characters

available. See Ta ble „Character RAM Access Logic“ (page 11).

UDC Address Register and UDC RAM

The UDC Address Register and UDC RAM allows the user to gen-

erate and store up to 16 custom characters. Each custom charac-

ter is defined in 5 x 7 dot matrix pattern. It takes 8 write cycles to

define a custom character, one cycle to load the UDC Address

UDC Address Re gister w ill store the 4 bi t addr ess f or one of t he 16

UDC RAM locations. The UDC RAM is used to store the custom

character.

Memory Selection

FL A4 A3 Section of Memory A2–A0 Data Bits Used

0XX F lash RAM Character Address D0

100 UDC Address Register Don’t Care D3–D0

101 UDC RAM Row Address D4–D0

111 Chara c ter RAM Character Address D7–D0

110 Control Word Register Don’t Care D7–D0

HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

2006-01-23 11

UDC Address Register

The UDC Address Register is selected by setting FL=1, A4=0,

A3=0. It is a 4 bit register and uses data bits, D3–D0 to store the

4 bit address code ( D7–D4 are ignored). The address code selects

one of 16 UDC RAM locations for custom character generation.

UDC RAM

The UDC RAM is selected by setting FL=1, A4=0, A3=1. The RAM

is comprised of a 7 x 5 bit RAM. As shown in Table „Flash RAM

Access Logic“ (page 12), address lines, A2–A0 select one of the

7 rows of the custom character. Data bits, D4–D0 determine the

5 bits of column data in each row. Each data bit corresponds to a

LED. I f the data bit is h igh, then the LED is o n. If the data bit is lo w,

the LED is off. To create a character , each of the 7 rows of column

data need to be defined. See Tables „UDCAddress Register and

UDC Character RAM“ (page 11) and „UDC Character Map“

(page 12) for logic.

Flash RAM

The Flash RAM allo w s the displ a y to flash one or mo re of t he char -

acters being displayed. The Flash Ram is accessed by setting FL

low. A4 and A3 are ignore d. The Flash RA M is a 8 x 1 bit RAM with

each bit corresp on di ng to a d i gi t a ddr e ss. Digit 0 i s o n the left side

of the displa y and d igit 7 is on the right side of t he displa y. Addre ss

lines, A2–A0 sel ect the digi t addr ess with A2 be ing the most signif -

icant digit and A0 being the least significant digit. Data bit, D0, sets

and resets the flash bit f or each dig it. When D 0 is high, the fla sh bit

is set and when D0 is low, It is reset. See Table „Flash RAM

Access Logic“ (page 12).

Contro l Word

The Control Word is used to set up the attributes required by the

user. It is addressed by setting FL=1, A4=1, A3=0. The Control

Word is an 8 bit register and is accessed using data bits, D7–D0.

See Table „Control Word Access Logic“ (page 12) and Figure

„Control Word Data Definition“ (page 13) for the logic and attrib-

uted control. The Control Word has 5 functions. They are bright-

ness control, flashing ch aracter enable, blinking character en able,

self test, and clear (Flash and Character RAMS only).

Brightness Control

Control Word bits, D2–D0, control the brightness of the display

with a binary code of 000 being 100% brightness and 111 being

display blank. S ee Figure „Contro l Word D ata Definition“ (page 13)

for brightness level versus binary code. The average ICC can be

calculated by multiplying the 100% brightness level ICC value by

the display’s brightness level. For example, a display set to 80%

brightness with a 100% average ICC value of 200 mA will have an

average ICC value of 200 mA x 80%=160 mA.

Flash Fu nc tion

Control Word bit, D3, enables or disables the Flash Function.

When D3 is 1, the Flash Function is enabled and any digit with its

corresponding bit set in the Flash RAM will flash at approximately

2.0 Hz. When using an external clock, the flash rate can be deter-

mined by dividing the clock rate by 28,672. When D3 is 0, the

Flash Function is disabled and the contents of the Flash RAM is

ignored. For synchronized flashing on mul ti ple di splays , see the

Reset Section (page 12)..

Character RAM Access Logic

RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

1 001111Character Address for Digits 0–7 0 7 bit ASCII code for a Write Cycle

1 010111Character Address for Digits 0–7 0 7 bit ASCII code read d uring a Read Cycle

1 001100Character Address for Digits 0–7 1 D3–D0=UDC address for a Write Cycle

1 010100Character Address for Digits 0–7 1 D3–D0=UDC address for Read Data

UDC Address Register and UDC Character RAM

RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

1 001100Not used for UDC

Address Register D3–D0=UDC RAM Address Code for Write

Cycle UDC

Address

1 010100Not used for UDC

Address Register D3–D0=UDC RAM Address Code for Read

Cycle

1 001101A2–A0=Character

Row Address D4–D0=Character Column Data for

Write Cycle UDC

RAM

1 010101A2–A0=Character

Row Address D4–D0=Character Column Data read

during a Read Cycle

HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

2006-01-23 12

Blink Function

Control W ord bit, D 4, enab les or disab les the Blin k Function. When

D4 is 1, the Bli nk Functi on is enab l ed an d all ch ar acters on the dis-

play will blink at appro ximately 2.0 Hz. The Blink Function will over-

ride the Flash Function if bot h functions are enabled. When D4 is 0,

the Blink Function is disabled. When using an external clock, the

blink rate can be determined by dividing the clock rate by 28,672.

For synchronized blinking on multiple displays, see the Reset Sec-

tion.

Self Test

Before starting Self Test, Reset must first be activated. Control

Word bits, D6 and D5, are used for the Self Test Function. When

D6 is 1, the Self Test is initiated. Results of the Self Test are stored

in bits D5. Control Word bit, D5, is a read only bit. When D5 is 1,

Self Test passed is indicated. When D5 is 0, Self Test failed is indi-

cated. The Self Test function of the IC consists of two internal rou-

tines which exercise major portions of the IC and illuminates all of

the LEDs. The first rou tine cycles the ASCII decoder R OM throug h

all states and performs a check sum on the output. If the check

sum agrees with the correct value, D5 is set to a 1.

The second routine provides a visual test of the LEDs using the

drive circuitry. This is accomplished by writing checkered and

inverse checkered patterns to the display. Each pattern is dis-

played f o r ap proximate ly 2. 0 se cond s. During the self te st fu ncti o n

the displa y must not be accesse d. The time need ed to ex ecute the

self test function is calculated by multiplying the clock time by

262,144 (typical time = 4.6 sec.). At the end of the self test func-

tion, the Character RAM is loaded with blanks; the Control Word

and the UDC Address Register is set to all 1.0 s.

Clear Function (see Table „Clear Function“ (page 13) and Figure

„Control Word Data Definition“ (page 13))

Control Word bit, D7 clears the character RAM to 20 hex and the

flash RAM to all zeroes. The RAMs are cleared within three clock

cycles (110 µs minimum, using the internal clock) when D7 is set

to 1. During the clear time the display must not be accessed.

When the clear function is finished, bit 7 of the

Control Word RAM will be reset to a “0”.

Reset Function

The display should be reset on power up of the display

(RST=LO W). When th e displa y i s reset, the Char acter RAM , Flash

RAM, and Control Word Register are cleared.

The display's internal counters are reset. Reset cycle takes three

clock cycles (110 µsec onds minim um us ing the inte rnal clock) .The

display must not be accessed during this time.

To synchronize the flashing and blinking of multiple displays, it is

necessary for the display to use a commo n cloc k source a nd reset

all the displays at the same time to start the internal counters at

the same place.

While RST is low, the display must not be accessed by RD nor

WR.

UDC Character Map

Row Data

A2 A1 A0 Row #

Column Data

C1 C2 C3 C4 C5

D4 D3 D2 D1 D0

0001

5 x 7

Dot Matrix

Pattern

0012

0103

0114

1005

1016

1107

Flash RAM Access Logic

RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 1 0 X X Flash RAM Address

for Digits 0–7 D0=Flash Data, 0-Flash O ff and 1=Flash On (Write Cycle)

1 0 1 0 0 X X Flash RAM Address

for Digits 0–7 D0=Flash Data, 0-Flash Off a nd 1=Flash On (Read Cycle)

Control Word Access Logic

RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

1 001110Not us ed for Cont rol Word Control Word data for a Write Cycle,

see Figure „Control Word Data Definition“ (page 13)

1 010110Not us ed for Cont rol Word Control Word data for a Read during a Read Cycle

HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

2006-01-23 13

Control Word Data Definition

Clear Function

CE WR FL AL A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation

XClear disabled

Clear user RAM, page RAM,

flash RAM and display

X=don’t care

Display Cycle Using Built -in RO M Exa mple

Display message “Showtime.” Dig it 0 is leftmost—closest to pin 1.

Logic levels: 0=Low, 1=High, X=Don’t care

RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation Display

0 X 1 1 1 X X X X X X X X X X X X X Reset. No Read/Write

Within 3 Clock Cycles All Blank

1 0 0 1 1 1 0 X X X 0 0 X 0 0 0 1 1 53% Brightness

Selected All Blank

1 0 0 1 1 1 1 0 0 0 0 1 0 1 0 0 1 1 Write “S” to Digit 0 S

1 0 0 1 1 1 1 0 0 1 0 1 0 0 1 0 0 0 Write “H” to Digit 1 SH

1 0 0 1 1 1 1 0 1 0 0 1 0 0 1 1 1 1 Write “O” to Di g it 2 SHO

1 0 0 1 1 1 1 0 1 1 0 1 0 1 0 1 1 1 Write “W” to Di g it 3 SHOW

1 0 0 1 1 1 1 1 0 0 0 1 0 1 0 1 0 0 Write “T” to Digit 4 SHOWT

1 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 0 1 Write “I” to Dig it 5 SHOWTI

1 0 0 1 1 1 1 1 1 0 0 1 0 0 1 1 0 1 Write “M” to Di g it 6 SHOWTIM

1 0 0 1 1 1 1 1 1 1 0 1 0 0 0 1 0 1 Write “E” to Digit 7 SHOWTIME

Key

C Clear Fu nction

ST Self test

BL Blink function

FL Flash function

Br Brightness control

IDCW5161

Function

Blink

Self Test

Function Brightness Control

D7 D6 D5 D4 D3 D2 D1 D0

D1 D0 Brightness Control

100% Brightness0080% Brightness01

1 53% Brightness0

1 40% Brightness1

Disabled

Flash FunctionD3

0Enabled1

Enabled (overrides Flash Function)

Disabled

Blink Function

Normal Operation (X = bit ignored)

XRun Self Test, R = Test Result (1 = pass, 0 = fail)

Self Test

Clear Flash RAM & Character RAM (Character RAM = 20 Hex)

Normal Operation0

Clear FunctionD7

Clear Flash

Function

27% Brightness

Blank Display11

0 20% Brightness

13% Brightness

HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

2006-01-23 14

Electrical and Mechanical Considerations

Voltage Transient Suppression

For best results power the display and the components that inter-

face with the display to avoid logic inputs higher than VCC. Addi-

tionally, the LEDs may cause transients in the power supply line

while they change display states. The common practice is to place

a parallel combinat ion of a 0.01 µF and a 22 µF capacito r betwee n

VCC and GND for all display packages.

ESD Protection

The input protection structure of the HDSP211XS provides signifi-

cant protection ag ai nst E SD dam a ge. It is capable of withstandi ng

discharges greater than 2.0 kV. Take all the standard precautions,

normal for CMOS components. These include properly grounding

personnel, tools, tables, and transport carriers that come in con-

tact with unshi elded parts. If these condi tions are not, or cannot be

met, keep the leads of the device shorted together or the parts in

antistatic pac kaging.

Soldering Considerations

The HDSP211XS can be hand s oldered with SN6 3 s older using a

grounded iron set to 260°C.

Wave soldering is also possible following these conditions:

Preheat that does not exceed 93°C on the solder side of the PC

board or a package surface temperature of 85°C. Water soluble

organic acid flux (except carboxylic acid) or rosin-based RMA flux

without alc ohol can be used.

Direct contact with alcohol or alcohol vapor will cause degradation

of the packag e.

Wave temperature of 245°C ±5°C with a dwell betwee n 1.5 sec.

to 3.0 sec. Exposure to the wave should not exceed tempera-

tures above 260°C for five seconds at 0.063" below the seating

plane. The packages should not be immersed in the wave.

Post Solder Cleaning Procedures

The least offensive cleaning solution is hot D.I. water (60°C) for

less than 15 minutes. Addition of mild saponifiers is acceptable. Do

not use commercial dishwasher detergents.

For faster cleaning, solvents may be used. Exercise care in choos-

ing solvents as some may chemically attack the nylon package.

Maximum exposure should not exceed two minutes at elevated

temperatures. Acceptable solvents are TF (trichorotrifluorethane),

TA, 111 Trichloroethane, and unheated acetone.(1)

Note:

1) Acceptable commercial solvents are: Basic TF, Arklone, P.

Genesolv, D. Genesolv DA, Blaco-Tron TF and Blaco-Tron TA.

Unaccept able solvents cont ain a lcoho l, met hanol, methylene

chloride, ethanol, TP35, TCM, TMC, TMS+, TE, or TES. Since

many commercial mixtures exist, contact a solvent vendor for

chemical co mposi tion inform ation. Some ma jor solvent manu-

facturers are: Allied Chemical Cor poration, Specialty Chemica l

Division, Morristown, NJ; Baron- Blakeslee, Chicago, IL; Dow

Chemical, Midland, MI; E.I. DuPont de Nemours & Co., Wilm-

ington, DE.

For further information refer to Appnotes 18 and 19 at

www.osram-os.com

An alternative to soldering and cleaning the display modules is to

use sockets. Naturally, 28 pin DIP sockets .600" wide with .100"

centers work well for single displays. Multiple display assemblies

are best handled by longer SI P socke ts or DI P socke ts w hen avai l-

able for uniform package alignment. Socket manufacturers are

Aries Electronics, Inc., Frenchto wn, NJ; Garry Manuf acturing, Ne w

Brunswick, NJ; Robinson-Nugent, New Albany, IN; and Samtec

Electronic Hardward, New Albany, IN.

For further information refer to Appnote 22 at www.osram-os.com

Displaying User Defined Char act e r Example

Load character “A” into UDC-5 and then display it in digit 2

Logic levels: 0=Low, 1=High, X=Don‘t care

RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation Display

0 X 1 1 1 X X X X X X X X X X X X X Reset. No Read/W rite

Within 3 Clock Cycles All Blank

1 0 0 1 1 0 0 X X X X X X X 0 1 0 1 Select UDC-5 All Blank

1 0 0 1 1 0 1 0 0 0 X X X 0 1 1 1 0 Write into Row 1 of UDC-5 All Blank

1 0 0 1 1 0 1 0 0 1 X X X 1 0 0 0 1 Write into Row 2 of UDC-5 All Blank

1 0 0 1 1 0 1 0 1 0 X X X 1 0 0 0 1 Write into Row 3 of UDC-5 All Blank

1 0 0 1 1 0 1 0 1 1 X X X 1 1 1 1 1 Write into Row 4 of UDC-5 All Blank

1 0 0 1 1 0 1 1 0 0 X X X 1 0 0 0 1 Write into Row 5 of UDC-5 All Blank

1 0 0 1 1 0 1 1 0 1 X X X 1 0 0 0 1 Write into Row 6 of UDC-5 All Blank

1 0 0 1 1 0 1 1 1 0 X X X 1 0 0 0 1 Write into Row 7 of UDC-5 All Blank

1 0 0 1 1 1 1 0 1 0 1 X X X 0 1 0 1 Write UDC-5 into Digit 2 (Digit 2) A

HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

2006-01-23 15

Optical Considerations

The .200" high character of the HDSP21 1XS gives readability up to eight feet. Proper filter selection enhances readability over this dis-

tance.

Using filters emphasizes the contrast ratio between a lit LED and the character background. This will increase the discrimination of differ-

ent characte rs. The only li mita tion i s cost. Take into con si deration the ambi e nt l ig hti ng environmen t for the be st co st/be ne fit r atio for filters.

Incandescent (with almost no green) or fluorescent (with almost no red) lights do not have the flat spectral response of sunlight. Plastic

band-pass fi lter s are an in e x pensive and ef fective way to str ength en con tr ast r atios. The HDSP21 10/21 12S a re red /hig h effi cienc y red d is-

plays and sh oul d be ma tched w ith long wavelength p ass filte r i n the 570 n m to 590 n m r ange . Th e HDSP 2113S sho uld be match ed wi th a

yellow-green band-pass filter that peaks at 565 nm. For displays of multiple colors, neutral density grey filters offer the best compromise.

Additional contrast enhancement is gained by shading the displays. Plastic band-pass filters with built-in louvers offer the next step up in

contrast impro v ement. Plastic filter s can be impro ved further with anti-refl ectiv e coatings to reduce glar e. The trad e-off is fuzzy cha racters.

Mounting the filters close to the display reduces this effect. Take care not to overheat the plastic filter by allowing for proper air flow.

Optimal filter enhancements are gained by using circular polarized, anti-reflective, band-pass filters. The circular polarizing further

enhances contrast by reducing the light that travels through the filter and reflects back off the display to less than 1%.

Several filter manufacturers supply quality filter materials. Some of them are: Panelgraphic Corporation, W. Caldwell, NJ; SGL Homalite,

Wilmington, DE; 3M Company, Visual Products Division, St. Paul, MN; Polaroid Corporation, Polarizer Division, Cambridge, MA; Marks

Polarized Corporation, Deer Park, NY, Hoya Optics, Inc., Fremont, CA.

One last no te on mo un ting f ilter s: re ce ssi ng disp lays and bezel as se mblies is a n in expensive way to provide a shad in g effect in overhead

lighting si tuation s. Several bezel manufacturers are: R. M.F. Products, Baklava, IL; Nobody Com ponents, Gr iffith Pla stic Cor p., Burningly,

CA; Photo Chemical Products of California, Santa Monica, CA; I.E.E.-Atlas, Van Nuys, CA.

2006-01-23 16

HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S

Published by

OSRAM Opto Semiconductors GmbH

Wernerwerkstrasse 2, D-93049 Regensburg

www.osram-os.com

Attention please!

The information describes the type of component and shall not be considered as assured characteristics.

Terms of delivery and rights to change design reserved. Due to technical requirements components may contain

dangerous substances. For information on the types in question plea se contact our Sales Organization.

If printed or downloaded, please find the latest version in the Internet .

Packing

Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office.

By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing

material that is retu rned to us unsorted or which we are not obliged to a ccept, we shall have t o invoice you for any costs

incurred.

Components used in life-support devices or systems must be expressly authorized for such purpose! Critical

components1) may only be used in life-support devices or systems2) with the express written approval of OSRAM OS.

1) A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or the effectiveness of that device or system.

2) Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain

human life. If they fail, it is reasonable to assume that the health and the life of the user may be endangered.

Revision History: 2006-01-23

Previous Version: 2004-11-11

Page Subjects (major changes since last revision) Date of change

all Lead free device 2006-01-23