LT4321 PoE Ideal Diode Bridge Controller Features n n n n n n n n n n Description Reduces Heat, Eliminates Thermal Design Problems Maximizes Power Efficiency Less than 800A Quiescent Operating Current Fully Compatible with IEEE 802.3 Detection and Classification IEEE 802.3 Compliant When Paired with a Powered Device (PD) Controller Works with 2-Pair and 4-Pair PoE Applications Compatible with PoE, PoE+, and LTPoE++TM 100V Absolute Maximum Voltage H-Grade Version Operates Up to 125C 16-Lead 4mm x 4mm QFN Package Applications n n PoE/PoE+/ LTPoE++ Powered Devices DC Polarity Correction and Ideal Diode-ORing of Telecom Supplies The LT(R)4321 is a dual ideal diode bridge controller that enables a Power over Ethernet (PoE) powered device (PD) to receive power in either voltage polarity from RJ-45 data pairs, spare pairs, or both. The LT4321 and eight N-channel MOSFETs replace the eight diodes in a passive PoE rectifier bridge. The LT4321 eases thermal design and increases delivered power. An internal charge pump allows an all-NMOS bridge eliminating larger and more costly PMOS switches. The LT4321 works with 2-pair and 4-pair applications. High impedance input sense pins prevent reverse current on unused pairs. If the power source fails or is shorted, a fast turn-off minimizes reverse current transients. Unlike discrete ideal bridge solutions, the LT4321 will operate through transients without enabling the MOSFETs on unpowered pairs. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PowerPath and LTPoE++ are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application Powered Device for PoE (to 13W), PoE+ (to 25.5W), or Linear LTPoE++ (to 90W) Systems 1 0.1F DATA PAIRS 2 TG12 BG12 BG36 TG36 3 + SMAJ60A VPORT HSGATE 10F HSSRC OUTP EN IN12 LT4275 VIN 6 IN36 LT4321 IN45 EN IN78 OUTN 4 SPARE PAIRS PWRGD ISOLATED POWER SUPPLY + VOUT - RUN 5 7 GND GND BG45 TG45 TG78 BG78 4321 TA01 8 4321f For more information www.linear.com/LT4321 1 LT4321 Absolute Maximum Ratings Pin Configuration (Notes 1, 2) BG36 BG12 IN12 TG12 TOP VIEW 16 15 14 13 12 OUTP TG36 1 IN36 2 11 EN 17 OUTN IN45 3 10 EN TG45 4 6 7 8 IN78 BG78 BG45 9 5 TG78 OUTP-OUTN.............................................. -0.3V to 100V IN12, IN36, IN45, IN78........................ -2V to OUTP + 2V BG12, BG36, BG45, BG78 Voltages........... -0.3V to 100V TG12, TG36, TG45, TG78 Voltages ........................................ -0.3V to OUTP + 12V TG12-IN12 Voltage.......................................-0.3V to 12V TG36-IN36 Voltage......................................-0.3V to 12V TG45-IN45 Voltage......................................-0.3V to 12V TG78-IN78 Voltage.......................................-0.3V to 12V EN, EN,...................................................... -0.3V to 100V Operating Ambient Temperature Range LT4321I.................................................-40C to 85C LT4321H.............................................. -40C to 125C Storage Temperature Range................... -65C to 150C OUTN UF PACKAGE 16-LEAD (4mm x 4mm) PLASTIC QFN TJMAX = 125C, JC = 4.5C/W EXPOSED PAD (PIN 17) IS OUTN, MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT4321IUF#PBF LT4321IUF#TRPBF 4321 16-Lead 4mm x 4mm Plastic QFN -40C to 85C LT4321HUF#PBF LT4321HUF#TRPBF 4321 16-Lead 4mm x 4mm Plastic QFN -40C to 125C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 4321f 2 For more information www.linear.com/LT4321 LT4321 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, OUTP = 20V to 80V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN Operating Supply Range |IN12-IN36|, |IN45-IN78|, OUTP l VUVLO Undervoltage Lockout OUTP-OUTN l 20 15 TYP 17 MAX UNITS 80 V 18 V IS(DET) Total Supply Current in Detect Region OUTP < 10V l 0.8 5 A IS(OFF) Total Supply Current in Shutdown OUTP > 12V, EN < VIL and EN > VIH l 32 60 A IS(ON) Total Operating Supply Current EN > VIH or EN < VIL, OUTP > 20V l 0.5 0.8 mA Top Gate Drive INn = OUTP + VSD(MAX) + 5mV, 10A Out of TGn (Note 3) l 7.7 9.5 11 V Bottom Gate Drive 10A Out of BGn (Note 3) l 10 11.5 13 V Top Gate Pull-Up Current TGn = INn (Note 3) l 50 120 250 A Top Gate Pull-Down Current INn = OUTP - 0.25V; TGn - INn = 5V l 1.25 Bottom Gate Pull-Up Current BGn < VBG (Note 3) l 15 Bottom Gate Pull-Down Current BGn = 5V l 3 EN Pull-Up Resistance (Active Low) OUTP = 55V l 160 250 310 k EN Pull-Down Resistance (Active High) OUTP = 55V l 160 250 310 k VIH Digital Input High EN, EN l 2.6 V VBG VIL Digital Input Low EN, EN l 0.5 VENOC EN Open Circuit Voltage OUTP = 55V l 2 VSD Topside Forward Regulation Voltage INn - OUTP l Bottom Comparator Turn-On Threshold INn - OUTN l Bottom Comparator Turn-Off Threshold INn - OUTN l 2 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. mA 30 45 A mA V 2.5 3 V 2 10 18 mV -30 -15 0 mV 15 30 mV Note 2: Referenced with respect to OUTN unless otherwise specified. Note 3: All conditions for external MOSFET turn on must be met. See Table 1 and Table 2. 4321f For more information www.linear.com/LT4321 3 LT4321 Typical Performance Characteristics Total Supply Current in Ideal Bridge Mode, 2-Pair Total Supply Current in Shutdown 700 35 CURRENT (A) CURRENT (A) 30 25 20 15 10 0 20 10 30 40 50 VIN (V) 60 70 IN12 = IN45 = VIN IN36 = IN78 = 0 600 EN = EN = 0 500 400 300 200 -40C 25C 100C 125C 5 0 700 IN12 = VIN IN36 = 0 600 FLOAT IN45, IN78 EN = EN = 0 500 IN12 = IN45 = VIN IN36 = IN78 = 0V CURRENT (A) 40 100 0 80 0 20 10 30 40 50 VIN (V) 60 70 0 80 1.5 80 10 8 6 -40C 25C 100C 125C 0.5 0 0 10 20 30 40 50 OUTP (V) 60 70 4 2 0 80 0 2 4 6 VBGn (V) BGn Pull-Up Strength 30 3.0 25 2.5 OUTP = 20V OUTP = 80V IN12 - IN36 = 20V IN12 - IN36 = 30V IN12 - IN36 = 80V 160 5 0.5 2 4 6 8 10 12 VBGn (V) 4321 G07 ITG12 (A) ITG12 (mA) IBGn (mA) 1.5 1.0 0 120 2.0 10 0 12 TG Pull-Up Strength 180 140 0 10 4321 G06 TG Pull-Down Strength 3.5 15 8 4321 G05 4321 G04 35 80 12 IBGn (mA) CURRENT (A) VENOC (V) -40C 25C 100C 125C 20 70 14 1.0 60 60 16 2.0 40 INn (V) 40 50 VIN (V) BGn Pull-Down Strength 0.5 20 30 20 10 18 2.5 -0.5 0 4321 G03 EN Open Circuit Voltage 0.0 -40C 25C 100C 125C 100 3.0 OUTP = 80V 0 300 4321 G02 Input Pin Current -1.0 400 200 -40C 25C 100C 125C 4321 G01 1.0 Total Supply Current in Ideal Bridge Mode, 4-Pair 100 80 60 IN45 = IN78 = FLOAT EN = OUTP IN12 = OUTP -250mV IN36 = OUTN -50mV 0 2 4 6 VTGATE (V) 8 40 IN45 = IN78 = FLOAT EN = OUTP 20 10 4321 G08 0 0 2 4 6 VTGATE (V) 8 10 4321 G09 4321f 4 For more information www.linear.com/LT4321 LT4321 Pin Functions IN12: Data Pair Input 1. In a PoE system, IN12 connects to the center tap of the transformer connected to pins 1 and 2 on an RJ45 connector. BG36: Bottom-Side Gate Driver Output. BG36 pin pulls high with respect to OUTN when IN12 is greater than OUTP and IN36 is less than OUTN. IN36: Data Pair Input 2. In a PoE system, IN36 connects to the center tap of the transformer connected to pins 3 and 6 on an RJ45 connector. BG45: Bottom-Side Gate Driver Output. BG45 pin pulls high with respect to OUTN when IN78 is greater than OUTP and IN45 is less than OUTN. IN45: Spare Pair Input 1. In a PoE system, IN45 connects to the center tap of the transformer connected to pins 4 and 5 on an RJ45 connector. BG78: Bottom-Side Gate Driver Output. BG78 pin pulls high with respect to OUTN when IN45 is greater than OUTP and IN78 is less than OUTN. IN78: Spare Pair Input 2. In a PoE system, IN78 connects to the center tap of the transformer connected to pins 7 and 8 on an RJ45 connector. EN: Enable, Active Low. Pull down to OUTN to enable ideal diode bridge mode. EN is internally pulled up to VENOC. Tie to OUTP if the application circuit uses the EN pin to enable ideal bridge mode. TG12: Top-Side Gate Driver Output. TG12 pin pulls high with respect to IN12 when IN12 is greater than OUTP and IN36 is less than OUTN. TG36: Top-Side Gate Driver Output. TG36 pin pulls high with respect to IN36 when IN36 is greater than OUTP and IN12 is less than OUTN. TG45: Top-Side Gate Driver Output. TG45 pin pulls high with respect to IN45 when IN45 is greater than OUTP and IN78 is less than OUTN. TG78: Top-Side Gate Driver Output. TG78 pin pulls high with respect to IN78 when IN78 is greater than OUTP and IN45 is less than OUTN. EN: Enable, Active High. Pull up to enable ideal diode bridge mode. EN is internally pulled down to OUTN. Tie to OUTN if the application circuit uses the EN pin to enable ideal bridge mode. OUTP: Positive Output Voltage. OUTP is the rectified voltage from which the LT4321 draws power. OUTN: Negative Output Voltage. OUTN is the negative rectified voltage. EXPOSED PAD: The exposed pad must be electrically connected to the OUTN pin. BG12: Bottom-Side Gate Driver Output. BG12 pin pulls high with respect to OUTN when IN36 is greater than OUTP and IN12 is less than OUTN. 4321f For more information www.linear.com/LT4321 5 LT4321 Applications Information OVERVIEW 1.8 A very common application is an IEEE 802.3 powered device which is required to accept voltage in either polarity at its RJ-45 input. Polarity correction devices allow the PD to work equally well with standard or cross-over cables and endspan or midspan PSEs. They also prevent the PD from back feeding current into the Ethernet cable. PD polarity correction is commonly done with a traditional diode bridge, but this results in an efficiency loss due to the forward drop generated across two conducting diodes. This voltage drop reduces the available supply voltage and dissipates significant power. The LT4321 uses actively driven MOSFETs to nearly eliminate the forward voltage drop. By maximizing available voltage and reducing power dissipation (Figure 1), the LT4321 simplifies PD design and reduces power supply cost. It can also eliminate thermal design problems, costly heat sinks, and reduce PC board area. Some designs use ideal diode bridge circuits implemented with discrete components. These bridges often suffer from a trade-off between quiescent current and tolerance to transients and leakage. With quiescent current properly tuned for PoE, stray PCB leakage between bridge components can be enough to cause accidental turn-on, latchup, and destruction of the circuit. The LT4321 offers significant improvements over discrete solutions. The integrated bridge controller allows for sophisticated sensing and control of the PowerPathTM MOSFETs, ensuring that MOSFETs that are supposed to be off, stay off. An ideal bridge controlled by the LT4321 is tolerant to hot-plugs, input short-circuits, common mode shift, and PCB leakage in the application circuit. LT4321 (50m FETs) DIODES (S2B) IN12 = 55V IN36 = 0V IN45 = FLOAT IN78 = FLOAT 1.6 POWER DISSIPATION (W) The LT4321 is a dual ideal diode bridge controller designed to rectify two independent DC channels into a single output. The LT4321 senses the greater of the two input channels, |IN12-IN36| or |IN45-IN78|, and connects them to the output with the correct polarity. Smooth crossover between channels is guaranteed by the enforced dropout voltage, VSD. 1.4 1.2 1.0 0.8 POWER SAVED 0.6 0.4 0.2 0 0 200 600 400 800 CURRENT (mA) 1000 4321 F01 Figure 1. Power Dissipation vs Load Current OPERATING MODES Ideal Diode Bridge Mode In ideal bridge mode the LT4321 saves power by activating MOSFETs in place of power path diodes. The LT4321 enters ideal bridge mode when OUTP is greater than VUVLO and either EN or EN is asserted. When the LT4321 is enabled, it senses the inputs with respect to the output to decide which external MOSFETs to turn on. Inputs are grouped into pairs, IN12/IN36 and IN45/IN78. Within each pair, one input voltage must be greater than OUTP and one must be less than OUTN before the external MOSFETs related to that pair are enabled. For example, if IN36 is greater than OUTP and IN12 is less than OUTN, TG36 and BG12 will turn on. Table 1 and Table 2 outline the conditions that activate the ideal diode bridge. Shutdown Mode Shutdown mode is intended to keep the LT4321 quiescent current from interfering with detection and classification in a PoE system (Figure 2). The LT4321 is always in shutdown mode when OUTP < VUVLO. It can be held in shutdown mode over the full operating voltage range by deasserting both the EN and EN pins. 4321f 6 For more information www.linear.com/LT4321 LT4321 Applications Information Table 1. Conditions for Ideal Bridge Mode on IN12/IN36 PoE MODE OUTP Detect/Class < VUVLO Class/Inrush EN | EN X O Power ON > VUVLO |IN12 - IN36| < 1 IN12 IN36 IN45 IN78 X X X X > OUTP < OUTN ON OFF OFF ON < OUTN > OUTP OFF ON ON OFF BG45 BG78 > OUTN OUTP - OUTN X X TG12 TG36 BG12 BG36 OFF OFF < OUTP Table 2. Conditions for Ideal Bridge Mode on IN45/IN78 PoE MODE OUTP EN | EN Detect/Class < VUVLO X Class/Inrush O Power ON > VUVLO |IN45 - IN78| < 1 IN12 IN36 IN45 IN78 X X X X > OUTP < OUTN ON OFF OFF ON < OUTN > OUTP OFF ON ON OFF X X OUTP - OUTN TG45 TG78 OFF > OUTN OFF < OUTP Shutting down the LT4321 does not disconnect the load. The external MOSFETs are shorted gate to source and bridge current is carried by the MOSFETs' body diodes. The eight body diodes will act like two traditional diode bridges. EXTERNAL INTERFACE AND COMPONENT SELECTION At light load, the power dissipated in the forward drop of the body diodes will be less than the power dissipated by the LT4321 quiescent current. In applications with a low power sleep mode, the LT4321 can optionally be shut down to save power if the load current is less than 20mA. In PD applications, the IEEE 802.3 standard limits the port capacitance at the PD interface (CPD) to 0.12F. The LT4321 and the PD interface controller both need local bypass capacitance, but they can share the same 0.1F capacitor. If the LT4321 and the PD interface controller cannot both be positioned next to a shared bypass capacitor, split the CPD capacitance between the two chips by placing a 0.047F ceramic close to the LT4321 and another 0.047F ceramic close to the PD interface controller. 300 LT4321 SHUTDOWN MODE B2100 SCHOTTKY BRIDGE CURRENT (A) 250 200 A 0.1F ceramic capacitor must be placed across the OUTP and OUTN pins. A 10F or greater capacitance must be connected across OUTP and OUTN pins when the LT4321 is enabled. In PoE applications it is sufficient for the CPORT capacitor to be connected by the PD interface controller's hot swap FET. In non PoE applications the CPORT capacitor may be permanently connected between OUTP and OUTN. 150 100 50 0 Bypass Capacitance 0 5 15 10 VIN (V) 20 25 4321 F02 Figure 2. Leakage Current at 125C 4321f For more information www.linear.com/LT4321 7 LT4321 Applications Information Transient Voltage Suppressor The LT4321 specifies an absolute maximum voltage of 100V and is designed to tolerate brief overvoltage events. However, pins that interface to Ethernet cables or remote telecom supplies can routinely see excessive peak voltages. To protect the LT4321, install a unidirectional transient voltage suppressor (TVS) such as an SMAJ60A between OUTP and OUTN. This TVS must be mounted as close as possible to the LT4321. For extremely high cable discharge and surge protection contact Linear Technology Applications. MOSFET Selection Select external MOSFETs that have a drain-source breakdown voltage higher than the maximum input voltage. For PoE systems the drain-source breakdown should be at least 100V. For all applications the gate threshold must be a minimum of 2V. The amount of power saved by the LT4321 depends on the channel resistance, RDS(ON), of the external MOSFETs. To maximize performance and power savings select RDS(ON) such that the forward voltage drop, VF, is between 20mV and 70mV. Given the average output load current, IAVG: RDS(ON) = VF/IAVG For example, a PoE+ class 4 PD's maximum average current, IAVG, is 600mA. Choosing a MOSFET forward voltage drop of 40mV reduces power consumption to 1/15th that of a B2100 Schottky diode bridge. RDS(ON) = 40mV/600mA = 66m Enable Pins When OUTP is greater than VUVLO, the enable pins EN and EN will control whether the LT4321 is in shutdown mode or ideal bridge mode (Table 1 and Table 2). EN and EN may be driven by a 3.3V or 5V logic signal, or with an open drain or collector. The EN pin is pulled up to the internally generated voltage VENOC by an internal 250k resistor. The EN pin is pulled down to OUTN by an internal 250k resistor. When OUTP is less than 12V the enable pins are high impedance to prevent these resistors from corrupting PoE detection. The enable pins tolerate 100V (absolute maximum) and may be tied directly to the OUTP or OUTN pins as needed. Figure 3 and Figure 4 show how to interface the enable pins to a PD interface controller. In these configurations, the LT4321 PoE ideal bridge will be enabled after detection and classification are complete and before the PD is consuming a significant amount of current. 4321f 8 For more information www.linear.com/LT4321 LT4321 Applications Information + 0.1F VPORT 100k OUTP EN HSGATE 10F HSSRC LT4275 VIN LT4321 EN PWRGD ISOLATED POWER SUPPLY GND OUTN + VOUT - RUN GND 4321 F03 Figure 3. PD Interface Using the EN Pin OUTP LT4321 EN 100k GND 0.1F PWRGD VIN 10F PWRGD 100k ISOLATED POWER SUPPLY RUN + VOUT - LTC4265 EN OUTN + VIN VOUT RTN 4321 F04 Figure 4. PD Interface Using the EN Pin 4321f For more information www.linear.com/LT4321 9 LT4321 Typical Applications High Efficiency 25W PD Solution with 12VDC and 24VAC Auxiliary Input BSZ110N06NS3 x4 TG2 TG1 LT4320 VAUX 9V TO 57VDC OR 24VAC PSMN075-100MSE x4 OUTP IN1 IN2 1F BG2 BG1 MMSD4148 x3 OUTN PSMN075-100MSE 1 0.1F DATA PAIRS 2 TG12 BG12 3 OUTP VPORT SMAJ60A 0.1F 6 IN36 HSGATE HSSRC LT4275B RCLASS AUX LT4321 IN45 EN IN78 OUTN 150nF 34.8 931k 4 680F VIN 3.3k 158k EN IN12 SPARE PAIRS + BG36 TG36 PWRGD GND IEEEUVLO 100k ISOLATED POWER SUPPLY + VOUT - RUN GND 4321 TA02 5 BG45 TG45 7 TG78 BG78 8 WURTH 749022017 PSMN075-100MSE x4 4321f 10 For more information www.linear.com/LT4321 LT4321 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UF Package 16-Lead Plastic QFN (4mm x 4mm) (Reference LTC DWG # 05-08-1692 Rev O) 0.72 0.05 4.35 0.05 2.15 0.05 2.90 0.05 (4 SIDES) PACKAGE OUTLINE 0.30 0.05 0.65 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW--EXPOSED PAD 4.00 0.10 (4 SIDES) 0.75 0.05 R = 0.115 TYP 15 PIN 1 NOTCH R = 0.20 TYP OR 0.35 x 45 CHAMFER 16 0.55 0.20 PIN 1 TOP MARK (NOTE 6) 1 2.15 0.10 (4-SIDES) 2 (UF16) QFN 10-04 0.200 REF 0.00 - 0.05 0.30 0.05 0.65 BSC NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4321f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more information www.linear.com/LT4321 tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LT4321 Typical Application LTPoE++ 70W Powered Device PSMN075-100MSE x4 PSMN040-100MSE 1 0.1F DATA PAIRS 2 BG36 TG36 TG12 BG12 3 OUTP VPORT HSSRC RCLASS++ SMAJ60A EN IN12 + HSGATE LT4275 IN36 AUX 4 IN78 SPARE PAIRS 64.9 100k 47nF 76.8 PWRGD EN LT4321 IN45 GND VIN 3.3k RCLASS 6 22F ISOLATED POWER SUPPLY + VOUT - RUN IEEEUVLO GND OUTN 5 4321 TA03 BG45 TG45 7 TG78 BG78 8 WURTH 749022016 PSMN075-100MSE x4 Related Parts PART NUMBER DESCRIPTION COMMENTS LTC4265 IEEE 802.3at PD Interface Controller LTC4266/LTC4266A/ LTC4266C Quad PoE PSE Controller Internal 100V, 1A Switch, 2-Event Classification Recognition IEEE 802.3at, LTPoE++, IEEE 802.3af Power Levels LTC4269-1/ LTC4269-2 IEEE 802.3af PD Interface with Switching Regulator 12-Port PoE/PoE+/LTPoE++ PSE Controller LTC4270/LTC4271 LTC4269-1 for Flyback, LTC4269-2 for Forward Regulator Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE++ PDs LTC4274/LTC4274A/ LTC4274C Single PoE PSE Controller IEEE 802.3at, LTPoE++ 90W, IEEE 802.3af Power Levels LT4275A/LT4275B/ LT4275C LTPoE++/PoE+/PoE PD Controller External Switch, LTPoE++ Support LTC4278 IEEE 802.3af PD Interface with Integrated Flyback Switching Regulator 8-Port PoE/PoE+/LTPoE++ PSE Controller 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller, 50kHz to 250kHz, 12V Aux Support LT4320 Ideal Diode Bridge Controller 9V to 72V, DC to 600Hz, N-Channel Ideal Diode Bridge LTC4354 Negative Voltage Diode-OR Controller Controls Two N-Channel MOSFETs, 1.2s Turn-Off, -80V Operation and Monitor LTC4355 Positive Voltage Diode-OR Controller and Monitor Controls Two N-Channel MOSFETs, 0.4s Turn-Off, 9V to 80V Operation LTC4359 Ideal Diode Controller with Reverse Input Protection N-Channel, 4V to 80V, MSOP-8 and DFN-6 Packages LTC4290/LTC4271 Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE++ PDs 4321f 12 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LT4321 (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LT4321 LT 0913 * PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2013