SN65LVDS1 SN65LVDS2 SN65LVDT2 www.ti.com.................................................................................................................................................... SLLS373K - JULY 1999 - REVISED NOVEMBER 2008 HIGH-SPEED DIFFERENTIAL LINE DRIVER/RECEIVERS FEATURES 1 * * Meets or Exceeds the ANSI TIA/EIA-644A Standard Designed for Signaling Rates The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second) * * * * * * * * * * * * up to: - 630 Mbps Drivers - 400 Mbps Receivers Operates From a 2.4-V to 3.6-V Supply Available in SOT-23 and SOIC Packages Bus-Terminal ESD Exceeds 9 kV Low-Voltage Differential Signaling With Typical Output Voltages of 350 mV Into a 100- Load Propagation Delay Times - 1.7 ns Typical Driver - 2.5 ns Typical Receiver Power Dissipation at 200 MHz - 25 mW Typical Driver - 60 mW Typical Receiver LVDT Receiver Includes Line Termination Low Voltage TTL (LVTTL) Level Driver Input Is 5-V Tolerant Driver Is Output High Impedance With VCC < 1.5 V Receiver Output and Inputs Are High Impedance With VCC < 1.5 V Receiver Open-Circuit Fail Safe Differential Input Voltage Threshold Less Than 100 mV DESCRIPTION SN65LVDS2 and SN65LVDT2 DBV Package (TOP VIEW) SN65LVDS1 DBV Package (TOP VIEW) VCC 1 GND 2 Z 3 5 VCC 1 GND 2 A 3 D 4 Y 5 R 4 B 110- Resistor for LVDT Only SN65LVDS1 D Package (TOP VIEW) VCC D NC GND 1 8 2 7 3 6 4 5 Z Y NC NC SN65LVDS2 and SN65LVDT2 D Package (TOP VIEW) B A NC NC 1 8 2 7 3 6 4 5 VCC R NC GND 110- Resistor for LVDT Only AVAILABLE OPTIONS PART NUMBER INTEGRATED TERMINATION PACKAGE PACKAGE MARKING SN65LVDS1DBV SOT23-5 SAAI SN65LVDS1D SOIC-8 LVDS1 SN65LVDS2DBV SOT23-5 SABI SN65LVDS2D SOIC-8 LVDS2 SN65LVDT2DBV SN65LVDT2D SOT23-5 SACI SOIC-8 LVDT2 The SN65LVDS1, SN65LVDS2, and SN65LVDT2 are single, low-voltage, differential line drivers and receivers in the small-outline transistor package. The outputs comply with the TIA/EIA-644A standard and provide a minimum differential output voltage magnitude of 247 mV into a 100- load at signaling rates up to 630 Mbps for drivers and 400 Mbps for receivers. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1999-2008, Texas Instruments Incorporated SN65LVDS1 SN65LVDS2 SN65LVDT2 SLLS373K - JULY 1999 - REVISED NOVEMBER 2008.................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION CONTINUED When the SN65LVDS1 is used with an LVDS receiver (such as the SN65LVDT2) in a point-to-point connection, data or clocking signals can be transmitted over printed-circuit-board traces or cables at very high rates with very low electromagnetic emissions and power consumption. The packaging, low power, low EMI, high ESD tolerance, and wide supply voltage range make the device ideal for battery-powered applications. The SN65LVDS1, SN65LVDS2, and SN65LVDT2 are characterized for operation from -40C to 85C. FUNCTION TABLES DRIVER INPUT RECEIVER OUTPUTS Z INPUTS OUTPUT VID = VA - VB R D Y H H L VID 100 mV H L L H -100 mV < VID < 100 mV ? Open L H VID -100 mV L Open H H = high level, L = low level , ? = indeterminate DRIVER EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC VCC 50 D Input 10 k 7V 5 Y or Z Output 300 k 7V 2 Submit Documentation Feedback Copyright (c) 1999-2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2 SN65LVDS1 SN65LVDS2 SN65LVDT2 www.ti.com.................................................................................................................................................... SLLS373K - JULY 1999 - REVISED NOVEMBER 2008 RECEIVER EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC VCC 300 k 300 k 5 A Input R Output B Input 7V 7V 7V 110- LVDT Only ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) PARAMETER Supply voltage range, VCC RATINGS (2) -0.5 V to 4 V (A or B) Input voltage range, VI -0.5 V to 4 V (D) -0.5 V to VCC + 2 V Output voltage, VO (Y or Z) -0.5 V to 4 V Differential input voltage magnitude, |VID| SN65LVDT2 only 1V Receiver output current, IO -12 mA to 12 mA Human-body model electrostatic discharge, HBM ESD (3) All pins 4000 V Bus pins (A, B, Y, Z) 9000 V Machine-model electrostatic discharge, MM ESD (4) 400 V Field-induced-charge device model electrostatic discharge, FCDM ESD (5) 1500 V Continuous total power dissipation, PD See Dissipation Rating Table Storage Temperature Range (non operating) (1) (2) (3) (4) (5) -65C to 150C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages are with respect to network ground terminal. Test method based upon JEDEC Standard 22, Test Method A114-A. Bus pins stressed with respect to GND and VCC separately. Test method based upon JEDEC Standard 22, Test Method A114-A. Test method based upon EIA-JEDEC JESD22-C101C. DISSIPATION RATING TABLE (1) PACKAGE TA 25C POWER RATING DERATING FACTOR ABOVE TA = 25C (1) TA = 85C POWER RATING D 725 mW 5.8 mW/C 402 mW DBV 385 mW 3.1 mW/C 200 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-K) and with no air flow. Copyright (c) 1999-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2 3 SN65LVDS1 SN65LVDS2 SN65LVDT2 SLLS373K - JULY 1999 - REVISED NOVEMBER 2008.................................................................................................................................................... www.ti.com RECOMMENDED OPERATING CONDITIONS PARAMETER MIN NOM MAX 2.4 3.3 UNIT VCC Supply voltage 3.6 V VIH High-level input voltage 2 5 V VIL Low-level input voltage 0 0.8 V TA Operating free-air temperature -40 85 C |VID| Magnitude of differential input voltage 0.1 0.6 V 0 VCC-0.8 V Input voltage (any combination of input or common-mode voltage) 4 Submit Documentation Feedback Copyright (c) 1999-2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2 SN65LVDS1 SN65LVDS2 SN65LVDT2 www.ti.com.................................................................................................................................................... SLLS373K - JULY 1999 - REVISED NOVEMBER 2008 DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) MIN (1) TYP (2) MAX RL = 100 , 2.4 VCC <3 V 200 350 454 RL = 100 , 3 VCC <3.6 V 247 350 454 See Figure 2 -50 50 1.125 1.375 -50 50 mV 25 100 mV 2 4 5.5 8 PARAMETER |VOD| Differential output voltage magnitude |VOD| Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common-mode output voltage VOC(SS) Change in steady-state common-mode output voltage between logic states VOC(PP) Peak-to-peak common-mode output voltage TEST CONDITIONS See Figure 2 VI = 0 V or VCC, No load UNIT mV V ICC Supply current IIH High-level input current VIH = 5 V 2 20 A IIL Low-level input current VIL = 0.8 V 2 10 A IOS Short-circuit output current VOY or VOZ = 0 V 3 10 IO(OFF) Power-off output current VCC = 1.5 V, VO = 3.6 V Ci Input capacitance VI = 0.4 Sin (4E6t)+0.5 V (1) (2) VI = 0 V or VCC, RL = 100 VOD = 0 V 10 -1 1 3 mA mA A pF The algebraic convention, in which the least positive (most negative) limit is designated as a minimum, is used in this data sheet. All typical values are at 25C and with a 3.3-V supply. DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX 1.5 3.1 ns 1.8 3.1 ns 0.6 1 ns 1 ns tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tr Differential output signal rise time tf Differential output signal fall time 0.7 tsk(p) Pulse skew (|tPHL - tPLH|) (2) 0.3 (1) (2) RL = 100 , CL = 10 pF, See Figure 5 UNIT ns All typical values are at 25C and with a 3.3-V supply. tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. Copyright (c) 1999-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2 5 SN65LVDS1 SN65LVDS2 SN65LVDT2 SLLS373K - JULY 1999 - REVISED NOVEMBER 2008.................................................................................................................................................... www.ti.com RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VITH+ Positive-going differential input voltage threshold VITH- Negative-going differential input voltage threshold VOH High-level output voltage VOL Low-level output voltage IOL = 8 mA ICC Supply current No load, Steady state LVDS2 Input current (A or B inputs) LVDT2 TYP (2) MAX UNIT 100 See Figure 3 mV -100 IOH = -8 mA, VCC = 2.4 V 1.9 IOH = -8 mA, VCC = 3 V 2.4 V 0.25 0.4 4 VI = 0 V, other input = 1.2 V II MIN (1) 7 -20 mA -2 VI = 2.2 V, other input = 1.2 V, VCC = 3.0 V VI = 0 V, other input open V -3 -1.2 -40 A -4 VI = 2.2 V, other input open, VCC = 3.0 V -6 -2.4 Differential input current (IIA - IIB) II(OFF) Power-off input current (A or B inputs) RT Differential input resistance CI Input Capacitance VI = 0.4sin(4E6t) + 0.5V 5.8 pF CO Output Capacitance VI = 0.4sin(4E6t) + 0.5V 3.4 pF (1) (2) LVDS2 VIA = 2.4 V VIB = 2.3 V -2 LVDS2 VCC = 0 V, VIA = VIB = 2.4 V 20 LVDT2 VCC = 0 V, VIA = VIB = 2.4 V 40 LVDT2 VIA = 2.4 V VIB = 2.2 V A IID 2 90 111 A 132 The algebraic convention, in which the least positive (most negative) limit is designated as a minimum, is used in this data sheet. All typical values are at 25C and with a 2.7-V supply. RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tsk(p) MIN TYP ( 1) MAX UNIT 1.4 2.6 3.6 ns 1.4 2.5 3.6 ns Pulse skew (|tpHL - tpLH|) (2) 0.1 0.6 ns tr Output signal rise time 0.8 1.4 ns tf Output signal fall time 0.8 1.4 ns tr(slew) CL = 10 pF, See Figure 6 Output slew rate (rising) CL = 10 pF tf(slew) (1) (2) 6 Output slew rate (falling) VCC = 3.0 V - 3.6 V 2.2 3 5.5 V/ns VCC = 2.4 V - 2.7 V 1.5 1.9 2.9 V/ns VCC = 3.0 V - 3.6 V 2.7 3.8 6 V/ns VCC = 2.4 V - 2.7 V 2.1 2.3 3.9 V/ns All typical values are at 25C and with a 2.7-V supply. tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. Submit Documentation Feedback Copyright (c) 1999-2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2 SN65LVDS1 SN65LVDS2 SN65LVDT2 www.ti.com.................................................................................................................................................... SLLS373K - JULY 1999 - REVISED NOVEMBER 2008 PARAMETER MEASUREMENT INFORMATION IOY Y II D IOZ VOD V VOY Z VI OY )V OZ 2 VOC VOZ Figure 1. Driver Voltage and Current Definitions 49.9 , 1% (2 Places) Y Input Z 50 pF VI 1.4 V VI 1V VOC VOC(PP) VOC(SS) VOC A. All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. The measurement of VOC(PP) is made on test equipment with a -3 dB bandwidth of at least 300 MHz. Figure 2. Driver Test Circuit and Definitions for the Driver Common-Mode Output Voltage IIA V IA )V A IO IB 2 VIA VIC IIB VID B R VO VIB Figure 3. Receiver Voltage and Current Definitions Copyright (c) 1999-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2 7 SN65LVDS1 SN65LVDS2 SN65LVDT2 SLLS373K - JULY 1999 - REVISED NOVEMBER 2008.................................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) 1000 100 1000 VIC + - 100 VID 10 pF, 2 Places VO 15 pF Remove for testing LVDT device. NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of < 1 ns. VIT+ 0V VID -100 mV VO 100 mV VID 0V VIT- VO NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of <1 ns. Figure 4. VIT+ and VIT- Input Voltage Threshold Test Circuit and Definitions 8 Submit Documentation Feedback Copyright (c) 1999-2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2 SN65LVDS1 SN65LVDS2 SN65LVDT2 www.ti.com.................................................................................................................................................... SLLS373K - JULY 1999 - REVISED NOVEMBER 2008 PARAMETER MEASUREMENT INFORMATION (continued) Y 100 1% VOD Input Z CL = 10 pF (2 Places) 2V 1.4 V or 1.2 V (see Note B) 0.8 V Input tPHL tPLH 100% 80% VOD(H) Output 0V VOD(L) 20% 0% tf tr A. All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. B. This point is 1.4 V with VCC = 3.3 V or 1.2 V with VCC = 2.7 V. Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal Copyright (c) 1999-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2 9 SN65LVDS1 SN65LVDS2 SN65LVDT2 SLLS373K - JULY 1999 - REVISED NOVEMBER 2008.................................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VID VIA VIB CL 10 pF VO VIA 1.4 V VIB 1V VID 0.4 V 0V -0.4 V tPHL VO tPLH VOH 80% 0.45 VCC 20% VOL tf A. tr All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. Figure 6. Receiver Timing Test Circuit and Waveforms 10 Submit Documentation Feedback Copyright (c) 1999-2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2 SN65LVDS1 SN65LVDS2 SN65LVDT2 www.ti.com.................................................................................................................................................... SLLS373K - JULY 1999 - REVISED NOVEMBER 2008 TYPICAL CHARACTERISTICS DRIVER HIGH-TO-LOW LEVEL PROPAGATION DELAY TIMES vs FREE-AIR TEMPERATURE DRIVER LOW-TO-HIGH LEVEL PROPAGATION DELAY TIMES vs FREE-AIR TEMPERATURE 1.9 2.6 2.4 t PLH - Driver High-to-Low Propagation Delay Times - ns t PHL - Driver High-to-Low Propagation Delay Times - ns VCC = 2.4 V VCC = 3 V 2.2 2 VCC = 2.7 V 1.8 VCC = 3.3 V 1.6 VCC = 3.6 V 1.4 1.2 1 -40 -20 0 20 40 60 80 VCC = 2.4 V 1.8 1.7 VCC = 2.7 V 1.6 VCC = 3.6 V 1.5 1.4 1.3 1.2 1.1 1 -40 100 -20 TA - Free-Air Temperature - C RECEIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 20 40 60 80 100 RECEIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4 VOL- Receiver Low-Level Output Voltage - V 4 VOH - Receiver High-Level Output Voltage - V 0 TA - Free-Air Temperature - C Figure 8. Figure 7. 3.5 3 2.5 VCC = 3.3 V 2 1.5 VCC = 2.7 V 1 0.5 0 -70 VCC = 3.3 V VCC = 3 V 3.5 3 2.5 VCC = 2.7 V 2 1.5 VCC = 3.3 V 1 0.5 0 -60 -50 -40 -30 -20 -10 IOH - High-Level Output Current - mA 0 0 10 20 40 50 60 70 IOL - Low-Level Output Current - mA Figure 9. Copyright (c) 1999-2008, Texas Instruments Incorporated 30 Figure 10. Submit Documentation Feedback Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2 11 SN65LVDS1 SN65LVDS2 SN65LVDT2 SLLS373K - JULY 1999 - REVISED NOVEMBER 2008.................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) RECEIVER HIGH-TO-LOW LEVEL PROPAGATION DELAY TIMES vs FREE-AIR TEMPERATURE RECEIVER LOW-TO-HIGH LEVEL PROPAGATION DELAY TIMES vs FREE-AIR TEMPERATURE t PLH - Receiver Low-to-High Level Propagation Delay time s - ns t PHL - Receiver High-to-Low level Propagation Delay Times - ns 2.9 2.85 VCC = 2.4 V 2.8 2.75 VCC = 3.6 V 2.7 2.65 VCC = 3.3 V 2.6 VCC = 3 V 2.55 2.5 VCC = 2.7 V 2.45 2.4 -40 -20 0 20 40 60 3 VCC = 2.4 V 2.9 2.8 VCC = 3.3 V 2.7 VCC = 3.6 V 2.6 2.5 VCC = 3 V 2.4 VCC = 2.7 V 2.3 2.2 -40 80 20 0 Figure 12. RISE/FALL TIME vs CAPACITIVE LOAD RISE/FALL TIME vs CAPACITIVE LOAD 60 80 100 1200 VCC = 2.5 V VCC = 3.3 V 1200 1000 tr, tf - Rise/Fall Time - ps 1000 Rise Time 800 Fall Time 600 400 Rise Time 800 600 Fall Time 400 200 200 0 0 0 5 10 15 CL - Capacitive Load - pF 20 25 0 5 10 Submit Documentation Feedback 15 20 25 CL - Capacitive Load - pF Figure 13. 12 40 Figure 11. 1400 tr, tf - Rise/Fall Time - ps -20 TA - Free-Air Temperature - C TA - Free-Air Temperature - C Figure 14. Copyright (c) 1999-2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2 SN65LVDS1 SN65LVDS2 SN65LVDT2 www.ti.com.................................................................................................................................................... SLLS373K - JULY 1999 - REVISED NOVEMBER 2008 APPLICATION INFORMATION FAIL-SAFE One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between -100 mV and 100 mV and within its recommended input common-mode voltage range. However, TI's LVDS receiver is different in how it handles the open-input circuit situation. Open circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver pulls each line of the signal pair to near VCC through 300-k resistors as shown in Figure 15. The fail-safe feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the output to a high level regardless of the differential input voltage. VCC 300 k 300 k A Rt = 100 (Typ) Y B VIT 2.3 V Figure 15. Open-Circuit Fail Safe of the LVDS Receiver It is only under these conditions that the output of the receiver is valid with less than a 100 mV differential input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that could defeat the pullup currents from the receiver and the fail-safe feature. Copyright (c) 1999-2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2 13 SN65LVDS1 SN65LVDS2 SN65LVDT2 SLLS373K - JULY 1999 - REVISED NOVEMBER 2008.................................................................................................................................................... www.ti.com Parallel Terminated 100 100 Point to Point 100 Multidrop 100 Figure 16. Typical Application Circuits 14 Submit Documentation Feedback Copyright (c) 1999-2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2 PACKAGE OPTION ADDENDUM www.ti.com 19-Oct-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SN65LVDS1D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDS1DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDS1DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDS1DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDS1DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDS1DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDS1DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDS1DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDS2D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDS2DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDS2DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDS2DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDS2DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDS2DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDS2DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDS2DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDT2D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 19-Oct-2011 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SN65LVDT2DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDT2DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDT2DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDT2DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDT2DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDT2DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart SN65LVDT2DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 19-Oct-2011 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 19-Feb-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) SN65LVDS1DBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 SN65LVDS1DBVT SOT-23 DBV 5 250 SN65LVDS1DR SOIC D 8 2500 180.0 9.0 3.15 3.2 1.4 330.0 12.4 6.4 5.2 2.1 SN65LVDS2DBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 SN65LVDS2DBVT SOT-23 DBV 5 250 180.0 9.0 3.15 W Pin1 (mm) Quadrant 8.0 Q3 4.0 8.0 Q3 8.0 12.0 Q1 1.4 4.0 8.0 Q3 3.2 1.4 4.0 8.0 Q3 SN65LVDS2DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65LVDT2DBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 SN65LVDT2DBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 SN65LVDT2DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Feb-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS1DBVR SOT-23 DBV 5 3000 182.0 182.0 20.0 SN65LVDS1DBVT SOT-23 DBV 5 250 182.0 182.0 20.0 SN65LVDS1DR SOIC D 8 2500 340.5 338.1 20.6 SN65LVDS2DBVR SOT-23 DBV 5 3000 182.0 182.0 20.0 SN65LVDS2DBVT SOT-23 DBV 5 250 182.0 182.0 20.0 SN65LVDS2DR SOIC D 8 2500 340.5 338.1 20.6 SN65LVDT2DBVR SOT-23 DBV 5 3000 182.0 182.0 20.0 SN65LVDT2DBVT SOT-23 DBV 5 250 182.0 182.0 20.0 SN65LVDT2DR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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