DATA SHEET MC100ES8011H Rev 1, 2/2005 Freescale Semiconductor Technical Data MC100ES8011H Low Voltage 1:2 Differential HSTL Low Voltage 1:2 Differential HSTL Clock Fanout Buffer MC100ES8011H Clock Fanout Buffer The MC100ES8011H is a low voltage 1:2 Differential HSTL fanout buffer. Designed for the most demanding clock distribution systems, the MC100ES8011H supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are in high performance clock distribution in computing, networking and telecommunication systems. 1:2 DIFFERENTIAL HSTL CLOCK FANOUT DRIVER Features * * * * * * * * * 1:2 differential clock fanout buffer 20 ps maximum device skew SiGe Technology Supports DC to 625 MHz operation HSTL compatible differential clock outputs HSTL compatible differential clock inputs 3.3V power supply Supports industrial temperature range Standard 8 lead SOIC package D SUFFIX 8-LEAD SOIC PACKAGE CASE 751-06 ORDERING INFORMATION VCC 1 D 2 Device Package MC100ES8011HD SO-8 MC100ES8011HDR2 SO-8 8 Q0 PIN DESCRIPTION 7 Q0 D 3 6 Q1 VEE 4 5 Q1 Pin Function D, D HSTL Data Inputs Qn, Qn HSTL Data Outputs VCC Positive Supply VEE Negative Supply Figure 1. 8-Lead Pinout (Top View) and Logic Diagram IDTTM Low Voltage 1:2 Differential HSTL Clock Fanout Buffer MC100ES8011H (c) Freescale Semiconductor, Inc., has 2005. All rights reserved. Freescale Timing Solutions Organization been acquired by Integrated Device Technology, Inc 1 MC100ES8011H Low Voltage 1:2 Differential HSTL Clock Fanout Buffer NETCOM Table 1. Absolute Maximum Ratings(1) Symbol VSUPPLY Parameter Conditions Rating Unit 3.9 V VCC + 0.3 VEE - 0.3 V V 50 100 mA mA Operating Temperature Range -40 to +85 C Storage Temperature Range -65 to +150 C Power Supply Voltage Difference between VCC & VEE VIN Input Voltage VCC - VEE 3.6V IOUT Output Current Continuous Surge TA TSTG 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 2. DC Characteristics (VCC = 3.3 V 5%; TJ = 0C to 110C)(1) Symbol Characteristic Min Typ Max Unit Condition HSTL differential input signals (D, D) VDIF Differential Input Voltage(2) 0.2 VX, IN Differential Cross Point Voltage(3) 0.25 IIN V 0.68 - 0.9 Input Current VCC - 1.3 V 150 mA 0.9 V VIN = VX 0.1V HSTL clock outputs (Q[0:1], Q[0:1]) VX, OUT Output Differential Crosspoint VOH Output High Voltage VOL Ouput Low Voltage 0.68 0.75 1 V 0.4 V 105 mA Supply Current ICC Maximum Quiescent Supply Current without output termination current 80 VCC pin (core) 1. DC characteristics are design targets and pending characterization. 2. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. 3. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. MC100ES8011H IDTTM Low Voltage 1:2 Differential HSTL Clock Fanout Buffer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 2 2 MC100ES8011H Product Group Freescale Semiconductor MC100ES8011H Low Voltage 1:2 Differential HSTL Clock Fanout Buffer NETCOM Table 3. AC Characteristics (VCC = 3.3 V 5%; TJ = 0C to 110C)(1) (2) Symbol Characteristic Min Typ Max Unit Condition HSTL differential input signals (D, D) VDIF Differential Input Voltage (peak-to-peak)(3) 0.4 VX, IN Differential Cross Point Voltage(4) 0.68 fCLK Input Frequency tPD Propagation Delay D to Q[0:1} V 0.9 V 625 MHz Differential ps Differential 700 920 1200 0.68 0.75 0.9 HSTL clock outputs (Q[0:1], Q[0:1]) VX, OUT Output Differential Crosspoint VOH Output High Voltage VOL Ouput Low Voltage VO(P-P) Differential Output Voltage (peak-to-peak) 1 V V 0.5 V 20 ps Differential Differential 0.5 V tSK(O) Output-to-Output Skew tSK(PP) Output-to-Output Skew (part-to-part) 500 ps tSK(P) Output Pulse Skew 100 ps 1 ps 800 ps tJIT(CC) tr / tf Output Cycle-to-Cycle Jitter Output Rise/Fall Times 150 20% to 80% 1. AC characteristics are design targets and pending characterization. 2. AC characteristics apply for parallel output termination of 50 to VTT. 3. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. 4. VX (AC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (AC) range and the input swing lies within the VDIF (AC) specification. Violation of VX (AC) or VDIF (AC) impacts the device propagation delay, device and part-to-part skew. IDTTM Low Voltage 1:2 Differential HSTL Clock Fanout Buffer Product Freescale TimingGroup Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor 3 MC100ES8011H MC100ES8011H 3 MC100ES8011H Low Voltage 1:2 Differential HSTL Clock Fanout Buffer Differential Pulse Generator Z = 50 NETCOM ZO = 50 RT = 50 ZO = 50 DUT MC100ES8011H RT = 50 VTT=GND VTT=GND Figure 2. MC100ES8011H AC Test Reference D VDIF=1.0V VX=0.75V D Q[0-1] Q[0-1] tPD (D to Q[0-1]) Figure 3. MC100ES8011H AC Reference Measurement Waveform (HSTL Input) MC100ES8011H IDTTM Low Voltage 1:2 Differential HSTL Clock Fanout Buffer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 4 4 MC100ES8011H Product Group Freescale Semiconductor MC100ES8011H Low Voltage 1:2 Differential HSTL Clock Fanout Buffer NETCOM PACKAGE DIMENSIONS D A 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETER. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. C 5 0.25 H E M B M 1 4 h B e X 45 A C SEATING PLANE L 0.10 A1 B 0.25 M C B S A S DIM A A1 B C D E e H h L MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0 7 D SUFFIX 8-LEAD SOIC PACKAGE CASE 751-06 IDTTM Low Voltage 1:2 Differential HSTL Clock Fanout Buffer Product Freescale TimingGroup Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor 5 MC100ES8011H MC100ES8011H 5 MC100ES8011H MPC92459 PART NUMBERS 900 Low MHz Voltage Low1:2 Voltage Differential LVDS Clock HSTL Clock Synthesizer Fanout Buffer INSERT PRODUCT NAME AND DOCUMENT TITLE NETCOM NETCOM Innovate with IDT and accelerate your future networks. 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