TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com LOW IQ, SINGLE BOOST, DUAL SYNCHRONOUS BUCK CONTROLLER Check for Samples: TPS43335-Q1, TPS43336-Q1 FEATURES 1 * * * * * * * * * * * Two Synchronous Buck Controllers One Pre-Boost Controller Input Range up to 40V, (transients up to 60V), Operation Down to 2V when Boost is enabled Low Power Mode IQ: 30A (one Buck on), 35A (two Bucks on) Low Shutdown Current Ish < 4 A Buck Output Range 0.9V to 11V Boost Output Selectable: 7V/10V/11V Programmable frequency and External Synchronization Range 150kHz to 600kHz Separate Enable Inputs (ENA, ENB) Frequency Spread Spectrum (TPS43336) Selectable Forced Continuous Mode or Automatic Low Power Mode at Light Loads * * * * * Sense Resistor or Inductor DCR Sensing Out of Phase Switching between Buck Channels Peak Gate Drive Current 0.7 A Thermally Enhanced Package - 38-Pin HTSSOP (DAP) with PowerPadTM Qualified for Automotive APPLICATIONS * * Automotive Start-Stop, Infotainment, Navigation Instrument Cluster Systems Industrial/Automotive Multi-Rail DC Power Distribution Systems and Electronic Control Units DESCRIPTION The TPS43335-Q1/TPS43336-Q1 includes two current mode synchronous buck controllers and a voltage mode boost controller. The part is ideally suited as pre-regulator stage with low Iq requirements and systems that need to survive supply drops due to cranking events. The integrated boost controller allows the device to operate down to 2V at the input without seeing a drop on the Buck regulator output stages. At light loads, the buck controllers can be enabled to operate automatically in Low Power Mode consuming just 30A of quiescent current. The buck controllers have independent soft start capability and power good indicators. External MOSFET protection is provided by current fold back in the buck controllers and cycle-by-cycle current limitation in the boost controller. The switching frequency can be programmed over 150 kHz to 600 kHz or synchronized to an external clock in the same range. Additionally, the TPS43336-Q1 offers frequency-hopping spread spectrum operation. spacer VBAT VBUCKA VBuckA VBAT TPS43335-Q1/ TPS43336-Q1 VBUCKB VBuckB 2V Figure 1. Typical Application Diagram 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011, Texas Instruments Incorporated TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TJ -40C to 150C (1) (2) (3) OPTION Frequency Hopping Spread Spectrum OFF Frequency Hopping Spread Spectrum ON PACKAGE (2) ORDERABLE PART NUMBER TPS43335QDAPQ1 DAP (3) TPS43336QDAPQ1 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. The DAP package is available in tape and reel. Add the R suffix (TPS43335QDAPR, TPS43336QDAPR) to order. space ABSOLUTE MAXIMUM RATINGS (1) Voltage Voltage (Buck Function: Buck A and Buck B) Voltage (Boost Function) Voltage (PMOS Driver) Temperature MIN MAX Input Voltage: VIN, VBAT -0.3 60 V Enable Inputs: ENA, ENB -0.3 60 V Bootstrap Inputs: CBA, CBB -0.3 68 V Phase Inputs: PHA, PHB -0.7 60 V Phase Inputs: PHA, PHB (for 150ns) -1.0 Feedback Inputs: FBA, FBB -0.3 13 V Error amplifier outputs: COMPA, COMPB -0.3 13 V High-Side MOSFET Driver: GA1-PHA, GB1-PHB -0.3 8.8 V Low-Side MOSFET Drivers: GA2, GB2 -0.3 8.8 V Current Sense Voltage: SA1, SA2, SB1, SB2 -0.3 13 V Soft Start: SSA, SSB -0.3 13 V Power Good Output: PGA, PGB -0.3 13 V Power Good Delay: DLYAB -0.3 13 V Switching Frequency Timing Resistor: RT -0.3 13 V SYNC, EXTSUP -0.3 13 V Low-Side MOSFET Driver: GC1 -0.3 8.8 V Error amplifier output: COMPC -0.3 13 V Enable Input: ENC -0.3 13 V Current Limit Sense: DS -0.3 60 V Output Voltage Select: DIV -0.3 8.8 V P-Channel MOSFET Driver: GC2 -0.3 60 V P-Channel MOSFET Driver: VIN-GC2 -0.3 8.8 V Gate Driver Supply: VREG -0.3 8.8 V Junction Temperature: TJ -40 150 C Operating Temperature: TA -40 125 C Storage Temperature: TS -55 165 2 Human Body Model (HBM) UNIT V C kV Charged Device Model (CDM) Electrostatic Discharge Ratings - FBA, FBB, RT, DLYAB 400 - VBAT, ENC, SYNC, VIN 750 - all other pins 500 V Machine Model (MM) (1) 2 - PGA, PGB 150 - all others 200 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS Buck Function: Buck A and Buck B Voltage Boost Function MIN MAX Input Voltage: VIN, VBAT 4 40 V Enable Inputs: ENA, ENB 4 40 V Boot Inputs: CBA, CBB 4 44 V -0.6 40 V Current Sense Voltage: SA1, SA2, SB1, SB2 0 11 V Power Good Output: PGA, PGB 0 11 V Power Good Delay: DLYAB 0 6 V SYNC, EXTSUP 0 9 V Error amplifier output: COMPC 0 6 V Enable Input: ENC 0 9 V 40 V Phase Inputs: PHA, PHB Voltage Sense: DS DIV 0 Thermal Resistance Junction to Ambient, JA (1) Temperature Ratings Thermal Resistance Junction to pad, JC (2) Operating Temperature: TA (1) (2) UNIT 6 C/W 10 -40 V C/W 28 125 C This assumes a JEDEC JESD 51-5 standard board with thermal vias - See Power Pad section and application note from Texas Instruments SLMA002 for more information. This assumes junction to exposed pad. Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 Submit Documentation Feedback 3 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com DC ELECTRICAL CHARACTERISTICS VIN = 8 V to 18 V, TJ = -40C to 150C (unless otherwise noted) NO. TEST (1) 1.0 Input Supply 1.1 1.2 PT PT PARAMETER VBat TEST CONDITIONS MIN Supply Voltage Boost Controller enabled, after initial start up condition is satisfied Device Operating Range Input voltage required for device on initial start up VIN Buck regulator operating range after initial start up 1.3 PT VIN 1.4 PT VBAT-Off UV Buck Undervoltage Lockout Boost unlock threshold VIN Falling PT Iq_LPM_ LPM Quiescent Current: TA = 25C (2) V 6.5 40 V 4 40 V 3.6 3.8 V 3.8 4 V 8.5 8.8 V 30 40 A 35 45 A 40 50 A 45 55 A 4.85 5.3 mA 7 7.6 mA 5 5.5 mA 3.5 8.2 VIN = 13V, BuckB: LPM, BuckA: off VIN = 13V, BuckA, B: LPM VIN = 13V, BuckA: LPM, BuckB: off 1.6 PT Iq_LPM LPM Quiescent Current: TA = 125C (2) UNIT 40 VIN = 13V, BuckA: LPM, BuckB: off 1.5 MAX 2 VIN Rising VBAT Rising TYP VIN = 13V, BuckB: LPM, BuckA: off VIN = 13V, BuckA, B: LPM Normal operation, SYNC = 5V 1.7 PT Iq_NRM Quiescent Current: TA = 25C (2) VIN = 13V, BuckA: CCM, BuckB: off VIN = 13V, BuckB: CCM, BuckA: off VIN = 13V, BuckA, B: CCM Normal operation, SYNC = 5V VIN = 13V, BuckA: CCM, BuckB: off 1.8 PT Iq_NRM Quiescent Current: TA = 125C (2) VIN = 13V, BuckA, B: CCM 7.5 8 mA 1.9 PT Ibat_sh Shutdown current ,TA = 25C BuckA, B: off, VBat = 13V 2.5 4 A 1.10 PT Ibat_sh Shutdown current ,TA = 125C BuckA, B: off, VBat = 13V 3 5 A V 2.0 Input voltage VBAT - Undervoltage lock out 2.1 PT VBATUV Boost Input Undervoltage 2.2 PT UVLOHys Hysteresis PT UVLOfilter Filter time 2.3 3.0 VOVLO Overvoltage shutdown 3.2 PT OVLOHys Hysteresis 3.3 PT OVLOfilter Filter time 4.2 1.8 1.9 2 VBAT rising 2.4 2.5 2.6 V 500 600 700 mV (based on VIN sense) Rising 45 46 47 V Falling 43 44 45 V 1 2 3 4.4 4.5 (1) (2) 4 V s 5 Boost Controller PT PT Vboost7-VIN Vboost7-th Boost VOUT = 7V Boost mode threshold Boost VOUT = 7V DIV = low, VBAT = 2 V to 7 V 7 PT PT Info Vboost10-VIN Vboost10-th Vboost11-VIN Boost VOUT = 10V Boost mode threshold Boost VOUT = 10V Boost VOUT = 11V V VBAT falling - Boost enable threshold 7.5 8 8.5 V VBAT rising - Boost disable threshold 8 8.5 9 V 0.4 0.5 0.6 V Hysteresis 4.3 s 5 PT 4.1 VBAT falling Input voltage VIN - Over voltage lock out 3.1 4.0 VIN = 13V, BuckB: CCM, BuckA: off DIV = open, VBAT = 2 V to 10 V 10 V VBAT falling - Boost enable threshold 10.5 11 11.5 V VBAT rising - Boost disable threshold 11 11.5 12 V Hysteresis 0.4 0.5 0.6 V DIV = VREG, VBAT = 2 V to 11 V 11 V PT = Production tested; CT = Characterization only, not production tested; Info = Information based on simulations and lab evaluation, not production tested Quiescent current specification is non-switching current consumption without including the current in the external feedback resistor divider. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com DC ELECTRICAL CHARACTERISTICS (continued) VIN = 8 V to 18 V, TJ = -40C to 150C (unless otherwise noted) NO. 4.6 TEST (1) Info PARAMETER Vboost11-th Boost mode threshold Boost VOUT = 11V MIN TYP MAX UNIT VBAT falling - Boost enable threshold TEST CONDITIONS 11.5 12 12.5 V VBAT rising - Boost disable threshold 12 12.5 13 V Hysteresis 0.4 0.5 0.6 V 0.2 0.225 Boost Switch current limit 4.7 PT VDS Current limit sensing 4.8 Info tDS leading edge blanking DS input with respect to PGNDA 0.175 200 V ns Gate Driver for Boost Controller 4.9 Info IGC1 4.10 PT RDS(ON) Peak Gate driver peak current Source and Sink driver 1.5 VREG = 5.8V, IGC1 current = 200mA A 2 Gate Driver for PMOS 4.11 PT RDS 4.12 PT IPMOS_ON Gate current VIN = 13.5V, Vgs = -5V PT tdelay_ON Turn ON delay C = 10nF 4.13 ON PMOS OFF 10 20 10 mA 5 10 s Boost Controller Switching frequency 4.14 PT fsw-Boost Boost Switching Frequency 4.15 PT DBoost Boost duty cycle fSW_Buck/2 kHz 90% Error Amplifier (OTA) for Boost Converters 4.16 5.0 5.1 5.2 5.3 5.4 PT GmBOOST PT PT Info PT Info VBuckA/B PT 5.6 CT 5.9 5.10 0.8 1.35 VBAT = 5V 0.35 0.65 Info CT Info CT Adjustable. output voltage range 0.9 Vref, NRM internal reference voltage in normal mode Measure FBX pin Vref, internal reference voltage in low power mode Measure FBX pin LPM PT 5.5 5.8 VBAT = 12V mmho Buck Controllers Vsense 5.7 Forward Transconductance tdead shoot through delay, blanking time DCNRM Duty cycle DCLPM Duty Cycle LPM ILPM_Entry LPM entry threshold load current as fraction of maximum set load current 0.800 -1% 0.784 Internal tolerance on reference Sense voltage in foldback FBx = 0V 11 V 0.808 V +1% 0.800 -2% V sense for reverse current limit in Minimum sense voltage FBx = 1V CCM V sense for output short ILPM_Exit Internal tolerance on reference V sense for forward current limit in Maximum sense voltage FBx = 0.75V CCM (low duty cycles) VI-Foldback Info 0.792 0.816 V +2% 60 75 90 mV -65 -37.5 -23 mV 17 32.5 48 mV High side minimum on time Maximum duty cycle (digitally controlled) 20 ns 100 ns 98.75% 80% 1% The exit threshold is specified to be always LPM exit threshold load current as higher than entry threshold fraction of maximum set load current 10% High Side external NMOS Gate Drivers for Buck Controller 5.11 Info IGX1_peak Gate driver peak current 5.12 PT RDS Source and Sink driver ON 0.7 VVREG = 5.8V, IGX1 current = 200mA A 4 4 Low Side NMOS Gate Drivers for Buck Controller 5.13 Info IGX2_peak Gate driver peak current 5.14 PT RDS Source and sink driver ON 0.7 VREG = 5.8V, IGX2 current = 200mA A Error Amplifier (OTA) for Buck Converters 5.15 5.16 6.0 6.1 PT GmBUCK Transconductance COMPA, COMPB = 0.8V, source/sink = 5A, Test in feedback loop PT IPULLUP_FBx Pull-Up Current at FBx pins 0.72 1 1.35 mmho FBx = 0V 50 100 200 nA VIN = 13V 1.7 Digital Inputs: ENA, ENB, ENC, SYNC PT Vih Higher threshold Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 Submit Documentation Feedback V 5 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com DC ELECTRICAL CHARACTERISTICS (continued) VIN = 8 V to 18 V, TJ = -40C to 150C (unless otherwise noted) NO. TEST (1) 6.2 PT Vil Lower threshold VIN = 13V 6.3 PT Rih_SYNC Resistance VSYNC = 5V, SYNC: pull down resistance 500 k 6.4 PT Ril_ENC Resistance VENC = 5V, ENC: pull down resistance 500 k pull-up current VENx = 0V, ENA, ENB: pull up current source 0.5 6.5 6 PT PARAMETER Iil_ENx Submit Documentation Feedback TEST CONDITIONS MIN TYP MAX 0.7 2 UNIT V A Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com DC ELECTRICAL CHARACTERISTICS (continued) VIN = 8 V to 18 V, TJ = -40C to 150C (unless otherwise noted) NO. TEST (1) 7.0 Boost Output Voltage: DIV PARAMETER 7.1 PT Vih_DIV Higher threshold 7.2 PT Vil_DIV Lower threshold 7.3 PT Voz_DIV open 8.0 TEST CONDITIONS MIN TYP MAX Vreg0.2 VREG = 5.8V V 0.2 floating UNIT Vreg/2 V V Switching Parameter - Buck DC-DC Controllers 8.1 PT fSW_Buck Buck switching frequency RT pin: GND 360 400 440 kHz 8.2 PT fSW_Buck Buck switching frequency RT pin: 60k external resistor 360 400 440 kHz 8.3 PT fSW_adj Buck adjustable range RT pin: using external resistor 150 600 kHz 8.4 PT fSYNC Buck synch. range External clock input 150 600 kHz 8.5 PT fSS Spread Spectrum spreading TPS43336-Q1 only 5.8V 6.1 V 0.2% 1% 7.5 7.8 V 0.2 1 % 4.6 4.8 V 9.0 5% Internal Gate Driver Supply 9.1 PT VREG 9.2 PT VREG-EXTSUP 9.3 PT VEXTSUP- Internal regulated supply VIN = 8V to 18V, EXTSUP = 0V, SYNC = high Load Regulation IVREG = 0mA to 100mA, EXTSUP = 0V, SYNC = high Internal Regulated supply EXTSUP = 8.5V Load Regulation IEXTSUP = 0mA to 125mA, SYNC = High EXTSUP = 8.5V to 13V Switch over voltage IVREG = 0mA to 100mA , EXTSUP ramping positive VREG 5.5 7.2 4.4 9.4 PT VEXTSUP-Hys Switch over hysteresis 150 250 mV 9.5 PT IREG-Limit Current Limit on VREG EXTSUP = 0V, normal mode as well as LPM 100 400 mA PT IREG_EXTSUP- Current Limit on VREG when using EXTSUP IVREG = 0mA to 100mA, EXTSUP = 8.5V, SYNC = High 125 400 mA Soft Start source current SSA and SSB = 0V 0.75 1.25 A 9.6 Limit 10.0 10.1 11.0 11.1 12.0 Soft Start PT ISSx 1 Oscillator (RT) PT VRT Oscillator reference voltage 1.2 V Power Good / Delay 12.1 PT PGpullup Pullup for A and B internal pullup to Sx2 12.2 PT PGth1 Power Good Threshold FBx falling 12.3 PT PGhys Hysteresis 12.4 PT PGdrop Voltage drop 12.5 PT 12.6 PT PGleak Leakage VSx2 = VPGx = 13V 12.7 PT tdeglitch Deglitch Time Power Good deglitch 50 -5 -7 k -9 % IPGA = 5mA 450 mV IPGA = 1mA 100 mV 1 A 16 s 2% 2 12.8 PT tdelay Reset Delay External capacitor = 1nF VBUCKX < PGth1 12.9 PT tdelay_fix Fixed Reset Delay No external capacitor, pin open 20 50 s 12.10 PT Ioh Activate current source Current to charge external capacitor 30 40 50 A PT Iil Activate current sink Current to discharge external capacitor 30 40 50 A 150 165 C 15 C 12.11 13.0 1 ms Over Temperature Protection 13.1 CT Tshutdown 13.2 CT Thys shutdown threshold Junction temperature Hysteresis Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 Submit Documentation Feedback 7 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com DEVICE INFORMATION DAP PACKAGE (TOP VIEW) VBAT 1 38 DS 2 37 GC1 3 36 DIV GC2 4 35 VREG CBA 5 34 CBB GA1 6 33 GB1 PHA 7 32 PHB GA2 8 31 9 30 SA1 10 29 SB1 SA2 11 28 SB2 FBA 12 27 13 26 SSA 14 25 SSB PGA 15 24 PGB PGNDA COMPA VIN EXTSUP GB2 PGNDB FBB COMPB ENA 16 23 AGND ENB 17 22 RT 18 21 DLYAB 19 20 SYNC COMPC ENC PIN FUNCTIONS NO. 8 NAME I/O DESCRIPTION 1 VBAT I Battery input sense for the boost controller. If the boost controller is enabled and the voltage at VBAT falls below the boost threshold, the device will activate the boost controller and regulate the voltage at VIN to the programmed boost output voltage. 2 DS I This input monitors the voltage on the external Boost converter low-side MOSFET for over current protection. Alternatively, it can be connected to a sense resistor between the source of the low-side MOSFET and ground via a filter network for better noise immunity. 3 GC1 O An external low-side N-channel MOSFET for the boost regulator can be driven from this output. This output provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG. 4 GC2 O A floating output drive to control the external P-channel MOSFET is available at this pin. This MOSFET can be used to bypass the boost rectifier diode or a reverse protection diode when the boost is not switching or disabled, and thus reduce power losses. 5 CBA I A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate drive circuitry in the buck controller BUCK A. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to re-charge. 6 GA1 O External high-side N-channel MOSFET for the buck regulator BUCK A can be driven from these output. The output provides high peak currents to drive capacitive loads. The gate drive is referred to a floating ground reference provided by the PHA and has a voltage swing provided by CBA. 7 PHA O Switching terminal of the buck regulator BUCK A, providing a floating ground reference for the high-side MOSFET gate driver circuitry and is used to sense current reversal in the inductor when discontinuous mode operation is desired. 8 GA2 O External low-side N-channel MOSFET for the buck regulator BUCK A can be driven from this output. The output provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG. 9 PGNDA O Power ground connection to the source of the low-side N-channel MOSFETs of BUCK A. 10 SA1 I 11 SA2 I High Impedance differential voltage inputs from the current sense element (sense resistor or inductor DCR) for each buck controller. The current sense element should be chosen to set the maximum current through the inductor based on the current limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle and VIN. (SA1 positive node, SA2 negative node). Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com PIN FUNCTIONS (continued) NO. NAME I/O DESCRIPTION 12 FBA I Feedback voltage pin for BUCK A. The buck controller regulates the feedback voltage to the internal reference of 0.8V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output voltage. 13 COMPA O Error amplifier output of BUCK A and compensation node for voltage loop stability. The voltage at this node sets the target for the peak current through the respective inductor. This voltage is clamped on the upper and lower ends to provide current limit protection for the external MOSFETs. 14 SSA O Soft-start or tracking input for the buck controller BUCK A. The buck controller regulate the FBA voltage to the lower of 0.8V or the SSA pin voltage. An internal pull-up current source of 1A is present at the pin and an appropriate capacitor connected here can be used to set the soft-start ramp interval. A resistor divider connected to another supply can also be used to provide a tracking input to this pin. 15 PGA O Open drain power good indicator pin for BUCK A. An internal power good comparator monitors the voltage at the feedback pin and pull this output low when the output voltage falls below 93% of the set value, or if either Vin or Vbat drops below their respective undervoltage threshold. 16 ENA I Enable inputs for BUCK A (active high with an internal pull up current source). An input voltage higher than 1.5V enables the controller while an input voltage lower than 0.7V disables the controller. When both ENA and ENB are low, the device is shut down and consumes less than 4A of current. 17 ENB I Enable inputs for BUCK B (active high with an internal pull up current source). An input voltage higher than 1.5V enables the controller while an input voltage lower than 0.7V disables the controller. When both ENA and ENB are low, the device is shut down and consumes less than 4A of current. 18 COMPC O Error amplifier output and loop compensation node of the boost regulator. 19 ENC I This input enables and disables the boost regulator. An input voltage higher than 1.5V enables the controller. Voltages lower than 0.7V disable the controller. When enabled, the controller will start switching as soon as VBAT falls below the boost threshold depending upon the programmed output voltage. 20 SYNC I If an external clock is present on this pin the device detects it and the internal PLL locks on to the external clock. This overrides the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600 kHz. A high logic level on this pin ensures forced continuous mode operation of the buck controllers and inhibits transition to low power mode. An open or low allows discontinuous mode operation and entry into low power mode at light loads. On the TPS43336-Q1, a high level enables frequency-hopping spread spectrum while an open or a low level disables it. 21 DLYAB O The capacitor at the DLYAB pin sets the power good delay interval used to de-glitch the outputs of the power good comparators. When this pin is left open, the power good delay is set to an internal default value of 20sec typical. 22 RT O The operating switching frequency of the buck and boost controllers is set by connecting a resistor to ground on this pin. A short circuit to ground on this pin defaults operation to 400 kHz for the buck controllers and 200 kHz for the boost controller. 23 AGND O Analog Ground Reference 24 PGB O Open drain power good indicator pin for BUCK B. An internal power good comparator monitors the voltage at the feedback pin and pull this output low when the output voltage falls below 93% of the set value, or if either Vin or Vbat drops below their respective undervoltage threshold. 25 SSB O Soft-start or tracking input for the buck controller BUCK B. The buck controller regulate the FBB voltage to the lower of 0.8V or the SSB pin voltage. An internal pull-up current source of 1A is present at the pin and an appropriate capacitor connected here can be used to set the soft-start ramp interval. A resistor divider connected to another supply can also be used to provide a tracking input to this pin. 26 COMPB O Error amplifier output of BUCK B and compensation node for voltage loop stability. The voltage at this node sets the target for the peak current through the respective inductor. This voltage is clamped on the upper and lower ends to provide current limit protection for the external MOSFETs. 27 FBB I Feedback voltage pin for BUCK B. The buck controller regulates the feedback voltage to the internal reference of 0.8V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output voltage. 28 SB2 I 29 SB1 I 30 PGNDB O Power ground connection to the source of the low-side N-channel MOSFETs of BUCK B. 31 GB2 O External low-side N-channel MOSFETs for the buck regulator BUCK B can be driven from this output. The output provides high peak currents to drive capacitive loads. The voltage swing on this pin is provided by VREG. 32 PHB O Switching terminal of the buck regulator BUCK B, providing a floating ground reference for the high-side MOSFET gate driver circuitry and is used to sense current reversal in the inductor when discontinuous mode operation is desired. High Impedance differential voltage inputs from the current sense element (sense resistor or inductor DCR) for each buck controller. The current sense element should be chosen to set the maximum current through the inductor based on the current limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle and VIN. (SB1 positive node, SB2 negative node). Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 Submit Documentation Feedback 9 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com PIN FUNCTIONS (continued) NO. NAME I/O DESCRIPTION 33 GB1 O External high-side N-channel MOSFET for the buck regulator BUCK B can be driven from these output. The output provides high peak currents to drive capacitive loads. The gate drive is referred to a floating ground reference provided by the PHB and has a voltage swing provided by CBB. 34 CBB I A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate drive circuitry in the buck controller BUCK B. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to re-charge. 35 VREG O An external capacitor on this pin is required to provide a regulated supply for the gate drivers of the buck and boost controllers. A capacitance in the order of 4.7uF is recommended. The regulator can be used such that it is either powered from VIN or EXTSUP. This pin has a current limit protection and should not be used to drive any other loads. 36 DIV I The status of this pin defines the output voltage of the boost regulator. A high input regulates the Boost converter at 11V, a low input sets the value at 7V and a floating pin sets 10V. 37 EXTSUP I EXTSUP can be used to supply the VREG regulator from one of the TPS43335-Q1/TPS43336-Q1 buck regulator rails to reduce power dissipation in cases where VIN is expected to be high. When EXTSUP is open or lower than 4.6V, the regulator is powered from VIN. 38 VIN I Main Input pin. This is the buck controller input pin as well as the output of the boost regulator. Additionally it powers the internal control circuits of the device. 10 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com 38 Internal ref (Band gap) EXTSUP 37 Gate Driver Supply VREG 35 VIN SYNC GC2 PWM logic VREG Internal Oscillator 22 180 deg RT Duplicate for second Buck controller channel Current sense Slope Comp Amp + PWM + + comp SYNC & LPM 20 + OTA gm + - + SA2 FBA EN VREF 6 GA1 7 PHA 8 GA2 9 PGNDA 10 SA1 11 SA2 12 FBA 13 COMPA 15 PGA 21 DLYAB Filter timer 1mA SSA 0.8V CBA SSA Source/ Sink Logic 4 - 5 14 ENA VIN VREF 40 mA ENA 16 SSB 25 ENB 17 500 nA VREF 1mA COMPC 40 mA VIN ENB 500 nA 18 OTA VBAT 1 DIV 36 DS 2 gm + Second Buck Controller Channel Vref OCP + 0.2V - + VIN VREG GC1 3 ENC 19 AGND 23 PGNDA PWM comp PWM Logic 34 CBB 33 GB1 32 PHB 31 GB2 30 PGNDB 29 SB1 28 SB2 27 FBB 26 COMPB 24 PGB Figure 2. Functional Block Diagram Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 Submit Documentation Feedback 11 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS EFFICIENCY ACROSS OUTPUT CURRENTS (BUCKS) VIN = 12V, VOUT = 5V, SWITCHING FREQUENCY = 400kHz INDUCTOR = 4.7H, RSENSE = 10mW 90 10000 EFFICIENCY, SYNC = LOW 1000 EFFICIENCY (%) 80 70 60 POWER LOSS, SYNC = HIGH 100 50 40 POWER LOSS, SYNC = LOW 30 10 1 20 EFFICIENCY, SYNC = HIGH 10 0 0.0001 POWER LOSS (mW) 100 0.1 0.001 0.01 0.1 1 10 OUTPUT CURRENT (A) Figure 3. Figure 4. SOFT-START OUTPUTS (BUCK) VOUTA VOUTB 1V/DIV 2ms/DIV 12 Figure 5. Figure 6. Figure 7. Figure 8. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) EFFICIENCY ACROSS OUTPUT CURRENTS (BOOST) LOAD STEP RESPONSE (BOOST) (0 TO 5A AT 2.5A/s) VIN (BOOST OUTPUT) = 10V, SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0H, RSENSE = 7.5mW VBAT (BOOST INPUT) = 5V, VIN (BOOST OUTPUT) = 10V, SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0H, RSENSE = 7.5mW, CIN = 440F, COUT = 660F 100 90 VBAT = 8V EFFICIENCY (%) 80 500mV/DIV 70 VIN (BOOST OUTPUT) AC-COUPLED VBAT = 5V 60 VBAT = 3V 50 40 30 20 5A/DIV 10 IIND 0 0.01 1 OUTPUT CURRENT (A) 10 2ms/DIV Figure 9. Figure 10. CRANKING PULSE BOOST RESPONSE (12V to 3V IN 1ms AT BUCK OUTPUTS 7.5W/11.5W) CRANKING PULSE BOOST RESPONSE (12V to 4V IN 1ms AT BOOST DIRECT OUTPUT 25W) VIN (BOOST OUTPUT) = 10V, BUCKA = 5V/1.5A, BUCKB = 3.3V/3.5A, SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0H, RSENSE = 7.5mOHM, CIN = 440F, COUT = 660F VIN (BOOST OUTPUT) = 10V, BUCKA = 5V/1.5A, BUCKB = 3.3V/3.5A, SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0H, RSENSE = 7.5mOHM, CIN = 440F, COUT = 660F 5V/DIV VBAT (BOOST INPUT) 5V/DIV 0V 200mV/DIV 200mV/DIV 10A/DIV 0V VOUT BUCKA AC-COUPLED VBAT (BOOST INPUT) VIN (BOOST OUTPUT) 5V/DIV VOUT BUCKB AC-COUPLED 0V 10A/DIV IIND 0A IIND 0A 20ms/DIV 20ms/DIV Figure 11. Figure 12. INDUCTOR CURRENTS (BOOST) VBAT (BOOST INPUT) = 5V, VIN (BOOST OUTPUT) = 10V, SWITCHING FREQUENCY = 200kHz, INDUCTOR = 1.0H, RSENSE = 7.5mW, CIN = 440F, COUT = 660F 3A LOAD 5A/DIV 100mA LOAD 5A/DIV 2s/DIV Figure 13. Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 Submit Documentation Feedback 13 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) BUCKx PEAK CURRENT LIMIT vs. COMPx VOLTAGE PEAK CURRENT SENSE VOLTAGE (mV) NO-LOAD QUIESCENT CURRENT ACROSS TEMPERATURE Quiescent Current (A) 60 50 BOTH BUCKS ON 40 30 ONE BUCK ON 20 10 NEITHER BUCK ON 0 -40 -15 10 85 35 60 Temperature (C) 110 135 160 75 62.5 50 37.5 25 12.5 SYNC = LOW 0 -12.5 -25 SYNC = HIGH -37.5 0.65 0.8 0.95 Figure 14. 150C 25C 2 3 5 4 6 7 8 9 10 11 12 80 70 60 50 40 30 20 10 0 0 0.2 OUTPUT VOLTAGE (V) 0.4 Figure 17. CURRENT LIMIT VS DUTY CYCLE (BUCK) PEAK CURRENT SENSE VOLTAGE (mV) REGULATED FBx VOLTAGE vs TEMPERATURE (BUCK) REGULATED FBx VOLTAGE (mV) 805 804 803 802 801 800 799 798 797 796 795 -15 10 35 60 85 110 135 160 80 70 60 VIN = 8V 50 40 VIN = 12V 30 20 10 0 0 10 20 30 Figure 18. Submit Documentation Feedback 40 50 60 70 80 90 100 DUTY CYCLE (%) TEMPERATURE (C) 14 0.8 0.6 FBx VOLTAGE (V) Figure 16. -40 1.55 FOLDBACK CURRENT LIMIT (BUCK) PEAK CURRENT SENSE VOLTAGE (mV) SENSE CURRENT (A) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 1 1.4 Figure 15. CURRENT SENSE PINS INPUT CURRENT (BUCK) 0 1.25 1.1 COMPx VOLTAGE (V) Figure 19. Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com DETAILED DESCRIPTION BUCK CONTROLLERS: NORMAL MODE PWM OPERATION Frequency Selection and External Synchronization The buck controllers operate using constant frequency peak current mode control for optimal transient behavior and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz depending upon the resistor value at the RT pin. A short circuit to ground at this pin sets the default switching frequency to 400 kHz. The frequency can also be set by a resistor at RT according to the formula: fSW = X (X=24kxMHz) RT fSW =24x 109 RT Equation 1 Switching Frequency Feedback Inputs The output voltage is set by choosing the right resistor feedback divider network connected to the FBx (feedback) pins. This is to be chosen such that the regulated voltage at the FBx pin equals 0.8V. The FBx pins have a 100nA pull up current source as a protection feature in case the pins open up as a result of physical damage. Soft-Start Inputs In order to avoid large inrush currents, both buck controllers have independent programmable soft-start timer. The voltage at the SSx pins acts as the soft-start reference voltage. A 1A pull-up current is available at the SSx pins and by choosing a suitable capacitor a ramp of the desired soft-start speed can be generated. After start-up, the pull-up current ensures that this node is higher than the internal reference of 0.8V which then becomes the reference for the buck controllers. The soft-start ramp time is defined by: For example, I xt CSS = SS V 600kHz requires 40k (Farads) 150kHz requires 160k Equation 2 SoftStart Ramp Time It is also possible to synchronize to an external clock at the SYNC pin in the same frequency range of 150 kHz to 600 kHz. The device detects clock pulses at this pin and an internal PLL locks on to the external clock within the specified range. The device can also detect a loss of clock at this pin and when this is detected it sets the switching frequency to the internal oscillator. The two buck controllers operate at identical switching frequencies 180 degrees out of phase. Where, ISS = 1A (typical) V = 0.8V CSS is the required capacitor for t, the desired soft-start time. Alternatively the soft-start pins can be used as tracking inputs. In this case, they should be connected to the supply to be tracked via a suitable resistor divider network. Enable Inputs The buck controllers are enabled using independent enable inputs from the ENA and ENB pins. These are high voltage pins with a threshold of 1.5V for high level and can be connected directly to the battery for self-bias. The low threshold is 0.7V. Both these pins have internal pull-up currents of 0.5A (typical). As a result, an open circuit on these pins enables the respective buck controllers. When both buck controllers are disabled, the device is shut down and consumes a current less than 4A. Current Mode Operation Peak current-mode control regulates the peak current through the inductor such that the output voltage is maintained to its set value. The error between the feedback voltage at FBx and the internal reference produces a signal at the output of the error amplifier (COMPx) which serves as target for the peak inductor current. The current through the inductor is sensed as a differential voltage at Sx1-Sx2 and compared with this target during each cycle. A fall or rise in load current produces a rise or fall in voltage at FBx causing COMPx to fall or rise respectively, thus increasing/decreasing the current through the inductor until the average current matches the load. In this way the output voltage is maintained in regulation. Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 Submit Documentation Feedback 15 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 The top N-channel MOSFET is turned on at the beginning of each clock cycle and kept on until the inductor current reaches its peak value. Once this MOSFET is turned off, and after a small delay (shoot-through delay) the lower N-channel MOSFET is turned on until the start of the next clock cycle. In dropout operation the high-side MOSFET stays on 100%. In every fourth clock cycle the duty cycle is limited to 95% in order to charge the bootstrap capacitor at CBx. This allows a maximum duty cycle of 98.75% for the buck regulators. During dropout the buck regulator switches at one-fourth of its normal frequency. www.ti.com Inductor L TPS43335-Q1/ TPS43336-Q1 VBUCK X DCR R1 C1 Sx2 VC Sx1 Figure 20. DCR Sensing Configuration Current Sensing and Current Limit with Foldback The maximum value of COMPx is clamped such that the maximum current through the inductor is limited to a specified value. When the output of the buck regulator (and hence the feedback value at FBx) falls to a low value due to a short circuit/over-current condition, the clamped voltage at the COMPx successively decreases, thus providing current fold back protection. This protects the high-side external MOSFET from excess current (forward direction current limit). Slope Compensation Similarly, if due to a fault condition the output is shorted to a high voltage and the low-side MOSFET turns fully on, the COMPx node will drop low. It is clamped on the lower end as well in order to limit the maximum current in the low-side MOSFET (reverse direction current limit). Where The current through the inductor is sensed by an external resistor. The sense resistor should be chosen such that the maximum forward peak current in the inductor generates a voltage of 75mV across the sense pins. This value is specified at low duty cycles only. At typical duty cycle conditions around 40% (assuming 5V output and 12V input), 50mV is a more reasonable value, considering tolerances and mismatches. the typical characteristics provide a guide for using the correct current limit sense voltage. Power Good Outputs and Filter Delays The current sense pins Sx1 and Sx2 are high impedance pins with low leakage across the entire output range. This allows DCR current sensing using the DC resistance of the inductor for higher efficiency. DCR sensing is shown in the below figure. Here the series resistance (DCR) of the inductor is used as the sense element. The filter components should be placed close to the device for noise immunity. It should be remembered that while the DCR sensing gives high efficiency, it is inaccurate due to the temperature sensitivity and a wide variation of the parasitic inductor series resistance. Hence it may often be advantageous to use the more accurate sense resistor for current sensing. 16 Submit Documentation Feedback Optimal slope compensation which is adaptive to changes in input voltage and duty cycle allows stable operation at all conditions. For optimal performance of this circuit, the following condition must be satisfied in the choice of inductor and sense resistor: LxfSW =200 RS Equation 3 Inductor and Sense Resistor Choice L is the buck regulator inductor in Henry RS is the sense resistor in Ohm fsw is the buck regulator switching frequency in Hertz Each buck controller has an independent power good comparator monitoring the feedback voltage at the FBx pins and indicating whether the output voltage has fallen below a specified power good threshold. this threshold has a typical value of 93% of the regulated output voltage. the power good indicator is available as an open drain output at the PGx pins. An internal 50k pull-up resistor to Sx2 is available or an external resistor can be used. When a buck controller is shut down, the power good indicator is pulled down internally. Connecting the pull/up resistor to a rail other than the output of that particular buck channel will cause a constant current flow through the resistor when the buck controller is powered down. In order to avoid triggering the power good indicators due to noise or fast transients on the output voltage, an internal delay circuit for de-glitching is used. Similarly, when the output voltage returns to its set value after a long negative transient, the power good indicator will be asserted high (the open-drain pin released) after the same delay. This can be used to delay the reset to the circuits being powered from the buck regulator rail. The delay of this circuit can be programmed by using a suitable capacitor at the DLYAB pin according to the equation: Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com tDELAY 1 msec = CDLYAB 1 nF Equation 4 Power Good Indicator Delay When the DLYAB pin is open the delay is set to a default value of 20sec typical. The power good delay timing is common to both the buck rails but the power good comparators and indicators function independently. Light Load PFM Mode An external clock or a high level on the SYNC pin results in forced continuous mode operation of the bucks. When the SYNC pin is low or open, the buck controllers will be allowed to operate in discontinuous mode at light loads by turning off the low-side MOSFET whenever a zero-crossing in the inductor current is detected. In discontinuous mode, as the load decreases, the duration of the clock period when both the high-side as well the low-side MOSFET is turned off increases (deep discontinuous mode). In case the duration exceeds 60% of the clock period and VBAT > 8V, the buck controller switches to a low power operation mode. The design ensures that this typically occurs at 1% of the set full load current if the inductor and the sense resistor have been chosen appropriately as recommended in the slope compensation section. In Low Power PFM Mode the buck monitors the FBx voltage and compares it with the 0.8V internal reference. Whenever the FBx value falls below the reference, the high-side MOSFET is turned on for a pulse-duration inversely proportional to the difference VIN-Sx2. At the end of this on-time, the high-side MOSFET is turned off and the current in the inductor decays until it becomes zero. The low-side MOSFET is not turned on. The next pulse occurs the next time FBx falls below the reference value. This results in a constant volt-second Ton hysteretic operation with a total device quiescent current consumption of 30A when a single buck channel is active and 35A when both channels are active. As the load increases, the pulse become more and more frequent and move closer to each other until the current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed frequency current mode control. Another criteria to exit the low power mode is when VIN falls low enough to require higher than 80% duty cycle of the high-side MOSFET. The TPS43335-Q1/TPS43336-Q1 can support the full current load during low power mode until the transition to normal mode takes place. The design ensures the low power mode exit occurs at 10% (typical) of full load current if the inductor and sense resistor have been chosen as recommended. Moreover, there is always a hysteresis between the entry and exit thresholds to avoid oscillating between the two modes. In the event that both buck controllers are active, low power mode is only possible when both buck controllers have light loads that are low enough for low power mode entry. When the boost controller is enabled, low power mode is possible only if VBAT is high enough to prevent the boost from switching and if DIV is open or set to GND. If DIV is high (VREG), low power mode is inhibited. . Boost Controller The boost controller has a fixed frequency voltage mode architecture and includes a cycle-by-cycle current limit protection for the external N-channel MOSFET. The switching frequency is derived from and set to one half of the buck controller switching frequency. The output voltage of the boost controller at the VIN pin is set by an internal resistor divider network and is programmable to 7V, 10V and 11V based on the low, open and high status respectively of the DIV pin. A change of the DIV-setting is not recognized, while the device is in low power mode. The boost controller is enabled by the active-high ENC pin and is active when the input voltage at the VBAT pin has crossed the unlock threshold of 8.5V at least once. After that, the boost controller is armed and starts switching as soon as VIN falls below the value set by the DIV pin and regulates the VIN voltage. Thus, the boost regulator maintains a stable input voltage for the buck regulators during transient events such as cranking pulse at VBAT. Whenever the voltage at the DS pin exceeds 200mV, the boost external MOSFET is turned off by pulling the GC1 pin low. By connecting the DS pin to the drain of the MOSFET or to a sense resistor between the MOSFET source and ground, cycle-by-cycle over-current protection for the MOSFET can be achieved. The on-resistance of the MOSFET or the value of the sense resistor has to be chosen in such a way that the on-state voltage at the DS does not exceed 200mV at the maximum load and minimum input voltage conditions. When sense resistor is used , a filter network is recommended to be connected between the DS pin and the sense resistor for better noise immunity. Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 Submit Documentation Feedback 17 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com The boost output (VIN) can also be used to supply other circuits in the system. However they should be high-voltage tolerant. The boost output is regulated to the programmed value only when VIN is low and so VIN can reach battery levels. Vbat Vbat VIN TPS43335-Q1/ TPS43336-Q1 GC1 RIFLT DS VIN TPS43335-Q1/ TPS43336-Q1 CIFLT DS RISEN GC1 Figure 22. External Current Shunt Resistor Figure 21. External Drain-Source Voltage Sensing Frequency-Hopping Spread Spectrum (TPS43336-Q1 only) The TPS43336-Q1 features a frequency-hopping pseudo-random spectrum spreading architecture. On this device, whenever the SYNC pin is high, the internal oscillator frequency is varied from one cycle to the next within a band of 5% around the value programmed by the resistor at the RT pin. The implementation uses a linear feedback shift register that changes the frequency of the internal oscillator based on a digital code. The shift register is long enough to make the hops pseudo-random in nature and is designed in such a way that the frequency shifts only by one step at each cycle to avoid large jumps in the buck and boost switching frequencies. Table 1. Frequency Hopping Control Sync Terminal Frequency Spread Spectrum (FSS) Comments External clock Not active Device in forced continuous mode, internal PLL locks into external clock between 150kHz and 600kHz. Low or open Not active Device can enter discontinuous mode. Automatic LPM entry and Exit depending on load conditions TPS43335-Q1: FSS not active High Device in forced continuous mode TPS43336-Q1: FSS active Table 2. Mode of Operation ENABLE AND INHIBIT PINS ENA ENB ENC Low Low Low Low High High Low Low Low High High Low Low Low Low Low High High 18 High Low High High High High SYNC X Low High Low High Low High X Low High Low High Low High DRIVER STATUS BUCK CONTROLLERS Shutdown BOOST CONTROLLER disabled Buck B running disabled Buck A running disabled DEVICE STATUS QUIESCENT CURRENT Shutdown ~4 A Buck B: LPM enabled ~30A (light loads) Buck B: LPM inhibited mA range Buck A: LPM enabled ~30A (light loads) Buck A: LPM inhibited mA range Buck A/B: LPM enabled ~35A (light loads) Buck A/B: LPM inhibited mA range Buck A&B running disabled Shutdown disabled Shutdown ~4 A Buck B running Boost running for VIN < set Boost Output Buck B: LPM enabled ~50A (no boost, light loads) Buck B: LPM inhibited mA range Buck A running Boost running for VIN < set Boost Output Buck A: LPM enabled ~50A (no boost, light loads) Buck A: LPM inhibited mA range Buck A and B running Boost running for VIN < set Boost Output Buck A/B: LPM enabled ~60A (no boost, light loads) Buck A/B: LPM inhibited mA range Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com Gate Driver Supply (VREG, EXTSUP) The gate drivers of the buck and boost controllers are supplied from an internal linear regulator whose output (5.8V typical) is available at the VREG pin and should be decoupled using at least a 1F ceramic capacitor. This pin has an internal current limit protection and should not be used to power any other circuits. scheme of reverse battery protection which may require only a smaller sized diode to protect the N-channel MOSFET as it conducts only for a part of the switching cycle. Since it is not always in series path, the system efficiency can be improved. R10 GC2 D3 Q6 Q7 VIN Vbat The VREG linear regulator is powered from VIN by default when the EXTSUP voltage is lower than 4.6V (typ.). In case VIN expected to go to high levels, there can be excessive power dissipation in this regulator, especially at high switching frequencies and when using large external MOSFET's. In this case, it is advantageous to power this regulator from the EXTSUP pin which can be connected to a supply lower than VIN but high enough to provide the gate drive. When EXTSUP is connected to a voltage greater than 4.6V, the linear regulator automatically switches to EXTSUP as its input to provide this advantage. Efficiency improvements are possible when one of the switching regulator rails from the TPS43335-Q1/TPS43336-Q1 or any other voltage available in the system is used to power the EXTSUP. The maximum voltage that should be applied to EXTSUP is 13V. Using a large value for EXTSUP is advantageous as it provides a large gate drive and hence better on-resistance of the external MOSFET's. A 0.1F ceramic capacitor is recommended for decoupling the EXTSUP pin when not being used. During low power mode, the EXTSUP functionality is not available. The internal regulator operates as a shunt regulator powered from VIN and has a typical value of 7.5V. Current limit protection for VREG is available in low power mode as well. External P-Channel Drive (GC2) and Reverse Battery Protection The TPS43335-Q1/TPS43336-Q1 includes a gate driver for an external P-channel MOSFET which can be connected across the rectifier diode of the boost regulator. This is useful to reduce power losses when the boost controller is not switching. The gate driver provides a swing of 6V typical below the VIN voltage in order to drive a P-channel MOSFET. When VBAT falls below the boost enable threshold, the gate driver turns off the P-channel MOSFET and the diode is no longer bypassed. The gate driver can also be used to bypass any additional protection diodes connected in series as shown in Figure 23. Figure 24 also shows a different TPS43335-Q1/ TPS43336-Q1 L3 Fuse (S1) D2 C16 C17 D1 C15 C14 DS GC1 COMPC C13 R9 VBAT Figure 23. Reverse Battery Protection Option for Buck Boost Configuration GC2 VBAT VIN Fuse TPS43335-Q1/ TPS43336-Q1 DS GC1 COMPC VBAT Figure 24. Reverse Battery Protection Option for Buck Boost Configuration Undervoltage Lockout and Overvoltage Protection The TPS43335-Q1/TPS43336-Q1 starts up at a VIN voltage of 6.5V (min). Once it has started up, the device operates down to a VIN voltage of 3.6V, below this voltage level the undervoltage lockout will disable the device. A voltage of 46V at VIN triggers the overvoltage comparator which shuts down the device. In order to prevent that transient spikes shutting down the device, the under and overvoltage protection have filter times of 5s (typical). When the voltages return to the normal operating region, the enabled switching regulators start including a new soft-start ramp for the buck regulators. When the boost controller is enabled, a voltage less than 1.9V (typical) on VBAT triggers an undervoltage lockout and pulls the boost gate driver (GC1) low. As a result VIN will fall at a rate dependent on its capacitor and load, eventually triggering VIN Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 Submit Documentation Feedback 19 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 undervoltage. A short falling transient at VBAT even lower than 2V can thus be survived, if VBAT returns to higher than 2.5V before VIN is discharged to the undervoltage threshold. This detection has a filter delay of 5sec typical. 20 Submit Documentation Feedback www.ti.com Thermal Protection The TPS43335-Q1/TPS43336-Q1 protects itself from overheating using an internal thermal shutdown circuit. If the die temperature exceeds the thermal shutdown threshold of 165 degrees Celsius due to excessive power dissipation (e.g.: Due to fault conditions such as a short circuit at the gate drivers or VREG), the controllers are turned off and restarted when the temperature has fallen by 15 degrees. Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com APPLICATION INFORMATION The following example illustrates the design process and component selection for the TPS43335-Q1. The design goal parameters are given in Table 3. Table 3. PARAMETER VBUCK A VBUCK B BOOST VIN 6 V to 30 V 12 V - typ VIN 6 V to 30 V 12 V - typ VBAT - 5 V (cranking pulse input) to 30V Output voltage, VO 5V 3.3 V 10 V Max - output current, IO 3A 2A 2.5 A Input voltage Load step output tolerance, VO Current output load step, IO Converter switching frequency, fSW 0.2 V 0.12 V 0.5 V 0.1 A to 3 A 0.1 A to 2 A 0.1 A to 2.5 A 400 kHz 400 kHz 200 kHz This is a starting point and theoretical representation of the values to be used for the application, further optimization of the components derived may be required to improve the performance of the device. Boost Component Selection VIN A Boost converter operating in continuous conduction mode (CCM) has a right-half-plane (RHP) zero in its transfer function. The RHP zero is inversely related to the load current and inductor value and directly related to the input voltage. The RHP zero limits the maximum bandwidth achievable for the boost regulator. If the bandwidth is too close to the RHP zero frequency, the regulator may become unstable. Thus, for high power systems with low input voltages, a low inductor value is chosen. This increases the amplitude of the ripple currents in the N-channel MOSFET, the inductor and the capacitors for the boost regulator. They must be designed with the ripple/RHP zero trade-off in mind and considering the power dissipation effects in the components due to parasitic series resistance. A boost converter that operates in the discontinuous mode does not contain the RHP-zero in its transfer function. However, this needs an even lower inductor value and has high ripple currents. Also, it must be ensured that the regulator never enters the continuous conduction mode otherwise it may become unstable. CO 7V COMPx OTA-gmEA R ESR 10 V C1 + VREF C2 R3 12 V Figure 25. Boost Compensation Components This design is done assuming continuous conduction mode. During light load conditions, the boost converter will operate in discontinuous mode without affecting stability. Hence the assumptions here cover the worst case for stability. Boost Maximum Input Current IIN_MAX The maximum input current is drawn at the minimum input voltage and maximum load. the efficiency for VBAT = 5V at 2.5A is 80% based on the typical characteristics plot Hence, Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 Submit Documentation Feedback 21 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com Boost Inductor Selection, L Allow input ripple current of 40% of IIN VBAT = 5 V L= VBAT * TON IIN max VBAT = IIN max* 2 * fSW 5V = 2.52A * 2 * 200kHz max at = 4.9 mH Choose a lower value of 4 H in order to ensure a high RHP-zero frequency while making a compromise that expects a high current ripple. Also, this can make the boost converter operate in discontinuous conduction mode where it is easier to compensate. The inductor saturation current needs to be higher than the peak inductor current and some percentage higher than the maximum current limit value set by the external sensing resistive element. This rating should be determined at the minimum input voltage, maximum output current and maximum core temperature for the application Inductor Ripple Current, IRIPPLE Based on an Inductor value of 4 H, the ripple current is approximately 3.1 A. Select CO = 660 F. This capacitor is usually aluminum electrolytic with ESR in the 10s of m. This is good for loop stability since it provides a phase boost due to the ESR. The output filter components LC create a double pole (180 degree phase shift) at a frequency fLC and the ESR of the output capacitor RESR creates a "zero" for the modulator at frequency fESR. These frequencies can be determined by the following; Peak Current in Low Side FET, IPEAK Based on this peak current value the external current sense resistor RSENSE is calculated. Select 20 m allowing for tolerance The filter component values RIFLT and CIFLT for current sense are 1.5 k and 1 nF respectively. This allows for good noise immunity. This satisfies fLC 0.1 fRHP . Right Half Plane Zero RHP Frequency, fRHP Bandwidth of Boost Converter, fC Use the following guidelines to set the frequency poles, zeroes and crossover values for trade off between stability and transient response: fLC < fESR< fC< fRHP Zero spacer fC < fRHP Zero / 3 spacer fC < fSW / 6 Output Capacitor, CO fLC < fC / 3 To ensure stability, the output capacitor CO is chosen such that 22 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com Output Ripple Voltage Due to Load Transients, VO Output Schottky Diode D1 Selection Since the boost converter is active only during brief events such as a cranking pulse and the buck converters are high-voltage tolerant, a higher excursion on the boost output may be tolerable in some cases. In such cases, smaller component choices for the boost output may be used. Selection of Components for Type II Compensation A schottky diode with low forward conducting voltage VF over temperature and fast switching characteristics is required to maximize efficiency. The reverse breakdown voltage should be higher than the maximum input voltage and the component should have low reverse leakage current. Additionally the peak forward current should be higher than the peak inductor current The power dissipation in the Schottky diode is given by : Since this is activated for low input voltage profile related to crank pulse the duration is less than 25ms Low-Side MOSFET (BOT_SW3) The required loop gain for unity gain bandwidth (UGB) is The boost converter error amplifier (OTA) has a Gm that is proportional to the VBAT voltage. This allows a constant loop response across the input voltage range and makes it easier to compensate by removing the dependency on VBAT. 10 G 20 R3 = = 5.9k W 85 * 10 -6 *VO C1 = 10 10 = 2p * fC * R 3 2p * 8kHz * 5.9k W C1 C2 = 2p * R 3 * C 1* ( fSW 2 = 33nF 33nF = ) -1 2p * 5.9k W * 33nF * ( 200kHz 2 = 265pF ) -1 The times tr and tf denote the rising and falling times of the switching node and are related to the gate driver strength of the TPS43335-Q1/TPS43336-Q1 and gate Miller capacitance of the MOSFET. The first term denotes the conduction losses which are minimized when the on-resistance of the MOSFET is low. The second term denotes the transition losses which arise due to the full application of the input voltage across the drain-source of the MOSFET as it turns on or off. They are higher at high output currents and low input voltages (due to the large input peak current) and when the switching time is low. Note: The on resistance RDS(ON) has a positive temperature coefficient which produces the (TC=d*DeltaT) term that signifies the temperature dependence.( Temperature coefficient d is available as a normalized value from MOSFET data sheets and can be assumed to be 0.005/degrees Celsius as a starting value) BUCKA Component Selection Input Capacitor, CI Minimum ON Time, tON min The input ripple required is lower than 50 mV. DVC 1 = DVESR IRIPPLE 5 416 = 10mV 8 * fSW * C 1 = IRIPPLE * RESR = 40mV Therefore our 10mOhm ESR. recommendation is 330F with This is higher than the min duty cycle specified (100 ns typ). Hence the minimum duty cycle is achievable at this frequency. Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 Submit Documentation Feedback 23 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 Current Sense Resistor RSENSE Based on the typical characteristics for VSENSE limit with VIN versus duty cycle, the sense limit is approximately 65 mV (at VIN = 12V and duty cycle of 5V/12V = 0.416). Allowing for tolerances and ripple currents choose VSENSE max of 50mV. www.ti.com Selection of Components for Type II Compensation VO R ESR RL R1 VSENSE COMP gmea CO R2 Vref Type2A R3 R0 Select 15 m C2 C1 Inductor Selection L As explained in the description of the buck controllers, for optimal slope compensation and loop response, the inductor should be chosen such that: Figure 26. Buck Compensation Components R3 = 2p * fC * VO * CO gm * KCFB * VREF = 2p * 50kHz * 5 * 100 mF gm * KCFB * VREF = 23.57k W Use standard value of R3 = 24 k KFLR = Coil selection constant = 200 Choose a standard value of 8.2H. For the buck converter, the inductor saturation currents and core should be chosen to sustain the maximum currents. Where; VO = 5V, CO = 100uF, gm = 1ms, VREF = 0.8V KCFB = 0.125 / RSENSE = 8.33 (0.125 is an internal constant) C1 = 10 2p * R 3 * fC Inductor Ripple Current IRIPPLE 10 = = 1.35nF 2p * 24k W * 50kHz Use standard value of 1.5 nF At nominal input voltage of 12V, this gives a ripple current of 30% of IO max 1A. Output Capacitor CO Select an output capacitance CO of 100F with low ESR in the range of 10m. This give VO(Ripple) 15mV and V drop of 180 mV during a load step, which will not trigger the power good comparator and is within the required limits. Bandwidth of Buck Converter fC Use the following guidelines to set frequency poles, zeroes and cross over values for trade off between stability and transient response * Crossover frequency fC between fSW/6 and fSW/10 Assume fC = 50kHz * Select the zero fz fC/10 * Make the second pole fP2 fSW/2 The resulting bandwidth of Buck Converter fC This is close to the target bandwidth of 50 kHz The resulting zero frequency fZ1 This is close to the fC/10 guideline of 5 kHz The second pole frequency fP2 spacer spacer spacer This is close to the fSW/2 guideline of 200 kHz. Hence all requirements for a good loop response are satisfied. spacer 24 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com Resistor Divider Selection for setting VO Voltage 10 C1 = 10 = 2p * R3* fC 2p *30k W *50kHz C1 C2 = 2p * R3* C1* ( Choose divider current through R1 and R2 to be 50 A. Then fsw 2 2p *30k W *1.2nF * ( Therefore, R2 = 16 k and R1 = 84 k fC = Using the same method as VBUCKA, the following parameters and components are realized 400kHz 2 = 33 pF ) -1 gm * R3* KCFB VREF = * 2p * CO VO fC = BUCKB Component Selection ) -1 1.2nF = And = 1.2nF 1ms * 20k W * 4.16 * 0.8 2p *100 m F *3.3 = 48kHz This close to the target bandwidth of 50 kHz The resulting zero frequency fZ1 5 416 This is higher than the min duty cycle specified (100 ns typ) fZ 1 = 1 1 = 2p * R3* C1 2p *30k W *1.2nF = 4.4kHz This close to the fC guideline of 5kHz The second pole frequency fP2 fP 2 = 1 2p * R3* C 2 = 1 2p *30k W *33 pF = 160kHz This close to the fSW/2 guideline of 200 kHz Iripple current 0.4 A (approx.20% of IO max) Select an output capacitance CO of 100F with low ESR in the range of 10m. This give VO (Ripple) 7.5mV and V drop of 120 mV during a load step Hence all requirements for a good loop response are satisfied Resistor Divider Selection for Setting VO Voltage Assume fC = 50kHz R3 = = 2p * fC * VO * CO gm * KCFB * VREF 2p *50kHz *3.3*100 m F 1ms * 4.16 * 0.8 = 30k W Choose divider current through R1 and R2 to be 50 A. Then Use standard value of R3 = 30k And Therefore, R2 = 16 k and R1 = 50 k Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 Submit Documentation Feedback 25 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 BUCKX High-Side and Low-Side N-Channel MOSFETs The gate drive supply for these MOSFET is supplied by an internal supply which is 5.8V typical under normal operating conditions. The output is a totem pole allowing full voltage drive of VREG to the gate with peak output current of 1.2 A. The High-Side MOSFET is referenced to a floating node at the phase terminal (PHx) and the Low-Side MOSFET is referenced to power ground (PGx) terminal. For a particular applications these MOSFET`s should be selected with consideration for the following parameters Rds ON, gate charge Qg, drain to source breakdown voltage BVDSS, Maximum DC current IDC(max) and thermal resistance for the package. The times tr and tf denote the rising and falling times of the switching node and are related to the gate driver strength of the TPS43335-Q1/TPS43336-Q1 and gate Miller capacitance of the MOSFET. The first term denotes the conduction losses which are minimized when the on-resistance of the MOSFET is 26 Submit Documentation Feedback www.ti.com low. The second term denotes the transition losses which arise due to the full application of the input voltage across the drain-source of the MOSFET as it turns on or off. They are lower at low currents and when the switching time is low. PBuckTOPFET = V I * IO (IO )2 * RDS (ON )(1 + TC ) * D + ( ) * (tr + tf ) * fSW 2 PbuckLOWERFET = (IO )2 * RDS (ON )(1 + TC ) * (1 - D ) + VF * IO * (2 * td ) * fSW In addition, during the dead time td when both the MOSFETs are off, the body diode of the low-side MOSFET conducts, increasing the losses. This is denoted by the second term in the above equation. Using external Schottky diodes in parallel to the low-side MOSFETs of the buck converters helps to reduce this loss. Note: The RDS(ON) has a positive temperature coefficient which is accounted for in the TC term for RDS(ON). TC = d * delta T[C]. The temperature coefficient d is available as a normalized value from MOSFET data sheets and can be assumed to be 0.005/degrees Celsius as a starting value Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com Schematic The following section summarize the previously calculated example and gives schematic + component proposals. Table 3. Table 4. Application Example 1 PARAMETER VBUCK A VBUCK B BOOST VIN 6 V to 30 V 12 V - typ VIN 6 V to 30 V 12 V - typ VBAT - 5 V (cranking pulse input) to 30V Output voltage, VO 5V 3.3 V 10 V Max - output current, IO 3A 2A 2.5 A Input voltage Load step output tolerance, VO Current output load step, IO 0.2 V 0.12 V 0.5 V 0.1 A to 3 A 0.1 A to 2 A 0.1 A to 2.5 A 400 kHz 400 kHz 200 kHz Converter switching frequency, fSW 2.5V to 40V L1 D1 BOOST 10V, 25W VBAT 3.9H 10F CIN 330F 680F COUT1 TOP-SW3 1k VBAT DS BOT-SW3 0.02 0.1F 1.5k GC1 DIV 1nF GC2 VREG CBA CBB L2 GA1 GB1 TOP-SW2 L3 8.2H PHA PHB 15H TPS43335-Q1 or PGNDA TPS43336-Q1 GB2 BOT-SW2 0.1F TOP-SW1 VBUCKA - 5V, 15W VIN EXTSUP 0.015 100F COUT2 BOT-SW1 GA2 84k VBUCKB - 3.3V, 6.6W 0.03 100F COUT3 PGNDB SA1 SB1 SA2 SB2 FBA 1F 0.1F 50k FBB 16k 16k 33pF COMPA 1.5nF COMPB 20k 24k 10nF SSA SSB PGA PGB ENA AGND 47pF 1.8nF 10nF 5k 5k ENB 270pF 33nF 5.6k COMPC RT DLYAB 1nF ENC SYNC Table 5. Application Example 1 - Component Proposals Name Component Proposal Value L1 MSS1278T-392NL (Coilcraft) 4H L2 MSS1278T-822ML (Coilcraft) 8.2H L3 MSS1278T-153ML (Coilcraft) 15H D1 SK103 (Micro Commercial Components) TOP_SW3 IRF7416 (International Rectifier) TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay) BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay) BOT_SW3 IRFR3504ZTRPBF (International Rectifier) COUT1 EEVFK1J681M (Panasonic) 680F COUT2,3 ECASD91A107M010K00 (Murata) 100F CIN EEEFK1V331P (Panasonic) 330F Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 Submit Documentation Feedback 27 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com Table 6. Application Example 2 PARAMETER VBUCK A VBUCK B BOOST VIN 5 V to 30 V 12 V - typ VIN 6 V to 30 V 12 V - typ VBAT - 5 V (cranking pulse input) to 30V Output voltage, VO 5V 2.5 V 10 V Max - output current, IO 3A 1A 2A 0.2 V 0.12 V 0.5 V 0.1 A to 3 A 0.1 A to 1 A 0.1 A to 2 A 400 kHz 400 kHz 200 kHz Input voltage Load step output tolerance, VO Current output load step, IO Converter switching frequency, fSW 5V to 30V L1 D1 BOOST 10V, 20W VBAT 3.9H CIN 330F 10F 470F COUT1 TOP-SW3 1k VBAT DS BOT-SW3 0.03 0.1F 1.5k GC1 DIV 470pF GC2 VREG CBA CBB L2 GA1 GB1 10uH PHA PHB 22uH TPS43335-Q1 or PGNDA TPS43336-Q1 GB2 BOT-SW2 0.1F TOP-SW1 VBUCKA - 5V, 15W VIN EXTSUP 0.015 150F COUT2 BOT-SW1 GA2 84k TOP-SW2 L3 0.045 VBUCKB - 2.5V, 2.5W 100uF COUT3 PGNDB SA1 SB1 SA2 SB2 FBA 1F 0.1F 34k FBB 16k 16k 20pF COMPA 1nF COMPB 36k 39k 10nF SSA SSB PGA PGB ENA AGND 22pF 1nF 10nf 5k 5k ENB 220pF 24nF 6.8k COMPC RT DLYAB 1nF ENC SYNC Table 7. Application Example 2 - Component Proposals Name Component Proposal Value L1 MSS1278T-392NL (Coilcraft) 3.9H L2 MSS1278T-822ML (Coilcraft) 8.2H L3 MSS1278T-223ML (Coilcraft) 22H D1 SK103 (Micro Commercial Components) TOP_SW3 IRF7416 (International Rectifier) TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay) BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay) BOT_SW3 IRFR3504ZTRPBF (International Rectifier) COUT1 EEVFK1V471Q (Panasonic) 470F COUT2 ECASD91A157M010K00 (Murata) 150F COUT3 ECASD40J107M015K00 (Murata) 100F CIN EEEFK1V331P (Panasonic) 330F 28 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com Power Dissipation De-Rate Profile 32 pin HTTSOP package with power PAD Figure 27. Power dissipation de rating profile based on high K Jedec PCB PCB Layout Guidelines Grounding and PCB Circuit Layout Considerations Boost converter 1. The path formed from the input capacitor to the inductor and BOT_SW3 with low side current sense resistor should have short leads and PC trace lengths. The same applies for the trace from the inductor to the Schottky Diode D1 to the COUT1 capacitors. The negative terminal of the input capacitor and the negative terminal of the sense resistor be connected together with short trace lengths. 2. The over current sensing shunt resistor may require noise filtering and this capacitor should be close to the IC pin. Buck Converter 1. Connect the drain of TOP_SW1 and TOP_SW2 together with positive terminal of the input capacitor COUT1. The trace length between these terminals should be short. 2. Connect a local decoupling capacitor between Drain of TOP_SWx and Source of BOT_SWx. 3. The Kelvin current sensing for the shunt resistor should have minimum trace spacing and routed together. Any filtering capacitors for noise should be placed near the IC pins. 4. The resistor divider for sensing output voltage is connected between the positive terminal of the respective output capacitor and COUT2 or COUT3 and the IC signal ground. These components and the traces should not be routed near any switching nodes or high current traces. Other Considerations 1. PGNDx and AGND should be shorted to thermal pad. Use a star ground configuration if connecting to non ground plane system. Use tie-ins for EXTSUP capacitor, compensation network ground and voltage sense feedback ground networks to this start ground. 2. Connect compensation network between compensation pins and IC signal ground. Connect the oscillator resistor (frequency setting) between the RT pin and IC signal ground. These sensitive circuits should NOT be located near the dv/dt nodes; these include the gate drive outputs, phase pins and boost circuits (bootstrap). 3. Reduce the surface area of the high current carrying loops to a minimum, by ensuring optimal component placement. Ensure the bypass capacitors are located as close as possible to their respective power and ground pins. Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 Submit Documentation Feedback 29 TPS43335-Q1 TPS43336-Q1 SLVSAV6A - JUNE 2011 - REVISED NOVEMBER 2011 www.ti.com PCB Layout POW ER IN PUT Powe r L ines Connec tion to GND P lane o fPCB th rough v ias Connec tion to top /bo ttom o fPCB th rough v ias Vo ltage Ra ilO u tpu ts V BOOST VBAT V IN EXTSUP GC1 D IV GC2 VREG CBA CBB GA1 GB1 PHA PHB GA2 GB2 PGNDA PGNDB SA1 SB1 SA2 SB2 FBA FBB COMPA COMPB SSA SSB PGA PGB ENA AGND ENB RT COMPC ENC M ic rocon tro lle r 30 Submit Documentation Feedback VBUCKB VBUCKA DS DLYAB Exposed Pad connec ted to GND P lane SYNC Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): TPS43335-Q1 TPS43336-Q1 PACKAGE OPTION ADDENDUM www.ti.com 7-Dec-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS43335QDAPRQ1 ACTIVE HTSSOP DAP 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPS43336QDAPRQ1 ACTIVE HTSSOP DAP 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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