Features
• Performance specied for common IPM applications
over industrial temperature range: -40°C to 100°C
• Fast maximum propagation delays
tPHL = 400 ns,
tPLH = 490 ns
• Minimized Pulse Width Distortion (PWD = 370 ns)
• Very high Common Mode Rejection (CMR):
15 kV/µs at VCM = 1500 V
• CTR > 44% at IF = 10 mA
• Safety approval
UL recognized per UL1577 (le no. E55361)
– 3750 Vms for 1 minute
• Lead free option “-000E”
Applications
• IPM isolation
• Isolated IGBT/MOSFET gate drive
• AC and brushless dc motor drives
• Industrial inverters
Schematic Diagram
The connection of a 0.1 µF bypass capacitor between pins 4 and 6 is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage
and/or degradation which may be induced by ESD.
6
5
4
1
3SHIELD
HCPL-M456 pkg
Truth Table
LED V
O
ON L
OFF H
Description
The HCPL-M456 consists of a GaAsP LED optically coupled
to an integrated high gain photo detector. Minimized
propagation delay dierence between devices make these
optocouplers excellent solutions for improving inverter
eciency through reduced switching dead time.
Specications and performance plots are given for typical
IPM applications.
HCPL-M456
Small Outline, 5 Lead Intelligent Power Module Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
2
Ordering Information
HCPL-M456 is UL Recognized with 3750 Vrms for 1 minute per UL1577.
Part number
Option
Package
Surface
Mount
Tape
& Reel
IEC/EN/DIN
EN 60747-5-2 Quantity
RoHS
Compliant
Non RoHS
Compliant
HCPL-M456
-000E No option
SO-5
X 100 per tube
-500E #500 X X 1500 per reel
-060E -060 X X 100 per tube
-560E -560 X X X 1500 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-M456-560E to order product of SO-5 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN
60747-5-2 Safety Approval in RoHS compliant.
Example 2:
HCPL-M456 to order product of SO-5 Surface Mount package in tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and
RoHS compliant option will use ‘-XXXE‘.
HCPL-M456 Outline Drawing
Pin Location (for reference only)
MXXX
XXX
6
5
43
1
7.0 ± 0.2
(0.276 ± 0.008)
2.5 ± 0.1
(0.098 ± 0.004)
0.102 ± 0.102
(0.004 ± 0.004)
VCC
VOUT
GND
CATHODE
ANODE
4.4 ± 0.1
(0.173 ± 0.004)
1.27
(0.050)
BSC
0.15 ± 0.025
(0.006 ± 0.001)
0.71
(0.028)MIN
0.4 ± 0.05
(0.016 ± 0.002)
3.6 ± 0.1*
(0.142 ± 0.004)
DIMENSIONS IN MILLIMETERS (INCHES)
* MAXIMUM MOLD FLASH ON EACH SIDE IS 0.15 mm (0.006)
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
TYPE NUMBER (LAST 3 DIGITS)
DATE CODE
7° MAX.
MAX. LEAD COPLANARITY
= 0.102 (0.004)
3
Figure 1. 5 Pin SOIC Package (JEDEC MO-155) Device Outline Drawing.
Land Pattern Recommendation
8.27
(0.325)
2.0
(0.080)
2.5
(0.10)
1.3
(0.05)
0.64
(0.025)
4.4
(0.17)
DIMENSION IN MILLIMETERS (INCHES)
Absolute Maximum Ratings
Parameter Symbol Min. Max. Units
Storage Temperature TS -55 125 °C
Operating Temperature TA -40 100 °C
Average Input Current[1] IF(avg) 25 mA
Peak Input Current[2] IF(peak) 50 mA
(50% duty cycle, <1 ms pulse width)
Peak Transient Input Current IF(tran) 1.0 A
(<1 µs pulse width, 300 pps)
Reverse Input Voltage (Pin 3-1) VR 5 Volts
Average Output Current (Pin 5) IO(avg) 15 mA
Output Voltage (Pin 5-4) VO -0.5 30 Volts
Supply Voltage (Pin 6-4) VCC -0.5 30 Volts
Output Power Dissipation[3] PO 100 mW
Total Power Dissipation[4] PT 145 mW
Infrared and Vapor Phase Reow Temperature See Reow Thermal Prole below.
4
Solder Reow Thermal Prole
Recommended Pb-Free IR Prole
0
TIME (SECONDS)
TEMPERATURE (°C)
200
100
50 150100 200 250
300
0
30
SEC.
50 SEC.
30
SEC.
160°C
140°C
150°C
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
SOLDERING
TIME
200°C
PREHEATING TIME
150°C, 90 + 30 SEC.
2.5°C ± 0.5°C/SEC.
3°C + 1°C/–0.5°C
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
217 °C
RAMP-DOWN
6 °C/SEC. MAX.
RAMP-UP
3 °C/SEC. MAX.
150 - 200 °C
260 +0/-5 °C
t 25 °C to PEAK
60 to 150 SEC.
20-40 SEC.
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
t
p
t
s
PREHEAT
60 to 180 SEC.
t
L
T
L
T
smax
T
smin
25
T
p
TIME
TEMPERATURE
NOTES:
THE TIME FROM 25 °C to PEAK
TEMPERATURE = 8 MINUTES MAX.
T
smax
= 200 °C, T
smin
= 150 °C
Note: Non-halide ux should be used.
Note: Non-halide ux should be used.
Recommended Operating Conditions
Parameter Symbol Min. Max. Units
Power Supply Voltage VCC 4.5 30 Volts
Output Voltage VO 0 30 Volts
Input Current (ON) IF(on) 10 20 mA
Input Voltage (OFF) VF(o ) -5 0.8 V
Operating Temperature TA -40 100 °C
5
Regulatory Notes
• The HCPL-M456 is recognized under the component program of U.L. (File No. 55361) for dielectric withstand proof
voltages of 2500 VRMS, 1 minute.
Insulation Related Specications
Parameter Symbol Value Units Conditions
Minimum External Air Gap L(101) ≥5 mm Measured from input terminals to output
External Clearance terminals, shortest distance through air.
Minimum External Tracking L(102) ≥5 mm Measured from input terminals to output
External Creepage terminals, shortest distance path along body.
Minimum Internal Plastic Gap 0.08 mm Insulation thickness between emitter and
Internal Clearance detector; also known as distance through
insulation.
Tracking Resistance CTI 200 Volts DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group DIN VDE 0110
Electrical Specications
Over recommended operating conditions unless otherwise specied:
TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(o) = -5 V to 0.8 V
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
Current Transfer Ratio CTR 44 90 % IF = 10 mA, VO = 0.6 V 5
Low Level Output IOL 4.4 9.0 mA IF = 10 mA, VO = 0.6 V 2,3
Current
Low Level Output Voltage VOL 0.3 0.6 V IO = 2.4 mA
Input Threshold Current ITH 1.5 5.0 mA VO = 0.8 V, IO = 0.75 mA 2 9
High Level Output IOH 5 50 µA VF = 0.8 V 4
Current
High Level Supply Current ICCH 0.6 1.3 mA VF = 0.8 V, VO = Open 9
Low Level Supply Current ICCL 0.6 1.3 mA IF = 10 mA, VO = Open 9
Input Forward Voltage VF 1.5 1.8 V IF = 10 mA 5
Temperature Coecient ∆VF/∆T
A -1.6 mV/°C IF = 10 mA
of Forward Voltage
Input Reverse Breakdown BVR 5 V IR = 10 µA
Voltage
Input Capacitance CIN 60 pF f = 1 MHz, VF = 0 V
Input-Output VISO 3750 VRMS RH < 50%, t = 1 min, 6, 7
Insulation Voltage TA = 25°C
Resistance (Input - Output) RI-O 1012 Ω VI-O = 500 Vdc 6
Capacitance CI-O 0.6 pF f = 1 MHz 6
(Input - Output)
*All typical values at 25°C, VCC = 15 V.
6
Switching Specications (RL= 20 kΩ)
Over recommended operating conditions unless otherwise specied:
TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(o) = -5 V to 0.8 V
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
Propagation Delay tPHL IF(on) = 10 mA, 6, 8, 9
Time to Low VF(o) = 0.8 V, 8-12
Output Level
Propagation Delay tPLH
Time to High
Output Level
Pulse Width PWD 200 450 ns CL = 100 pF 13
Distortion
Propagation Delay tPLH-tPHL -150 200 450 ns 10
Dierence Between
Any 2 Parts
Output High Level |CMH| 15 30 kV/µs IF = 0 mA, VCC = 15.0 V, 7 11
Common Mode VO > 3.0 V CL = 100 pF,
Transient Immunity VCM = 1500 V
P-P
,
Output Low Level |CML| 15 30 kV/µs IF = 10 mA, 12
Common Mode VO < 1.0 V
Transient Immunity
*All typical values at 25°C, VCC = 15 V.
TA = 25°C
VCC = 15.0 V,
VTHLH = 2.0 V,
VTHHL = 1.5 V
130 CL = 10 pF
30 200 400 ns CL = 100 pF
100 ns CL = 10 pF
270 400 550 ns CL = 100 pF
Notes:
1. Derate linearly above 90°C free-air temperature at a rate of 0.8 mA/°C.
2. Derate linearly above 90°C free-air temperature at a rate of 1.6 mA/°C.
3. Derate linearly above 90°C free-air temperature at a rate of 3.0 mW/°C.
4. Derate linearly above 90°C free-air temperature at a rate of 4.2 mW/°C.
5. CURRENT TRANSFER RATIO in percent is dened as the ratio of output collector current (IO) to the forward LED input current (IF) times 100.
6. Device considered a two-terminal device: Pins 1 and 3 shorted together and Pins 4, 5 and 6 shorted together.
7. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 VRMS for 1 second (leakage detec-
tion current limit, II-O ≤ 5 µA).
8. Pulse: f = 20 kHz, Duty Cycle = 10%.
9. Use of a 0.1 µF bypass capacitor connected between pins 4 and 6 can improve performance by ltering power supply line noise.
10. The dierence between tPLH and tPHL between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay Speci-
cations section.)
11. Common mode transient immunity in a Logic High level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that
the output will remain in a Logic High state (i.e., VO > 3.0 V).
12. Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in a Logic Low state (i.e., VO < 1.0 V).
13. Pulse Width Distortion (PWD) is dened as |tPHL - tPLH| for any given device.
7
LED Drive Circuit Considerations For Ultra High CMR Per-
formance
Without a detector shield, the dominant cause of op-
tocoupler CMR failure is capacitive coupling from the
input side of the optocoupler, through the package, to
the detector IC as shown in Figure 14. The HCPL-M456
improves CMR performance by using a detector IC with
an optically transparent Faraday shield, which diverts the
capacitively coupled current away from the sensitive IC
circuitry. However, this shield does not eliminate the ca-
pacitive coupling between the LED and the optocoupler
output pin and output ground as shown in Figure 15. This
capacitive coupling causes perturbations in the LED cur-
rent during common mode transients and becomes the
major source of CMR failures for a shielded optocoupler.
The main design objective of a high CMR LED drive circuit
becomes keeping the LED in the proper state (on or o)
during common mode transients. For example, the rec-
ommended application circuit (Figure 13), can achieve
15 kV/µs CMR while minimizing component complexity.
Note that a CMOS gate is recommended in Figure 13
to keep the LED o when the gate is in the high state.
Another cause of CMR failure for a shielded optocou-
pler is direct coupling to the optocoupler output pins
through CLEDO1 in Figure 15. Many factors inuence the
eect and magnitude of the direct coupling including:
the position of the LED current setting resistor and the
value of the capacitor at the optocoupler output (CL).
Techniques to keep the LED in the proper state
and minimize the effect of the direct cou-
pling are discussed in the next two sections.
CMR With The LED On (CMRL)
A high CMR LED drive circuit must keep the LED on
during common mode transients. This is achieved by
overdriving the LED current beyond the input threshold
so that it is not pulled below the threshold during a
transient. The recommended minimum LED current of
10 mA provides adequate margin over the maximum
ITH of 4.0 mA (see Figure 2) to achieve 15 kV/µs CMR.
The placement of the LED current setting resistor eects
the ability of the drive circuit to keep the LED on during
transients and interacts with the direct coupling to the
optocoupler output. For example, the LED resistor in
Figure 16 is connected to the anode. Figure 17 shows the
AC equivalent circuit for Figure 16 during common mode
transients. During a +dVCM/dt in Figure 17, the current
available at the LED anode (Itotal) is limited by the series
resistor. The LED current (IF) is reduced from its DC value
by an amount equal to the current that ows through
CLEDP and CLEDO1. The situation is made worse because
the current through CLEDO1 has the eect of trying to pull
the output high (toward a CMR failure) at the same time
the LED current is being reduced. For this reason, the
recommended LED drive circuit (Figure 13) places the
current setting resistor in series with the LED cathode.
Figure 18 is the AC equivalent circuit for Figure 13 during
common mode transients. In this case, the LED current
is not reduced during a +dVCM/dt transient because the
current owing through the package capacitance is sup-
plied by the power supply. During a -dVCM/dt transient,
however, the LED current is reduced by the amount of
current owing through CLEDN. But, better CMR perfor-
mance is achieved since the current owing in CLEDO1
during a negative transient acts to keep the output low.
CMR With The LED O (CMRH)
A high CMR LED drive circuit must keep the LED o
(VF ≤ VF(OFF)) during common mode transients. For example,
during a +dVCM/dt transient in Figure 18, the current ow-
ing through CLEDN is supplied by the parallel combination
of the LED and series resistor. As long as the voltage de-
veloped across the resistor is less than VF(OFF) the LED will
remain o and no common mode failure will occur. Even
if the LED momentarily turns on, the 100 pF capacitor
from pins 5-4 will keep the output from dipping below
the threshold. The recommended LED drive circuit (Figure
13) provides about 10 V of margin between the lowest op-
tocoupler output voltage and a 3 V IPM threshold during
a 15kV/µs transient with VCM = 1500 V. Additional margin
can be obtained by adding a diode in parallel with the
resistor, as shown by the dashed line connection in Fig-
ure 18, to clamp the voltage across the LED below VF(OFF).
Since the open collector drive circuit, shown in Figure 19,
cannot keep the LED o during a +dVCM/dt transient, it is
not desirable for applications requiring ultra high CMRH
performance. Figure 20 is the AC equivalent circuit for
Figure 19 during common mode transients. Essentially
all the current owing through CLEDN during a +dVCM/dt
transient must be supplied by the LED. CMRH failures can
occur at dv/dt rates where the current through the LED
and CLEDN exceeds the input threshold . Figure 21 is an
alternative drive circuit which does achieve ultra high
CMR performance by shunting the LED in the o state.
8
IPM Dead Time and Propagation Delay Specications
The HCPL-M456 includes a Propagation Delay Dier-
ence specication intended to help designers mini-
mize “dead time” in their power inverter designs. Dead
time is the time period during which both the high
and low side power transistors (Q1 and Q2 in Figure
22) are o. Any overlap in Q1 and Q2 conduction will
result in large currents flowing through the power
devices between the high and low voltage motor rails.
To minimize dead time the designer must consider the
propagation delay characteristics of the optocoupler
as well as the characteristics of the IPM IGBT gate drive
circuit. Considering only the delay characteristics of the
optocoupler (the characteristics of the IPM IGBT gate
drive circuit can be analyzed in the same way) it is im-
portant to know the minimum and maximum turn-on
(tPHL) and turn-o (tPLH) propagation delay specications,
preferably over the desired operating temperature range.
The limiting case of zero dead time occurs when the
input to Q1 turns o at the same time that the input to
Q2 turns on. This case determines the minimum delay
between LED1 turn-o and LED2 turn-on, which is re-
lated to the worst case optocoupler propagation delay
waveforms, as shown in Figure 23. A minimum dead
time of zero is achieved in Figure 23 when the signal to
turn on LED2 is delayed by (tPLH max - tPHL min) from the
LED1 turn o. Note that the propagation delays used to
calculate PDD are taken at equal temperatures since the
optocouplers under consideration are typically mounted
in close proximity to each other. (Specically, tPLH max
and tPHL min in the previous equation are not the same as
the tPLH max and tPHL min, over the full operating tempera-
ture range, specied in the data sheet.) This delay is the
maximum value for the propagation delay dierence
specication which is specied at 370 ns for the HCPL-M456
over an operating temperature range of -40°C to 100°C.
Delaying the LED signal by the maximum propagation
delay dierence ensures that the minimum dead time is
zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time occurs in the
highly unlikely case where one optocoupler with the fast-
est tPLH and another with the slowest tPHL are in the same
inverter leg. The maximum dead time in this case becomes
the sum of the spread in the tPLH and tPHL propagation
delays as shown in Figure 24. The maximum dead time is
also equivalent to the dierence between the maximum
and minimum propagation delay dierence specica-
tions. The maximum dead time (due to the optocouplers)
for the HCPL-M456 is 520 ns (= 370 ns - (-150 ns)) over an
operating temperature range of -40°C to 100°C.
Figure 2. Typical Transfer Characteristics. Figure 3. Normalized Output Current vs. Temperature. Figure 4. High Level Output Current vs. Temperature.
IO – OUTPUT CURRENT – mA
0
IF – FORWARD CURRENT – mA
6
4
2
5
HCPL-M456 fig 2
10
10 15 20
VO = 0.6 V
8
0
100 °C
25 °C
-40 °C
NORMALIZED OUTPUT CURRENT
T
A
– TEMPERATURE – °C
0.95
0.90
0.85
0
HCPL-M456 fig 3
40 60 100
I
F
= 10 mA
V
O
= 0.6 V
1.00
-40 -20 20 80
1.05
0.80
9
Figure 5. Input Current vs. Forward Voltage.
Figure 7. CMR Test Circuit.
Figure 6. Propagation Delay Test Circuit.
Typical CMR Waveform.
HCPL-M456 fig 6
0.1 µF
VCC = 15 V
20 k
6
5
4
1
3SHIELD
I
F(ON)
=10 mA
V
OUT
C
L
*
+
–
*TOTAL LOAD
CAPACITANCE
+
–
I
f
V
O
V
THHL
t
PHL
t
PLH
t
f
t
r
90%
10%
90%
10%
V
THLH
HCPL-M456 fig 7a
0.1 µF
V
CC
= 15 V
20 k
6
5
4
1
3SHIELD
A
I
F
V
OUT
100 pF*
+
–
*100 pF TOTAL
CAPACITANCE
+
–
+
–
B
V
FF
V
CM
= 1500 V
HCPL-M456 fig 7b
VCM
�t
OV
VO
VO
SWITCH AT A: I
F
= 0 mA
SWITCH AT B: I
F
= 10 mA
VCC
VOL
VCM
�t
δV
δt=
10
Figure 8. Propagation Delay with External 20 kΩ RL vs.
Temperature.
Figure 14. Optocoupler Input to Output Capacitance Model for Un-
shielded Optocouplers.
Figure 13. Recommended LED Drive Circuit.
HCPL-M456 fig 14
6
5
4
1
3
CLEDP
CLEDN
0.1 µF
V
CC
= 15 V
20 k
HCPL-M456 fig 13
6
5
4
1
3SHIELD
CMOS
310
+5 V
V
OUT
100 pF
+
–
*100 pF TOTAL
CAPACITANCE
Figure 9. Propagation Delay vs. Load Resistance. Figure 10. Propagation Delay vs. Load Capacitance.
Figure 12. Propagation Delay vs. Input Current.Figure 11. Propagation Delay vs. Supply Voltage.
t
P
– PROPAGATION DELAY – ns
RL – LOAD RESISTANCE – K
600
400
200
HCPL-M456 fig 9
30 50
800
0 10 20 40
t
PLH
t
PHL
I
F
= 10 mA
V
CC
= 15 V
CL = 100 pF
T
A
= 25 °C
tP – PROPAGATION DELAY – ns
0
VCC – SUPPLY VOLTAGE – V
800
600
400
10
HCPL-M456 fig 11
1400
15 20 25
IF = 10 mA
CL = 100 pF
RL = 20 k
TA = 25°C
200
1000 tPLH
tPHL
5 30
1200
tP – PROPAGATION DELAY – ns
100
IF – FORWARD LED CURRENT – mA
300
10
HCPL-M456 fig 12
500
15
VCC = 15 V
CL = 100 pF
RL = 20 k
TA = 25°C
200
400
tPLH
tPHL
50 20
11
Figure 21. Recommended LED Drive Circuit for Ultra
High CMR.
6
5
4
1
3SHIELD
HCPL-M456 fig 21
+5 V
Figure 19. Not Recommended Open Collector LED Drive
Circuit.
Figure 20. AC Equivalent Circuit for Figure 19 during Common Mode Tran-
sients.
6
5
4
1
3SHIELD
HCPL-M456 fig 19
Q1
+5 V
Figure 17. AC Equivalent Circuit for Figure 16 during
Common Mode Transients.
Figure 18. AC Equivalent Circuit for Figure 13 during Common Mode Tran-
sients.
Figure 15. Optocoupler Input to Output Capacitance
Model for Shielded Optocouplers.
Figure 16. LED Drive Circuit with Resistor Connected to LED Anode (Not Rec-
ommended).
0.1 µF
V
CC
= 15 V
20 k
HCPL-M456 fig 16
6
5
4
1
3SHIELD
CMOS
310
+5 V
V
OUT
100 pF
+
–
*100 pF TOTAL
CAPACITANCE
HCPL-M456 fig 15
6
5
4
1
3
C
LEDP
C
LEDN
SHIELD
C
LED01
20 k
HCPL-M456 fig 17
6
5
4
1
3
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dV
CM
/dt TRANSIENTS.
300
V
OUT
100 pF
I
CLEDP
C
LEDN
SHIELD
C
LED01
+
–
I
TOTAL*
I
CLED01
I
F
V
CM
20 k
HCPL-M456 fig 18
6
5
4
1
3
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dV
CM
/dt TRANSIENTS.
** OPTIONAL CLAMPING DIODE FOR IMPROVED CMH
PERFORMANCE. V
R
< V
F (OFF)
DURING +dV
CM
/dt.
V
OUT
100 pF
C
LEDP
C
LEDN
SHIELD
C
LED01
+
–
I
CLEDN*
300
+ V
R
** –
V
CM
20 k
HCPL-M456 fig 20
6
5
4
1
3
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dVCM/dt TRANSIENTS.
V
OUT
100 pF
C
LEDP
CLEDN
SHIELD
C
LED01
+
–
I
CLEDN*
Q1
V
CM
Figure 22. Typical Application Circuit.
Figure 23. Minimum LED Skew for Zero Dead Time.
Figure 24. Waveforms for Deadtime Calculation.
0.1 µF 20 k
HCPL-M456 fig 22
6
5
4
1
3SHIELD
CMOS
310
+5 V
V
OUT1
HCPL-M456
I
LED1
V
CC1
0.1 µF 20 k
6
5
4
1
3SHIELD
CMOS
310
+5 V
V
OUT2
HCPL-M456
I
LED2
V
CC2
M
Q2
Q1
-HV
+HV
IPM
HCPL-M456
HCPL-4506
HCPL-M456
HCPL-M456
HCPL-M456
HCPL-M456 fig 23
V
OUT1
V
OUT2
I
LED2
t
PLH MAX.
PDD* MAX. =
(t
PLH-
t
PHL) MAX. =
t
PLH MAX. -
t
PHL MIN.
t
PHL
MIN.
I
LED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE
PDD ARE TAKEN AT EQUAL TEMPERATURES.
HCPL-M456 fig 24
VOUT1
VOUT2
ILED2 tPLH
MIN.
MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER)
= (tPLH MAX. - tPLH MIN.) + (tPHL MAX. - tPHL MIN.)
= (tPLH MAX. - tPHL MIN.) - (tPLH MIN. - tPHL MAX.)
= PDD* MAX. - PDD* MIN.
tPHL
MIN.
ILED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
*PDD = PROPAGATION DELAY DIFFERENCE
tPLH
MAX.
tPHL
MAX.
PDD*
MAX.
MAX.
DEAD TIME
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM
DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES.
13
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Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes 5989-2118EN
AV01-0555EN July 16, 2007