Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www . exa r .c om
áç
áçáç
áç
XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
FEBRUARY 2002 REV. 1.1.1
GENERAL DESCRIPTION
The XRT7300 DS3/E3/STS-1 Line Interface Unit is
designed to be used in DS3, E3 or SONET STS-1 ap-
plications and consists of a line transmitter and re-
ceiver integrated on a single chip.
XRT7300 can be configured to support the E3
(34.368 Mbps), DS3 (44.736 Mbps) or the SONET
STS-1 (51.84 Mbps) rates.
In the transmit direction, the XRT7300 encodes input
data to either B3ZS (for DS3/STS-1 applications) or
HDB3 (for E3 applications) format and converts the
data into the appropriate pulse shapes for transmis-
sion over coaxial cable via a 1:1 transformer.
In the receive direction the XRT7300 performs equal-
ization on incoming signals, performs Clock Recov-
ery, decodes data from either B3ZS or HDB3 format,
converts the receive data into TTL/CMOS format,
checks for LOS or LOL conditions and detects and
declares the occurrence of line code violations.
The XRT7300 also contains a 4-Wire Microprocessor
Serial Interface for accessing the on-chip Command
registers.
FEATURES
•Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
•Full Loop-Back Capability
•Transmit and Receive Power Down Modes
•Full Redundancy Support
•Contains a 4-Wire Microprocessor Serial Interface
•Uses Minimum External components
•Requires Single +5V Power Supply
•-40°C to +85°C Operating Temperature Range
•Available in a 44 pin TQFP package
APPLICATIONS
•Interfaces to E3, DS3 or SONET STS-1 Networks
•CSU/DSU Equipment
•PCM Test Equipment
•Fiber Optic Terminals
•Multiplexers
N
OTE
: This Device is Protected by US Patent # 6,157,270
FIGURE 1. BLOCK DIAGRAM OF THE XRT7300
AGC/
Equalizer
Serial
Processor
Interface
Peak
Detector
LOS Detector
Slicer Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR
SDI
SDO/(LCV)
SClk
CS
REGRESET
RTIP
RRING
REQDIS
Device
Monitor
MTIP
MRING
DMO
Transmit
Logic Duty Cycle Adjust
TTIP
TRING
Pulse
Shaping
HDB3/
B3ZS
Encoder
E3 STS-1/DS3 Host/(HW) RLOL EXCLK ICT RCLK2INV
Tx
Control
DECODIS
RLOS
LLB
RLB
ENCODIS
TAOS
TPDATA
TNDATA
TClk
TXLEV
TXOFF
RCLK1
RNEG
RPOS
LCV/(RCLK2)
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
2
ORDERING INFO RMATION
PART NUMBER PACKAGE TYPE OPERATING TEMPERATURE RANGE
XRT7300IV 44 Pin TQFP (10mm x 10mm) -40°C to +85°C
FIGURE 2. PIN OUT OF THE XRT7300 IN THE 44 PIN TQFP
LCV/(RCLK2)
44 43 42 41 40 39 38 37 36 35 34
12 13 14 15 16 17 18 19 20 21 22
23
24
33
32
31
30
29
28
27
26
25
XRT7300
(Top View)
TxLEV
TAOS
VDD
DMO
GND
RTIP
GND
GND
RRING
VDD
REGRESET/
RCLK2INV
REQDIS
LOSTHR
LLB
RLB
STS1/DS3
E3
HOST/HW
SDI/(LOSMUTEN)
SDO/(LCV)
SCLK/(ENCODIS)
CS/(DECODIS)
RPOS
RNEG
RCLK1
VDD
VDD
GND
EXCLK
GND
RLOS
RLOL
MTIP
MRING
VDD
TTIP
TRING
GND
TNDATA
TPDATA
TCLK
TXOFF
ICT
11
10
1
2
3
4
5
6
7
8
9
áç
áçáç
áç E3/DS3/STS-1 LINE INTERFACE UNIT XRT7300
REV. 1.1.1
I
TABLE OF CONTENTS
General description ........................................................................................................... 1
FEATURES ................................................................................................................................................. 1
APPLICATIONS .......................................................................................................................................... 1
Figure 1.Block Diagram of the XRT7300............................................................................................................ 1
Ordering Information ......................................................................................................... 2
Figure 2.Pin Out of the XRT7300 in the 44 Pin TQFP........................................................................................ 2
TABLE OF CONTENTS.........................................................................................................I
Pin Description ................................................................................................................... 3
Electrical Characteristics ................................................................................................ 10
DC ELECTRICAL CHARACTERISTICS (TA = 25°C, VDD = 5.0V + 5%, UNLESS OTHERWISE SPECI-
FIED) ............................................................................................................................................................... 10
AC ELECTRICAL CHARACTERISTICS (TA = 25°C, VDD = 5.0V + 5%, UNLESS OTHERWISE SPECI-
FIED) ............................................................................................................................................................... 10
Figure 3.Timing Diagram of the Transmit Terminal Input Interface.................................................................. 11
Figure 4.Timing Diagram of the Receive Terminal Output Interface................................................................11
AC ELECTRICAL CHARACTERISTICS (CONTINUED) (TA = 25°C, VDD = 5.0V + 5%, UNLESS OTHER-
WISE SPECIFIED) .......................................................................................................................................... 12
AC ELECTRICAL CHARACTERISTICS (CONTINUED) (TA = 25°C, VDD = 5.0V + 5%, UNLESS OTHER-
WISE SPECIFIED) .......................................................................................................................................... 13
ABSOLUTE MAXIMUM RATINGS .....................................................................................14
Figure 5.Transmit Pulse Amplitude Test Circuit for DS3, E3 and STS-1 Rates............................................... 15
Figure 6.ITU-T G.703 Transmit Output Pulse Template for E3 Applications.................................................... 15
Figure 7.Bellcore GR-499-CORE Transmit Output Pulse Template for DS3 Applications............................... 16
Figure 8.Bellcore GR-253-CORE Transmit Output Pulse Template for SONET STS-1 Applications .............. 16
MICROPROCESSOR SERIAL INTERFACE TIMING (SEE FIGURE 9) .................................................. 17
Figure 9.Timing Diagram for the Microprocessor Serial Interface.................................................................... 17
System Description ......................................................................................................... 18
THE TRANSMIT SECT ION ...... ...... .................... ...... ....... ...... ...... .................... ...... ....... ...... ....... ...... ....... ... 1 8
THE RECEIVE SEC TION .................................. ...... ....... ...... ...... .................... ...... ....... ...... ....... ............. ... 1 8
THE MICROPROCES SO R SE RIAL INTERFACE ...................... ....... ...... ....... ...... ....... ...... ....... ...... ....... ... 18
Table 1:Role of Microprocessor Serial Interface pins when the XRT7300 is operating in the Hardware Mode18
1.0 SELECTING THE DATA RATE ............................................................................................................... 19
Table 2:Selecting the Data Rate for the XRT7300 via the E3 and STS-1/DS3 input pins (Hardware Mode)... 19
COMMAND REGISTER CR4 (ADDRESS = 0X04) .................................................................................. 19
Table 3:Selecting the Data Rate for the XRT7300 Via the STS-1/DS3 and the E3 Bit-fields Within Command
Register CR4 (HOST Mode)................................................................................................................ 19
2.0 THE TRANSMIT SECTION ...................................................................................................................... 20
2.1 THE TRANSMIT LOGIC BLOCK ................................................................................................................. 20
Figure 10.The Typical Interface for the Transmission of Data in a Dual-Rail Format From the Transmitting Ter-
minal Equipment to the Transmit Section of the XRT7300 ................................................................ 20
Figure 11.How the XRT7300 Samples the Data on the TPDATA and TNDATA Input Pins............................. 20
Accepting Single-Rail Data from the Terminal Equipment .................................................................. 21
COMMAND REGISTER CR1 (ADDRESS = 0X01) .................................................................................. 21
Figure 12.The Behavior of the TPDATA and TCLK Input Signals While the Transmit Logic Block is Accepting
Single-Rail Data From the Terminal Equipment................................................................................. 21
XRT7300 E3/DS3/STS-1 LINE INTERFACE UNIT áç
áçáç
áç
REV. 1.1.1
II
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY .........................................................................21
2.3 THE HDB3/B3ZS ENCODER BLOCK........................................................................................................22
B3ZS Encoding....................................................................................................................................22
Figure 13.An Example of B3ZS Encoding ........................................................................................................22
HDB3 Encoding....................................................................................................................................22
Figure 14.An Example of HDB3 Encoding........................................................................................................23
Enabling/Disabling the HDB3/B3ZS Encoder ......................................................................................23
2.4 THE TRANSMIT PULSE SHAPER CIRCUITRY..............................................................................................23
COMMAND REGISTER CR2 (ADDRESS = 0X02 ....................................................................................23
Enabling the Transmit Line Build-Out Circuit.......................................................................................23
Disabling the Transmit Line Build-Out Circuit ......................................................................................23
COMMAND REGISTER CR1 (ADDRESS = 0X01) ...................................................................................23
Design Guideline for Setting the Transmit Line Build-Out Circuit ........................................................24
COMMAND REGISTER CR1 (ADDRESS = 0X01) ...................................................................................24
The Transmit Lin e Build-O ut Circu it and E3 Appli catio ns......................... ....... ...... ....... ...... .................24
2.5 INTERFACING THE TRANSMIT SECTION OF THE XRT7300 TO THE LINE .....................................................24
Figure 15.Recommended Schematic for Interfacing the Transmit Section of the XRT7300 to the Line...........24
TRANSFORMER RECOMMENDATIONS........................................................................................................25
3.0 THE RECEIVE SECTION ......................................................................................................................... 25
3.1 INTERFACING THE RECEIVE SECTION OF THE XRT7300 TO THE LINE .......................................................25
Figure 16.Recommended Schematic for Interfacing the Receive Section of the XRT7300 to the Line (Transform-
er-Coupling)........................................................................................................................................26
Figure 17.Recommended Schematic for Interfacing the Receive Section of the XRT7300 to the Line (Capaci-
tive-Coupling)......................................................................................................................................26
3.2 THE RECEIVE EQUALIZER BLOCK ............................................................................................................26
Figure 18. The Typical Application for the System Installer..............................................................................27
COMMAND REGISTER CR2 (ADDRESS = 0X02) ...................................................................................28
3.3 PEAK DETECTOR AND SLICER .................................................................................................................28
3.4 CLOCK RECOVERY PLL............... ...... ....... ...... ....... ................... ...... ....... ...... ....... ................... ....... ...... ....28
3.5 THE HDB3/B3ZS DECODER...................................................................................................................28
B3ZS Decoding DS3/STS-1 Applications ............................................................................................29
Figure 19.An Example of B3ZS Decoding ........................................................................................................29
HDB3 Decoding E3 Applications..........................................................................................................29
Figure 20.An Example of HDB3 Decoding........................................................................................................29
Enabling/Disabling the HDB3/B3ZS Decoder......................................................................................30
3.6 LOS DECLARATION/CLEARANCE .............................................................................................................30
COMMAND REGISTER CR2 (ADDRESS = 0X02) ...................................................................................30
The LOS Declaration/Clearance Criteria for E3 Applications...............................................................30
Figure 21.The Signal Levels that the XRT7300 Declares and Clears LOS (E3 Mode Only)............................31
Figure 22.The Behavior the LOS Output Indicator In Response to the Loss of Signal and the Restoration of Sig-
nal.......................................................................................................................................................31
The LOS Declaration/Clearance Criteria for DS3 and STS-1 Applications..........................................32
Table 4:The ALOS Declaration and Clearance Thresholds for a Given Setting of LOSTHR (DS3 and STS-1 Ap-
plications) for Equalizer Enabled or Disabled ......................................................................................32
COMMAND REGISTER CR0 (ADDRESS = 0X00) ...................................................................................32
COMMAND REGISTER CR2 (ADDRESS = 0X02) ...................................................................................33
COMMAND REGISTER CR0 (ADDRESS = 0X00) ...................................................................................33
áç
áçáç
áç E3/DS3/STS-1 LINE INTERFACE UNIT XRT7300
REV. 1.1.1
III
COMMAND REGISTER CR2 (ADDRESS = 0X02) .................................................................................. 33
Muting the Recovered Data while the LOS is being Declared............................................................. 33
3.7 ROUTING THE RECOVERED TIMING AND DATA INFORMATION TO THE RECEIVING TERMINAL EQUIPMENT .... 33
COMMAND REGISTER CR3 (ADDRESS = 0X03) .................................................................................. 33
Figure 23. The Typical Interface for the Transmission of Data in a Dual-Rail Format From the Receive Section
of the XRT7300 to the Receiving Terminal Equipment...................................................................... 34
Figure 24. How the XRT7300 Outputs Data on the RPOS and RNEG Output Pins ........................................ 34
Figure 25.The Behavior of the RPOS, RNEG and RCLK1 Signals When RCLK1 is Inverted ......................... 35
Routing Single-Rail Format data (Binary Data Stream) to the Receive Terminal Equipment ............. 35
COMMAND REGISTER CR3 (ADDRESS = 0X03) .................................................................................. 35
COMMAND REGISTER CR3 (ADDRESS = 0X03) .................................................................................. 35
Figure 26.The Typical Interface for the Transmission of Data in a Single-Rail Format From the Receive Section
of the XRT7300 to the Receiving Terminal Equipment...................................................................... 36
Figure 27.The Behavior of the RPOS and RCLK1 Output Signals While the XRT7300 is Transmitting Single-Rail
Data to the Receiving Terminal Equipment........................................................................................36
4.0 DIAGNOSTIC FEATURES OF THE XRT7300 ........................................................................................ 36
4.1 THE ANALOG LOCAL LOOP-BACK MODE ................................................................................................. 36
Figure 28.The Analog Local Loop-Back in the XRT7300 ................................................................................. 37
COMMAND REGISTER CR4 (ADDRESS = 0X04) .................................................................................. 37
4.2 THE DIGITAL LOCAL LOOP-BACK MODE .................................................................................................. 37
Figure 29.The Digital Local Loop-Back path in the XRT7300 .......................................................................... 38
COMMAND REGISTER CR4 (ADDRESS = 0X04) .................................................................................. 38
4.3 THE REMOTE LOOP-BACK MODE............................................................................................................ 38
Figure 30.The Remote Loop-Back Path in the XRT7300................................................................................. 39
COMMAND REGISTER CR4 (ADDRESS = 0X04) .................................................................................. 39
4.4 TXOFF FEATURES................................................................................................................................. 40
COMMAND REGISTER CR1 (ADDRESS = 0X01) .................................................................................. 40
4.5 THE TRANSMIT DRIVE MONITOR FEATURES ............................................................................................ 40
Figure 31.The XRT7300 Employing the Transmit Drive Monitor Features....................................................... 40
Figure 32. Two LIU’s, Each Monitoring the Transmit Output Signal of the Other LIU IC ................................. 41
4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE.......................................................................................... 41
COMMAND REGISTER CR1 (ADDRESS = 0X01) .................................................................................. 41
5.0 THE MICROPROCESSOR SERIAL INTERFACE ................................................................................... 42
5.1 DESCRIPTION OF THE COMMAND REGISTERS .......................................................................................... 42
Table 5:Addresses and Bit Formats of XRT7300 Command Registers ........................................................... 42
DESCRIPTION OF BIT-FIELDS FOR EACH COMMAND REGISTER .................................................... 42
Command Register - CR0 ................................................................................................................... 42
Command Register - CR1 ................................................................................................................... 43
Command Register - CR2 ................................................................................................................... 44
Command Register - CR3 ................................................................................................................... 44
Command Register - CR4 ................................................................................................................... 45
5.2 OPERATING THE MICROPROCESSOR SERIAL INTERFACE.......................................................................... 45
Table 6:Loop-Back Modes................................................................................................................................ 45
Figure 33.Microprocessor Serial Interface Data Structure ............................................................................... 46
Figure 34. How to Interface the XRT7300 IC to the XRT7234/45 E3/DS3 ATM UNI IC .................................. 47
Figure 35.How to Interface the XRT7300 IC to the XRT7250 DS3/E3 Framer IC............................................ 48
ORDERING INFORMATION ..................................................................................................................... 49
Package Dimensions ....................................................................................................... 49
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
3
PIN DESCRIPTION
PIN DESCRIPTION
PIN #S
YMBOL TYPE DESCRIPTION
1TXLEV ITransmit Line Build-Out Enable/Disable Select:
This input pin is used to enable or disable the Transmit Line Build-Out circuit in
the XRT7300.
Setting this pin to “High” disables the Line Build-Out circuit. In this mode, the
XRT7300 outputs partially shaped pulses onto the line via the TTIP and TRING
output pins.
Setting this pin to “Low” enables the Line Build-Out circuit. In this mode, the
XRT7300 outputs partially-shaped pulses onto the line via the TTIP and TRING
output pins.
To comply with the isolated DSX-3/STSX-1 Pulse Template Requirements per
Bellcore GR-499-Core or Bellcore GR-253-Core:
1. Set this input pin to a "1" if the cable length between the Cross-Connect and
the transmit output of the XRT7300 is greater than 225 feet.
2. Set this input pin to a "0" if the cable length between the Cross-Connect and
the transmit output of the XRT7300 is less than 225 feet.
This pin is active only if both of the following are tr ue:
(a) The XRT7300 is configured to operate in either the DS3 or SONET STS -1
modes and
(b) The XRT7300 is configured to operate in the Har dware Mode.
N
OTE
: This pin should be tied to GND if the XRT7300 is to be operated in the
HOST mode.
2TAOSI
Transmit All Ones Select:
A “High” on this pin causes a continuous AMI all “1’s” pattern to be transmitted
onto the line. The frequency of this “1’s” pattern is determined by TCLK.
N
OTES
:
1. This input pi n is ignor ed if the XRT73 00 is operating in the HOST Mode.
2. Tie this pin to GN D if the XRT7300 is going to be ope rati ng in the HOST
Mode.
3 VDD **** Transmit Digital Power Supply
4DMOO
Drive Monitor Output:
If no transmitted AMI signal is present on MTIP and MRING input pins for
128±32 TCLK periods, then the DMO pin toggles and remains “High” until the
next AMI signal is detected.
5GND **** Transmit Digital GND
6GND **** Analog GND (Substrate)
7GND **** Receive Analog GND
8RTIPI
Receive TIP Input:
This input pin along with RR ING is used to re ceive the line s ignal from the
Remote DS3/E3/STS-1 Terminal.
9RRINGI
Receive RING Input:
This inp ut pin a lon g wi th R T I P is u se d to rece ive the line si gnal from the Remo te
DS3/E3/STS-1 Terminal.
10 VDD **** Receive Analog VDD
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
4
11 REGRESET/
(RCLK2INV) IRegister Reset Input pin (Invert RCLK2 Output - Select):
The function of this pin depends upon whether the XRT7300 is operating in the
HOST Mode or in the Hardware Mode.
HOST Mode - Register Reset Input pin:
Setting this input pin “Low” causes the XRT7300 to reset the contents of the
Command Re gi ste r s to their default settin gs and oper ating confi gur a t ion . This
pin is internally pulled “High”.
Hardware Mode - Invert RCLK2 Output Select:
Setting this input pin “Low” configures the Receive Section of the XRT7300 to
output the recovered data via the RPOS and RNEG output pins on the rising
edge of the RCLK2 output signal.
Setting this input pin “High” configures the Receive Section t o output the recov-
ered data on the falling edge of the RCLK2 output signal.
12 REQDIS I Receive Equalization Disable Input:
Setting this input pin “High” disables the Internal Receive Equalize r in the
XRT7300. Setting this pin “Low” enables the Internal Receive Equalizer. The
guidelines for enabling and disabling the Receive Equalizer are described in
Section 3.2.
N
OTES
:
1. This input pi n is ignored if the XRT7300 is operat ing in the HOST Mode.
2. Tie this pin to GN D if the XRT7300 is going to be ope rati ng in the HOST
Mode.
13 LOSTHR I Loss of Signal Threshold Control:
The voltage forced on this pin controls the input loss of signal (LOS) threshold.
Two settings are provided by forcing this signal to either GND or VDD.
N
OTE
: This pin is only applicable during DS3 or STS-1 operations.
14 LLB I Local Loop-Back Select:
This input pin along with RLB dictates which Loop-Back mode the XRT7300 is
oper ati ng in.
A “High” on this pin with RLB being set to “Low” configures the XR T7300 to oper-
ate in the Analog Local Loop-Back Mode.
A “High” on th is pin wi th RLB also being set to “High” con figur es the XRT7300 to
operate in the Digital Local Loop-Back Mode.
N
OTES
:
1. This input pi n is ignored if the XRT7300 is operat ing in the HOST Mode.
2. Tie this pin to GN D if the XRT7300 is going to be ope rati ng in the HOST
Mode.
15 RLB I Remote Loop-Back Select:
This inpu t pin alon g with LLB di ctates whi ch Loop-Bac k mo de the XR T7300 is be
oper ati ng in.
A “High” on thi s pin w i th LL B be ing se t to “L ow” con figu res the XRT7300 to ope r-
ate in the Remote Loop-Back Mode.
A “High” on thi s pin w i th L LB al so bei ng set to “High” c on fig ures the XRT7300 to
operate in the Digital Local Loop-Back Mode.
N
OTES
:
1. This input pi n is ignored if the XRT7300 is operat ing in the HOST Mode.
2. Tie this pin to GN D if the XRT7300 is going to be ope rati ng in the HOST
Mode.
PIN DESCRIPTION
PIN #S
YMBOL TYPE DESCRIPTION
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
5
16 STS-1/DS3 ISTS-1/DS3 Select Input:
A “High” on this pi n configu res the Cloc k Reco v ery Phase Loc k ed Lo op to set its
VCO Center frequency to around 51.84 MHz (optimal for SONET STS-1 opera-
tions). A “L ow ” on t his pin c onfigu res th e Cloc k Reco v ery Phase Loc k e d Loop to
set its VCO Center frequency to around 44.736 MHz (optimal for DS3 opera-
tions).
N
OTES
:
1. The XRT7300 ignores this pin if the E3 pin (pin 17) is set to “1”.
2. This input pi n is ignor ed if the XRT73 00 is operating in the HOST Mode.
3. Tie this pin to GN D if the XRT7300 is going to be ope rati ng in the HOST
Mode.
17 E3 I E3 Select Input:
A “High” on this pin configures the XRT7300 to operate in the E3 Mode.
A “Low ” on this pi n conf igures the XRT7300 to chec k t he stat e of the ST S-1/DS3
input pin.
N
OTES
:
1. This input pi n is ignor ed if the XRT73 00 is operating in the HOST Mode.
2. Tie this pin to GN D if the XRT7300 is going to be ope rati ng in the HOST
Mode.
18 HOST/HW IHOST/HW Mode Select:
This input pin is used to enable or disable the Microprocessor Serial Interface
(e.g., consisting of the SDI, SDO, SCLK, CS and REGRESET pins).
Setting this input pin “High” enables the Mi croprocessor Serial Interface (e.g.
configures the XRT7300 to operate in the HOST Mode). In this mode, the
XRT7300 is configured by writing data into the on-chip Command Registers via
the Microprocessor Serial Interface. When the XRT7300 is operating in the
HOST Mod e, it ignores the states of many of the di screte input pi ns.
Setting this input pin “Low” disables the Microprocessor Serial Interface (e.g.,
configures the XRT7300 to operate in the Hardware Mode). In this mode, many
of the external input control pins are functional.
19 SDI/
(LOSMUTEN) ISerial Data Input for the Microprocessor Serial Interface (HOST Mode) or
MUTE-upon-LOS Enable Input (Hardware Mode):
The functio n of this input pi n depends up on whethe r the XRT 7300 is op erating in
the HOST or the Hardware Mode.
Serial Data Input for the Microprocessor Serial Interface (HOST Mode):
This pin is used to read or write data into the Command Registers of the Micro-
processor Serial Interface. The Read/Write bit, the Address Values of the Com-
mand Registers and Data Value to be written during Write Operations are
applied to this pin.
This input is sampled on the rising edge of the SCLK pin (pin 21).
MUTE-upon-LOS Enable Input (Hardware Mode):
When in the Hardware Mode, this input pin is used to configure the XRT7300 to
MUTE the recovered data via the RPOS and RNEG output pins whenever it
declares an LOS condition.
Setting this input pin “High” configures the XRT7300 to automatically pull the
RPOS and R NEG output pins to GND whene v er it is de claring an LOS c ondition ,
thereby MUTing the data being output to the Terminal Equipment.
Setting thi s inp ut pin “Lo w” con figures the XRT7300 to NO T a utoma ticall y MUTE
the recovered data whenever an LOS condition is declared.
PIN DESCRIPTION
PIN #S
YMBOL TYPE DESCRIPTION
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
6
20 SDO/(LCV) O Serial Data Output from the Controller Port/(Line Code Violation Output
(LCV) Indicator.):
The functio n of this input pi n depends up on whethe r the XRT 7300 is op erating in
the HOST or the Hardware Mode.
HOST Mode - Microprocessor Serial Interface - Serial Data Output.
This pin serially outputs the contents of the specified Command Register during
Read Operations. The data on this pin is updated on the falling edge of the
SCLK input signal. This pin is tri-stated upon completion of data transfer.
Hardware Mode - Line Code Violation Output Indicator.
This pin pulses “High” for one bit period any time the Receive Section of the
XRT7300 detects a Line Code Violation in the incoming E3, DS3 or STS-1 Data
Stream.
21 SCLK/(ENCO-
DIS) IMicroprocessor Serial Interface Clock Signal/Encoder Disable:
HOST Mode - Microprocessor Serial Interface Clock Signal
This signal is used to sample the data on the SDI pin on the rising edge of this
signal. Additionally, during Read operations the Microprocessor Serial Interface
updates the SDO output on the falling edge of this signal.
Hardware Mode - B3ZS/HDB3 Encoder Disable
Setting this input pin “High” disables the B3ZS/HDB3 Encoder and configures
the XRT7300 to transmit the line signal in an AMI Format.
Setting this input pin “Lo w ” enab le s the B3ZS /HDB3 En coder and c onfigu res the
XRT7300 to transmit the line signal in the B3ZS format (for DS3/STS-1 opera-
tion) or in the HDB3 format (for E3 operation).
22 CS/(DECODIS) I Microprocessor Serial Interface - Chip Select/Decoder Disable
The functio n of this input pi n depends up on whethe r the XRT 7300 is op erating in
the HOST or the Hardware Mode.
HOST Mode - Chip Select Input:
The Local Microprocessor must assert this pin (e.g., set it to “0”) in order to
enable communication with the XRT7300 via the Microprocessor Serial Inter-
face.
Hardware Mode - (B3ZS/HDB3 Decoder Disable)
Setting th is i nput p in “Hig h” dis ab les the B3ZS/HDB 3 Deco der. Set ting t his i nput
pin “Low” enables the B3ZS/HDB3 Decoder.
23 RLOL O Receive Loss of Lock Output Indicator
This output pin toggles “High” if the XRT7300 has detected a Loss of Lock Con-
dition. The XRT7300 declares an LOL (Loss of Lock) Condition if the recovered
clock frequency deviates from the Reference Clock frequency (available at the
EXCLK input pin) by more than 0.5%.
24 RLOS O Receive Loss of Signal Output Indicator
This output pin toggles “High” if the XRT7300 has detected a Loss of Signal
Condition in the incoming line signal.
The criteria the XRT7300 uses to declare an LOS Condition depends upon
whether the device is operating in the E3 or DS3/STS-1 Mode.
25 GND **** Digital GND
26 VDD **** Digital VDD
PIN DESCRIPTION
PIN #S
YMBOL TYPE DESCRIPTION
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
7
27 EXCLK I External Reference Clock Input:
Apply a 34.368MHz clock signal for E3 applications, a 44.736 MHz clock signal
for DS3 ap pli ca tio ns o r a 51. 84 M Hz c lock signal for SONET STS-1 applic at ions.
28 GND **** Receiver Digital Ground
29 VDD **** Receiver Digital VDD
30 LCV/(RCLK2) O Line Code Violation Indicator/Receive Clock Output pin 2:
The function of this pin depends upon whether the XRT7300 is operating in the
HOST Mode, the Hardware Mode or User selection.
HOST Mode - Line Code Violation Indicator Output:
If the XRT7300 is configured to operate in the HOST Mode, then this pin func-
tions as the L CV outpu t pin b y default. Ho wever, b y u sing the on-ch ip Com mand
Registers, this pin can be configured to function as the second Receive Clock
signal output pin (RCLK2).
Hardware Mode - Receive Clock Output pin 2:
This outpu t pin is th e Reco v ere d Clock signal from th e incomin g line si gnal. Th e
receive section of the XRT7300 outputs data via the RPOS and RNEG output
pins on the rising edge of this clock signal.
N
OTE
: If the XRT7300 is o per a ting in the HO ST M ode and t his pin is con fig ured
to function as the additional Receive Clock signal output pin, then the XRT7300
can be c onfigured to up date the d ata on the RPOS an d RNEG o utput pin s on the
falling edge of this clock signal.
31 RCLK1 O Receive Clock Output pin 1:
This output pin is the Recovered Clock signal from the incoming line signal. The
receive section of the XRT7300 outputs data via the RPOS and RNEG output
pins on the rising edge of this clock signal.
N
OTE
: I f the XRT7300 device is operatin g in the “H o st” M od e , then the u se r can
configure the device to update the data on the RPOS and RNEG output pins on
the falling edge of this clock signal.
32 RNEG O Receive Negative Pulse Output:
This output pin pulses “High” whenever the XRT7300 has received a Negative
Polarity pulse in the incoming line signal at the RTIP/RRING inputs.
N
OTE
: If the B3ZS/HDB3 Decoder is enabled, then the zero suppression pat-
terns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is not
reflected at this output.
33 RPOS O Receive Positive Pulse Output:
This output pin pulses “High” whenever the XRT7300 has received a Positive
Polarity pulse in the incoming line signal at the RTIP/RRING inputs.
N
OTE
: If the B3ZS/HDB3 Decoder is enabled, then the zero suppression pat-
terns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is not
reflected at this output.
34 ICT IIn-Circuit Test Input:
Setting this pin “Low” causes all digital and analog outputs to go into a high-
impedance state to allow for in-circuit testing. This pin is internally pulled “High”.
PIN DESCRIPTION
PIN #S
YMBOL TYPE DESCRIPTION
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
8
35 TXOFF I Transmitter OFF Input:
Setting this input pin “H igh” co nfigure s the XRT7300 to turn off the Tran smitt er in
the device.
N
OTES
:
1. This input pi n is ignored if the XRT7300 is operat ing in the HOST Mode.
2. Tie this pin to GN D if the XRT7300 is going to be ope rati ng in the HOST
Mode.
36 TCLK I Transmit Clock Input for TPDATA and TNDATA:
This input pin must be driven at 3 4.368 MHz for E3 applications, 44.736MHz for
DS3 applications, or 51.84MHz for SONET STS-1 applications. The XRT7300
uses this signal to sample the TPDATA and TNDATA input pins. By default, the
XRT7300 is configured to sample these two pins on the falling edge of this sig-
nal.
If the XRT7300 is operating in the HOST Mode, then the device can be config-
ured to sample the TPDATA and TNDATA input pins on the rising edge of TCLK.
37 TPDATA I Transmit Positive Data Input:
The XRT73L00 samples this pin on the falling edge of TCLK. If the device sam-
ples a “1” at this input pin, then it generates and transmits a positive polarity
pulse to the line.
N
OTES
:
1. The data should be applied to this input pin if the Transmit Section is
configured to accept Single-Rail data from the Terminal Equipment.
2. If the XRT73L00 is operating in the HOST Mode, then the XRT73L00
can be configured to sample the TPDATA pin on either the rising or fall-
ing edge of TCLK.
38 TNDATA I Transmit Negative Data Input:
The XRT7300 samples this pin on the falling edge of TCLK. If the device sam-
ples a “1” at this input pin, then it generates and transmits a negative polarity
pulse to the line.
N
OTES
:
1. This input pi n is ignored and should b e tied to GND if the Transmi t Sec-
tion is configured to accept Single-Rail data from the Termi nal Equip-
ment.
2. If the XRT7300 is operating in the HOST Mode, then the XRT7300 can
be configured to sample the TNDATA pin on either the rising or falling
edge of TCLK.
39 GND - Transmit Analog Ground
40 TRING O Transmit TIP Output:
The XR T730 0 uses th is pin, al ong wit h TTIP, to tra nsmit a bipo lar line s ignal vi a a
1:1 transformer.
41 TTIP O Transmit RING Output:
The XRT7300 uses this pin, along with TRING, to transmit a bipolar line signal
via a 1:1 transformer.
42 VDD - Transmit Analog Power Supply
PIN DESCRIPTION
PIN #S
YMBOL TYPE DESCRIPTION
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
9
43 MRING I Monitor Ring Input:
The bipol ar line o utp ut signal f rom TRING ca n be con ne cted to this pin v ia a 270
Ω resistor in order to check for line dr iver failure. This pin is inter nally pulled
“High”.
44 MTIP I Monitor Tip Input:
The bipol ar lin e o utput sig nal fro m TTIP can b e con nected to th is pin via a 270 Ω
resistor in order to check f or line driv er failure . This pin is internally pull ed “High”.
PIN DESCRIPTION
PIN #S
YMBOL TYPE DESCRIPTION
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
10
ELECTR ICAL CHARACTERISTICS
* Not applicable to pins with pull-up/pull-down resistors.
DC ELECTRICAL CHARACTERISTICS (TA = 25°C, VDD = 5.0V + 5%, UNLESS OTHERWISE SPECIFIED)
SYMBOL PARAMETER MIN.T
YP.M
AX.U
NITS
VDDD DC Supply Voltage 4.75 5 5.25 V
VDDA DC Supply Voltage 4.75 5 5.25 V
ICC Supply Current (Measured while Transmitting and Receiving all “1’s”)
DS-3 Mode 167 200 mA
STS-1 Mode 180 220 mA
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 VDD V
VOL Output Low Voltage, IOUT = -4.0mA 0 0.4 V
VOH Output High Vo ltage, IO UT = 4.0mA 2.8 VDD V
ILInput Leakage Current* ±10 mA
AC ELECTRICAL CHARACTERIS TICS (TA = 25°C, VDD = 5.0V + 5%, UNLESS OTHERWISE SPECIFIED)
SYMBOL PARAMETER MIN.T
YP.M
AX.U
NITS
Terminal Side Timing Parameters (See Figure 3 & Figure 4)
TCLK Clock Duty Cycle (DS3/STS-1) 30 50 70 %
TCLK Clock Duty Cycle (E3) 30 50 7 0 %
TCLK Frequency (SONET STS-1) 51.84 MHz
TCLK Frequency (DS3) 44.736 MHz
TCLK Frequency (E3) 34.368 MHz
tRTX TCLK Clock Rise Time (10% to 90%) 4 ns
tFTX TCLK Clock Fall Time (90% to 10%) 4 ns
tTSU TPDATA/TNDATA to TCLK Falling Set up time 3 ns
tTHO TPDATA/TNDATA to TCLK Falling Hold time 3 ns
tLCVO RCLK to rising edge of LCV output delay 2.5 ns
tTDY TTIP/TRING to TCLK Rising Propagation Delay time 0.6 14 ns
RCLK Clock Duty Cycle 45 50 55 %
RCLK Frequency (SONET STS-1) 51.84 MHz
RCLK Frequency (DS3) 44.736 MHz
RCLK Frequency (E3) 34.368 MHz
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
11
tCO RCLK to RPOS/RNEG Delay Time 4 ns
tRRX RCLK Clock Rise Time (10% to 90%) 2 4 ns
tFRX RCLK Clock Fall Time (10% to 90%) 1.5 3 ns
Ci Input Capacitance 10 pF
CLLoad Capacitance 10 pF
AC ELECTRICAL CHARACTERIS TICS (TA = 25°C, VDD = 5.0V + 5%, UNLESS OTHERWISE SPECIFIED)
SYMBOL PARAMETER MIN.T
YP.M
AX.U
NITS
FIGURE 3. TIMING DIAGRAM OF THE TRANSMIT TERMINAL INPUT INTERFACE
TPDATA or
TNDATA
TTIP or
TRING
TClk
t
TSU
t
THO
t
RTX
t
FTX
t
TDY
FIGURE 4. TIMING DIAGRAM OF THE RECEIVE TERMINAL OUTPUT INTERFACE
RClk
t
RRX
t
FRX
RPOS or
RNEG
LCV
t
LCVO
t
CO
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
12
(1) Measured at Nominal DSX3 level, Equalizer enabled,
VDD = 5V and TA = 25
o
C
AC ELECTRICAL CHARACTERISTICS (CONTINUED) (TA = 25°C, VDD = 5.0V + 5%, UNLESS OTHER-
WISE SPECIFIED)
Line Side Parameters
SYMBOL PARAMETER MIN.T
YP.M
AX.U
NITS
DS3 Application Parameters
Transmit Line Characteristics (See Figure 5)
Transmit Output Pulse Amplitude (Measured at 0 feet, TXLEV = 0) 0.68 0.75 0.85 Vpk
Transmit Output Pulse Amplitude (Measured at 0 feet, TXLEV = 1) 0.90 1.0 1.1 Vpk
Transmit Output Pulse Width 10.10 11.18 12.28 ns
Transmit Output Pulse Amplitude Ratio 0.9 1.0 1.1
Transmit Output Jitter with jitter-free input clock at TCLK 0.02 0.05 UIpp
Receive Line Character istics
Receive Sensitivity (Length of Cable) 900 1000 feet
Receive Intrinsic Jitter (All One’s Pattern) 0.01 UI
Receive Intrinsic Jitter (100 Pattern) (1) 0.02 UI
LOS Level With Equalizer Enabled (Table 4)
Signal Level to Declare Loss of Signal (LOSTHR = 0) 55 mV
Signal Level to Clear Loss of Signal (LOSTHR = 0) 220 mV
Signal Level to Declare Loss of Signal (LOSTHR = 1) 22 mV
Signal Level to Clear Loss of Signal (LOSTHR = 1) 90 mV
LOS Level With Equalizer Disabled (Table 4)
Signal Level to Declare Loss of Signal (LOSTHR = 0) 35 mV
Signal Level to Clear Loss of Signal (LOSTHR = 0) 155 mV
Signal Level to Declare Loss of Signal (LOSTHR = 1) 17 mV
Signal Level to Clear Loss of Signal (LOSTHR = 1) 70 mV
Max Jitter Tolerance @ Jitter Frequency = 100Hz 64 UI
Max Jitter Tolerance @ Jitter Frequency = 1KHz 64 UI
Max Jitter Tolerance @ Jitter Frequency = 10KHz 5 UI
Max Jitter Tolerance @ Jitter Frequency = 800KHz 0.4 UI
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
13
AC ELECTRICAL CHARACTERISTICS (CONTINUED) (TA = 25°C, VDD = 5.0V + 5%, UNLESS OTHER-
WISE SPECIFIED)
Line Side Parameters
SYMBOL PARAMETER MIN.T
YP.M
AX.U
NITS
E3 Application Parameters
Transmit Line Characteristics (See Figure 5)
Transmit Output Pulse Amplitude (Measured at Secondary Out-
put of Transformer) 0.9 1.00 1.1 Vpk
Transmit Output Pulse Amplitude Ratio 0.95 1.00 1.05
Transmit Output Pulse Width 12.5 14.55 16.5 ns
Transmit Output Pulse Width Ratio 0.95 1.00 1.05
Transmit Output Jitter with jitter-free input clock at TCLK 0.02 0.05 UIpp
Receive Line Character istics
Receive Sensitivity (Length of cable) 1100 feet
Interference Margin -20 -17 dB
Signal Level to Declare Loss of Signal -35 dB
Signal Level to Clear Loss of Signal -15 dB
Occurrence of LOS to LOS Declaration Time 10 100 255 UI
Termination of LOS to LOS Clearance Time 10 100 2 55 UI
Intrinsic Jitter (all "1’s" Pattern) (1) 0.01 UI
Intrinsic Jitter (100 Pattern) 0.03
Max Jitter Tolerance @ Jitter Frequency = 100Hz 64 UI
Max Jitter Tolerance @ Jitter Frequency = 1KHz 30 UI
Max Jitter Tolerance @ Jitter Frequency = 10KHz 4 UI
Max Jitter Tolerance @ Jitter Frequency = 800KHz 0.15 UI
SONET STS-1 Application Parameters
Transmit Line Characteristics (See Figure 5)
Transmit Output Pulse Amplitude (Measured with TXLEV = 0) 0.68 0.75 0.85 Vpk
Transmit Output Pulse Amplitude (Measured with TXLEV = 1) 0.93 0.98 1.08 Vpk
Transmit Output Pulse Width 8.6 9.65 10.6 ns
Transmit Output Pulse Amplitude Ratio 0.9 1.0 1.1
Transmit Output Jitter with jitter-free clock input at TCLK 0.02 0.05 UIpp
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
14
(1) Measured with Equalizer enabled, 12db cable attenua-
tion, VDD = 5V and TA = 25°C
(2) Measured at nominal STSX-1 level with Equalizer en-
abled, VDD = 5V and TA = 25°C
Figure 5 presents the test circuit that was used to test
and measure the pulse amplitudes as listed in the
ELECTRICAL CHARACTERISTICS tables.
Figure 6, Figure 7 and Figure 8 present the Pulse
Template requirements for the E3, DS3 and STS-1
Rates.
Receive Line Character istics
Receive Sensitivity (Length of cable) 900 feet
Signal Level to Declare or Clear Loss of Signal (see Table 4) mV
Intrinsic Jitter (all "1’s" Pattern) (2) 0.03 UI
Intrinsic Jitter (100 Pattern) 0.03 UI
Max Jitter Tolerance @ Jitter Frequency = 100Hz 64 UI
Max Jitter Tolerance @ Jitter Frequency = 1KHz 64 UI
Max Jitter Tolerance @ Jitter Frequency = 10KHz 5 UI
Max Jitter Tolerance @ Jitter Frequency = 800KHz 0.4 UI
AC ELECTRICAL CHARACTERISTICS (CONTINUED) (TA = 25°C, VDD = 5.0V + 5%, UNLESS OTHER-
WISE SPECIFIED)
Line Side Parameters
SYMBOL PARAMETER MIN.T
YP.M
AX.U
NITS
ABSOLUTE MAXIMUM RATINGS
POWER SUPPLY -0.5 TO +6.5V
STORAGE TEMPERATURE -65OC TO 150OC
INPUT VOLTAGE AT ANY PIN -0.5V TO VDD +0.5V
POWER DISSIPATION TQFP PACKAGE 1.2W
INPUT CURRENT AT ANY PIN +100MA
ESD RATING (MIL-STD-8 83, M-3 015 ) AT LEAST 1500V
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
15
FIGURE 5. TRANSMIT PULSE AMPLITUDE TEST CIRCUIT FOR DS3, E3 AND STS-1 RATES
R1
36Ω
R2
36Ω
TTIP
TRING
1:1
R3
75Ω
T1
FIGURE 6. ITU-T G.703 TRANSMIT OUTPUT PULSE TEMPLATE FOR E3 APPLICATIONS
0%
50%
V = 100%
14.55ns
Nominal Pulse
12.1ns
(14.55 - 2.45)
17 ns
(14.55 + 2.45)
8.65 ns
10%
10%
20%
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
16
FIGURE 7. BELLCORE GR-499-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR DS3 APPLICATIONS
DS3 Pulse Templat e
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
-1-0.9-0.8-0.7-0.6-0.5-0.4-0.3-0.2-0.1 00.1 0.20.30.4 0.50.6 0.70.8 0.9 11.11.2 1.31.4
Time, in UI
Normalized Amplitude
Lowe r Cu rve
Uppe r Cu rve
FIGURE 8. BELLCORE GR-253-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS
STS-1 Pulse Templat e
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
-1-0.9-0.8-0.7-0.6-0.5-0.4-0.3-0.2-0.1 00.10.20.30.40.50.60.70.80.9 11.11.21.31.4
Time, in UI
Normalized Amplitude
Lower Curve
Upper Curve
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
17
MICROPROCESSOR SERIAL INTERFACE TIMING (SEE FIGURE 9)
SYMBOL PARAMETER MIN.T
YP.M
AX.U
NITS
t21 CS Low to Rising Edge of SCLK Setup Time 50 ns
t22 CS High to Rising Edge of SCLK Hold Time 20 ns
t23 SDI to Rising Edge of SCLK Setup Time 50 ns
t24 SDI to Rising Edge of SCLK Hold Time 50 ns
t25 SCLK “Low” Time 240 ns
t26 SCLK “High” Time 240 ns
t27 SCLK Period 500 ns
t28 CS Low to Rising Edge of SCLK Hold Time 50 ns
t29 CS Inactive Time 250 ns
t30 Falling Edge of SCLK to S DO Vali d Time 200 ns
t31 Falling Edge of SCLK to SDO Invalid Time 100 ns
t32 Falling Edge of SCLK or Rising Edge of CS to High Z 100 ns
t33 Rise/Fall time of SDO Output 40 ns
FIGURE 9. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
SDI R/W A1
A0
CS
SCLK
CS
SCLK
SDI
SDO D0 D1 D2 D7
t22
t21
t23 t24
t25 t26
t27 t28
t29
t30 t31 t32t33
Hi-Z
Hi-Z
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
18
SYSTEM DESCRIPTION
A functional block diagram of the XRT7300 E3/DS3/
STS-1 Transceiver IC (see Figure 1) shows that the
device contains three distinct sections:
•The Transmit Section
•The Receive Section
•The Microprocessor Serial Interface
THE TRANSMIT SECTION
The Transmit Section accepts TTL/CMOS level sig-
nals from the Terminal Equipment in either a Single-
Rail or Dual-Rail format. The Transmit Section then
takes this data and does the following:
•Encodes the data into the B3ZS format if the DS3
or SONET STS-1 Modes have been selected or
into the HDB3 format if the E3 Mode has been
selected.
•Converts the CMOS le vel B3ZS or HDB3 encoded
data into pulses with shapes that are compliant with
the various industry standard pulse template
requirements.
•Drives these pulses onto the line via the TTIP and
TRING output pins across a 1:1 Transformer.
N
OTE
: The Transmit Section drives a "1" (or a Mark) on the
line by driving either a positive or negative polarity pulse
across the 1:1 Transformer within a given bit per iod. The
Transmit Section drives a "0" (or a Space) onto the line by
driving no pulse onto the line.
THE RECEIVE SEC TION
The Receive Section receives a bipolar signal from
the line either via a 1:1 Transformer or a 0.01mF Ca-
pacitor. As the Receive Section receives this line sig-
nal it does the following:
•Adjusts the signal level through an AGC circuit.
•Optionally equalizes this signal for cable loss.
•Attempts to quantify a bit-interval within the line sig-
nal as either a “1”, “-1” or a “0” by slicing this data.
This slic ed d ata is used b y t he Cl oc k R eco v e ry PLL
to recover the timing element within the line signal.
•The sliced data is routed to the HDB3/B3ZS
Decoder, during which the original data content as
transmitted by the Remote Terminal Equipment is
restored to its original content.
•Outputs the recovered clock and data to the Local
Terminal Equipment in the form of CMOS level sig-
nals via the RPOS, RNEG, RCLK1 and RCLK2 out-
put pins.
THE MICROPROCESSOR SERIAL INTERFACE
The XRT7300 can be configured to operate in either
the Hardware Mode or the HOST Mode.
The Hardware Mode
Connect the HOST/HW input pin (pin 18) to GND to
configure the XRT7300 to operate in the Hardware
Mode.
When the XRT7300 is operating in the Hardware
Mode, the follo wing is true:
1. The Microprocessor Serial Interface block is
disabled.
2. The XRT7300 is confi gured via inp ut pin set tin gs.
Each of the pins associated with the Microprocessor
Serial Interface takes on their alternativ e role as de-
fined in Table 1.
3. All of the remaining input pins become active.
TABLE 1: ROLE OF M ICROPROCESSOR SERIAL INTERFACE PINS WHEN THE XRT7300 IS OPERATING IN THE
HARDWARE MODE
PIN #P
IN NAME FUNCTION WHILE IN THE HARDWARE MODE
11 REGRESET/(RCLK2INV) RCLK2INV
19 SDI/(LOSMUTEN) LOSMUTEN
20 SDO/(LCV) LCV
21 SCLK/(ENCODIS) ENCODIS
22 CS/(DECODIS) DECODIS
30 LCV/(RCLK2) RCLK2
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
19
The HOST Mode
To configure the XRT7300 to operate in the HOST
Mode, connect the HOST/HW input pin (pin 18) to
VDD.
When the XRT7300 is operating in the HOST Mode,
the following is true:
1. The Microprocessor Serial Interface block is
enabled. Many configuration selections are
made by writing the appropriate data into the on-
chip Command Registers via the Microprocessor
Serial Interface.
2. All of the following input pins are disabled:
•Pin 1 - TXLEV
•Pin 2 - TAOS
•Pin 12 - REQDIS
•Pin 14 - LLB
•Pin 15 - RLB
•Pin 16 - STS-1/DS3
•Pin 17 - E3
•Pin 35 - TXOFF
Tie each of these pins to GND if the XR T7300 IC is to
be operated in the HOST Mode.
Please see Section 5.0 for a detailed description on
operating the Microprocessor Serial Interface or the
on-chip Command Registers.
1.0 SELECTING THE DATA RATE
The XRT7300 can be configured to support the E3
(34.368 Mbps), DS3 (44.736 Mbps) or the SONET
STS-1 (51.84 Mbps) rates. Selection of the data rate
is dependent on whether the XRT7300 is operating in
the Hardware or HOST Mode.
A. When operating in the Hardware Mode.
To configure the XRT7300 for the desired data rate,
the E3 and the STS-1/DS3 pins must be set to the ap-
propriate logic states shown in Table 2.
B. When operating in the HOST Mode.
To configure the XRT7300 for the desired data rate,
appropriate values need to be written into the STS-1/
DS3 and E3 bit-fields in Command Register CR4.
Table 3 relates the values of these two bit-fields with
respect to the selected data rates.
The results of making these selections are:
1. The VCO Center Frequency of the Clock Recov-
ery Phase-Locked-Loop is configured to match
the selected data rate.
2. The B3ZS/HDB3 Encoder and Decoder blocks
are configured to support B3ZS Encoding/Decod-
ing if the DS3 or STS-1 data rates were selected
or,
3. The B3ZS/HDB3 Encoder and Decoder blocks
are configured to support HDB3 Encoding/
Decoding if the E3 data rate was selected.
4. The on-chip Pulse-Shaping circuitry is configured
to generate Transmit Output pulses of the correct
TABLE 2: SELECTING THE DATA RATE FOR THE XRT7300 VIA THE E3 AND STS-1/DS3 INPUT PINS (HARDWARE
MODE)
DATA RATE STATE OF E3 PIN
(PIN 17) STATE OF STS-1/DS3 PIN
(PIN 16) MODE OF B3ZS/HDB3 ENCODER/
DECODER BLOCKS
E3 (34.368 Mbps) VDD X (Don’t Care) HDB3
DS3 (44.736 Mbps) 0 0 B3ZS
STS-1 (51.84 Mbps) 0 VDD B3ZS
COMMAND REGISTER CR4 (ADDRESS = 0X04)
D4 D3 D2 D1 D0
XSTS-1/DS3 E3 LLB RLB
X X XXX
TABLE 3: SELECTING THE DATA RATE FOR THE
XRT7300 VIA THE STS-1/ DS3 AND THE E3 BIT-FIELDS
WITHIN COMMAND REGISTER CR4 (HOST MODE)
SELECTED DATA RATE STS-1/DS3 E3
E3 Don't Care 1
DS3 0 0
STS-1 1 0
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
20
shape and width to meet the applicable pulse
template requirement.
5. The LOS Declaration/Clearance Criteria is estab-
lished.
2.0 THE TRANSMIT SECTION
Figure 1 indicates that the Transmit Section of the
XRT7300 consists of the following blocks:
•Transmit Logic Block
•Duty Cycl e Adjust Block
•HDB3/B3ZS Encoder
•Pulse Shaping Block
The purpose of the Transmit Section in the XRT7300
is to take TTL/CMOS le vel data from the terminal
equipment and encode it into a format that can:
1. be efficiently transmitted ov er coaxial cab le at E3,
DS3 or STS-1 data rates.
2. be reliab ly received by the Remote Terminal at
the other end of the E3, DS3 or STS-1 data link.
3. comply with the applicable pulse template
requirements.
2.1 THE TRANSMIT LOGIC BLOCK
The purpose of the Transmit Logic Block is to accept
either Dual-Rail or Single-Rail (a binary data stream)
TTL/CMOS le v el data and timing inf ormation from the
Terminal Equipment.
Accepting Dual-Rail Data from the Terminal
Equipment
The XRT7300 accepts Dual-Rail data from the Termi-
nal Equipment via the following input signals:
•TPDATA
•TNDATA
•TCLK
Figure 10 illustrates the typical interface for the trans-
mission of data in a Dual-Rail Format between the
Terminal Equipment and the Transmit Section of the
XRT7300.
FIGURE 10. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL-RAIL FORMAT FROM THE TRANS-
MITTING TERMINAL EQUIPMENT TO THE TRANSMIT SECTION OF THE XRT7300
Exar E3/DS3/STS-1 LIU
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
TxPOS
TxNEG
TxLineClk
Transmit
Logic
Block
Transmit
Logic
Block
TPDATA
TNDATA
TCLK
FIGURE 11. HOW THE XRT7300 SAMPLES THE DATA ON THE TPDATA AND TNDATA INPUT PINS
TCLK
TPDATA
TNDATA
Data 1 1 0 0
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
21
The manner that the LIU handles Dual-Rail data is
described below and illustrated in Figure 11. The
XRT7300 typically samples the data on the TPDATA
and TNDATA input pins on the falling edge of TCLK.
TCLK is typically a clock signal that is of the selected
data rate frequency. For the E3 data rate, TCLK is
34.368 MHz. For the DS3 data rate, TCLK is 44.736
MHz and for the SONET STS-1 rate, TCLK is 51.84
MHz. In general, if the XRT7300 samples a “1” on
the TPDATA input pin, the Transmit Section of the de-
vice ultimately generates a positive polarity pulse via
the TTIP and TRING output pins across a 1:1 trans-
f ormer . If the XRT7300 samples a “1” on the TNDATA
input pin, the Transmit Section of the device ultimately
generates a negative polarity pulse via the TTIP and
TRING output pins across a 1:1 transformer.
2.1.1 Accepting Single-Rail Data from the Ter-
minal Equipment
Do the following if data is to be transmited from the
Terminal Equipment to the XRT7300 in Single-Rail
format (a binary data stream) without having to con-
vert it into a Dual-Rail format.
A. Configure the XRT7300 to operate in the HOST
Mode or,
B. access the Microprocessor Serial Interface and
write a “1” into the TXBIN (TRANSMIT BINary)
bit-field in Command Register 1.
After taking these steps, the Transmit Logic Block ac-
cepts Single-Rail data via the TPD ATA input pin. The
XRT7300 samples this input pin on the f alling edge of
the TCLK clock signal and encodes it into the appro-
priate bipolar line signal across the TTIP and TRING
output pins.
N
OTES
:
1. In this mode the Transmit Logic Block ignores the
TNDATA input pin.
2. If the Transmit Section of the XRT7300 is config-
ured to accept Single-Rail data from the Ter minal
Equipment, the B3ZS/HDB3 Encoder must be
enabled.
Figure 12 illustrates the behavior of th e TPDATA and
TCLK signals when the Transmit Logic Block has
been configured to accept Single-Rail data from the
Terminal Equipment.
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIR-
CUITRY
The on-chip Pulse-Shaping circuitry (in the Transmit
Section of the XRT7300) has the responsibility for
generating pulses of the shape and width to comply
with the applicable pulse template requirement. The
widths of these output pulses are defined by the width
of the half-period pulses in the TCLK signal.
Allowing the widths of the pulses in the TCLK clock
signal to vary significantly could jeopardize the chip’s
ability to generate Transmit Output pulses of the ap-
propriate width, thereby failing the applicable Pulse
Template Requ ir em ent Spe ci fic at ion . Conseque ntl y,
the chips ability to generate compliant pulses could
depend upon the duty cycle of the clock signal ap-
plied to the TCLK input pin.
In order to combat this phenomenon, the Transmit
Clock Duty Cycle Adjust circuit was designed into the
XRT7300. The Transmit Clock Duty Cycle Adjust Cir-
cuitry is a PLL that was designed to accept clock
pulses via the TCLK input pin at duty cycles ranging
from 30% to 70% and to regenerate these signals
with a 50% duty cycle.
COMMAND REGISTER CR1 (ADDRESS = 0X01)
D4 D3 D2 D1 D0
TXOFF TAOS TXCLKINV TXLEV TXBIN
XXXX
1
FIGURE 12. THE BEHAVIOR OF THE TPDATA AND TCLK INPUT SIGNALS WHILE THE TRANSMIT LOGIC BLOCK IS
ACCEPTING SINGLE-RAIL DATA FROM THE TERMINAL EQUIPMENT
TCLK
TPDATA
Data 1 1 0 0
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
22
The XRT7300 Transmit Clock Duty Cycle Adjust cir-
cuit alleviates the need to supply a signal with a 50%
duty cycle to the TCLK input pin.
2.3 THE HDB3/B3ZS ENCODER BLOCK
The purpose of the HDB3/B3ZS Encoder Block is to
aid in the Clock Recovery process (at the Remote
Terminal Equipment) by ensuring an upper limit on
the number of consecutive zeros that can exist in the
line signa l.
2.3.1 B3ZS Encoding
If the XR T7300 is configured to operate in the DS3 or
SONET STS-1 Modes, then the HDB3/B3ZS Encoder
bloc k operates in the B3ZS Mode. When the Encoder
is operating in this mode, it parses through and
searches the Transmit Binary Data Stream (from the
Transmit Logic Block) for the occurrence of three (3)
consecutive z eros (“000”). If the B3ZS Encoder finds
an occurrence of three consecutive zeros, it substi-
tutes these three “0’s” with either a "00V" or a "B0V"
pattern.
“B” represents a Bipolar pulse that is compliant with
the Alternating Polarity requirements of the AMI (Al-
ternate Mark Inversion) line code and “V” represents
a bipolar Violation (e.g., a bipolar pulse that violates
the Alternating Polarity requirements of the AMI line
code).
The B3ZS Encoder decides whether to substitute
with either a "00V" or a "B0V" pattern in order to in-
sure that an odd number of bipolar pulses exist be-
tween any two consecutive violation pulses.
Figure 13 illustrates the B3ZS Encoder at work with
two separate strings of three (or more) consecutive
zeros.
2.3.2 HDB3 Encoding
If the XRT7300 is configured to operate in the E3
Mode, then the HDB3/B3ZS Encoder block operates
in the HDB3 Mode. When the Encoder is operating in
this mode, it parses through and searches the Trans-
mit Data Stream (from the Transmit Logic Block) for
the occurrence of f our (4) consecutiv e zeros (“0000”).
If the HDB3 Encoder finds an occurrence of four con-
secutive z eros, then it substitutes these four “0’s” with
either a “000V” or a “B00V” pattern in order to insure
that an odd number of bipolar pulses exist between
any two consecutive violation pulses.
FIGURE 13. AN EXAMPLE OF B3ZS ENCODING
Data
TPDATA
TNDATA
1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1
0 0 V
Line Signal
B 0 V
TCLK
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
23
Figure 14 illustrates the HDB3 Encoder at work with
two separate strings of four (or more) consecutive ze-
ros.
2.3.3 Enabling/Disabling the HDB3/B3ZS
Encoder
The XRT7300 allows two methods to enable or dis-
able the HDB3/B3ZS Encoder.
If the XRT7300 is operating in the Hard ware Mode.
To enable the HDB3/B3ZS Encoder, set the ENCO-
DIS input pin (pin 21) to “0”. To disable the HDB3/
B3ZS Encoder , set the ENCODIS input pin (pin 21) to
“1”.
If the XRT7300 is operating in the HOST Mode.
To enable the HDB3/B3ZS Encoder, set the ENCO-
DIS bit-field in Command Register (CR2) to “0”.
To disable the HDB3/B3ZS Encoder, set the ENCO-
DIS bit-field in Command Register (CR2) to “1”.
If either of these two methods is employed to disable
the HDB3/B3ZS Encoder, the LIU transmits the data
onto the line as it is received via the TPDATA and
TNDATA input pins.
2.4 THE TRANSMIT PULSE SHAPER CIRCUITRY
The Transmit Pulse Shaper Circuitry consists of a
Transmit Line Build-Out circuit which can be enabled
or disabled by setting the TXLEV input pin (or TXLEV
bit-field) to “High” or “Low”. The purpose of the
Transmit Line Build-Out circuit is to permit configuring
of the XRT7300 to transmit an output pulse which is
compliant to either of the following Bellcore pulse
template requirements when measured at the Digital
Cross Connect System. Each of these Bellcore spec-
ifications further state that the cable length between
the Transmit Output and the Digital Cross Connect
system can range anywhere from 0 to 450 feet.
The Isolated DSX-3 Pulse Template Requirement per
Bellcore GR-499-CORE is illustrated in Figure 7.
The Isolated STSX-1 Pulse Template Requirement
per Bellcore GR-253-CORE is illustrated in Figure 8.
2.4.1 Enabling the Transmit Line Build-Out Cir-
cuit
If the Transmit Line Build-Out Circuit is enabled, the
XRT7300 outputs shaped pulses onto the line via the
TTIP and TRING output pin s.
Do the f ollowing to enable the Transmit Line Build-Out
circuit in the XRT7300:
•If the XRT7300 is operating in the Hardware Mode,
set theTXLEV input pin (pin 1) to “Low”
•If the XRT7300 is operating in the HOST Mode, set
the TXLEV bit-field to “0” as illustrated below.
2.4.2 Disabling the Transmit Line Build-Out Cir-
cuit
FIGURE 14. AN EXAMPLE OF HDB3 ENCODING
Data
TPDATA
TNDATA
1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1
0 0 0 V
Line Signal
B 0 0 V
TCLK
COMMAND REGISTER CR2 (ADDRESS = 0X02
D4 D3 D2 D1 D0
DECODIS ENCODIS ALOSDIS DLOSDIS REQDIS
X0XXX
COMMAND REGISTER CR1 (ADDRESS = 0X01)
D4 D3 D2 D1 D0
TXOFF TAOS TXCLKINV TXLEV TXBIN
0X X 01
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
24
If the Transmit Line Build-Out circuit is disabled, then
the XRT7300 outputs partially-shaped pulses onto
the line via the TTIP and TRING output pins.
Disable the Transmit Line Build-Out circuit in the
XRT7300 by doing the following:
•If the XRT7300 is operating in the Hardware Mode,
set the TXLEV input pin (pin 1) to “High”
•If the XRT7300 is operating in the HOST Mode, set
the TXLEV bit-field to “1” as illustrated below.
2.4.3 D esign Guideline for Setting the Transmit
Line Build-Out Cir cuit
The setting ofTXLEV input pin or bit-field should be
based upon the overall cable length between the
Transmitting Terminal and the Digital Cross Connect
system (where the pulse template measurements are
made).
If the cable length between the Transmitting Terminal
and the DSX-3 or STSX-1 is less than 225 feet, it is
advisable to enable the Transmit Line Build-Out circuit
by setting the TXLEV input pin or bit-field to "0".
N
OTE
: In this case the XRT7300 outputs shaped (e.g., not
square-wave) pulses onto the line via the TTIP and TRING
output pins. The shape of this outpu t pulse is such that it
complies with the pulse template requirements even when
subjected to cable loss ranging from 0 to 225 feet.
If the cable length between the Transmitting
Terminal and the DSX-3 or STSX-1 is greater than
225 feet, it is advisable to disable the Transmit Line
Build-Out circuit by setting the TXLEV input pin or bit-
field to "1".
N
OTE
: In this case the XRT7300 outputs partially-shaped
pulses onto the line via the TTIP and TRING output pins.
The cab le loss that the se pulses e xperience o ver lo ng cable
lengths (e .g ., g r e ate r tha n 22 5 feet) causes t hes e pu ls es to
be properly shaped and comply with the appropriate pulse
template requirement.
2.4.4 The Transmit Line Build-Out Circuit and
E3 Applications
The ITU-T G.703 Pulse Template Requirements f o r
E3 states that the E3 transmit output pulse should be
measured at the Secondary Side of the Transmit Out-
put Transformer for Pulse Template compliance. In
other words, there is no Digital Cross Connect Sys-
tem pulse template requirement for E3 and the Trans-
mit Line Build-Out circuit in the XRT7300 is disabled
whenever it is operating in the E3 Mode.
2.5 INTERFACING THE TRANSMIT SECTION OF THE
XRT7300 TO THE LINE
The E3, DS3 and SONET STS-1 specification docu-
ments all state that line signals transmitted over coax-
ial cable are to be terminated with 75 Ohms. There-
fore, interface the Transmit Section of the XRT7300,
as illustrated in Figure 15 which shows two 36 Ohm
resistors in series with the primary side of the trans-
former. These two 36Ohm resistors closely match
the 75Ohm load termination resistor thereby minimiz-
ing Transmit Return Loss.
COMMAND REGISTER CR1 (ADDRESS = 0X01)
D4 D3 D2 D1 D0
TXOFF TAOS TXCLKINV TXLEV TXBIN
0X X 11
FIGURE 15. RECOMMENDED SCHEMATIC FOR INTERFACING THE TRANSMIT SECTION OF THE XRT7300 TO THE LINE
R1
36.0Ω
R2
36.0Ω
TTIP
TRING
1:1
BNC
T1
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
25
TRANSFORMER VENDOR INFORMATION
Pulse
Cor porate Office
12220 World Trade Drive
San Diego, CA 92128
Tel: (619)-674-8100
FAX: (619)-674-8262
Europe
1 & 2 Huxley Road
The Surrey Research Park
Guildford, Surrey GU2 5RE
United Kingd om
Tel: 44-1483-401700
FAX: 44-1483-401701
Asia
150 Kampong Ampat
#07-01/02
KA Centre
Singapor e 3683 24
Tel: 65-287-8998
FAX: 65- 280 -0080
3.0 THE RECEIVE SECTION
Figure 1 indicates that the XRT7300 Receive Section
consists of the following blocks:
•AGC/Equalizer
•Peak Detector
•Slicer
•Clock Recovery PLL
•Data Recovery
•HDB3/B3ZS Decoder
The purpose of the XRT7300 Receive Section is to
take an incoming attenuated/distorted bipolar signal
from the line and encode it back into the TTL/CMOS
format where it can be received and processed by
digital circuitry in the Terminal Equipment.
3.1 INTERFACING THE RECEIVE SECTION OF THE
XRT7300 TO THE LINE
By design, the Receive Section of the XRT7300 can
be transformer-coupled or capacitive-coupled to the
line. The specification documents for E3, DS3 and
STS-1 all specify 75Ohm termination loads when
transmitting ov er coaxial cable . It is recommended to
TRANSFORMER RECOMMENDATIONS
PARAMETER VALUE
Turns Ratio 1:1
Primary Inductance 40µH
Isolati on Voltage 1500Vrms
Leakage Inductance 0.6µH
PART NUMBER VENDOR INSULATION PACKAGE TYPE
PE-68629 Pulse 3000V Large Thru-Hole
PE-65966 Pulse 1500V Small Thru-Hole
PE-65967 Pulse 1500V Small SMT
T3001 Pulse 1500V Small SMT
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
26
interface the Receive Section of the XRT7300 to the
line as shown in Figure 16 or Figure 17.
3.2 THE RECEIVE EQUALIZER BLOCK
After the XRT 7300 has received the incoming line
signal via the RTIP and RRING input pins, the first
block that this signal passes through is the AGC cir-
cuit follow ed by the Receive Equalizer.
As the line signal is transmitted from a giv en transmit-
ting terminal, the pulse shapes at that location are ba-
sically square. Hence, these pulses consist of a com-
bination of “Low” and “High” frequency Fourier com-
ponents. As this line signal travels from the transmit-
ting terminal via the coaxial cable to the receiving
terminal, it is subjected to frequency-dependent loss.
In other words, the higher-frequency components of
the signal is subjected to a greater amount of attenu-
ation than the lower-frequency components. If this
line signal travels over reasonably long cable lengths
(e.g., greater than 450 feet), then the shape of the
pulse s (whi ch we re origi nally squa re) is disto rted and
inter- symb o l inte rference increas es.
The purpose of the Receive Equalizer is to equalize
the distortion of the incoming signal due to cable loss.
The Receive Equalizer accomplishes this by subject-
ing the received line signal to frequency-dependent
amplification (which attempts to counter the frequen-
cy dependent loss that the line signal has experi-
enced) and to restore the shape of the line signal so
FIGURE 16. RECOMMENDED SCHEMATIC FOR INTERFACING THE RECEIVE SECTION OF THE XRT7300 TO THE LINE
(TRANSFORMER-COUPLING)
BNC
1:1
R1
37.5Ω
R2
37.5Ω
RTIP
RRING
C1
0.01uF
RPOS
RNEG
RCLK1
RLOS
RLOL
RxLOS
RxLOL
RxPOS
RxNEG
RxLineClk T2
FIGURE 17. RECOMMENDED SCHEMATIC FOR INTERFACING THE RECEIVE SECTION OF THE XRT7300 TO THE LINE
(CAPACITIVE-COUPLING)
R1
75Ω
RTIP
RRING
C1
0.01uF
C2
0.01uF
Receive Line Signal
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
27
that the transmitted data and cloc k can be recovered
reliably.
The Use of the Receive Equalizer in a T y pical DS3
or STS-1 Application
Most System Manuf acturers of equipment supporting
DS3 and STS-1 lines interface their equipment to a
Digital Cross-Connect System. While installing their
equipment, the Transmit Line Build-Out circuit is set
to the proper setting that makes the transmit output
pulse compliant with the Isolated DSX-3 or STSX-1
Pulse Template requirements. For the XRT7300 this
is achieved by setting the TXLEV input pin or bit-field
to the appropriate level.
When the System Manuf acturer is interfacing the Re-
ceive Section of the XRT7300 to the Digital Cross-
Connect system, they should keep aware of the fol-
lowing facts:
1. By definition, all DS3 or STS-1 line signals that
are pres ent at the Digital Cross-Connect system
are required to meet the Isolated Pulse Template
Requirements per Bellcore GR-499-CORE for
DS3 applications or Bellcore GR-253-CORE for
STS-1 applications.
2. Further, these Bellcore documents state that the
amplitude of these pulses at the DSX-3 or STSX-
1 can range in amplitude from 360mVpk to
850mVpk.
3. Finally, these Bellcore documents stipulate that
the Receiving Terminal must be able to receive
this pulse-template compliant line signal over a
cable length of 0 to 450 feet from the Digital
Cross Connect system.
These facts are reflected in Figure 18.
Design Considerations for DS3 and STS-1 Appli-
cations
When installing equipment into environments as de-
picted in Figure 15, it is recommended that the Re-
ceive Equalizer be enabled by setting the REQDIS in-
put pin or bit-field to "0". In fact, the only time that the
Receive Equalizer should be disabled is when there
is an off-chip equalizer in the Receive path between
the Digital Cross-Connect system and the RTIP/
RRING input pins or, in applications where the Re-
ceiver is monitoring the transmit output signal directly.
FIGURE 18. THE TYPICAL APPLICATION FOR THE SYSTEM INSTALLER
DSX-3
or
STSX-1
Digital Cross-
Connect System
Transmitting
Terminal
Receiving
Terminal
0 to 450 feet of
Cable
Pulses that are
compliant to the
Isolated DSX-3 or
STSX-1 Pulse
Template
Requirement
0 to 450 feet of
Cable
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
28
Design Considerations for E3 Applications or if
the Overall Cable Length is known
Figure 18 indicates the following:
A. the length of cable between the Transmitting Ter-
minal and the Digital Cross-Connect system can
range between 0 and 450 feet and
B. the length of cable between the Digital Cross-
Connect system and the Receive Terminal can
range between 0 and 450 feet.
The overall cable length between the Transmitting
Terminal and the Receiving Terminal can range be-
tween very short cable length (near 0 feet) up to 900
feet.
If during system installation the overall cable length is
known, then (to optimize the performance of the
XRT 7300 in terms of receive jitter performance, etc.),
the Receive Equalizer should be enabled or disabled
based upon the following recommendations:
The Receive Equalizer should be turned ON if the
Receive Section is going to receive a line signal with
an overall cable length of 300 feet or greater. The
Receive Equalizer sh ould be turned OFF if the Re-
ceive Section is going to receive a line signal over a
cable length of less than 300 feet.
N
OTES
:
1. If the Receive Equalizer block is turned ON (in a
giv en Rec eive Sec tion that is receiving a line sig nal
over short cable length), there is the risk of over-
equalizing the received line signal which could
degrade performance by increasing the amount of
jitter that exists in the recovered data and clock sig-
nals or by creating bit-errors.
2. The Receive Equalizer has been designed to
counter the frequency-dependent cable loss that a
line signal experiences as it travels from the Trans-
mitting Terminal to the Receiving Terminal. How-
ever, Receive Equalizer was not desig ned to
counter flat loss where all of the Fourier frequency
components in the line signal are subject to the
same amount of attenuation. Flat loss is handled
by the AGC block.
The Receive Equalizer block can be disabled setting
the REQDIS input pin “High” when operating in the
Hardware Mode or writing a "1" to the REQDIS bit-
field in Command Register CR2 when operating the
XRT7300 in the HOST Mode.
3.3 PEAK DETECTOR AND SLICER
After the incoming line signal has passed through the
Receive Equalizer it is routed to the Slicer bloc k. The
purpose of the Slicer is to quantify a given bit-period
(or symbol) within the incoming line signal as either a
“1” or a “0”.
3.4 CLOCK RECOVERY PLL
The output of the Slicer , which is now Dual-Rail digital
pulses, is routed to the Cloc k Recovery PLL. The
purpose of the Clock Recovery PLL is to track the in-
coming Dual-Rail data stream and to derive and gen-
erate a recovered clock signal.
It is important to note that the Clock Recov ery PLL re-
quires a line rate clock signal at the EXCLK input pin.
The Clock Recovery PLL operates in one of two
modes:
•The Training Mode.
•The Data/Clock Recovery Mode
1. The Training Mode
If the XRT7300 is not receiving a line signal via the
RTIP and RRING input pins or if the frequency differ-
ence between the line signal and that applied via the
EXCLK input pin exceeds 0.5%, then the XRT7300
LIU IC is operating in the Training Mode. When the
LIU is operating in the Training Mode it does the fol-
lowing:
A. declares a Loss of Lock indication by toggling the
RLOL output pin “High” and
B. outputs a clock signal via the RCLK1 and RCLK2
output pins which is derived from the signal ap-
plied to the EXCLK input pin.
2. The Data/Clock Recovery Mode
If the frequency difference between the line signal
and that applied via the EXCLK input pin is less than
0.5%, the XRT7300 LIU IC is operating in the Data/
Clock Recovery Mode. In this mode, the Clock Re-
cov ery PLL is lock ed onto the line signal via the RTIP
and RRING input pins.
3.5 THE HDB3/B3ZS DECODER
The Remote Transmitting Terminal typically encodes
the line signal into some sort of Zero Suppression
Line Code (e.g., HDB3 for E3 and B3ZS for DS3 and
STS-1). The purpose of this encoding activity was to
aid in the Clock Recovery process of th is data in the
Near-End Receiving Terminal. Howev er, once the da-
ta has made it across the E3, DS3 or STS-1 Trans-
port Medium and has been recovered by the Clock
Reco very PLL, it is no w necess ary to restor e the orig-
inal content of the data. The purpose of the HDB3/
B3ZS Decoding block is to restore the data (transmit-
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4 D3 D2 D1 D0
DECODIS ENCODIS ALOSDIS DLOSDIS REQDIS
X0XX1
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
29
ted ov er the E3, DS3 or STS-1 line) to its original con-
tent prior to Zero Suppression encoding.
3.5.1 B 3ZS Decoding DS3/STS-1 Applications
If the XRT7300 is configured to operate in the DS3 or
STS-1 Modes, then the HDB3/B3ZS Decoding Block
performs B3ZS Decoding. When the Decoder is op-
erating in this mode it parses through the incoming
Dual-Rail data and checks f or the occurrence of ei-
ther a “00V” or a “B0V” pattern. If the B3ZS Decoder
detects this particular pattern it substitutes these bits
with a “000” pattern.
N
OTE
: If the B3ZS Decoder detects any bipolar violations
that is not in accordance with the”B3ZS Line Code” format,
or if the B3ZS Decoder detects a string of 3 (or more) con-
secutive “0’s” in the incoming line signal, then the B3ZS
Decoder flags this event as a Line Code Violation by puls-
ing the LCV output pin “High”.
Figure 19 illustrates the B3ZS Decoder at work with
two separate Zero Suppression patterns in the in-
coming Dual-Rail Data Stream.
3.5.2 HDB3 Decoding E3 Applications
If the XRT7300 is configured to operate in the E3
Mode, the HDB3/B3ZS Decoding Block performs
HDB3 Decoding. When the Decoder is operating in
this mode it parses through the incoming Dual-Rail
data and checks f or the occurrence of either a “000V”
or a “B00V” pattern. If the HDB3 Decoder detects
this particular pattern, it substitutes these bits with a
“0000” pattern.
Figure 20 illustrates the HDB3 Decoder at work with
two separate Zero Suppression patterns in the in-
coming Dual-Rail Data Stream.
N
OTE
: If the HDB3 Decoder detects any bipolar violation
(e.g., “V”) pulses that is not in accordance with the HDB3
Line Code format, or if the HDB3 Decoder detects a string
of 4 (or more) “0’s” in the incoming line signal, then the
HDB3 Decoder flags this event as a Line Code Violation by
pulsing the LCV output pin “High”.
FIGURE 19. AN EXAMPLE OF B3ZS DECODING
Data 0 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1
RPOS
RNEG
0 0 V
Line Signal
B 0 V
RCLK
FIGURE 20. AN EXAMPLE OF HDB3 DECODING
Data 0 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1
0 0 0 V
Line Signal
B 0 0 V
RPOS
RNEG
RCLK
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
30
3.5.3 Enabling/Disabling the HDB3/B3ZS
Decoder
The HDB3/B3ZS Decoder of the XRT7300 can be
enabled or disabled by either of the following means:
If the XRT7300 is operating in the Hard ware Mode:
Enable the HDB3/B3ZS Decoder by pulling the DE-
CODIS input pin (pin 22) to GND. To disable the
HDB3/B3ZS Decoder, pull the DECODIS input pin to
VDD.
If the XRT7300 is operating in the HOST Mode:
Enable the XRT7300 HDB3/B3ZS Decoder by writing
a “0” into the DECODIS bit-field in Command Regis-
ter CR2. To disable the HDB3/B3ZS Decoder , write a
“1” into the DECODIS bit-field.
3.6 LOS DECLARATION/CLEARANCE
The XRT7300 contains circuitry that monitors the fol-
lowing two parameters associated with the incoming
line signa ls.
1. The amplitude of the incoming line signal via the
RTIP and RRING inputs; and
2. The number of pulses detected (in the incoming
line signal) within a certain amount of time.
If the XRT7300 determines that the incoming line sig-
nal is missing (either due to insufficient amplitude or a
lack of pulses in the incoming line signal), then it de-
clares a Loss of Signal (LOS) condition. The
XRT7300 declares the LOS condition by toggling the
RLOS output pin “High” and by setting the RLOS bit
field in C ommand Register 0 to “1”.
If the XRT7300 determines that the incoming line sig-
nal has been restored (e.g., there is sufficient ampli-
tude and pulses in the incoming line signal) then it
clears the LOS condition by toggling the RLOS output
pin “Low” and setting the RLOS bit-field to “0”.
The LOS Declaration/Clearance scheme that is em-
ployed in the XRT7300 is based upon ITU-T Recom-
mendation G.775 for both E3 and DS3 applications.
The LOS Declaration and Clearance criteria that the
XRT7300 uses for each of these modes (e.g., E3 and
DS3) are presented below.
3.6.1 The LOS Declaration/Clearance Criteria
for E3 Applications
When the XRT7300 is operating in the E3 Mode, it
declares an LOS Condition if the signal amplitude
drops to -35dB or below. Further, the XRT7300
clears the LOS Condition if the signal amplitude rises
back up to -15dB or above. Figure 21 illustrates the
signal levels at which the XRT7300 asserts and
clears LOS.
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4 D3 D2 D1 D0
DECODIS ENCODIS ALOSDIS DLOSDIS REQDIS
0XXXX
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
31
Timing Requirements associated with Declaring
and Clearing the LOS Indicator for E3 Applica-
tions
The XRT7300 w as designed to meet the ITU-T G.775
specification timing requirements for declaring and
clearing the LOS indicator. In particular, the
XRT7300 declares an LOS between 10 and 255 UI
(or E3 bit-periods) after the actual time the LOS con-
dition occurred. Further, the XRT7300 clears the
LOS indicator within 10 to 255 UI after restoration of
the incoming line signal. Figure 22 illustrates the
LOS Declaration and Clearance behavior in response
to the first loss of signal event and then afterwards to
the restoration of the signal.
FIGURE 21. THE SIGNAL LEVELS THAT THE XRT7300 DECLARES AND CLEARS LOS (E3 MODE ONLY)
0 dB
-12 dB
-15dB
-35dB
Maxim u m Cab le Loss for E3
LOS Signal Must be Declared
LOS Signal Must be Cleared
LOS Signal may be Cleared or Declared
FIGURE 22. THE BEHAVIOR THE LOS OUTPUT INDICATOR IN RESPONSE TO THE LOSS OF SIGNAL AND THE RESTO-
RATION OF SIGNAL
Actual Occurrence
of LOS Condition Line Signal
is Restored
Time Range for
LOS Declaration
Time Range for
LOS Clearance
G.775
Compliance G.775
Compliance
0 UI
10 UI
0 UI
10 UI 255 UI255 UI
RTIP/
RRing
RLOS Output Pin
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
32
3.6.2 The LOS Declaration/Clearance Criteria
for DS3 and STS-1 Applications
When the XRT7300 is operating in the DS3 or STS-1
Modes it declares and clears LOS based on either:
•Analog LOS (ALOS) Declaration/Clearance Criteria
or,
•Digital LOS (DLOS) Declaration/Clearance Criteria
In the DS3 or STS-1 Modes the LOS output (RLOS)
is simply the logical OR of the ALOS and DLOS
states.
1. The Analog LOS (ALOS) Declaration/Clear-
ance Criteria
The XRT7300 declares an Analog LOS (ALOS) Con-
dition if the amplitude of the incoming line signal
drops below a specific amplitude as defined by the
state of the LOSTHR input pin.
Declaring ALOS
The XRT7300 declares an ALOS (Analog LOS) con-
dition whenever the amplitude of the input signal falls
below the Signal Level to Declare ALOS levels speci-
fied in Table 4.
Clearing ALOS
The XRT7300 clears ALOS whenever the amplitude
of the input signal rises above the Signal Level to
Clear ALOS levels specified in Table 4.
N
OTE
: There is approximately a 2dB hysteresis in the
received signal level that exists between declaring and
cleari ng ALOS in order to prevent chatter ing in the R LOS
output signal.
Monitoring the State of ALOS
If the XRT7300 is operating in the HOST Mode, the
state of ALOS can be polled or monitored by reading
in the contents of Command Register 0. The bit-for-
mat of Command Register 0 is presented below.
If the ALOS bit-field contains a “1”, the XRT7300 is
currently declaring an ALOS condition. If the ALOS
bit-field contains a “0”, the device is NO T currently de-
claring an ALOS condition.
Disabling the ALOS Detector
It is useful to disable the ALOS Detector in the
XRT7300 for debugging purposes. If the XRT7300 is
operating in the HOST Mode, the ALOS Detector can
TABLE 4: THE ALOS DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF LOSTHR (DS3 AND
STS-1 APPLICATIONS) FOR EQUALIZER ENABLED OR DISABLED
APPLICATION LOSTHR SETTING SIGNAL LEVEL TO DECLARE
ALOS SIGNAL LEVEL TO CLEAR
ALOS
LOS LEVEL WITH EQUALIZER ENABLED
DS3 0 < 55mV > 220mV
1<
22mV > 70mV
Sonet STS-1 0 < 75mV > 270mV
1< 25mV > 110mV
LOS LEVEL WITH EQUALIZER DISABLED
DS3 0 < 35mV > 155mV
1< 17mV > 70mV
Sonet STS-1 0 < 55mV > 210mV
1<
20mV > 90mV
COMMAND REGISTER CR0 (ADDRESS = 0X00)
D4 D3 D2 D1 D0
RLOL RLOS ALOS DLOS DMO
Read
Only Read
Only Read
Only Read
Only Read
Only
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
33
be disabled by writing a “1” into the ALOSDIS bit-field
in Command Register 2 as depicted below.
N
OTE
: Setting both the ALOSDIS and DLOSDIS bit-fields
to “1” disables LOS Declaration in the XRT7300.
2. The Digital LOS (DLOS) Declaration/Clear-
ance Criteria
The XRT7300 declare a Digital LOS (DLOS) condi-
tion if the XRT7300 detects 160±32 or more consecu-
tive “0’s” in the incoming data.
The XR T7300 clears DLOS if it detects four consecu-
tive sets of 32 bit-periods each of which contains at
least 10 “1’s” (e.g., average pulse density of greater
than 33%).
Monitoring the State of DLOS
If the XRT7300 is operating in the HOST Mode, the
state of DLOS can be polled or monitored by reading
in the contents of Command Register 0 as shown.
If the DLOS bit-field contains a “1”, the XRT7300 is
currently declaring a DLOS condition. If the DLOS
bit-field contains a “0”, the device is NO T currently de-
clar i ng the DLOS con di tio n.
Disabling the DLOS Detector
It is useful to disable the DLOS Detector in the
XRT 7300 f or debugging purposes. If the XRT7300 is
operating in the HOST Mode, the DLOS Detector can
be disabled by writing a “1” into the DLOSDIS bit-field
in Command Register 2.
N
OTE
: Setting both the ALOSDIS and DLOSDIS bit-fields
to a “1” disables LOS Decla ratio n in the XRT7300 .
3.6.3 Muting the Recovered Data while the LOS
is being Declared
In some applications it is not desirable for the
XRT7300 E3/DS3/STS-1 LIU to recover data and
route it to the Receiving Terminal while the LIU is de-
claring an LOS condition. Consequently, the
XRT7300 includes a LOS Muting feature. This fea-
ture, if enabled, causes the XRT7300 to halt trans-
mission of the recovered data to the Receiving Termi-
nal while the LOS condition is True. In this case, the
RPOS and RNEG output pins are forced to “0”. Once
the LOS condition has been cleared, the XRT7300
resumes the transmission of the recovered data to
the Receiving Terminal. The XRT7300 allows en-
abling of the Muting Upon LOS feature by either of
the following means.
If the XRT7300 is Operating in the Hardware
Mode:
The Muting Upon LOS feature is enabled by pulling
the LOSMUTEN input pin (pin 19) to VDD.
If the XRT7300 is Operating in the HOST Mode:
To enable this feature, access the Microprocessor Se-
rial Interface and write a “1” into the LOSMUT bit-field
in Command Register 3.
N
OTE
: The XRT7300 automatically declares an LOS Con-
dition any time it has been configured to operate in either
the Anal og Local Loop-Back or Digital Local Loop-Back
Modes. Consequently, MUTing -upon -LOS must be dis-
abled prior to configuring the device to operate in either of
these local Loop-Back modes.
3.7 ROUTING THE RECOVERED TIMING AND DATA
INFORMATION TO THE RECEIVING TERMINAL
EQUIPMENT
The XRT7300 ultimately takes the Recovered Timing
and Data information, converts it into CMOS levels
and routes it to the Receiving Terminal Equipment via
the RPOS, RNEG, RCLK1 and RCLK2 output pins.
The XRT7300 can deliver the recovered data and
clock inf ormation to the Receiving Terminal in either a
Single-Rail or Dual-Rail format.
Routing Dual-Rail Format Data to the Receiving
Terminal Equipment
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4 D3 D2 D1 D0
DECODIS ENCODIS ALOSDIS DLOSDIS REQDIS
XX1XX
COMMAND REGISTER CR0 (ADDRESS = 0X00)
D4 D3 D2 D1 D0
RLOL RLOS ALOS DLOS DMO
Read
Only Read
Only Read
Only Read
Only Read
Only
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4 D3 D2 D1 D0
DECODIS ENCODIS ALOSDIS DLOSDIS REQDIS
XXX1X
COMMAND REGISTER CR3 (ADDRESS = 0X03)
D4 D3 D2 D1 D0
RNRZ LOSMUT CLK2DIS RCLK2INV CLK1INV
X1XXX
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
34
Whenever the XRT7300 delivers Dual-Rail format to
the Terminal Equipment it does so via the following
output signals.
•RPOS
•RNEG
•RCLK1
•RCLK2
Figure 23 illustrates the typical interface for the trans-
mission of data in a Dual-Rail Format from the Re-
ceive Section of the XRT7300 to the Receiving Termi-
nal Equipment.
The manner that the LIU transmits Dual-Rail data to
the Receiving Terminal Equipment is described below
and illustrated in Figure 24. The XRT7300 typically
updates the data on the RPOS and RNEG output
pins on the rising edge RCLK1 (or RCLK2).
RCLK1 (or RCLK2) is the Recovered Clock signal
from the incoming Received line signal. As a result,
these clock signals are typically 34.368 MHz for E3
applications, 44.736 MHz for DS3 applications and
51.84 MHz for SONET STS-1 applications.
In general, if the XRT7300 received a positive-polarity
pulse in the incoming line signal via the RTIP and
RRING input pins, then the XRT7300 pulses the
RPOS output pin “High”. If the XRT7300 received a
negative-polarity pulse in the incoming line signal via
the RTIP and RRING input pins, then the XRT7300
pulses the RNEG output pin “High”.
Inverting the RCLK1 or RCLK2 outputs
When using the XRT7300, either of the RCLK1 or
RCLK2 signals can be inv erted with respect to the de-
livery of the RPOS and RNEG output signals to the
Receiving Terminal Equipment. This feature may be
useful for those customers whose Receiving Terminal
Equipment logic design is such that the RPOS and
RNEG data must be sampled on the rising edge of
RCLK1 or RCLK2. Figure 25 illustrates the behavior
FIGURE 23. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL-RAIL FORMAT FROM THE
RECEIVE SECTION OF THE XRT7300 TO THE RECEIVING TERMINAL EQUIPMENT
Exar E3/DS3/STS-1 LIU
Receive
Logic
Block
RxPOS
RxNEG
RCLK1, 2
RPOS
RNEG
RCLK1, 2
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
FIGURE 24. HOW THE XR T7300 OUTPUTS DATA ON THE RPOS AND RNEG OUTPUT PINS
RCLK1
RPOS
RNEG
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
35
of the RPOS, RNEG and RCLK signals when the
RCLK signal has been inverted.
In order to configure the XRT7300 to invert the
RCLK1 output signal, the XRT7300 must be operat-
ing in the HOST Mode. This configuration can be im-
plemented by accessing the Microprocessor Serial
Interface block and writing a “1” into the RCLK1INV
bit-field in Command Register CR3 to invert RCLK1.
The RCLK2 output signal can also be inverted when
the XRT7300 is operating in the Hardware Mode by
setting the RCLK2INV input pin “High”.
3.7.1 Routing Single-Rail Format data (Binary
Data Stream) to the Receive Terminal Equipment
To route Single-Rail format data (e.g., a binary data
stream) from the Receive Section of the XRT7300 to
the Receiving Terminal Equipment, do the following:
A. configure the XRT7300 to operate in the HOST
Mode and
B. access the Microprocessor Serial Interface and
write a “1” into the RNRZ bit-field in Command
Register CR3.
After these steps are taken, the XRT7300 outputs
Single-Rail data to the Receiving Terminal Equipment
via the RPOS and RCLK1 (or RCLK2) output pins as
illustrated in Figure 26 and Figure 27.
N
OTE
: The RNEG output pin is internally tied to Ground
whenever this feature is enabled.
FIGURE 25. THE BEHAVIOR OF THE RPOS, RNEG AND RCLK1 SIGNALS WHEN RCLK1 IS INVERTED
RCLK1
RPOS
RNEG
COMMAND REGISTER CR3 (ADDRESS = 0X03)
D4 D3 D2 D1 D0
RNRZ LOSMUT CLK2DIS RCLK2INV RCLK1INV
XX X 1 1
COMMAND REGISTER CR3 (ADDRESS = 0X03)
D4 D3 D2 D1 D0
RNRZ LOSMUT CLK2DIS RCLK2INV RCLK1INV
1X X X X
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
36
4.0 DIAGNOSTIC FEATURES OF THE XRT7300
The XRT7300 supports equipment diagnostic activi-
ties by supporting the following Loop-Back modes in
the chip:
•Analog Local Loop-Back
•Digital Local Loop-Back
•Remote Loop- Back.
4.1 THE ANALOG LOCAL LOOP-BACK MODE
When the XRT7300 is configured to operate in the
Analog Local Loop-Back Mode, the XRT7300 ignores
any signals that are input to the RTIP and RRING in-
put pins. The Transmitting Terminal Equipment trans-
mits clock and data into the XRT7300 via the TPDA -
TA, TNDATA and TCLK input pins. This data is pro-
cessed through the Transmit Clock Duty Cycle Adjust
PLL and the HDB3/B3ZS Encoder. Finally, this data
outputs to the line via the TTIP and TRING output
pins and is looped back into the AGC/Receive Equal-
izer Block. Consequently, this data is also processed
through the Receive Section of the XRT7300. After
this post-loop-back data has been processed through
the Receive Section it outputs to the Near-End Re-
ceiving Terminal Equipment via the RPOS, RNEG,
RCLK1 and RCLK2 output pins.
Figure 28 illustrates the path that the data takes when
the chip is configured to operate in the Analog Local
Loop-Back Mode.
The XRT7300 can be configured to operate in the An-
alog Local Loop-Back Mode by employing either one
of the following two steps:
FIGURE 26. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A SINGLE-RAIL FORMAT FROM THE
RECEIVE SECTION OF THE XRT7300 TO THE RECEIVING TERMINAL EQUIPMENT
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
Exar E3/DS3/STS-1 LIU
Receive
Logic
Block
RxPOS
RCLK1, 2
RPOS
RCLK1, 2
FIGURE 27. THE BEHAVIOR OF THE RPOS AND RCLK1 OUTPUT SIGNALS WHILE THE XRT7300 IS TRANSMITTING
SINGLE-RAIL DATA TO THE RECEIVING TERMINAL EQUIPMENT
RCLK1
RPOS
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
37
If the XRT7300 is operating in the HOST Mode:
Access the Microprocessor Serial Interface and write
a “1” into the LLB bit-field and a “0” into the RLB bit-
field in Command Register 4.
If the XRT7300 is operating in the Hardware
Mode:
The LLB input pin (pin 14) must be set to “High” and
the RLB input pin (pin 15) must be set to “Low”.
N
OTES
:
1. The Analog Local Loop-Back Mode does not work
if the transmitter is turned off via the TXOFF fea-
ture.
2. The XRT7300 automatically Declares an LOS Con-
dition anytime it has been configured to operate in
either the Analog Local Loop-Back or Digital Local
Loop-Back Modes. Consequently, the MUTing -
upon -LOS must be disabled prior to configuring
the device to operate in either of these local Loop-
Back modes.
4.2 THE DIGITAL LOCAL LOOP-BACK MODE
When the XRT7300 is configured to operate in the
Digital Local Loop-Back Mode, it ignores any signals
that are input to the R TIP and RRING input pins. The
Transmitting Terminal Equipment transmits clock and
data into the XRT7300 via the TPDATA, TNDATA and
TCLK input pins. This data is processed through the
Transmit Clock Duty Cycle Adjust PLL and the HDB3/
B3ZS Encoder block and then looped back to the
HDB3/B3ZS Decoder block.
Figure 29 illustrates the path that the data takes when
the chip is configured to operate in the Digital Local
Loop-Back Mode.
FIGURE 28. THE ANALOG LOCAL LOOP-BACK IN THE XRT7300
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR
SDI
SDO/LCV
SCLK
CS
REGRESET
RTIP
RRING
REQDIS
RCLK1
RCLK2
RPOS
RNEG
DECODIS
RLOS
LLB
RLB
ENCODIS
TAOS
TPDATA
TNDATA
TCLK
RLOL EXCLK
Device
Monitor
MTIP
MRING
Transmit
Logic Duty Cycle Adjust
TXLEV
TXOFF
DMO
TTIP
TRING
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface Analog Local
Loop-Back Path
COMMAND REGISTER CR4 (ADDRESS = 0X04)
D4 D3 D2 D1 D0
X STS-1/DS3 E3 LLB RLB
XX X1 0
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
38
The Digital Local Loop-Back Mode, along with the Tx-
OFF feature, is useful in Redundancy System De-
sign. These two features permit the system to exe-
cute some diagnostic tests in the Back-up Line Card
without transmitting data onto the line and interfering
with the DS3/E3/STS-1 traffic from the Primary Line
Card.
The XRT7300 can be configured to operate in the
Digital Local Loop-Back Mode by employing either
one of the following two-steps.
A. If the XRT7300 is operating in the HOST Mode
Access the Microprocessor Serial Interface and write
a “1” into both the LLB and RLB bit-fields in Com-
mand Register 4.
B. If the XRT7300 is operating in the Hardware
Mode
Set both the LLB input pin (pin 14) and the RLB input
pin (pin 15) to “High”.
N
OTES
:
1. The Digital Local Loop-Back Mode feature works
even if the transmitter is turned off via the TXOFF
feature.
2. The XRT7300 automatically declares an LOS Con-
dition any time it has been configured to operate in
either the Analog Local Loop-Back or Digital Local
Loop-Back Modes. Consequently, the MUTing -
upon -LOS must be disabled prior to configuring
the device to operate in either of these local Loop-
Bac k mo des.
4.3 THE REMOTE LOOP-BACK MODE
When the XRT7300 is configured to operate in the
Remote Loop-Back Mode, it ignores any signals that
are input to the TPDATA and TND ATA input pins. The
XRT7300 receives the incoming line signal via the
RTIP and RRING input pins. This data is processed
through the Receive Section of the XRT7300 and out-
puts to the Receive Terminal Equipment via the
RPOS, RNEG, RCLK1 and RCLK2 output pins. Addi-
tionally, this data is internally looped back into the
Pulse-Shaping block in the Transmit Section. At this
point, this data is routed through the remainder of the
Transmit Section of the XRT7300 and transmitted out
onto the line via the TTIP and TRING output pins.
FIGURE 29. THE DIGITAL LOCAL LOOP-BACK PATH IN THE XRT7300
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR
SDI
SDO/LCV
SCLK
CS
REGRESET
RTIP
RRING
REQDIS
RCLK1
RCLK2
RPOS
RNEG
DECODIS
RLOS
LLB
RLB
ENCODIS
TAOS
TPDATA
TNDATA
TCLK
RLOL EXCLK
Device
Monitor
MTIP
MRING
Transmit
Logic Duty Cycle Adjust
TXLEV
TXOFF
DMO
TTIP
TRING
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Digital Local
Loop-Back Path
COMMAND REGISTER CR4 (ADDRESS = 0X04)
D4 D3 D2 D1 D0
X STS-1/DS3 E3 LLB RLB
XX X1 1
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
39
Figure 30 illustrates the path that the data tak es in the
XRT7300 when the chip is configured to operate in
the Remote Loop-Back Mode.
During Remote Loop-Bac k operation, any data which
is inputted via the RTIP and RRING input pins is also
outputted to the Terminal Equipment via the RPOS,
RNEG and RCLK output pin s.
The XR T7300 can be configured to operate in the Re-
mote Loop-Back Mode by employing either one of the
following two steps
If the XRT7300 is operating in the HOST Mode:
Access the Microprocessor Serial Interface and write
a “1” into the RLB bit-field and a “0” in the LLB bit-field
in Command Register CR4.
If the XRT7300 is operating in the Hardware
Mode:
Set the RLB input pin (pin 15) to “High” and the LLB
input pin (pin 16) to “Low”.
FIGURE 30. THE REMOTE LOOP-BACK PATH IN THE XRT7300
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR
SDI
SDO/LCV
SCLK
CS
REGRESET
RTIP
RRING
REQDIS
RCLK1
RCLK2/LCV
RPOS
RNEG
DECODIS
RLOS
LLB
RLB
ENCODIS
TAOS
TPDATA
TNDATA
TCLK
RLOL EXCLK
Device
Monitor
MTIP
MRING
Transmit
Logic Duty Cycle Adjust
TXLEV
TXOFF
DMO
TTIP
TRING
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Remote
Loop-Back Path
COMMAND REGISTER CR4 (ADDRESS = 0X04)
D4 D3 D2 D1 D0
X STS-1/DS3 E3 LLB RLB
XXX0 1
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
40
4.4 TXOFF FEATURES
The XRT7300 allows the Transmit Driver in the Trans-
mit Section of the chip to be shut off. This feature can
be advantageous for system redundancy conditions
or during diagnostic testing. This feature can be acti-
vated by either of the following ways.
When the XRT7300 is operating in the Hardware
Mode
Shut off the Transmit Driv er b y toggling the TXOFF in-
put pin (pin 35) “High”. Turn on the Tr ansmit Driver b y
toggling the TXOFF input pin “Low”.
When the XRT7300 is operating in the HOST
Mode
If the XRT7300 is operating in the HOST Mode, the
TXOFF input pin is disabled. Consequently, the-
Transmit Driver is turned off by writing to Command
Register CR1 and setting the TXOFF bit-field (bit D4)
to “1”.
N
OTE
: If the Transmitter is shut off via the TXOFF feature,
the XRT7300 can NOT be configured to operate in the Ana-
log Local Loop-Back Mode. To perform diagnostics on the
chip and still invoke the TXOFF feature as in System
Redund ancy Applic ations , us e the Digi tal Loc al Loo p-Bac k
feature instead.
4.5 THE TRANSMIT DRIVE MONITOR FEATURES
The Transmit Drive Monitor feature performs monitor-
ing of the line in the Transmit Direction for the occur-
rence of f ault conditions such as a short circuit on the
line or a defective Transmit Drive in the XRT7300.
The Transmit Drive Monitor is activated by connecting
the MTIP pin (pin 44) to the TTIP line through a 270 Ω
resistor connected in series and by connecting the
MRING pin (pin 43) to the TRING line through a 270
Ω resistor connected in series, as illustrated in
Figure 31.
When the Transmit Drive Monitor circuitry is connect-
ed to the line as illustrated in Figure 26, then it moni-
tors the line for transitions. As long as the Transmit
Drive Monitor circuitry detects transitions on the line
via the MTIP and MRING pins, it keeps the DMO
(Drive Monitor Output) signal “Low”. However, if the
Transmit Drive Monitor circuit detects no transitions
on the line for 128±32 TCLK periods, then the DMO
signal togg les “Hi gh”.
N
OTES
:
1. Th e Transmit D rive Monito r ci rcuit does no t have to
be used to operate the Transmit Section of the
XRT7300. This is purely a diagnostic feature.
COMMAND REGISTER CR1 (ADDRESS = 0X01)
D4 D3 D2 D1 D0
TXOFF TAOS TXCLKINV TXLEV TXBIN
1X X X X
FIGURE 31. THE XRT7300 EMPLOYING THE TRANSMIT DRIVE MONITOR FEATURES
R1 = 36Ω
R2 = 36Ω
TTIP
TRING 1:1
MTIP
MRING
R3 = 270Ω
R4 = 270Ω
T1
R5 = 75Ω
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
41
2. The Transmit Drive Monitor feature can also be
used to monitor the Transmit Output Line Signal of
another LIU IC as il lustrate d in Figure 32.
Presented in Figure 32, if LIU # 1 (U1) fails, then LIU
# 2 (U2) drives its DMO output pin “High”. Like wise, if
LIU # 2 (U2) fai ls, then LIU # 1 (U1) drives its DMO
output pin “High”.
The scheme presented in Figure 32 is a better design
approach. It overcomes situations in which a LIU
monitoring its own signal (Figure 31) ma y experience
a failure mode such that it cannot drive a bipolar sig-
nal onto the line. That same failure mode may pre-
vent the LIU from driving the DMO output pin “High”.
4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE
The XRT7300 can transmit an all “1’s” pattern onto
the line by toggling a single input pin or by setting a
single bit-field in one of the Command Registers to
“1”.
N
OTE
: When this feature is activated, the Transmi t Section
of the XRT7300 overwrites the Terminal Equipment data
with this all “1’s” pattern.
This f eature can be activated b y either of the following
methods.
When the XRT7300 is operating in the Hardware
Mode:
Configure the de vice to transmit an all “1’s” pattern by
toggling the TAOS input pin (pin 2) “High”. Terminate
the all “1’s” pattern by toggling the TAOS input pin
“Low”.
When the XRT7300 is operating in the HOST
Mode:
If the XRT7300 is operating in the HOST Mode, the
TAOS input pin is disabled. Consequently, the
XRT7300 can be configured to transmit an all “1’s”
pattern b y writing to Command Register CR1 and set-
ting the TAOS bit-field (bit D3) to “1”.
The all “1’s” pattern can be terminated by writing to
Command Register CR1 and setting the TAOS bit-
field (D3) to “0".
FIGURE 32. TWO LIU’S, EACH MONITORING THE TRANSMIT OUTPUT SIGNAL OF THE OTHER LIU IC
R1
36Ω
BNC
T1
R2
36Ω
R7
36Ω
BNC
R8
36Ω
TTIP
TRING
R3
270Ω
R4
270Ω
R5
270Ω
R6
270Ω
TRING
TTIP
MRING
MTIP
MRING
MTIP
DMO_Channel_2
DMO_Channel_1 DMO
DMO
T2
PE-68629
PE-68629
TXOFF
TXOFF
U1
U2
COMMAND REGISTER CR1 (ADDRESS = 0X01)
D4 D3 D2 D1 D0
TXOFF TAOS TXCLKINV TXLEV TXBIN
01XXX
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
42
5.0 THE MICROPROCESSOR SERIAL INTER-
FACE
The on-chip Command Registers of the XRT7300
DS3/E3/STS-1 Line Interface Unit IC are accessed to
configure the XRT7300 into a variety of modes. This
section describes the Command Registers and how
to use the Microprocessor Serial Interface.
5.1 DESCRIPTION OF THE COMMAND REGISTERS
A listing of these Command Registers, their Address-
es and their Bit-Formats are listed in Table 5.
Address:
The register addresses are in Hexadecimal format.
Type:
The Command Registers are either Read-Only (RO)
or Read/Write (R/W) registers.
N
OTES
:
1. The default value for each of the bit-fields in these
registers is “0”.
2. If the REGRESET input pin is asserted, then the
contents of the command registers is reset to all
"0's" resulting in the XRT7300 operating in the
mode corresponding to the default values of the
Command Registers.
DESCRIPTION OF BIT-FIELDS FOR EACH COM-
MAND REGISTER
5.1.1 Command Register - CR0
Bit D4 - RLOL (Receive Loss of Lock Status)
This Read-Only bit-field reflects the lock status of the
Clock Recov ery Phase-Lock ed-Loop in the XRT7300.
This bit-field is set to “0” if the Clock Recovery PLL is
in lock with the incoming line signal. This bit-field is
set to “1” if the Clock Recovery PLL is out of lock with
the incoming line signal.
Bit D3 - RLOS (Receive Loss of Signal Status)
This Read-Only bit-field indicates whether or not the
Receiver in the XRT7300 is currently declaring an
LOS (Loss of Signal) Condition.
This bit-field is set to “0” if the XRT7300 is not cur-
rently declaring the LOS Condition. This bit-field is
set to “1” if the XRT7300 is declaring an LOS Condi-
tion.
Bit D2 - ALOS (Analog Loss of Signal Status)
TABLE 5: ADDRESSES AND BIT FORMATS OF XRT7300 COMMAND REGISTERS
ADDRESS COMMAND REGISTER TYPE REGISTER BIT-FORMAT
D4 D3 D2 D1 D0
0x00 CR0 RO RLOL RLOS ALOS DLOS DMO
0x01 CR1 R/W TXOFF TAOS TXCLKINV TXLEV TXBIN
0x02 CR2 R/W DECODIS ENCODIS ALOSDIS DLOSDIS REQDIS
0x03 CR3 R/W RNRZ LOSMUT RCLK2/LCV RCLK2INV RCLK1INV
0x04 CR4 R/W Reserved STS-1/DS3 E3 LLB RLB
0x05 CR5 R/W Reserved Reserved Reserved Reserved Reserved
0x06 CR6 R/W Reserved Reserved Reserved Reserved Reserved
0x07 CR7 R/W Reserved Reserved Reserved Reserved Reserved
0x08 CR8 R/W Reserved Reserved Reserved Reserved Reserved
0x09 CR9 R/W Reserved Reserved Reserved Reserved Reserved
0x10 CR10 R/W Reserved Reserved Reserved Reserved Reserved
0x11 CR11 R/W Reserved Reserved Reserved Reserved Reserved
0x12 CR12 R/W Reserved Reserved Reserved Reserved Reserved
0x13 CR13 R/W Reserved Reserved Reserved Reserved Reserved
0x14 CR14 R/W Reserved Reserved Reserved Reserved Reserved
0x15 CR15 R/W Reserved Reserved Reserved Reserved Reserved
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
43
This Read-Only bit-field indicates whether or not the
Analog LOS Detector in the XRT7300 is currently de-
claring an LOS condition.
This bit-field is set to “0” if the Analog LOS Detector in
the XRT7300 is NOT currently declaring an LOS con-
dition. Conversely, this bit-field is set to “1” if the Ana-
log LOS Detector is currently declaring an LOS condi-
tion.
The purpose of this feature is to isolate either the An-
alog LOS or the Digital LOS detector that is declaring
the LOS condition. This feature may be useful for
troubleshooting/debugging purposes.
Bit D1 - DLOS (Digital Loss of Signal Status)
This Read-Only bit-field indicates whether or not the
Digital LOS Detector in the XRT7300 is currently de-
claring an LOS condition.
This bit-field is set to “0” if the Digital LOS Detector in
the XRT7300 is NOT currently declaring an LOS con-
dition. Conversely, this bit-field is set to “1” if the Digi-
tal LOS Detector is currently declaring an LOS condi-
tion.
N
OTE
: The purpose of this f eature is to iso late the Detector
(e.g., either the An alog LOS or the Digital LOS detect or)
that is declaring the LOS condition. This feature may be
use ful for troubleshooting/debugging purposes.
Bit D0 - DMO (Drive Monitor Output Status)
This Read-Only bit-field reflects the status of the
DMO output pin.
5.1.2 Command Register - CR1
Bit D4 - TXOFF (Tr ansmitter OFF)
This Read/Write bit-field is used to turn off the Trans-
mitter in the XRT7300.
Writing a “1” to this bit-field turns off the Transmitter
and tri-states the Transmit Output. Writing a “0” to
this bit-field turns on the Transmitter.
Bit D3 - TAOS (Transmit All OneS)
This Read/Write bit-field is used to command the
XRT7300 Transmitter to generate and transmit an all
“1’s” pattern onto the line.
Writing a “1” to this bit-field commands the Transmit-
ter to transmit an all “1’s” pattern onto the line. Writ-
ing a “0” to this bit-field commands normal operation.
Bit D2 - TXCLKINV (Transmit Clock Invert)
This Read/Write bit-field is used to configure the
XRT7300 Transmitter to sample the signal at the TP-
D ATA and TND ATA pins on the rising or falling edge of
TCLK (the Transmit Line Clock signal).
Writing a “1” to this bit-field configures the Transmitter
to sample the TPDATA and TNDATA input pins on the
rising edge of TCLK. Writing a “0” to this bit-field con-
figures the Transmitter to sample the TPDATA and
TNDATA input pins on the falling edge of TCLK.
Bit D1 - TXLEV (Transmit Level Select)
This Read/Write bit-field is used to enable or disable
the XRT7300 Transmit Line Build-Out circuit.
Setting this bit-field "High" disables the Line Build-Out
circuit of the XRT7300. In this mode, the XRT7300
outputs partially-shaped pulses onto the line via the
TTIP and TRING output pins. Setting this bit-field
"Low" enables the Line Build-Out circuit of the
XRT7300. In this mode the XR T7300 outputs shaped
pulses onto the line via the TTIP and TRING output
pins.
To comply with the Isolated DSX/STSX-1 Pulse Tem-
plate Requirements per Bellcore GR-499-CORE or
GR-253-CORE, either:
1. set this input pin to "1" if the cable length between
the Cross-Connect and the transmit output of the
XRT7300 is greater than 225 feet or
2. set this input pin to "0" if the cable length between
the Cross-Connect and the transmit output of the
XRT7300 is less than 225 feet.
N
OTE
: This option is only available when the XRT7300 is
operating in the DS3 or STS-1 Mode.
Bit D0 - TXBIN (Transmit Binary Data)
This Read/Write bit-field permits configuring of the
Transmitter in the XR T7300 to accept an un-encoded
binary data stream via the TPDATA input and con-
verts this data into the appropriate bipolar signal to
the line.
Writing a “1” configures the Transmitter to accept a bi-
nary data stream via the TPDATA input.
N
OTE
: The TNDATA input is ignored.
This form of data acceptance is sometimes referred
to as Single-Rail mode operation. The Transmitter
then encodes this data into the appropriate line code
(e.g., B3ZS or HDB3) prior to its transmission over
the line.
Writing a “0” configures the Transmitter to accept data
in a Dual-Rail manner (e.g., via both the TPD ATA and
TNDATA inputs).
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
44
5.1.3 Command Register - CR2
Bit D4 - DECODIS (B3ZS/HDB3 Decoder-Disable)
This Read/Write bit-field is used to either enable or
disable the B3ZS/HDB3 Decoder in the XRT7300.
Writing a “1” to this bit-field disables the B3ZS/HDB3
Decoder. Writing a “0” to this bit-field enables the
B3ZS/HD B3 Decode r.
N
OTE
: This Decoder performs HDB3 Decoding if the
XRT7300 is operating in the E3 Mode. Otherwise it per-
forms B3ZS Decoding.
Bit D3 - ENCODIS (B3ZS/HDB3 Encoder-Disable)
This Read/Write bit-field is used to enab le or disable
the B3ZS/HDB3 Encoder in the XRT7300.
Writing a “1” to this bit-field disables the B3ZS/HDB3
Encoder. Writing a “0” to this bit-field enables the
B3ZS/HD B3 Encoder.
N
OTE
: This Encoder performs HDB3 Encoding if the
XRT7300 is operating in the E3 Mode. Otherwise, it per-
forms B3ZS Encoding.
Bit D2 - ALOSDIS (Analog LOS Disable)
This Read/Write bit-field is used to disable the Analog
LOS Detecto r.
Writing a “0” to this bit-field enables the Analog LOS
Detector. Writing a “1” to this bit-field disables the
Analog LOS Detector.
N
OTE
: If the Analog LOS Detector is disabled, then the
RLOS input pin is only asserted by the DLOS (Digital LOS
Detector).
Bit D1 - DLOSDIS (Digital LOS Disable)
This Read/Write bit-field is used to disable the Digital
LOS Detecto r.
Writing a “0” to this bit-field enab les the Digital LOS
Detector. Writing a “1” to this bit-field disables the
Digital LOS Detector.
N
OTE
: If the Digital LOS Detector is disabled, then the
RLOS input pin is only asserted by the ALOS (Analog LOS
Detector).
Bit D0 - REQDIS (Receive Equalization Disable)
This Read/Write bit-field is used to either enable or
disable the internal Receive Equalizer in the
XRT7300.
Writing a “0” to this bit-field enables the Internal
Equalizer. Writing a “1” to this bit-field disables the
Internal Equalizer.
5.1.4 Command Register - CR3
Bit D4 - RNRZ (Receive Binary Data)
This Read/Write bit-field is used to configure the
XRT7300 to output the received data from the Re-
mote Terminal in a binary or Dual-Rail format.
Writing a “1” to this bit-field configures the XRT7300
to output data to the Terminal Equipment in a Single-
Rail (binary) format via the RPOS output pin. The
RNEG is grounded. A “0” to this bit-field configures
the XRT7300 to output data to the Terminal Equip-
ment in a Dual-Rail format via both the RPOS and
RNEG output pins.
Bit D3 - LOSMUT (R eco vered Data MUTing during
LOS Condition)
This Read/Write bit-field is used to configure the
XRT7300 to NO T output any recov ered data while it is
declaring an LOS condition to the terminal equip-
ment.
Writing a “0” to this bit-field configures the chip to out-
put recovered data even while the XR T7300 is declar-
ing an LOS condition. Writing a “1” to this bit-field
configures the chip to NO T output the recovered data
while an LOS condition is being declared.
N
OTE
: In this mode, RPOS and RNEG is set to “0” asyn-
chronously.
Bit D2 - RCLK2/LCV (Receive Clock Output 2/Line
Code Violation)
This Read/Write bit-field is used to select the function
of pin 30 (RCLK2/LCV). Pin 30 can be configured to
function as the Line Code Violation output indicator or
as the additional Receive Clock Output (RCLK2).
Writing a “0” to this bit-field configures the pin to func-
tion as the Line Code Violation output pin. Writing a
“1” to this bit-field configures this pin to function as
the RCLK2 output pi n.
Bit D1 - RCLK2INV (Invert RCLK2)
This Read/Write bit-field is used to configure the Re-
ceiver in the XRT7300 to output the recov ered data
on either the rising edge or the falling edge of the
RCLK2 clock signal.
Writing a “0” to this bit-field configures the Receiv er to
output the recov ered data on the rising edge of the
RCLK2 output signal. Writing a “1” to this bit-field
configures the Receiver to output the recovered data
on the falling edge of the RCLK2 output signal.
Bit D0 - RCLK1INV (Invert RCLK1)
This Read/Write bit-field is used to configure the Re-
ceiver in the XRT7300 to output the recov ered data
on either the rising edge or the falling edge of the
RCLK1 clock signal.
Writing a “0” to this bit-field configures the Receiv er to
output the recov ered data on the rising edge of the
RCLK1 output signal. Writing a “1” to this bit-field
configures the Receiver to output the recovered data
on the falling edge of the RCLK1 output signal.
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
45
5.1.5 Command Register - CR4
Bit D4 - Reser ve d
This bit-field has no defined functionality
Bit D3 - STS-1/DS3 Mode Select
This Read/Write bit-field is used to configure the
XRT7300 to operate in either the SONET STS-1
Mode or the DS3 Mode.
Writing a “0” into this bit-field configures the XR T7300
to operate in the DS3 Mode. Writing a “1” into this bit-
field configures the XRT7300 to operate in the SO-
NET STS-1 Mode.
N
OTE
: This bit-field is ignored if the E3 bit-field (D2 in this
Command Register) is set to “1”.
Bit D2 - E3 Mode Select
This Read/Write bit-field is used to configure the
XRT7300 to operate in the E3 Mode.
Writing a “0” into this bit-field configures the XR T7300
to operate in either the DS3 or SONET STS-1 Mode
specified by the setting of the DS3 bit-field in this
Command Register. Writing a “1” into this bit-field
configures the XRT7300 to operate in the E3 Mode.
Bit D1 - LLB (Local Loop-Back)
This Read/Write bit-field along with RLB (bit D0 in this
Command Register) is used to select which Loop-
Back mode the XRT7300 operates in. Table 6 relates
the state of the LLB and RLB to the selected Loop-
Back mode.
Bit D0 - RLB (Remote Loop-Back)
This Read/Write bit-field along with LLB (bit D1 in this
Command Register) is used to select which Loop-
Back mode the XRT7300 operate in. Table 6 relates
the state of the LLB and RLB bits to the selected
Loop-Back mode.
5.2 OPERATING THE MICROPROCESSOR SERIAL
INTERFACE.
The XRT7300 Serial Interface is a simple f our wire in-
terface that is compatible with many of the microcon-
trollers available in the market. This interface con-
sists of the following signals:
CS - Chip Select (Active Low)
SCLK - Serial Clock
SDI - Serial Data Input
SDO - Serial Data Output
Using the Microprocessor Serial Interface
The following instructions for using the Microproces-
sor Serial Interface are best understood by referring
to the diagram in Figure 33.
In order to use the Microprocessor Serial Interface, a
clock signal must be supplied to the SCLK input pin.
A Read or Write operation can then be initiated b y as-
serting the active-low Chip Select input pin (CS). It is
important to assert the CS pin (e.g., toggle it “Low”) at
least 50ns prior to the very first rising edge of the
clock signal.
Once the CS input pin has been asserted, the type of
operation and the target register address must now
be specified. This information is supplied to the Mi-
croprocessor Serial Interface by writing eight serial
bits of data into the SDI input.
N
OTE
: Each of these bits is clocked into the SDI input on
the rising edge of SCLK. These eight bits are identified and
described below.
Bit 1 - R/W (Read/Write) Bit
This bit is clocked into the SDI input on the first rising
edge of SCLK after CS has been asserted. This bit
indicates whether the current operation is a Read or
Write operation. A “1” in this bit specifies a Read op-
eration, a “0” in this bit specifies a Write operation.
Bits 2 through 5: The four (4) bit Address Values
(labeled A0, A1, A2 and A3)
The next f our rising edges of the SCLK signal clock in
the 4-bit address value for this particular Read (or
Write) operation. The address selects the Command
Register in the XRT7300 that the user is either read-
ing data from or writing data to. The address bits
must be supplied to the SDI input pin in ascending or-
der with the LSB (least significant bit) first.
Bits 6 and 7:
The next two bits, A4 and A5 must be set to “0” as
shown in Figure 33.
Bit 8:
The value of A6 is a “don’t care”.
TABLE 6: LOOP-BACK MODES
LLB
(BIT D1) RLB
(BIT D0) LOOP-BACK MODE
0 0 No Loop-Back Mode (Normal
Operation)
0 1 Remote Loop-Back Mode
1 0 Analog Loop-Back Mode
1 1 Digital Loop-Back Mode
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
46
Figure 34 illustrates how to interface the XRT7300 to
the XRT7234/45 E3/DS3 ATM UNI IC.
For more inf ormation on the XRT7234 E3 UNI or the
XRT7245 DS3 UNI IC’s please consult the XRT7234
E3 UNI IC or the XRT7245 DS3 UNI IC Data Sheets.
FIGURE 33. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE
D0 D1 D2 D7D6D5D4D3
High Z
SDO
A0 D0R/W D1A600A3A2A1 D7D6D5D4D3D2
SDI
12345678910111213141516
SClk
CS
High Z
- Denotes a “don’t care” value
A4 and A5 are always “0”.
R/W = “1” for “Read” Operations
R/W = “0” for “Write” Operations
Notes:
- Denotes a “don’t care” value
A4 and A5 are always “0”.
R/W = “1” for “Read” Operations
R/W = “0” for “Write” Operations
Notes:
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
47
FIGURE 34. HOW TO INTERFACE THE XRT7300 IC TO THE XRT7234/45 E3/DS3 ATM UNI IC
TxSoC
TxEnB
TxClk
TxPrty
TxClav
TxData0
TxData1
TxData2
TxData3
TxData4
TxData5
TxData6
TxData7
TxData8
TxData9
TxData10
TxData11
TxData12
TxData13
TxData14
TxData15
RESET
INT
CS
WR_RW
RD_DS
ALE_AS
Rdy_Dtck
MOTO
A0
A1
A2
A3
A4
A5
A6
A7
A8
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
RxLOS
RxOOF
RxLCS
RxRED
RxAIS
RxSOC
RxEnB
RxCLk
RxPrty
RxClav
RxData0
RxData1
RxData2
RxData3
RxData4
RxData5
RxData6
RxData7
RxData8
RxData9
RxData10
RxData11
RxData12
RxData13
RxData14
RxData15
TxSoC
TxEnB
TxClk
TxPrty
TxClav
TxData [15:0]
RESET
INT
CS
RW
DS
AS
DTACK
A[8:0]
D[15:0]
RxLOS
RxOOF
RxLCS
RxRED
RxAIS
RxSOC
RxEnB
RxCLk
RxPrty
RxClav
RxData[15:0]
TxPOS
TxNEG
TxLineClk
DMO
ExLOS
RLOL
LLOOP
RLOOP
TAOS
TxLEV
ENCODIS
REQB
RxPOS
RxNEG
RxLineClk
TPDATA
TNDATA
TCLK
DMO
RLOS
RLOL
LLB
RLB
TAOS
TxLEV
ENCODIS
REQDIS
RPOS
RNEG
RCLK1
TTIP
TRING
MTIP
MRING
RTIP
RRING
R4
270 Ω
R3
270 Ω
T1
R1
36Ω
R2
36Ω
1:1
TTIP
TRING
T2
1:1
RTIP
RRING
R5
37.5 ΩR6
37.5 Ω
0.01uF
C1
+5V
XRT7245
XRT7300
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
48
Figure 35 illustrates how to interface the XRT7300 to
the XRT7250 E3/DS3 Framer IC. Please note that in
this case, the XRT7300 has been configured to oper-
ate in the Hardware Mode.
For more inf ormation on the XRT7250 E3/DS3 Fram-
er IC’s please consult the XRT7250 E3/DS3 Framer
IC Data Sheet.
FIGURE 35. HOW TO INTERFACE THE XRT7300 IC TO THE XRT7250 DS3/E3 FRAMER IC
TxSER
TXInClk
TxFrame
NIBBLEINTF
RESET
INT
CS
RW
DS
AS
INT
A[8:0]
D[7:0]
5V
RxSer
RxClk
RxFrame
RxLOS
RxOOF
RxRED
RxAIS
TxSER
TXInClk
TxFrame
NIBBLEINTF
RESET
INT
CS
WR_RW
RD_DS
ALE_AS
Rdy Dtck
A0
A1
A2
A3
A4
A5
A6
A7
A8
D0
D1
D2
D3
D4
D5
D6
D7
MOTO
RxSer
RxClk
RxFrame
RxLOS
RxOOF
RxRED
RxAIS
TxPOS
TxNEG
TxLineClk
DMO
ExtLOS
RLOL
LLOOP
RLOOP
TAOS
TxLEV
ENCODIS
REQB
RxPOS
RxNEG
RxLineClk
XRT7250
TPDATA
TNDATA
TCLK
DMO
RLOS
RLOL
LLB
RLB
TAOS
TXLEV
ENCODIS
REQDIS
RPOS
RNEG
RCLK1
TTIP
TRING
MTIP
MRING
RTIP
RRING
R4
270Ω
R3
270Ω
T1
R1
36Ω
R2
36Ω
1:1
TTIP
TRING
T2
1:1
RTIP
RRING
R5
37.5Ω
R6
37.5Ω
0.01uF
C1
XRT7300
áç
áçáç
áç XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
49
ORDERING INFORMATION
PACKA GE DIMENSIONS
PART NO.P
ACKAGE OPERATING TEMPERATURE RANGE
XRT7300IV 44 Pin TQFP (10mm x 10mm) -40°C to +85°C
33 23
22
12
111
34
44
D
D
1
DD
1
B
e
α
A
2
A
1
A
Seating Plane L
C
44 LEAD THIN QUAD FLAT PACK
(10 x 10 x 1.4 mm TQFP)
rev. 1.00
Note:
The control dimension is the millimeter column
SYMBOL MIN MAX MIN MAX
A 0.055 0.063 1.4 1.6
A1 0.002 0.006 0.05 0.15
A2 0.053 0.057 1.35 1.45
B 0.012 0.018 0.3 0.45
C 0.004 0.008 0.09 0.2
D 0.465 0.48 11.8 12.2
D1 0.39 0.398 9.9 10.1
e
L 0.018 0.03 0.45 0.75
α
0
o
7
o
0
o
7
o
INCHES MILLIMETERS
0.0315 BSC 0.80 BSC
XRT7300 áç
áçáç
áç
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
50
REVISION HISTORY
Rev. 1.0.0 or igi nal
Rev. 1.0.1 page 12 Leackage Current Units from mA
to µA
Rev. 1.0.2 edits to missing symbols
Rev. 1.0.3 changes to Notes for Analog and Digital
Loop-Back modes and added ESD Rating
Rev. 1.0.4 and 1.0.5 Added REQDIS to block dia-
gram; renamed REG_RESET* to REGRESET, CS* to
CS, ICT* to ICT, HOST/HW* to HOST/HW, STS -1/
DS3* to STS- 1/DS3 ; changed f ormat/style of the data
sheetand removed uneccessary verbage; added ta-
ble of contents. Modified figures 3 & 4 for complet-
ness.
Rev. 1.0.7 added Device Monitor function to block di-
agram, changed figure 22, RxIN to RTIP/RRING.
Rev. 1.1.0 Electrical tables incorrectly stated 3.3V re-
placed with 5.0V, Rev # made consistent with produc-
ti on products.
Rev 1.1.1 Added connection points to various draw-
ings.
áç
áçáç
áç
XRT7300 E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
51
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order
to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no represen-
tation that the circuits are free of patent infringement. Charts and schedules contained here in are only for
illustration purposes and may vary depending upon a user’s specific application. While the information in
this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where
the failure or malfunction of the product can reasonably be e xpected to cause failure of the lif e support sys-
tem or to significantly affect its safety or effectiveness. Products are not authorized for use in such applica-
tions unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury
or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corpo-
ration is adequately protected under the circumstances.
Copyright 2001 EXAR Corporation
Datasheet February 2002.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
