SY89200U
Ultra-Precision 1:8 LVDS Fanout Buffer
with Three ÷1/÷2/÷4 Clock Divider
Output Banks
Precision Edge is a registered tradem ark of Micrel, Inc
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August 2007
M9999-082407-E
hbwhelp@micrel.com or (408) 955-1690
General Description
The S Y89200U is a 2.5 V precision, hig h-speed, integr ated
clock divider and LVDS fanout buffer capable of handling
clocks up to 1.5GHz. Optimized for communications
applications, the three independently controlled output
banks are phase matched and can be configured for pass
through (÷1), ÷2 or ÷4 divider ratios.
The differential input includes Micrel’s unique, 3-pin input
termination architecture that allows the user to interface to
any differential signal path. The low-skew, low-jitter
outputs are LVDS-compatible with extremely fast rise/fall
times guaranteed to be less than 150ps.
The EN (enable) input guarantees that the ÷1, ÷2 and ÷4
outputs will start from the same state without any runt
pulse af ter an asynchron ous master rest (MR) is as serted.
This is accomplished by enabling the outputs after a four-
clock delay to allow the counters to synchronize.
The S Y89200U is part of Micr el’s Precision Edge® product
family.
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Functional Block Diagram
Precision Edge®
Features
• Three low-skew LVDS output banks with programmable
÷1, ÷2 and ÷4 divider options
• Three independently programmable output banks
• Guaranteed AC performance over temperature and
voltage:
– Accepts a clock frequency up to 1.5GHz
– <900ps IN-to-OUT propagation delay
– <150ps rise/fall time
– <50ps bank-to-bank phase offset
• Ultra-low jitter design:
– <1psRMS random jitter
– <10psPP total jitter (clock)
• Patent-pend ing in put ter mination and VT pin accepts
DC- and AC-coupled inputs (CML, PECL, LVDS)
• LVDS-compatible outputs
• CMOS/TTL-compatible output enable (EN) and divider
select control
• 2.5V ±5% power supply
• –40°C to +85°C temperature range
• Available in 32-pin (5mm x 5mm) QFN package
Applications
• All SONET/SD applications
• All Fibre Channel applications
• All Gigabit Ethernet applications
Micrel, Inc.
SY89200U
August 2007 2 M9999-082407-E
hbwhelp@micrel.com or (408) 955-1690
Ordering Information(1)
Part Number Package
Type Temperature
Range Package Marking Lead Finish
SY89200UMI QFN-32 Industrial SY89200U Sn-Pb
SY89200UMITR(2) QFN-32 Industrial SY89200U Sn-Pb
SY89200UMG QFN-32 Industrial SY89200U with
Pb-Free bar-line ind icat or Pb-Free
NiPdAu
SY89200UMGTR(2) QFN-32 Industrial SY89200U with
Pb-Free bar-line ind icat or Pb-Free
NiPdAu
Note:
1. Contact f act ory for die availabi lity. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
Pin Configuration
32-Pin QFN
Micrel, Inc.
SY89200U
August 2007 3 M9999-082407-E
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number Pin Name Pin Function
3, 6 IN, /IN Differential Input: This input pair is the differential signal input to the device. This input
accepts AC- or DC-coupled signals as small as 100mV. The input pair internally
terminates to a VT pin through 50Ω. Note that these inputs will default to an indeterminate
state if left open. Please refer to the “Input Interface Applications” section for more details.
2
7
8
DIVSEL1
DIVSEL2
DIVSEL3
Single-Ended Inputs: These TTL/CMOS inputs select the device ratio for each of the
three banks of outputs. Note that each of these inputs is internally connected to a 25k Ω
pull-up resistor and will default to logic HIGH state if left open. The input-switching
threshold is VCC/2.
4 VT Input Termination Center-Tap: Each side of the differential input pair terminates to the VT
pin. The VT pin provides a center-tap to a termination netw or k for max imum int erfac e
flexibility . Se e “Input In terfa ce A ppli cat ion s” sect ion for more det ai ls.
5 VREF-AC Reference Voltage: This output biases to VCC-1.2V. It is used for AC-coupling inputs IN
and /IN. For AC-coupled applications, connect VREF-AC directly to the VT pin. Bypass
with 0.01µF low ESR capacitor to VCC. Maximum sink/source capability is 0.5mA.
9 EN Single-Ended Input: This TTL/CMOS input disable and enable the Q0 – Q7 outputs. This
input is internally connected to a 25kΩ pull-up resistor and will default to logic HIGH state
if left open. The input-switching thresh old is VCC/2. For the input enable and disable
functional description, refer to Figures 2a through 2c.
30, 29, 28,
27, 26, 25,
24, 23
Q0, /Q0, /Q1,
/Q1, Q2, /Q2
Q3, /Q3
Bank 1 LVDS differential output pairs controlled by DIVSEL1: LOW Q0 – Q3 = ÷1 HIGH,
Q0 – Q3 = ÷2. Unused output pairs should be terminated with 100Ω across the differential
pair.
16, 15, 14,
13, 12, 11 Q4, /Q4, Q5,
/Q5, Q6, /Q6 Bank 2 LVDS differential output pairs controlled by DIVSEL2: LOW Q4 – Q6 = ÷2 HIGH,
Q4 – Q6 = ÷2. Unused output pairs should be terminated with 100Ω across the differential
pair.
18, 17 Q7, /Q7 Bank 3 LVDS differential output pairs controlled by DIVSEL3: LOW Q7 = ÷2 HIGH. Q7 =
÷2. Unused output pairs should be terminated with 100Ω across the differential pair.
32 /MR Single-Ended Input: This TTL/CMOS-compatible master reset function asynchronously
sets Q0 – Q7 outp ut s LOW, /Q 0 – /Q7 outputs HIGH, and holds them in that state as long
as /MR remains LOW . This input is internally connected to a 25kΩ pull-up resistor and will
default to a logic HIGH state if left open. The input-switching threshold is V CC/2.
10, 19, 22, 31 VCC Positive power supply. Bypass with 0.1µF||0.01µF low ESR capacitors.
1, 20, 21 GND
Exposed Ground and exposed pad must be connected to the same GND plane on the board.
Truth Table
/MR
(1)
EN
(2,3)
DIVSEL1 DIVSEL2 DIVSEL3 Q0 – Q3 Q4 – Q6 Q7
0 X X X X 0 0 0
1 0 X X X 0 0 0
1 1 0 0 0 ÷1 ÷2 ÷2
1 1 1 1 1 ÷2 ÷4 ÷4
Notes:
1. /MR asynchronously forces Q0 – Q7 LOW (/Q0 – /Q7 HIGH).
2. EN forces Q0 – Q7 LOW between 2 and 6 input clock cycles after the falling edge of EN. Refer to “Timing Diagram” section.
3. EN synchronousl y enabl es the outputs between two and six input clock cycles after the rising edge of EN. Refer to “Timing Diagram” section.
Micrel, Inc.
SY89200U
August 2007 4 M9999-082407-E
hbwhelp@micrel.com or (408) 955-1690
Absolute Maximum Ratings(1)
Supply Voltage (VCC) .................................... –0.5V to +4.0V
Input Voltage (VIN) ............................................ –0.5V to VCC
Termination Current(3)
Source or sink current on VT ............................. ±100mA
Output Current (3)
Source or sink current on IN, /IN ........................ ±50mA
VREF-AC Current(3)
Source or sink current on VREF-AC ......................... ±2mA
Lead Temperature (soldering, 20 sec.) .................... +260°C
Storage Temperature (Ts) ......................... –65°C to +150°C
Operating Ratings(2)
Supply Voltage (VCC) ............................ +2.375V to +2.625V
Ambient Temperature (TA) .......................... –40°C to +85°C
Package Thermal Resistance(4)
QFN (θJA)
Still-Air ......................................................... 35°C/W
QFN (ΨJB)
Junction –to-Board ...................................... 20°C/W
DC Electrical Characteristics
TA = –40°C to +85°C, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VCC Power Supply 2.375 2.5 2.625 V
ICC Power Supply Current No load, max. VCC, Note 6 350 mA
RDIFF_IN Differential Input R esistance
(IN-to-/IN) 80 100 120 Ω
RIN Input Resis tance
(IN-to-VT, /IN-to-VT) 40 50 60 Ω
VIH Input High Voltage; (IN, /IN) 1.2 VCC V
VIL Input Low Voltage; (IN, /IN) 0 VIH-0.1 V
VIN Input Voltage Swing; (IN, /IN) See Fi gure 1a. 0.1 VCC V
VDIFF_IN Differential Input Voltage Swing
|IN - /IN| See Figure 1b. 0.2 V
VREF-AC Reference Voltage VCC–1.3 VCC–1.2 VCC–1.1 V
IN-to-VT Voltage from Input to VT 1.8 V
LVTTL/CMOS DC Electrical Characteristics(5)
VCC = 2.5V ±5%; TA = –40°C to +85°C, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VIH Input HIGH Voltage 2.0 V
VIL Input LO W Voltage 0.8 V
IIH Input HIGH Current –125 30 µA
IIL Input Low Current –300 µA
Notes:
1. Permanent device dam age may occur if ratings in the “Absolute Maximum Ratings” section are exceeded. This is a stress rating only and functional
operation is not implied for conditions other than those detailed in the operational sections of this datasheet. Exposure to absolute maximum ratings
conditi ons for extended periods may aff ect device rel i ability.
2. The datasheet lim its are not guaranteed i f t he device is operated beyond the operating ratings.
3. Due to the limited drive capabi lit y use for input of the same package only.
4. Package thermal resist ance assumes exposed pad is solder ed (or equivalent) to the device’s most negative potential on the PCB. ΨJB uses 4-layer
θJA in still-air, unless otherwise stated.
5. The ci rcuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been establis hed.
6. Includes current through internal 50Ω pull-up.
Micrel, Inc.
SY89200U
August 2007 5 M9999-082407-E
hbwhelp@micrel.com or (408) 955-1690
LVDS OUTPUT DC Electrical Characteristics(7)
VCC = 2.5V ±5%; TA = –40°C to +85°C; RL = 100Ω across Q and /Q, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VOH Output HIGH Voltage; (Q, /Q) 1.475 V
VOL Output LOW Voltage; (Q, /Q) 0.925 V
VOUT Output Voltage Swing; (Q, /Q) 250 350 mV
VDIFF_OUT Differential Output Voltage Swing
|Q – /Q| 500 700 mV
VOCM Output Common Mode Voltage
(Q, /Q) 1.125 1.275 V
∆VOCM Change in Common Mode Voltage
(Q, /Q) –50 +50 mV
AC Electrical Characteristics(8)
VCC = 2.5V ±5%; TA = –40°C to +85°C; RL = 100Ω across all outputs (Q and /Q), unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
fMAX Maximum Operating Frequency VOUT >200mV Clock 1.5 GHz
tPD Differential Propagation Delay IN-to-Q 500 700 900 ps
/MR-to-Q 900 ps
tRR Reset Recovery Time /MR(L-H)-to-(L-H) 900 ps
tPD
Tempco Differential Propagation Delay
Temperature Coefficient 115 fs/°C
tSKEW Within-Bank Skew Within same fanout bank, Note 9 10 25 ps
Bank-to-Bank Skew Same divide setting, Note 10 15 35 ps
Bank-to-Bank Skew Differential divide setting, Note 10 25 50 ps
Part-to-Park Skew Note 11 200 ps
tJITTER Random Jitter (RJ) Note 12 1 psRMS
Tot al Jitter (TJ) Note 13 10 psPP
Cycle-to-Cycle Jitter Note 14 1 psRMS
tf, tf Rise/Fall Time 20% to 80% at full output swing 40 80 150 ps
Notes:
7. The ci rcuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been establis hed.
8. Measured with 100mV i nput swing. See “Timing Diagram” secti on for definition of parameters. High-frequency AC-parameters are guaranteed by
design and characterization.
9. Within-bank is the difference in propagation delays among the outputs within the same bank.
10. Bank-to-bank skew is the difference in propagation delays between outputs from difference banks. Bank -to-bank skew is also the phase offset
between each bank after MR is applied.
11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs.
12. RJ is measured with a K28.7 comma detect character pattern.
13. Total jitter definition: with an ideal clock input of frequency ≤fMAX, no more than one output edge in 1012 output edges will deviate by more than the
specified peak-to-peak jitter value.
14. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the output
signal.
Micrel, Inc.
SY89200U
August 2007 9 M9999-082407-E
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Input Stage Internal Termination
Figure 3. Simplified Differential Input Stage
Input Interface Applications
Figure 4a. CML Interface
(DC-Coupled)
Figure 4b. CML Interface
(AC-Coupled)
Figure 4c. LVPECL Interface
(DC-Coupled)
Figure 4d. LVPECL Interface
(AC-Coupled)
Figure 4e. LVDS Interface
Micrel, Inc.
SY89200U
August 2007 10 M9999-082407-E
hbwhelp@micrel.com or (408) 955-1690
Output Interface Applications
LVDS specifies a small swing of 350mV typical, on a
nominal 1.25V common mode above ground. The
common mode voltage has tight limits to permit large
variations in ground between an LVDS driver and
receiver. Also, change in common mode voltage, as a
function of data input, is kept to a minimum to keep EMI
low.
Figure 5a. LVDS Differential Measurement
Figure 5b. LVDS Common Mode Measurement
Related Product and Support Documentation
Part Number Function Datasheet Link
HBW Solutions New Products and Applications www.micrel.com/product-info/products/solutions.shtml
Micrel, Inc.
SY89200U
August 2007 11 M9999-082407-E
hbwhelp@micrel.com or (408) 955-1690
Package Information
32-Pin QFN
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its
use. Micrel reserves the right to change circuit ry and specific ations at any time without notification to the customer.
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Purchaser’s use or sal e of Micrel Products for use in life support appliances, devices or syst ems is a Purchaser’s own risk and Purchaser agrees to
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© 2006 Micrel, Incorporated.
