eGaN® FET DATASHEET
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 1
EPC2010C
EPC2010C – Enhancement Mode Power Transistor
VDS , 200 V
RDS(on) , 25 mΩ
ID , 22 A
EPC2010C eGaN® FETs are supplied only in
passivated die form with solder bars
Applications
• High Speed DC-DC conversion
• Class D Audio
• Lidar
Benets
• Ultra High Eciency
• Ultra Low RDS(on)
• Ultra Low QG
• Ultra Small Footprint
EFFICIENT POWER CONVERSION
G
D
S
HAL
www.epc-co.com/epc/Products/eGaNFETs/EPC2010C.aspx
Maximum Ratings
PARAMETER VALUE UNIT
VDS Drain-to-Source Voltage (Continuous) 200 V
ID
Continuous (TA = 25˚C, RθJA = 5.3) 22 A
Pulsed (25°C, TPULSE = 300 µs) 90
VGS
Gate-to-Source Voltage 6V
Gate-to-Source Voltage -4
TJOperating Temperature -40 to 150 °C
TSTG Storage Temperature -40 to 150
Thermal Characteristics
PARAMETER TYP UNIT
RθJC
Thermal Resistance, Junction to Case
1.1
°C/W RθJB
Thermal Resistance, Junction to Board
2.7
RθJA
Thermal Resistance, Junction to Ambient (Note 1)
56
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
All measurements were done with substrate connected to source.
Static Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 200 μA 200 V
IDSS Drain-Source Leakage VGS = 0 V, VDS = 160 V 50 150 µA
IGSS
Gate-to-Source Forward Leakage VGS = 5 V 1 3 mA
Gate-to-Source Reverse Leakage VGS = -4 V 50 150 µA
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 3 mA 0.8 1.4 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 12 A 18 25 mΩ
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.7 V
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment
leveraging the infrastructure that has been developed over the last 60 years. GaN’s exceptionally
high electron mobility and low temperature coecient allows very low RDS(on), while its lateral
device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end
result is a device that can handle tasks where very high switching frequency, and low on-time are
benecial as well as those where on-state losses dominate.
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 2
eGaN® FET DATASHEET EPC2010C
ID
– Drain Current (A)
VGS – Gate-to-Source Voltage (V)
40
50
60
70
80
90
30
20
10
0
0.5 1 1.5 2 2.5 3 3.5
45
4.5
25˚C
125˚C
Figure 2: Transfer Characteristics
VDS = 6 V
RDS(on)
– Drain-to-Source Resistance (m
Ω)
VGS – Gate-to-Source Voltage (V)
50
60
40
30
20
10
02.5 23 3.5 4 4.5 5
ID = 10 A
ID = 20 A
ID = 40 A
ID = 60 A
Figure 3: RDS(on) vs. VGS for Various Drain Current
RDS(ON)
– Drain-to-Source Resistance (m
Ω)
VGS – Gate-to-Source Voltage (V)
50
60
40
30
20
10
02.5 23 3.5 4 4.5 5
Figure 4: RDS(on) vs. VGS for Various Temperatures
25˚C
125˚C
ID = 12 A
ID – Drain Current (A)
VDS – Drain-to-Source Voltage (V)
80
70
60
50
40
30
20
10
90
00 12 3456
Figure 1: Typical Output Characteristics at 25ºC
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
Dynamic Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CISS
Input Capacitance
VDS = 100 V, VGS = 0 V
380 540
pFCOSS
Output Capacitance
240 320
CRSS
Reverse Transfer Capacitance
1.8 2.7
RG
Gate Resistance
0.4 Ω
QG
Total Gate Charge
VDS = 100 V, ID = 12 A, VGS = 5 V 3.7 5.3
nC
QGS
Gate-to-Source Charge
VDS = 100 V, ID = 12 A
1.3
QGD
Gate-to-Drain Charge
0.7 1.3
QG(TH)
Gate Charge at Threshold
0.9
QOSS
Output Charge
VDS = 100 V, VGS = 0 V 40 52
QRR
Source-Drain Recovery Charge
0
All measurements were done with substrate connected to source.
Note 2: COSS(ER) is a xed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a xed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 3
eGaN® FET DATASHEET EPC2010C
C – Capacitance (nF)
VDS – Drain-to-Source Voltage (V)
0
0.2
0.4
0.6
0.8
1
0 50 100 150 200
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
Figure 5a: Capacitance Linear Scale
VDS – Drain-to-Source Voltage (V)
Capacitance (nF)
0 50 100 150 200
Figure 5b: Capacitance Log Scale
0.001
0.01
0.1
1
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
QG – Gate Charge (nC)
5
4
3
2
1
00 1 2 3 4
ID = 12 A
VDS = 100 V
Figure 6: Gate Charge
V
G
– Gate Voltage (V)
I
SD
– Source-to-Drain Current (A)
VSD – Source-to-Drain Voltage (V )
10
5
15
20
25
30
35
40
45
0
0 0.5 1 1.5 2 2.5 3 3.5 4 54.5
25˚C
125˚C
Figure 7: Reverse Drain-Source Characteristics
Normalized On-State Resistance – RDS(on)
TJ – Junction Temperature (˚C )
0
0.5
1
1.5
2
2.5
3
-25 0 25 50 75 100 125 150
ID = 12 A
VGS = 5 V
Figure 8: Normalized On Resistance vs. Temperature
Normalized Threshold Voltage (V)
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-25 0 25 50 75 100 125 150
ID = 3 mA
Figure 9: Normalized Threshold Voltage vs. Temperature
TJ – Junction Temperature ( ˚C )
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 4
eGaN® FET DATASHEET EPC2010C
Figure 11: Transient Thermal Response Curves
Duty Factors:
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
PDM
t1
t2
0.5
0.1
0.05
0.02
0.01
1
0.1
0.01
0.001
10-5 10-4 10-3 10-2 10-1 0 1
Junction-to-Board
tp, Rectangular Pulse Duration, seconds
ZθJB
, Normalized Thermal Impedance
Single Pulse
tp, Rectangular Pulse Duration, seconds
Duty Factors:
PDM
t1
t2
0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
ZθJC
, Normalized Thermal Impedance
10-5
10-6 10-4 10-3 10-2 10-1 1
1
0.1
0.01
0.001
0.0001
Junction-to-Case
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
IG – Gate Current (mA)
VGS – Gate-to-Source Voltage (V)
6
4
2
14
12
8
10
00 1 2 3 4 5 6
25˚C
125˚C
Figure 10: Gate Current
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 5
eGaN® FET DATASHEET EPC2010C
DIE MARKINGS
YYYY
2010
ZZZZ
TAPE AND REEL CONFIGURATION
4 mm pitch, 8 mm wide tape on 7” reel
7” reel
a
d e f g
c
b
Note 1: MSL 1 (moisture sensitivity level 1) classied according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
Die
orientation
dot
Gate
solder bar is
under this
corner
Die is placed into pocket
solder bar side down
(face side down)
Loaded Tape Feed Direction
Dimension (mm) target
EPC2010C (note 1)
min max
a 12.00 11.9 12.3
b 1.75 1.65 1.85
c (note 2) 5.50 5.45 5.55
d 4.00 3.90 4.10
e 4.00 3.90 4.10
f (note 2) 2.00 1.95 2.05
g 1.5 1.5 1.6
Figure 12: Safe Operating Area
0.1
1
10
100
0.1 1 10 100
ID- Drain Current (A)
VDS - Drain-Source Voltage (V)
Limited by RDS(on)
TJ = Max Rated, TC = +25°C, Single Pulse
100 µs
1 ms
Pulse Width
10 ms
100 ms
2010
YYYY
ZZZZ
Part
Number
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking line 2
Lot_Date Code
Marking Line 3
EPC2010C 2010 YYYY ZZZZ
Die orientation dot
Gate Pad solder bar
is under this corner
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 6
eGaN® FET DATASHEET EPC2010C
Information subject to
change without notice.
Revised May, 2019
RECOMMENDED
LAND PATTERN
(units in µm) Pad no. 1 is Gate;
Pads no. 3, 5, 7 are Drain;
Pads no. 4, 6 are Source;
Pad no. 2 is Substrate. *
*Substrate pin should be connected to Source
The land pattern is solder mask dened.
DIE OUTLINE
Solder Bar View
Side View
Pad no. 1 is Gate;
Pads no. 3, 5, 7 are Drain;
Pads no. 4, 6 are Source;
Pad no. 2 is Substrate. *
*Substrate pin should be connected to Source
DIM MICROMETERS
MIN Nominal MAX
A3524 3554 3584
B1602 1632 1662
c1379 1382 1385
d577 580 583
e262 277 292
f245 250 255
g600 600 600
Ecient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Ecient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
B
A
d
x2
c
e g
g
x4
f f
x5
815 Max
100 +/- 20
Seating Plane
(685)
2
3 4 5 6 7
1
1632
3554
560
802
x2
1362
600
600
x4
230 230
x5
1
3 4 5 6 7
2
RECOMMENDED
STENCIL DRAWING
(units in µm) Recommended stencil should be 4 mil (100 μm)
thick, must be laser cut , opening per drawing.
The corner has a radius of R60.
Intended for use with SAC305 Type 3 solder,
reference 88.5% metals content.
Additional assembly resources available at
http://www.epc-co.com/epc/DesignSupport/
AssemblyBasics.aspx
1632
3554
560
x2
1362
600
600
x4
230 230
R60
x5
1
3 4 5 6 7
2