SECTION 3 OVERVIEW This section contains information about the entire MC68336/376 modular microcontroller. It lists the features of each module, shows device functional divisions and pin assignments, summarizes signal and pin functions, discusses the intermodule bus, and provides system memory maps. Timing and electrical specifications for the entire microcontroller and for individual modules are provided in APPENDIX A ELECTRICAL CHARACTERISTICS. Comprehensive module register descriptions and memory maps are provided in APPENDIX D REGISTER SUMMARY. 3.1 MCU Features The following paragraphs highlight capabilities of each of the microcontroller modules. Each module is discussed separately in a subsequent section of this user's manual. 3.1.1 Central Processing Unit (CPU32) * 32-bit architecture * Virtual memory implementation * Table look-up and interpolate instruction * Improved exception handling for controller applications * High level language support * Background debug mode * Fully static operation 3.1.2 System Integration Module (SIM) * External bus support * Programmable chip select outputs * System protection logic * Watchdog timer, clock monitor and bus monitor * Two 8-bit dual function input/output ports * One 7-bit dual function output port * Phase-locked loop (PLL) clock system 3.1.3 Standby RAM Module (SRAM) * 4-Kbytes of static RAM * No standby supply 3.1.4 Masked ROM Module (MRM) * 8-Kbyte array, accessible as bytes or words * User selectable default base address * User selectable bootstrap ROM function * User selectable ROM verification code MC68336/376 USER'S MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 3-1 3.1.5 10-Bit Queued Analog-to-Digital Converter (QADC) * 16 channels internally; up to 44 directly accessible channels with external multiplexing * Six automatic channel selection and conversion modes * Two channel scan queues of variable length, each with a variable number of subqueues * 40 result registers and three result alignment formats * Programmable input sample time * Direct control of external multiplexers 3.1.6 Queued Serial Module (QSM) * Enhanced serial communications interface (SCI) * Modulus baud rate generator * Parity detection * Queued serial peripheral interface (QSPI) * 80-byte static RAM to perform queued operations * Up to 16 automatic transfers * Continuous cycling, 8 to 16 bits per transfer, LSB or MSB first * Dual function I/O pins 3.1.7 Configurable Timer Module Version 4 (CTM4) * Two 16-bit modulus counter submodules (MCSMs) * 16-bit free-running counter submodule (FCSM) * Four double-action submodules (DASMs) * Four pulse-width submodules (PWMSMs) 3.1.8 Time Processor Unit (TPU) * Dedicated micro-engine operating independently of the CPU32 * 16 independent programmable channels and pins * Each channel has an event register consisting of a 16-bit capture register, a 16bit compare register and a 16-bit comparator * Any channel can perform any time function * Each channel has six or eight 16-bit parameter registers * Each timer function may be assigned to more than one channel * Two timer counter registers with programmable prescalers * Each channel can be synchronized to one or both counters * Selectable channel priority levels 3.1.9 Static RAM Module with TPU Emulation Capability (TPURAM) * 3.5 Kbytes of static RAM * External VSTBY pin for separate standby supply * May be used as normal RAM or TPU microcode emulation RAM MC68336/376 USER'S MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 3-2 3.1.10 CAN 2.0B Controller Module (TouCAN) * Full implementation of CAN protocol specification, version 2.0 A and B * 16 receive/transmit message buffers of 0 to 8 bytes data length * Global mask register for message buffers 0 to 13 * Independent mask registers for message buffers 14 and 15 * Programmable transmit-first scheme: lowest ID or lowest buffer number * 16-bit free-running timer for message time-stamping * Low power sleep mode with programmable wake-up on bus activity 3.2 Intermodule Bus The intermodule bus (IMB) is a standardized bus developed to facilitate both design and operation of modular microcontrollers. It contains circuitry to support exception processing, address space partitioning, multiple interrupt levels, and vectored interrupts. The standardized modules in the MCU communicate with one another through the IMB. The IMB in the MCU uses 24 address and 16 data lines. 3.3 System Block Diagram and Pin Assignment Diagrams Figure 3-1 is a functional diagram of the MCU. There is not a one-to-one correspondence between location and size of blocks in the diagram and location and size of integrated-circuit modules. Figure 3-2 shows the MC68336 pin assignment package; Figure 3-3 shows the MC68376 pin assignment package. Note that the MC68376 is a pin-compatible upgrade for the MC68336 that provides a CAN protocol controller and an 8-Kbyte masked ROM module. Both devices use a 160-pin plastic surfacemount package. Refer to B.1 Obtaining Updated MC68336/376 Mechanical Information for package dimensions. Refer to subsequent paragraphs in this section for pin and signal descriptions. MC68336/376 USER'S MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 3-3 T2CLK TPUCH[15:0] VSTBY CTM2C CTD[10:9]/CTD[4:3] CPWM[8:5] CANTX0 CANRX0 CSBOOT VDD VSS BR/CS0 BG/CS1 BGACK/CS2 MC68376 ONLY 3.5 KBYTE TPURAM TPU CHIP BGACK SELECTS BR BG ADDR23/CS10/ECLK ADDR22/CS9/PC6 ADDR21/CS8/PC5 PORT C CTM4 CONTROL CS[10:0] 8K MRM TouCAN MC68376 ONLY ADDR20/CS7/PC4 ADDR19/CS6/PC3 FC0 FC1 FC2/CS5/PC2 FC2 FC1/CS4/PC1 FC0/CS3/PC0 ADDR [23:19] DSACK0 SIZ1/PE7 DSACK1 SIZ0/PE6 RMC DS EBI AS CONTROL AVEC PORT E 1 FCSM 2 MCSMs 4 DASMs 4 PWMSMs ADDR[18:0] AS/PE5 DS/PE4 RMC/PE3 AVEC/PE2 SIZ0 DSACK1/PE1 SIZ1 DSACK0/PE0 DATA[15:0] IMB R/W RESET HALT QSM 4K SRAM QADC BERR MODCLK/PF0 CPU32 IRQ[7:1] PCS1/PQS4 PCS0/SS/PQS3 SCK/PQS2 PORT QS PCS2/PQS5 MODCLK PORT F TXD/PQS7 PCS3/PQS6 IRQ7/PF7 CONTROL RXD IRQ6/PF6 IRQ5/PF5 IRQ4/PF4 IRQ3/PF3 IRQ2/PF2 CLOCK IRQ1/PF1 CLKOUT MOSI/PQS1 XTAL MISO/PQS0 XFC VDDSYN TSC TEST TSTME QUOT BKPT PQB[7:0] TSTME/TSC FREEZE/QUOT IFETCH IPIPE DSI DSO DSCLK CONTROL PQA[7:0] VRL VRH VSSA VDDA 1 FREEZE CONTROL PORT QA PORT QB EXTAL 1. PORT A PINS INCORPORATE OPEN DRAIN PULL DOWN DRIVERS BKPT/DSCLK IFETCH/DSI IPIPE/DSO 336/376 BLOCK Figure 3-1 MC68336/376 Block Diagram MC68336/376 USER'S MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 3-4 *NC CTM2C CTD3 CTD4 CPWM5 CPWM6 CPWM7 CPWM8 CTD9 CTD10 TPUCH0 VSS TPUCH1 TPUCH2 VDD TPUCH3 TPUCH4 TPUCH5 TPUCH6 VSS VDD TPUCH7 TPUCH8 TPUCH9 TPUCH10 VSTBY VSS TPUCH11 TPUCH12 VDD TPUCH13 TPUCH14 TPUCH15 T2CLK ADDR23/CS10/ECLK PC6/ADDR22/CS9 PC5/ADDR21/CS8 PC4/ADDR20/CS7 PC3/ADDR19/CS6 VSS 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 MC68336 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 VDD PC2/FC2/CS5 PC1/FC1/CS4 FC0/CS3 BGACK/CS2 BG/CS1 BR/CS0 CSBOOT DATA0 DATA1 DATA2 VSS DATA3 DATA4 VDD DATA5 DATA6 DATA7 DATA8 VSS DATA9 DATA10 DATA11 DATA12 DATA13 VSS DATA14 DATA15 VDD ADDR0 PE0/DSACK0 PE1/DSACK1 PE2/AVEC PE3/RMC PE4/DS PE5/AS PE6/SIZ0 PE7/SIZ1 R/W VSS AN51/PQB7 VRH VRL VSSA VDDA AN52/MA0/PQA0 AN53/MA1/PQA1 AN54/MA2/PQA2 AN55/ETRIG1/PQA3 AN56/ETRIG2/PQA4 AN57/PQA5 AN57/PQA6 AN59/PQA7 VSS XTAL VDDSYN EXTAL VSS VDD XFC VDD VSS CLKOUT IPIPE/DSO IFETCH/DSI FREEZE/QUOT BKPT/DSCLK TSTME/TSC RESET HALT BERR PF7/IRQ7 PF6/IRQ6 PF5/IRQ5 PF4/IRQ4 PF3/IRQ3 PF2/IRQ2 PF1/IRQ1 PF0/MODCLK VDD 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 *NC RXD TXD/PQS7 PCS3/PQS6 PCS2/PQS5 PCS1/PQS4 PCS0/SS/PQS3 SCK/PQS2 MOSI/PQS1 MISO/PQS0 ADDR1 VDD ADDR2 ADDR3 VSS ADDR4 ADDR5 ADDR6 ADDR7 VSS ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 VDD ADDR17 ADDR18 VSS AN0/ANW/PQB0 AN1/ANX/PQB1 AN2/ANY/PQB2 AN3/ANZ/PQB3 AN48/PQB4 AN49/PQB5 AN50/PQB6 *NOTE: MC68336 REVISION D AND LATER (F60K AND LATER MASK SETS) HAVE ASSIGNED PINS 1 AND 160 AS "NO CONNECT", TO ALLOW PIN COMPATIBILITY WITH THE MC68376. FOR REVISION C (D65J MASK SET) DEVICES, PIN 1 IS VSS AND PIN 160 IS V DD. Figure 3-2 MC68336 Pin Assignments for 160-Pin Package MC68336/376 USER'S MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 3-5 CANRX0 CTM2C CTD3 CTD4 CPWM5 CPWM6 CPWM7 CPWM8 CTD9 CTD10 TPUCH0 VSS TPUCH1 TPUCH2 VDD TPUCH3 TPUCH4 TPUCH5 TPUCH6 VSS VDD TPUCH7 TPUCH8 TPUCH9 TPUCH10 VSTBY VSS TPUCH11 TPUCH12 VDD TPUCH13 TPUCH14 TPUCH15 T2CLK ADDR23/CS10/ECLK PC6/ADDR22/CS9 PC5/ADDR21/CS8 PC4/ADDR20/CS7 PC3/ADDR19/CS6 VSS 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 MC68376 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 VDD PC2/FC2/CS5 PC1/FC1/CS4 FC0/CS3 BGACK/CS2 BG/CS1 BR/CS0 CSBOOT DATA0 DATA1 DATA2 VSS DATA3 DATA4 VDD DATA5 DATA6 DATA7 DATA8 VSS DATA9 DATA10 DATA11 DATA12 DATA13 VSS DATA14 DATA15 VDD ADDR0 PE0/DSACK0 PE1/DSACK1 PE2/AVEC PE3/RMC PE4/DS PE5/AS PE6/SIZ0 PE7/SIZ1 R/W VSS AN51/PQB7 VRH VRL VSSA VDDA AN52/MA0/PQA0 AN53/MA1/PQA1 AN54/MA2/PQA2 AN55/ETRIG1/PQA3 AN56/ETRIG2/PQA4 AN57/PQA5 AN57/PQA6 AN59/PQA7 VSS XTAL VDDSYN EXTAL VSS VDD XFC VDD VSS CLKOUT IPIPE/DSO IFETCH/DSI FREEZE/QUOT BKPT/DSCLK TSTME/TSC RESET HALT BERR PF7/IRQ7 PF6/IRQ6 PF5/IRQ5 PF4/IRQ4 PF3/IRQ3 PF2/IRQ2 PF1/IRQ1 PF0/MODCLK VDD 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 CANTX0 RXD TXD/PQS7 PCS3/PQS6 PCS2/PQS5 PCS1/PQS4 PCS0/SS/PQS3 SCK/PQS2 MOSI/PQS1 MISO/PQS0 ADDR1 VDD ADDR2 ADDR3 VSS ADDR4 ADDR5 ADDR6 ADDR7 VSS ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 VDD ADDR17 ADDR18 VSS AN0/ANW/PQB0 AN1/ANX/PQB1 AN2/ANY/PQB2 AN3/ANZ/PQB3 AN48/PQB4 AN49/PQB5 AN50/PQB6 376 160-PIN QFP Figure 3-3 MC68376 Pin Assignments for 160-Pin Package 3.4 Pin Descriptions The following tables summarize the functional characteristics of MC68336/376 pins. Table 3-1 shows all inputs and outputs. Digital inputs and outputs use CMOS logic levels. An entry in the "Discrete I/O" column indicates that a pin can also be used for general-purpose input, output, or both. The I/O port designation is given when it applies. Refer to Figure 3-1 for port organization. Table 3-2 shows types of output drivers. Table 3-3 shows the characteristics of power pins. MC68336/376 USER'S MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 3-6 Table 3-1 MC68336/376 Pin Characteristics Pin Mnemonic Output Driver Input Synchronized Input Hysteresis Discrete I/O Port Designation ADDR23/CS10/ECLK A Yes No O -- ADDR[22:19]/CS[9:6] A Yes No O PC[6:3] ADDR[18:0] A Yes No -- -- AN[51:48] -- Yes1 Yes I PQB[7:4] AN[3:0]/AN[w, x, y, z] -- Yes1 Yes I PQB[3:0] AN[59:57] Ba Yes Yes I/O PQA[7:5] AN[56:55]/ETRIG[2:1] Ba Yes Yes I/O PQA[4:3] AN[54:52]/MA[2:0] Ba Yes Yes I/O PQA[2:0] AS B Yes Yes I/O PE5 AVEC B Yes No I/O PE2 BERR B Yes No -- -- BG/CS1 B -- -- -- -- BGACK/CS2 B Yes No -- -- BKPT/DSCLK -- Yes Yes -- -- BR/CS0 B Yes No O -- CLKOUT A -- -- -- -- CANRX0 (MC68376 Only) -- Yes Yes -- -- CANTX0 (MC68376 Only) Bo -- -- -- -- CSBOOT B -- -- -- -- CTD[10:9]/[4:3] A Yes Yes I/O -- CPWM[8:5] A -- -- O -- CTM2C -- Yes Yes I -- DATA[15:0] Aw Yes1 No -- -- DS B Yes Yes I/O PE4 DSACK[1:0] B Yes No I/O PE[1:0] EXTAL2 -- -- Special -- -- FC[2:0]/CS[5:3] A Yes No O PC[2:0] FREEZE/QUOT A -- -- -- -- IPIPE/DSO A -- -- O -- IFETCH/DSI A Yes Yes -- -- HALT Bo Yes No -- -- IRQ[7:1] B Yes Yes I/O PF[7:1] MISO Bo Yes1 Yes I/O PQS0 MODCLK B Yes1 Yes I/O PF0 MOSI Bo Yes1 Yes I/O PQS1 PCS0/SS Bo Yes1 Yes I/O PQS3 PCS[3:1] Bo Yes1 Yes I/O PQS[6:4] R/W A Yes No -- -- MC68336/376 USER'S MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 3-7 Table 3-1 MC68336/376 Pin Characteristics (Continued) Pin Mnemonic Output Driver Input Synchronized Input Hysteresis Discrete I/O Port Designation RESET Bo Yes Yes -- -- RMC B Yes Yes I/O PE3 RXD -- No Yes -- -- SCK Bo Yes1 Yes I/O PQS2 SIZ[1:0] B Yes Yes I/O PE[7:6] T2CLK -- Yes Yes -- -- TPUCH[15:0] A Yes Yes -- -- TSTME/TSC -- Yes Yes -- -- TXD Bo Yes1 Yes I/O PQS7 XFC2 -- -- -- Special -- XTAL 2 -- -- -- Special -- NOTES: 1. DATA[15:0] are synchronized during reset only. MODCLK, and the QSM and QADC pins are synchronized only when used as input port pins. 2. EXTAL, XFC and XTAL are clock reference connections. Table 3-2 MC68336/376 Output Driver Types Type Description A Output only signals that are always driven. No external pull-up required. Ao Type A output that can be operated in an open-drain mode. Aw Type A output with p-channel precharge when reset. B Three-state output that includes circuitry to assert output before high impedance is established, to ensure rapid rise time. An external holding resistor is required to maintain logic level while in the high-impedance state. Bo Type B output that can be operated in an open-drain mode. Ba Three-state output that can be operated in open-drain mode only. Table 3-3 MC68336/376 Power Connections Pin Description VSTBY Standby RAM power VDDSYN Clock synthesizer power VDDA, VSSA QADC converter power VRH, VRL QADC reference voltage VSS, VDD Microcontroller power 3.5 Signal Descriptions The following tables define the MC68336/376 signals. Table 3-4 shows signal origin, type, and active state. Table 3-5 describes signal functions. Both tables are sorted alphabetically by mnemonic. MCU pins often have multiple functions. More than one description can apply to a pin. MC68336/376 USER'S MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 3-8 Table 3-4 MC68336/376 Signal Characteristics Signal Name MCU Module Signal Type Active State ADDR[23:0] SIM Bus -- AN[59:48]/[3:0] QADC Input -- AN[w, x, y, z] QADC Input -- AS SIM Output 0 AVEC SIM Input 0 BERR SIM Input 0 BG SIM Output 0 BGACK SIM Input 0 BKPT CPU32 Input 0 BR SIM Input 0 CLKOUT SIM Output -- CANRX0 (MC68376 Only) TouCAN Input -- CANTX0 (MC68376 Only) TouCAN Output -- CS[10:0] SIM Output 0 CSBOOT SIM Output 0 CPWM[8:5] CTM4 Output -- CTD[10:9]/[4:3] CTM4 Input/Output -- CTM2C CTM4 Input -- DATA[15:0] SIM Bus -- DS SIM Output 0 DSACK[1:0] SIM Input 0 DSCLK CPU32 Input Serial Clock DSI CPU32 Input Serial Data DSO CPU32 Output Serial Data ECLK SIM Output -- ETRIG[2:1] QADC Input -- EXTAL SIM Input -- MC68336/376 USER'S MANUAL FC[2:0] SIM Output -- FREEZE SIM Output 1 HALT SIM Input/Output 0 IFETCH CPU32 Output 0 IPIPE CPU32 Output 0 IRQ[7:1] SIM Input 0 MA[2:0] QADC Output 1 MISO QSM Input/Output -- MODCLK SIM Input -- MOSI QSM Input/Output -- PC[6:0] SIM Output -- PCS[3:0] QSM Input/Output -- PE[7:0] SIM Input/Output -- PF[7:0] SIM Input/Output -- OVERVIEW Rev. 15 Oct 2000 MOTOROLA 3-9 Table 3-4 MC68336/376 Signal Characteristics (Continued) Signal Name MCU Module Signal Type Active State PQA[7:0] QADC Input/Output -- PQB[7:0] QADC Input -- PQS[7:0] QSM Input/Output -- QUOT SIM Output -- R/W SIM Output 1/0 RESET SIM Input/Output 0 RMC SIM Output 0 RXD QSM Input -- SCK QSM Input/Output -- SIZ[1:0] SIM Output 1 SS QSM Input 0 T2CLK TPU Input -- TPUCH[15:0] TPU Input/Output -- TSTME/TSC SIM Input 0/1 TXD QSM Output -- XFC SIM Input -- XTAL SIM Output -- MC68336/376 USER'S MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 3-10 Table 3-5 MC68336/376 Signal Functions Mnemonic Signal Name ADDR[23:0] Address Bus Function AN[59:48]/[3:0] QADC Analog Input 16 channel A/D converter analog input pins AN[w, x, y, z] QADC Analog Input Four input channels utilized when operating in multiplexed mode 24-bit address bus used by the CPU32 AS Address Strobe AVEC Autovector Requests an automatic vector during interrupt acknowledge BERR Bus Error Indicates that a bus error has occurred BG Bus Grant Indicates that the MCU has relinquished the bus BGACK Bus Grant Acknowledge BKPT Breakpoint BR Bus Request CLKOUT System Clock Out Indicates that a valid address is on the address bus Indicates that an external device has assumed bus mastership Signals a hardware breakpoint to the CPU Indicates that an external device requires bus mastership System clock output CANRX0 TouCAN Receive Data CAN serial data input CANTX0 TouCAN Transmit Data CAN serial data output CS[10:0] Chip-Selects CSBOOT Boot Chip-Select Select external devices at programmed addresses Chip-select for external bootstrap memory CPWM[8:5] CTM4 PWMs CTD[10:9]/[4:3] CTM4 Double Action Channels Bidirectional double action timer channels Four pulse-width modulation channels CTM2C CTM4 Modulus Clock Modulus counter clock input DATA[15:0] Data Bus 16-bit data bus used by the CPU32 Indicates that an external device should place valid data on the data bus during a read cycle and that valid data has been placed on the data bus by the CPU during a write cycle. DS Data Strobe DSACK[1:0] Data and Size Acknowledge DSI, DSO, DSCLK Developmental Serial In, Out, Clock ECLK E-Clock ETRIG[2:1] QADC External Trigger External trigger pins used when a QADC scan queue is in external trigger mode EXTAL, XTAL Crystal Oscillator Connections for clock synthesizer circuit reference; a crystal or an external oscillator can be used FC[2:0] Function Codes FREEZE Freeze HALT Halt IFETCH Instruction Pipeline Indicates instruction pipeline activity IPIPE Instruction Pipeline Indicates instruction pipeline activity IRQ[7:1] Interrupt Request Requests an interrupt of specified priority level from the CPU MA[2:0] QADC Multiplexed Address When external multiplexing is used, these pins provide addresses to the external multiplexer MISO Master In, Slave Out Serial input to QSPI in the master mode; serial output from QSPI in the slave mode MODCLK Clock Mode Select MC68336/376 USER'S MANUAL Provides asynchronous data transfers and dynamic bus sizing Serial I/O and clock for background debug mode M6800 bus clock output Identify processor state and current address space Indicates that the CPU has acknowledged a breakpoint Suspend external bus activity Selects the source of the system clock OVERVIEW Rev. 15 Oct 2000 MOTOROLA 3-11 Table 3-5 MC68336/376 Signal Functions (Continued) Mnemonic Signal Name Function MOSI Master Out, Slave In PC[6:0] Port C PCS[3:0] Peripheral Chip-Selects PE[7:0] Port E SIM digital input/output port signals SIM digital input/output port signals Serial output from the QSPI in master mode; serial input to the QSPI in slave mode SIM digital output port signals QSPI peripheral chip-select PF[7:0] Port F PQA[7:0] QADC Port A QADC port A digital input/output port signals PQB[7:0] QADC Port B QADC port B digital input port signals PQS[7:0] Port QS QSM digital input/output port signals QUOT Quotient Out R/W Read/Write RESET Reset RMC RXD Read-Modify-Write Cycle Provides the quotient bit of the polynomial divider (test mode only) Indicates the direction of data transfer on the bus System reset Indicates an indivisible read-modify-write instruction SCI Receive Data Serial input to the SCI SCK QSPI Serial Clock Clock output from QSPI in master mode; clock input to QSPI in slave mode SIZ[1:0] Size SS Slave Select T2CLK TPU Clock Indicates the number of bytes remaining to be transferred during a bus cycle Starts serial transmission when QSPI is in slave mode; chip-select in master mode TPU clock input TPUCH[15:0] TPU I/O Channels TSC Three-State Control Bidirectional TPU channels TSTME Test Mode Enable Hardware enable for SIM test mode TXD SCI Transmit Data Serial output from the SCI XFC External Filter Capacitor Places all output drivers in a high impedance state Connection for external phase-locked loop filter capacitor 3.6 Internal Register Map In Figure 3-4, IMB ADDR[23:20] are represented by the letter Y. The value represented by Y determines the base address of MCU module control registers. In the MC68336/376, Y is equal to M111, where M is the logic state of the module mapping (MM) bit in the system integration module configuration register (SIMCR). MC68336/376 USER'S MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 3-12 $YFF000 UNUSED $YFF080 QADC 512 BYTES $YFF200 TouCAN 384 BYTES (MC68376) $YFF400 CTM4 256 BYTES $YFF500 UNUSED $YFF820 8K ROM CONTROL 32 BYTES (MC68376) ROM ARRAY 8 KBYTES (MC68376) $YFF83F UNUSED $YFFA00 SIM 128 BYTES $YFFA80 UNUSED $YFFB00 TPURAM CONTROL 64 BYTES TPURAM ARRAY 3.5 KBYTES SRAM CONTROL 8 BYTES SRAM ARRAY 4.0 KBYTES $YFFB40 $YFFB48 UNUSED $YFFC00 $YFFE00 $YFFFFF QSM 512 BYTES TPU 512 BYTES NOTES: 1. Y=M111, WHERE M IS THE MODMAP SIGNAL STATE ON THE IMB, WHICH REFLECTS THE STATE OF THE MODMAP IN THE MODULE CONFIGURATION REGISTER OF THE SYSTEM INTEGRATION MODULE. (Y=$7 OR $F) 2. ATTEMPTED ACCESSES TO UNUSED LOCATIONS OR UNUSED BITS WITHIN VALID LOCATIONS RETURN ALL ZEROS. 336/376 ADDRESS MAP Figure 3-4 MC68336/376 Address Map 3.7 Address Space Maps Figure 3-5 shows a single memory space. Function codes FC[2:0] are not decoded externally so that separate user/supervisor or program/data spaces are not provided. In Figure 3-6, FC2 is decoded, resulting in separate supervisor and user spaces. FC[1:0] are not decoded, so that separate program and data spaces are not provided. In Figures 3-7 and 3-8, FC[2:0] are decoded, resulting in four separate memory spaces: supervisor/program, supervisor/data, user/program and user/data. All exception vectors are located in supervisor data space, except the reset vector, which is located in supervisor program space. Only the initial reset vector is fixed in the processor's memory map. Once initialization is complete, there are no fixed assignments. Since the vector base register (VBR) provides the base address of the MC68336/376 USER'S MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 3-13 vector table, the vector table can be located anywhere in memory. Refer to SECTION 4 CENTRAL PROCESSOR UNIT for more information concerning memory management, extended addressing, and exception processing. Refer to 5.5.1.7 Function Codes for more information concerning function codes and address space types. $000000 COMBINED SUPERVISOR AND USER SPACE VECTOR OFFSET VECTOR NUMBER 0000 0004 0008 0 1 2 RESET -- INITIAL STACK POINTER RESET -- INITIAL PC BUS ERROR 000C 0010 0014 0018 001C 0020 0024 0028 002C 0030 0034 0038 003C 0040-005C 006C 0064 0068 006C 0070 0074 0078 007C 0080-00BC 00C0-00EB 3 4 5 6 7 8 ADDRESS ERROR ILLEGAL INSTRUCTION ZERO DIVISION CHK, CHK2 INSTRUCTIONS TRAPcc, TRAPV INSTRUCTIONS PRIVILEGE VIOLATION 9 10 11 12 13 14 TRACE LINE 1010 EMULATOR LINE 1111 EMULATOR HARDWARE BREAKPOINT (RESERVED COPROCESSOR PROTOCOL VIOLATION) FORMAT ERROR AND UNINITIALIZED INTERRUPT 15 16-23 24 25 26 27 28 29 30 31 32-47 48-58 00EC-00FC 59-63 0100-03FC 64-255 TouCAN (MC68376) TYPE OF EXCEPTION $XX0000 FORMAT ERROR AND UNINITIALIZED INTERRUPT (UNASSIGNED, RESERVED) SPURIOUS INTERRUPT LEVEL 1 INTERRUPT AUTOVECTOR LEVEL 2 INTERRUPT AUTOVECTOR LEVEL 3 INTERRUPT AUTOVECTOR LEVEL 4 INTERRUPT AUTOVECTOR LEVEL 5 INTERRUPT AUTOVECTOR LEVEL 6 INTERRUPT AUTOVECTOR LEVEL 7 INTERRUPT AUTOVECTOR TAP INSTRUCTION VECTORS (0-15) (RESERVED, COPROCESSOR) (UNASSIGNED, RESERVED) USER-DEFINED VECTORS $XX03FC $YFF000 $YFF080 $YFF200 QADC $YFF400 CTM4 $7FF000 $YFF500 $YFF820 INTERNAL REGISTERS (MM = 0) MRM CONTROL (MC68376) $YFF83F $YFFA00 SIM $YFFA80 $YFFB00 TPURAM CTL $YFFB40 SRAM CTL $YFFB48 QSM $FFF000 $YFFC00 $YFFE00 INTERNAL REGISTERS (MM = 1) TPU $FFFFFF $YFFFFF NOTES: 1. LOCATION OF THE EXCEPTION VECTOR TABLE IS DETERMINED BY THE VECTOR BASE REGISTER. THE VECTOR ADDRESS IS THE CONCATENATION OF THE UPPER 22 BITS OF THE VBR WITH THE 8-BIT VECTOR NUMBER OF THE INTERRUPTING MODULE. THE RESULT IS LEFT JUSTIFIED TO FORCE LONG WORD ALIGNMENT. 2. LOCATION OF THE MODULE CONTROL REGISTERS IS DETERMINED BY THE STATE OF THE MODULE MAPPING (MM) BIT IN THE SIM CONFIGURATION REGISTER. Y = M111 WHERE M IS THE STATE OF THE MM BIT. 3. SOME UNUSED ADDRESSES WITHIN THE INTERNAL REGISTER BLOCK ARE MAPPED EXTERNALLY. REFER TO THE APPROPRIATE MODULE REFERENCE MANUAL FOR INFORMATION ON MAPPING OF UNUSED ADDRESSES WITHIN INTERNAL REGISTER BLOCKS. 336//376 S/U COMB MAP Figure 3-5 Overall Memory Map MC68336/376 USER'S MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 3-14 $000000 $000000 SUPERVISOR SPACE VECTOR OFFSET VECTOR NUMBER 0000 0004 0008 000C 0010 0014 0018 001C 0020 0024 0028 002C 0030 0 RESET -- INITIAL STACK POINTER 1 2 3 4 5 6 RESET -- INITIAL PC BUS ERROR ADDRESS ERROR ILLEGAL INSTRUCTION ZERO DIVISION CHK, CHK2 INSTRUCTIONS 7 8 9 10 11 12 13 0034 14 0038 003C 15 0040-005C 16-23 24 006C 0064 25 26 0068 27 006C 28 0070 29 0074 30 0078 007C 31 0080-00BC 32-47 00C0-00EB 48-58 00EC-00FC 59-63 0100-03FC 64-255 TYPE OF EXCEPTION TRAPcc, TRAPV INSTRUCTIONS PRIVILEGE VIOLATION TRACE LINE 1010 EMULATOR LINE 1111 EMULATOR HARDWARE BREAKPOINT (RESERVED COPROCESSOR PROTOCOL VIOLATION) FORMAT ERROR AND UNINITIALIZED INTERRUPT FORMAT ERROR AND UNINITIALIZED INTERRUPT (UNASSIGNED, RESERVED) SPURIOUS INTERRUPT LEVEL 1 INTERRUPT AUTOVECTOR LEVEL 2 INTERRUPT AUTOVECTOR LEVEL 3 INTERRUPT AUTOVECTOR LEVEL 4 INTERRUPT AUTOVECTOR LEVEL 5 INTERRUPT AUTOVECTOR LEVEL 6 INTERRUPT AUTOVECTOR LEVEL 7 INTERRUPT AUTOVECTOR TAP INSTRUCTION VECTORS (0-15) (RESERVED, COPROCESSOR) (UNASSIGNED, RESERVED) USER-DEFINED VECTORS TouCAN (MC68376) $XX0000 USER SPACE $XX03FC $YFF000 $YFF080 $YFF200 QADC $YFF400 CTM4 $7FF000 $7FF000 $YFF500 INTERNAL REGISTERS $YFF820 INTERNAL REGISTERS MRM CONTROL (MC68376) $YFF83F $YFFA00 SIM $YFFA80 $YFFB00 TPURAM CTL $YFFB40 SRAM CTL $YFFB48 QSM $FFF000 INTERNAL REGISTERS $FFFFFF $YFFC00 $YFFE00 TPU $YFFFFF INTERNAL REGISTERS $FFF000 $FFFFFF NOTES: 1. LOCATION OF THE EXCEPTION VECTOR TABLE IS DETERMINED BY THE VECTOR BASE REGISTER. THE VECTOR ADDRESS IS THE CONCATENATION OFTHE UPPER 22 BITS OF THE VBR WITH THE 8-BIT VECTOR NUMBER OF THE INTERRUPTING MODULE. THE RESULT IS LEFT JUSTIFIED TO FORCE LONG WORD ALIGNMENT. 2. LOCATION OF THE MODULE CONTROL REGISTERS IS DETERMINED BY THE STATE OF THE MODULE MAPPING (MM) BIT IN THE SIM CONFIGURATION REGISTER. Y = M111 WHERE M IS THE STATE OF THE MM BIT. 3. SOME UNUSED ADDRESSES WITHIN THE INTERNAL REGISTER BLOCK ARE MAPPED EXTERNALLY. REFER TO THE APPROPRIATE MODULE REFERENCE MANUAL FOR INFORMATION ON MAPPING OF UNUSED ADDRESSES WITHIN INTERNAL REGISTER BLOCKS. 4. SOME INTERNAL REGISTERS ARE NOT AVAILABLE IN USER SPACE. 336/376 S/U SEP MAP Figure 3-6 Separate Supervisor and User Space Map MC68336/376 USER'S MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 3-15 $000000 $000000 SUPERVISOR PROGRAM SPACE VECTOR OFFSET VECTOR NUMBER EXCEPTION VECTORS LOCATED IN SUPERVISOR PROGRAM SPACE 0000 0 RESET -- INITIAL STACK POINTER 0004 1 RESET -- INITIAL PC VECTOR VECTOR EXCEPTION VECTORS LOCATED OFFSET NUMBER IN SUPERVISOR DATA SPACE 0008 000C 0010 0014 2 3 4 5 BUS ERROR ADDRESS ERROR ILLEGAL INSTRUCTION ZERO DIVISION 0018 001C 0020 0024 0028 002C 6 7 8 9 10 11 CHK, CHK2 INSTRUCTIONS TRAPcc, TRAPV INSTRUCTIONS PRIVILEGE VIOLATION TRACE LINE 1010 EMULATOR LINE 1111 EMULATOR 0030 0034 0038 003C 0040-005C 006C 12 13 14 15 16-23 24 25 0064 0068 26 006C 27 0070 28 0074 29 30 0078 007C 31 0080-00BC 32-47 00C0-00EB 48-58 00EC-00FC 59-63 0100-03FC 64-255 HARDWARE BREAKPOINT (RESERVED COPROCESSOR PROTOCOL VIOLATION) FORMAT ERROR AND UNINITIALIZED INTERRUPT FORMAT ERROR AND UNINITIALIZED INTERRUPT (UNASSIGNED, RESERVED) SPURIOUS INTERRUPT LEVEL 1 INTERRUPT AUTOVECTOR LEVEL 2 INTERRUPT AUTOVECTOR LEVEL 3 INTERRUPT AUTOVECTOR LEVEL 4 INTERRUPT AUTOVECTOR LEVEL 5 INTERRUPT AUTOVECTOR LEVEL 6 INTERRUPT AUTOVECTOR LEVEL 7 INTERRUPT AUTOVECTOR TAP INSTRUCTION VECTORS (0-15) (RESERVED, COPROCESSOR) (UNASSIGNED, RESERVED) USER-DEFINED VECTORS TouCAN (MC68376) $XX0000 $XX0004 $XX0008 SUPERVISOR PROGRAM SPACE $XX03FC $YFF000 $YFF080 $YFF200 QADC $YFF400 CTM4 $7FF000 $YFF500 INTERNAL REGISTERS $YFF820 MRM CONTROL (MC68376) $YFF83F $YFFA00 SIM $YFFA80 $YFFB00 TPURAM CTL $YFFB40 SRAM CTL $YFFB48 QSM $FFF000 $YFFC00 $YFFE00 INTERNAL REGISTERS $FFFFFF TPU $YFFFFF $FFFFFF NOTES: 1. LOCATION OF THE EXCEPTION VECTOR TABLE IS DETERMINED BY THE VECTOR BASE REGISTER. THE VECTOR ADDRESS IS THE CONCATENATION OF THE UPPER 22 BITS OF THE VBR WITH THE 8-BIT VECTOR NUMBER OF THE INTERRUPTING MODULE. THE RESULT IS LEFT JUSTIFIED TO FORCE LONG WORD ALIGNMENT. 2. LOCATION OF THE MODULE CONTROL REGISTERS IS DETERMINED BY THE STATE OF THE MODULE MAPPING (MM) BIT IN THE SIM CONFIGURATION REGISTER. Y = M111 WHERE M IS THE STATE OF THE MM BIT. 3. SOME UNUSED ADDRESSES WITHIN THE INTERNAL REGISTER BLOCK ARE MAPPED EXTERNALLY. REFER TO THE APPROPRIATE MODULE REFERENCE MANUAL FOR INFORMATION ON MAPPING OF UNUSED ADDRESSES WITHIN INTERNAL REGISTER BLOCKS. 4. SOME INTERNAL REGISTERS ARE NOT AVAILABLE IN USER SPACE. 336/376 SUPER P/D MAP Figure 3-7 Supervisor Space (Separate Program/Data Space) Map MC68336/376 USER'S MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 3-16 $000000 $000000 USER PROGRAM SPACE USER DATA SPACE TouCAN (MC68376) $YFF000 $YFF080 $YFF200 QADC $YFF400 CTM4 $YFF500 $7FF000 INTERNAL REGISTERS $YFF820 MRM CONTROL (MC68376) $YFF83F $YFFA00 SIM $YFFA80 $YFFB00 TPURAM CTL $YFFB40 SRAM CTL $YFFB48 $YFFC00 QSM $YFFE00 $FFF000 INTERNAL REGISTERS TPU $YFFFFF $FFFFFF $FFFFFF NOTES: 1. LOCATION OF THE MODULE CONTROL REGISTERS IS DETERMINED BY THE STATE OF THE MODULE MAPPING (MM) BIT IN THE SIM CONFIGURATION REGISTER. Y = M111, WHERE M IS THE STATE OF THE MM BIT. 2. UNUSED ADDRESSES WITHIN THE INTERNAL REGISTER BLOCK ARE MAPPED EXTERNALLY. "RESERVED" BLOCKS ARE NOT MAPPED EXTERNALLY. 3. SOME INTERNAL REGISTERS ARE NOT AVAILABLE IN USER SPACE. 336/376 USER P/D MAP Figure 3-8 User Space (Separate Program/Data Space) Map MC68336/376 USER'S MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 3-17 MC68336/376 USER'S MANUAL OVERVIEW Rev. 15 Oct 2000 MOTOROLA 3-18